WO2021115039A1 - Fpga platform, performance evaluation and design optimization method therefor, and storage medium - Google Patents

Abstract

An FPGA platform, a performance evaluation and design optimization method therefor, and a storage medium. The method comprises: classifying data to be processed of an algorithm to be operated of the FPGA platform according to variables, the data corresponding to each variable being classified into a same data class, and the number of the data classes being equal to the number of the variables and not less than 2 (S101); calculating a calculation amount and a read amount required by each data class (S102); summing the calculation amounts and the read amounts of the data classes to obtain a total calculation amount and a total read amount of the algorithm to be operated (S103); and performing performance evaluation and/or design optimization on the FPGA platform on the basis of the total calculation amount and the total read amount (S104). The data to be processed is classified according to the variables on the basis of the algorithm to be operated, so as to visually reflect the contribution of the data to be processed in the data classes to the calculation amount and the read amount of the algorithm to be operated, so that the FPGA platform is analyzed on the basis of the total calculation amount and the total read amount to find performance bottlenecks of the FPGA platform.

Description

FPGA platform and its performance evaluation and design optimization methods and storage media Technical field

This application relates to the technical field of high-performance computing, and specifically relates to an FPGA platform and its performance evaluation and design optimization methods and storage media.

Background technique

With the rapid development of big data and artificial intelligence, more and more data-intensive and computationally intensive algorithms have been proposed, and more calculations and faster processing speeds place higher requirements on the performance of computing devices. Compared with commonly used computing devices such as GPU (graphics processing unit), CPU (central processing unit) and ASIC (application-specific integrated circuit), FPGA (Field Programmable Gate Array) platform has good flexibility, Excellent performance and low power consumption make the FPGA platform widely used in application scenarios with high performance, low power consumption, and diverse algorithms.

Summary of the invention

The embodiment of the present application provides a method for performance evaluation and design optimization of an FPGA platform, where the method includes: classifying the data to be processed of the algorithm to be run on the FPGA platform according to variables; wherein, the data corresponding to each variable Are divided into the same data category, the number of data categories is equal to the number of variables, and not less than 2; calculate the amount of calculation and reading required for each data category; sum the calculation amount and reading amount of each data category , To calculate the total calculation volume and total read volume of the algorithm to be run; perform performance evaluation and/or design optimization of the FPGA platform based on the total calculation volume and total read volume.

An embodiment of the present application also provides an FPGA platform, where the FPGA platform includes a memory and a processor, the memory is coupled to the processor, the memory is used to store program data, and the processor is used to execute the program data to implement the above method.

The embodiment of the present application further provides a computer storage medium for storing a computer program, where the computer program implements the foregoing method when being executed by a processor.

The beneficial effect of this application is that the method provided in this application classifies the data to be processed according to variables based on the algorithm to be run, so that the data corresponding to each variable is classified into the same data category, so as to visually reflect the data categories The contribution of the data to be processed to the calculation and reading of the algorithm to be run, so as to analyze the FPGA platform based on the total calculation and total reading of the algorithm to be run, so as to find the performance bottleneck of the FPGA platform and guide the FPGA platform Design Optimization.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained from these drawings without creative work.

FIG. 1 is a schematic flowchart of an embodiment of a method for performance evaluation and design optimization of an FPGA platform provided by the present application;

FIG. 2 is a schematic flowchart of an embodiment of step S104 in FIG. 1;

FIG. 3 is a schematic structural diagram of an embodiment of the FPGA platform provided by the present application;

Fig. 4 is a schematic structural diagram of an embodiment of a computer storage medium provided by the present application.

Detailed ways

The application will be further described in detail below in conjunction with the drawings and embodiments. It is particularly pointed out that the following examples are only used to illustrate the application, but do not limit the scope of the application. Similarly, the following embodiments are only part of the embodiments of the present application, but not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without creative work shall fall within the protection scope of the present application.

The reference to "embodiments" in this application means that a specific feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art clearly and implicitly understand that the embodiments described in this application can be combined with other embodiments.

The inventor of this application has discovered through long-term research that an important issue in using the FPGA platform is the performance evaluation of FPGA circuit design and implementation, that is, the same algorithm can have multiple design solutions on the FPGA platform, and each design solution is implemented Performance may be different. Therefore, evaluating the performance that can be achieved by the design is the key to predicting performance bottlenecks and guiding design optimization. In addition, most of the current mathematical models are established for the CNN (Convolutional Neural Networks, convolutional neural network) algorithm to analyze the algorithm as a whole; it does not consider the different characteristics of the data corresponding to different variables in the algorithm, and does not optimize the memory for different variables.化 points out the direction. For this reason, this application proposes the following embodiments.

Refer to FIG. 1, which is a schematic flowchart of an embodiment of a method for performance evaluation and design optimization of an FPGA platform provided by the present application. The method includes:

S101: Classify the to-be-processed data of the algorithm to be run on the FPGA platform according to variables; wherein, the data corresponding to each variable is classified into the same data category, and the number of data categories is equal to the number of variables and is not less than 2.

In the embodiment of the present application, the algorithm to be executed includes at least preset algorithms such as matrix or vector multiplication and/or addition operations. Among them, the addition algorithm can specifically include addition and subtraction between data. For other types of operations, the multiplication algorithm can also specifically include multiplication and division between data. Further, based on the above-mentioned preset algorithm, the FPGA platform will process the data to be processed to calculate the result of the operation.

For a large amount of data in a certain algorithm, the total number of times each data participates in the operation is not necessarily the same. For example, for k*A _mn (k can be a constant, A _mn can be expressed as a matrix containing (m×n) data, and specifically contains (m×n+1) data) this operation, where the variable The number is 2; and the total number of times that the constant k participates in the operation is (m×n) times, and the total number of times that each data in the _{matrix A mn participates in the operation is 1 time.} In other words, in the process of performing the above operations on the FPGA platform, the constant k will be read (m×n) times; and _{each data in the matrix A mn} will only be read once. To this end, the constant k can be regarded as one type of data, and the data in the matrix A _mn can be regarded as another type of data, that is, the number of data types is two.

In summary, the embodiments of the present application categorize the data to be processed according to variables based on the algorithm to be run in a different way, so that the data corresponding to each variable is classified into the same data category, so as to visually reflect the data to be processed in each data category. The contribution of the calculation amount and reading amount of the algorithm to be run can point out the direction for the optimization of data reading, which will be explained in detail later.

S102: Calculate the amount of calculation and reading required for each data category.

Based on the above detailed description, for a certain algorithm, the amount of calculation and the amount of reading required for each data category are not necessarily the same. Therefore, in order to better analyze the contribution of each data category to the amount of calculation and reading during the operation of the algorithm, this application proposes a new approach to the contribution of a single data to participate in the calculation C and the total number of participations N of a single data. Basic analysis indicators.

On the one hand, when each data to be processed in each data category participates in a single operation, the ratio of the number of operations involved in a single operation and the number of data to be processed in a single operation is used as the single calculation contribution of each data to be processed degree. Therefore, the single calculation contribution C of each data to be processed can be described by formula (1):

C=Ops/Data (1)

In the above formula (1), Ops represents the number of operations involved in a single operation, and Data represents the number of data to be processed participating in a single operation. For example, for the above k*A _mn operation, a single operation can be regarded as the multiplication of two numbers. Therefore, the number of operations involved in a single operation is 1, and the number of data to be processed in a single operation is 2. Make the single calculation contribution degree of each data to be processed is 1/2.

On the other hand, the number of times each data to be processed repeatedly participates in a single operation can be used as the total number of participation times N of the data. For example, for the above k*A _mn operation, the total number of participations of the constant k is (m×n) times, and the total number of participations of each data in the _{matrix A mn is 1.}

For each data category, the product result of the single calculation contribution of each data to be processed and the number of repetitions of each data to be processed repeatedly participating in a single operation is averaged to obtain the average contribution of each data category. Thus, each category of data the average contribution of C _A can be described by equation (2):

Above formula (2), n represents a number of data categories of data to be processed, C _i represents the i-th single computing the contribution of data to be processed, N _i denotes the i-th data to be processed per operation was repeated participation The number of repetitions.

Further, the product result of the number of data to be processed and the average contribution degree in each data category is taken as the calculation amount required for each data category. At this time, the amount of calculation required for each data category can be described by the formula (D _A ×C _A ). Where D _A represents the number of data to be processed in each data category.

For each data category, the number of repetitions of each data to be processed is averaged to obtain the average number of repetitions of each data category. Thus, each category of data the average number of repetitions R _A can be described by equation (3):

The above equation (3), n represents a number of data categories of data to be processed, N _i denotes the i-th data to be processed participation repetitions repeated single operation.

Further, the product result of the number of data to be processed, the average number of repetitions, and the data bit width in each data category is taken as the required reading amount for each data category. At this time, the amount of reading required for each data category can be described by the formula (D _A ×R _A ×D _S ). Where D _S represents the data bit width of each data category.

It should be noted that for a single-precision 32-bit floating point number, the bit width of each data is 4 bytes; for a double-precision 64-bit floating point number, the bit width of each data is 8 bytes.

S103: The calculation amount and the reading amount of each data category are summed to calculate the total calculation amount and the total reading amount of the algorithm to be run.

Based on the above detailed description, _{the total calculation amount of the algorithm to be run can be obtained by summing the formula (D A} ×C _A ), and the algorithm to be run can be obtained by summing the formula (D _A ×R _A ×D _S ) The total number of reads. Therefore, the total calculation amount O _{A of the} algorithm to be run can be described by formula (4):

In the above formula (4), m represents the number of data categories in the algorithm to be run, D _Aj represents the number of data to be processed in the j-th data category, and C _Aj represents the average contribution of the j-th data category.

Further, the total read amount T _{A of the} algorithm to be run can be described by formula (5):

The above equation (5), m represents a number to be executed algorithm category of data, D _Aj represents the number of data to be processed in the j-th data categories, R _Aj represents an average repeating number of the j-th data categories, R _Aj represents The data bit width of the j-th data category.

It should be noted that, because the algorithm to be run may involve a very large amount of calculation and reading, the equations (1G=1000M≈1024M=2 ¹⁰ M) commonly used in this field can be used to compare the above formulas (4) and (5). The calculation result of) is converted on an order of magnitude, so that the total calculation amount can be expressed in GOps (billion operations), and the total read amount can be expressed in GB (gigabytes).

The following takes the multiplication of a 2048×1024 matrix A and a 1024×1024 matrix B as an example to briefly explain the above formulas and their main parameters:

For the algorithm of multiplying the above two matrices, (2048×1024+1024×1024) data to be processed can be divided into two categories according to variables. One type can be the (2048×1024) data to be processed contained in matrix A Data, the other type can be the (1024×1024) data to be processed contained in matrix B. Among them, based on the definition of matrix multiplication operation, each operation can be regarded as an element in a row of matrix A multiplied by a corresponding element in a column of matrix B and then summed. Further, the data type of the matrix A and the matrix B can be single-precision 32-bit floating point numbers, so the data bit width D _{S of the} matrix A and the matrix B can be 4 bytes. In this way, the main analysis results are shown in the following table:

It can be seen that for the above two matrix multiplication algorithm, the contribution of each data in matrix B to the calculation and reading of the algorithm is higher than that of matrix A. For this reason, either matrix B can be designed as on-chip storage, or a larger bandwidth memory can be allocated to matrix B to increase the efficiency of reading each data in matrix B, which will be described in detail later.

S104: Perform performance evaluation and/or design optimization of the FPGA platform based on the total calculation amount and the total read amount.

For the FPGA platform, the total computational load of the algorithm to be run can reflect the load to be borne by its processor, and the total read load of the algorithm to be run can reflect the load to be borne by its memory. In general, the greater the total amount of calculation, the greater the load the processor has to bear, that is, the higher the requirement for the processor's computing performance; the greater the total read amount, the greater the load the memory has to bear, that is, The higher the requirement for memory read performance. Therefore, the performance of the FPGA platform can be evaluated based on the total calculation amount and total read amount of the algorithm to be run, so as to find the performance bottleneck of the FPGA platform, and the design of the FPGA platform can be optimized based on the above-mentioned performance bottleneck.

Refer to FIG. 2, which is a schematic flowchart of an embodiment of step S104 in FIG. 1. Among them, this embodiment is mainly used to explain how to find the performance bottleneck of the FPGA platform based on the total calculation amount and total read amount of the algorithm to be run, and how to optimize the design of the FPGA platform based on the performance bottleneck.

Generally, FPGA platform can use DDR DRAM (Double Data Rate, Dynamic Random Access Memory, double data rate dynamic random access memory) and BRAM (Block Random Access Memory, block random access memory) to read data. . Among them, DRAM belongs to off-chip storage, and BRAM belongs to on-chip storage; the read performance of on-chip storage is better than that of off-chip storage. Further, the FPGA platform can use its internal DSP (Digital Signal Processor) when processing data multiplication and addition operations, so that the theoretical maximum operating speed is directly related to the number of processors used.

Therefore, for a certain FPGA platform, the theoretical maximum memory bandwidth and theoretical maximum operating speed are determined. Among them, the theoretical maximum memory bandwidth B _max can be described by formula (6):

In the above formula (6), n represents the number of types of memory used by the FPGA platform, W _idth represents the memory bit width of the i-th type of memory, and f _ram represents the operating frequency of the memory. Further, _{the unit of B max} can be expressed in GB/s (gigabytes per second).

Further, the theoretical maximum operating speed P _max can be described by formula (7):

P _max ＝N _DSP ×f _DSP ×2 (7)

In the above formula (7), N _DSP represents the number of processors used in the FPGA platform, f _DSP represents the clock frequency of the processors, and the constant 2 represents that the processors used can simultaneously perform two operations of addition and multiplication under the same clock pulse. Further, _{the unit of P max} can be expressed in GOps/s (billion operations per second).

其单位可以用GOps/GB表示。该常数可以表示待运行算法在FPGA平台上运行时，单位读取量能够支持的计算量。显然，该常数直接揭示了数据读取速度与算法运行速度之间的关系。进一步地，如果FPGA平台以内存带宽B在单位时间内读取数据T ₁；考虑到数据不一定会被完全使用，则FPGA平台在单位时间内也最多只能以速度P运行算法

次。基于此，可以得到如下关系式(8)： Based on the above detailed description, according to the above formulas (4)-(5), the total calculation amount and total read amount of the algorithm to be run can be calculated respectively. Further, since the amount of calculation algorithm to be run with the total amount of read interrelated, the present embodiment calculates the total amount of the total O _A T _A obtained by dividing the amount of read constant

The unit can be expressed in GOps/GB. This constant can represent the amount of calculation that can be supported by the unit read amount when the algorithm to be run is running on the FPGA platform. Obviously, this constant directly reveals the relationship between the data reading speed and the algorithm running speed. Further, if the FPGA platform uses the memory bandwidth B to read the data T ₁ in a unit time; considering that the data may not be fully used, the FPGA platform can only run the algorithm at the speed P at most per unit time

Times. Based on this, the following relationship (8) can be obtained:

In the above formula (8), P represents the actual running speed of the algorithm to be run on the FPGA platform, and B represents the memory bandwidth for the FPGA platform to read the data to be processed when the algorithm is running. Among them, the memory bandwidth includes not only the memory bandwidth provided by the on-chip storage during operation, but also the memory bandwidth provided by the off-chip storage during operation.

≤一个常数。产生这种情况的原因有两个：一是内存带宽不匹配，例如一类数据的内存带宽设计过大，而另一类数据的内存带宽设计过小，使得大带宽的数据等待，无法充分发挥作用，从而导致FPGA平台的实际运行速度小于最优值；二是处理器运算速度过低，数据处理速度低于数据读取速度，导致平台 实际运行速度小于最优值。如果是由于内存带宽不匹配导致的，为使公式(8)取得等号，本申请提出等式

以指导如何为不同数据匹配相应的内存带宽。其中，T _Aj表示第j个数据类别的读取量，B _j表示第j个数据类别所分配内存的带宽。显然，该等式成立意味着各个数据类别的内存带宽与其读取量成正比，以使得待运行算法在运行时读取的各类数据都能够被完全利用，从而改善内存带宽过大或过小的问题。也即是本申请在各个数据类别之间对内存的带宽进行分配，以使得各个数据类别的读取量与其所分配的带宽的比值趋于相等，从而优化FPGA平台的性能。进一步地，本申请根据各个数据类别中的待处理数据重复参与单次运算的重复次数，设置各个数据类别从FPGA平台的片外存储到片内存储的读取优先级别。其中，重复次数越大，读取优先级别越高，以优化不同数据类别的读取效率，从而优化FPGA平台的性能。并且，对于重复次数为1的数据类别，也即是其待处理数据仅参与一次单次运算，可以将该数据类别的待处理数据仅存储于片内DDR DRAM。如果是处理器运算速度导致的，使得公式(8)无法取得等号，那么FPGA平台性能瓶颈在于平台，运算速度等于实际使用处理器的运算速度。 Furthermore, since the data may not be fully used, so

≤a constant. There are two reasons for this situation: one is the memory bandwidth mismatch. For example, the memory bandwidth of one type of data is designed to be too large, while the memory bandwidth of the other type of data is designed to be too small, making large-bandwidth data waiting and unable to make full use of As a result, the actual operating speed of the FPGA platform is less than the optimal value; second, the processor's operating speed is too low, and the data processing speed is lower than the data reading speed, resulting in the actual operating speed of the platform being lower than the optimal value. If it is caused by the memory bandwidth mismatch, in order to get the equal sign of formula (8), this application proposes an equation

To guide how to match the corresponding memory bandwidth for different data. Among them, T _Aj represents the read volume of the j-th data category, and B _j represents the bandwidth of the memory allocated for the j-th data category. Obviously, the establishment of this equation means that the memory bandwidth of each data category is proportional to the amount of reading, so that all kinds of data read by the algorithm to be run at runtime can be fully utilized, thereby improving the memory bandwidth that is too large or too small The problem. That is, this application allocates the bandwidth of the memory among various data categories, so that the ratio of the read amount of each data category to the allocated bandwidth tends to be equal, thereby optimizing the performance of the FPGA platform. Further, the present application sets the read priority level of each data category from the off-chip storage of the FPGA platform to the on-chip storage according to the number of repetitions of the data to be processed in each data category repeatedly participating in a single operation. Among them, the greater the number of repetitions, the higher the read priority level to optimize the read efficiency of different data categories, thereby optimizing the performance of the FPGA platform. In addition, for a data category with a repetition number of 1, that is, its to-be-processed data only participates in a single operation, the to-be-processed data of this data category can only be stored in the on-chip DDR DRAM. If it is caused by the computing speed of the processor, which makes formula (8) unable to obtain the equal sign, then the performance bottleneck of the FPGA platform lies in the platform, and the computing speed is equal to the computing speed of the actual processor used.

Based on the above detailed analysis, step S104 may specifically include:

S1041: Calculate the first operating speed of the FPGA platform according to the read performance, total calculation amount, and total read amount of the memory of the FPGA platform.

In this embodiment, the first operating speed may be equal to the product result of the ratio of the total calculation amount to the total read amount and the bandwidth of the memory. At this time, the first running speed P ₁ can be described by formula (9):

In the above formula (9), the total calculation amount O _A can be expressed in units of the number of operations, the total read amount T _A can be expressed in bytes, and the bandwidth B of the memory can be expressed in bytes per second. , So that the first running speed P ₁ can be expressed in units of calculation times/second.

S1042: Calculate the second operating speed of the FPGA platform according to the computing performance of the processor of the FPGA platform.

In this embodiment, the second operating speed may be equal to the product of the number of processors, the clock frequency, and the number of operations that can be performed synchronously under the same clock pulse, and it may be expressed in units of operations/second. At this time, the second running speed P ₂ can be described by formula (10):

P ₂ ＝N _used ×f _DSP ×N (10)

In the above formula (10), N _used represents the number of processors in the FPGA platform, f _DSP represents the clock frequency of the processor, and N represents the number of operations that the used processor can perform synchronously under the same clock pulse. For example, N=2 means that the processor used can simultaneously perform two operations of addition and multiplication under the same clock pulse.

S1043: Compare the magnitude of the first running speed and the second running speed.

When the comparison result of step S1043 is that the first operating speed is less than the second operating speed, step S1044 is executed; and when the comparison result of step S1043 is that the second operating speed is less than the first operating speed, step S1045 is executed.

In this embodiment, the performance bottleneck of the FPGA platform can be found by comparing the size of the first operating speed and the second operating speed, and the design of the FPGA platform can be further optimized based on the comparison result. details as follows:

S1044: Determine that the performance of the FPGA platform is restricted by the read performance of the memory.

In this embodiment, when the computing performance of the processor has been determined, by adjusting the read performance of the memory, the first operating speed can be made greater than or equal to the second operating speed, thereby optimizing the design of the FPGA.

S1045: Determine that the performance of the FPGA platform is restricted by the computing performance of the processor.

In this embodiment, when the read performance of the memory has been determined, by adjusting the computing performance of the processor, the second operating speed can be made greater than or equal to the first operating speed, thereby optimizing the design of the FPGA.

The following is based on the above example of multiplying the 2048×1024 matrix A and the 1024×1024 matrix B to verify the feasibility of this embodiment, and briefly explain the main parameters:

This embodiment is based on the OpenCL 17.1 development environment, the FPGA platform is the C5P development board of Friends of the crystal, and the development board is further connected to the computer motherboard through the PCIe interface and communicates with the host.

为0.25GOps/GB。 Wherein, for the matrix A 2048 × 1024 matrix B 1024 × 1024 multiplies the calculation, since the amount of calculation is O _A 4GOps, T _A is the total amount of read 16GB, such constant

It is 0.25GOps/GB.

Further, this embodiment is verified three times in total. Among them, the first verification does not use on-chip storage, all the data to be processed is read from off-chip storage, that is, the data to be processed is stored in off-chip DDR DRAM in advance; the second time on-chip storage is used, that is Store the data to be processed in the on-chip BRAM in advance (the total bit width of the on-chip BRAM is 64 bits and the frequency is 400MHz); the third use of on-chip storage (where the total bit width of the on-chip BRAM is 2048 bits, The frequency is 400MHz). In this way, the main analysis results are shown in the following table:

To B P ₁ N _used f _DSP P ₂ P Verification One 0.2 0.05 1 0.13 0.26 0.05 Verification two 3.2 0.8 1 0.13 0.26 0.24 Verification Three 100 25 32 0.13 8.32 8.24

It should be noted that P ₁ is the first operating speed of the FPGA platform calculated based on formula (9), P _{2 is} the second operating speed of the FPGA platform calculated based on formula (10), and P represents the actual operation of the FPGA platform speed.

It can be seen that the performance bottleneck of the FPGA platform is the read performance of the memory, that is, the data to be processed is stored in off-chip DDR DRAM, which results in too low memory bandwidth. At this time, if you want to improve the performance of the FPGA platform, you can store the data to be processed in the on-chip BRAM in advance. For example, you can design the data of matrix B to be stored on-chip to increase the efficiency of reading the data in matrix B. Verification 2 also satisfies the comparison result of step S1043, and the actual operating speed of the FPGA platform is approximately equal to the theoretical operating speed of a processor, indicating that the performance bottleneck of the FPGA platform lies in the computing performance of the processor, resulting in data processing speed lower than data reading speed. At this time, if you want to improve the performance of the FPGA platform, you can increase the number of processors so that more processors can perform parameter operations. Further, verification three is similar to verification two. Although the read performance and computing performance of the FPGA platform have been optimized to a certain extent, the performance bottleneck of the FPGA platform still lies in the computing performance of the processor. This is mainly because the optimization of read performance (memory optimization) does not match the optimization of computing performance (processor optimization), causing the processor's computing speed to still fail to keep up with the memory read speed.

Based on the above detailed analysis, when optimizing the design of the FPGA platform, the difference between the first operating speed and the second operating speed can be reduced as much as possible, that is, to make the processor's computing speed and memory as much as possible. To match the reading speed.

Fig. 3 is a schematic structural diagram of an embodiment of the FPGA platform provided by the present application.

The FPGA platform 300 of this embodiment includes a memory 301 and a processor 302, and the memory 301 and the processor 302 may be coupled via a data bus. The memory 301 may be off-chip storage and/or on-chip storage, and is used to store program data. Further, the processor 302 may be a digital signal processor, and is used to execute the program data to implement the following method steps:

The data to be processed of the algorithm to be run on the FPGA platform are classified according to variables; among them, the data corresponding to each variable is divided into the same data category, and the number of data categories is equal to the number of variables and not less than 2; each data is calculated The amount of calculation and reading required by the category; the calculation amount and reading amount of each data category are summed to calculate the total calculation amount and total reading amount of the algorithm to be run; based on the total calculation amount and total reading amount Perform performance evaluation and/or design optimization on FPGA platform.

It should be noted that the FPGA platform 300 of this embodiment is a physical terminal based on any of the foregoing method embodiments, and its implementation principles and steps are similar, and will not be repeated here. Therefore, when the program data is executed by the processor 302, other method steps in any of the foregoing embodiments can also be implemented, which will not be repeated here.

Fig. 4 is a schematic structural diagram of an embodiment of a computer storage medium provided by the present application.

The computer storage medium 400 of this embodiment is used to store a computer program 401, and the computer program 401 is executed by a processor to implement the following method steps:

The data to be processed of the algorithm to be run on the FPGA platform are classified according to variables; among them, the data corresponding to each variable is divided into the same data category, and the number of data categories is equal to the number of variables and not less than 2; each data is calculated The amount of calculation and reading required by the category; the calculation amount and reading amount of each data category are summed to calculate the total calculation amount and total reading amount of the algorithm to be run; based on the total calculation amount and total reading amount Perform performance evaluation and/or design optimization on FPGA platform.

It should be noted that the method implemented by the computer program 401 in this embodiment is based on any of the foregoing method embodiments, and its implementation principles and steps are similar. Therefore, when the computer program 401 is executed by the processor, it can also implement other method steps in any of the foregoing embodiments, which will not be repeated here.

When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

The above descriptions are only part of the embodiments of this application, and do not limit the scope of protection of this application. Any equivalent device or equivalent process transformation made using the content of the description and drawings of this application, or directly or indirectly applied to other related The technical field is equally included in the scope of patent protection of this application.

Claims (11)

A method for performance evaluation and design optimization of an FPGA platform, characterized in that the method includes: The data to be processed of the algorithm to be run on the FPGA platform is classified according to variables; wherein the data corresponding to each variable is classified into the same data category, and the number of data categories is equal to the number of variables, And not less than 2; Calculate the amount of calculation and reading required for each of the data types; Summing the calculation amount and the reading amount of each of the data types to calculate the total calculation amount and the total reading amount of the algorithm to be run; Perform performance evaluation and/or design optimization on the FPGA platform based on the total calculation amount and the total read amount. The method according to claim 1, wherein the step of calculating the amount of calculation and the amount of reading required for each of the data types comprises: Taking a product result of the number of the data to be processed and the average contribution in each of the data categories as the calculation amount required for each of the data categories; The product result of the number of the data to be processed, the average number of repetitions, and the data bit width in each of the data categories is taken as the reading amount required for each of the data categories. The method according to claim 2, wherein the step of calculating the amount of calculation and the amount of reading required for each of the data types further comprises: When each of the data to be processed in each of the data categories participates in a single operation, the ratio of the number of operations involved in the single operation to the number of the data to be processed participating in the single operation is used as each State the contribution of a single calculation of the data to be processed; For each of the data categories, the product result of the single calculation contribution of each of the data to be processed and the number of repetitions of each of the data to be processed repeatedly participating in the single operation is averaged to obtain each of the The average contribution of the data category; For each of the data categories, the repetition times of each of the data to be processed are averaged to obtain the average repetition times of each of the data categories. The method according to claim 1, wherein the step of performing performance evaluation and/or design optimization of the FPGA platform based on the total calculation amount and the total read amount comprises: Calculating the first operating speed of the FPGA platform according to the read performance of the memory of the FPGA platform, the total calculation amount, and the total read amount; Calculating the second operating speed of the FPGA platform according to the computing performance of the processor of the FPGA platform; Comparing the magnitude of the first operating speed and the second operating speed; If the first operating speed is less than the second operating speed, it is determined that the performance of the FPGA platform is restricted by the read performance of the memory; If the second operating speed is less than the first operating speed, it is determined that the performance of the FPGA platform is restricted by the computing performance of the processor. The method according to claim 4, wherein the first operating speed is equal to the product result of the ratio of the total calculation amount to the total read amount and the bandwidth of the memory; wherein, the total calculation The amount is expressed in a unit of the number of operations, the total read amount is expressed in a unit of bytes, and the bandwidth of the memory is expressed in a unit of bytes/second; The second operating speed is equal to the product result of the number of processors, the clock frequency, and the number of operations that can be executed synchronously under the same clock pulse, and is expressed in units of the number of operations/second. The method according to claim 4, wherein the step of performing performance evaluation and/or design optimization of the FPGA platform based on the total calculation amount and the total read amount further comprises: When the computing performance of the processor has been determined, adjusting the read performance of the memory so that the first operating speed is greater than or equal to the second operating speed; When the read performance of the memory is determined, the calculation performance of the processor is adjusted so that the second operating speed is greater than or equal to the first operating speed. The method according to claim 4, wherein the step of performing performance evaluation and/or design optimization of the FPGA platform based on the total calculation amount and the total read amount further comprises: The bandwidth of the memory is allocated among the data categories, so that the ratio of the read amount of each data category to the allocated bandwidth tends to be equal. The method according to claim 4, wherein the step of performing performance evaluation and/or design optimization of the FPGA platform based on the total calculation amount and the total read amount, further comprising: According to the number of times the data to be processed in each data category repeatedly participates in a single operation, set the read priority level of each data category from the off-chip storage of the FPGA platform to the on-chip storage; The greater the number of repetitions, the higher the read priority level. The method according to claim 1, wherein the algorithm to be executed includes at least matrix or vector multiplication and/or addition operations. An FPGA platform, characterized in that the FPGA platform includes a memory and a processor, the memory is coupled to the processor, the memory is used for storing program data, and the processor is used for executing the program data, To achieve the method according to any one of claims 1-9. A computer storage medium for storing a computer program, wherein the computer program implements the method according to any one of claims 1-9 when the computer program is executed by a processor.

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