WO2021087533A2

WO2021087533A2 - Apparatus and method of configurable crest factor reduction

Info

Publication number: WO2021087533A2
Application number: PCT/US2021/021397
Authority: WO
Inventors: Huei Yuan Shih
Original assignee: Zeku, Inc.
Priority date: 2020-03-24
Filing date: 2021-03-08
Publication date: 2021-05-06
Also published as: WO2021087533A3; CN115244846A

Abstract

According to one aspect of the present disclosure, a baseband chip is disclosed. The baseband chip may include a multi-carrier peak detection circuit configured to identify a peak amplitude of a combined signal that includes a first signal associated with a first component carrier (CC) and a second signal associated with a second CC. The multi-carrier peak detection circuit may operate at a first sampling rate that is a function of carrier aggregation (CA) bandwidth. The baseband chip may also include at least one crest factor reduction (CFR) circuit configured to reduce, based at least in part on the peak amplitude identified for the combined signal, a first crest factor associated with the first signal and a second crest factor associated with the second signal. The at least one CFR circuit operating at a second sampling rate that is a function of CC bandwidth.

Description

APPARATUS AND METHOD OF CONFIGURABLE CREST FACTOR

REDUCTION

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is related to and claims the benefit and priority of U.S. Provisional Patent Application No. 62/993,853 filed March 24, 2020, the entirety of which is hereby incorporated herein by reference.

BACKGROUND

[0002] Embodiments of the present disclosure relate to apparatus and method for wireless communication. [0003] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various mechanisms for signal detection, e.g., such as multiple-input multiple-output (MIMO) detection.

SUMMARY

[0004] Embodiments of apparatus and method for crest factor reduction are disclosed herein.

[0005] According to one aspect of the present disclosure, a baseband chip is disclosed. The baseband chip may include a multi-carrier peak detection circuit configured to identify a peak amplitude of a combined signal that includes a first signal associated with a first component carrier

(CC) and a second signal associated with a second CC. The multi-carrier peak detection circuit may operate at a first sampling rate that is a function of carrier aggregation (CA) bandwidth. The baseband chip may also include at least one crest factor reduction (CFR) circuit configured to reduce, based at least in part on the peak amplitude identified for the combined signal, a first crest factor associated with the first signal and a second crest factor associated with the second signal.

The at least one CFR circuit operating at a second sampling rate that is a function of CC bandwidth.

[0006] According to another aspect of the present disclosure, an apparatus is disclosed. The apparatus may include a baseband chip. The baseband chip may include a multi-carrier peak detection circuit configured to identify a peak amplitude of a combined signal that includes a first signal associated with a first CC and a second signal associated with a second CC. The multicarrier peak detection circuit may operate at a first sampling rate that is a function of CA bandwidth. The baseband chip may also include at least one CFR circuit configured to reduce, based at least in part on the peak amplitude identified for the combined signal, a first crest factor associated with the first signal and a second crest factor associated with the second signal. The at least one CFR circuit may operate at a second sampling rate that is a function of CC bandwidth. The apparatus may further include at least one antenna configured to transmit a transmit signal after crest factor reduction. The transmit signal may be transmitted using CA. [0007] According to yet another aspect of the present disclosure, a multi-carrier peak detection circuit is disclosed. The multi-carrier peak detection circuit may include a first interpolation block configured to interpolate a first signal associated with a first CC by a first amount. The multi-carrier peak detection circuit may also include a second interpolation block configured to interpolate a second signal associated with a second CC by a second amount. The multi-carrier peak detection circuit may further include an adder configured to combine the interpolated first signal and the interpolated second signal to generate a combined signal. The multi-carrier peak detection circuit may also include an envelope detection circuit configured to identify a peak amplitude associated with the combined signal.

[0008] According to still another aspect of the present disclosure, a CFR circuit configured to operate in a first sample rate domain of a baseband chip is disclosed. The CFR circuit may include a window function block configured to receive a clipping function from a multi-rate peak detection circuit that operates in a second sample rate domain of the baseband chip. The window function block may also include a window signal block configured to generate a windowing signal based at least in part on the first clipping function. The CFR circuit may further include a delay pipeline configured to delay a source signal by a predetermined amount. The CFR circuit may further include a multiplier configured to generate an output signal by combining the delayed source signal and the windowing signal, where the output signal has a reduced crest factor as compared to the source signal, and a first sample rate associated with the first sample rate domain is slower than a second sample rate associated with the second sample rate domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0010] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0011] FIG.2 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure. [0012] FIG. 3A illustrates an expanded view of the baseband chip depicted in FIG. 2, according to some embodiments of the present disclosure.

[0013] FIG. 3B illustrates an expanded view of the multi-carrier peak detection circuit depicted in FIG. 3A, according to some embodiments of the present disclosure.

[0014] FIG. 3C illustrates an expanded view of a multi-rate CFR circuit depicted in FIG. 3A, according to some embodiments of the present disclosure.

[0015] FIG. 4A illustrates a flow chart of a first exemplary method of multi-carrier CFR, according to some embodiments of the present disclosure.

[0016] FIG.4B illustrates a flow chart of a second exemplary method of multi-carrier CFR, according to some embodiments of the present disclosure. [0017] FIG. 5 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0018] FIG. 6 illustrates a block diagram of a prior multi-rate CFR circuit.

[0019] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0020] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. [0021] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. [0022] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0023] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0024] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0025] In a communication system, the crest factor of a signal may represent a ratio of peak values to the effective value of the signal. In some cases, the crest factor may be calculated by dividing the peak amplitude of a signal by the root mean square of the signal. Therefore, the crest factor may indicate the peak-to-average power ratio (PAPR) of the signal. A signal with a high crest factor may distort the linearity of a radio frequency power amplifier (RFPA) in the transmitter, thereby causing harmonic leakage of the transmit signal to an adjacent channel when carrier aggregation (CA) is used. To reduce the crest factor, and therefore the harmonic leakage, various conventional techniques have been proposed that reduce the PAPR and improve the adjacent channel leakage ratio (ACLR) of such a device. Examples of these conventional techniques include, e.g., implementing a hard-clipping algorithm, a peak cancellation algorithm, and/or a peak window algorithm to reduce the crest factor of a transmit signal prior to transmission. However, each of these conventional techniques have significant drawbacks as described below.

[0026] Hard-clipping, for example, suffers from poor peak reduction performance. Moreover, a large number of filter banks are required to remove the adjacent channel leakage caused by signals transmitted using different bandwidths. As such, baseband chips that use this hard-clipping technique use a significant amount of power and occupy a significant silicon area to maintain die filter banks.

[0027] Conventional peak detection techniques use an undesirable amount of lime, power, and silicon area. Multiple iterations of this algorithm are performed to achieve optimal peak reduction performance for different signal configurations, but at the cost of utilizing large memory banks to store the parameters and calibration time. Moreover, conventional peak detection uses a single sample rate design which requires a longer filter length and operating at the highest sample rate domain, which requires an undesirable amount of power and silicon area. [0028] On die other hand, die peak window algorithm uses a smaller silicon area than the aforementioned techniques due to the fixed filter parameters associated with processing symmetric window sequences. Moreover, the peak window algorithm can use a single filter (rather than the multiple filters used by the peak detection algorithm) since it operates with an envelope channel. However, the performance of this single sample rate algorithm (also referred to as a “single-rate algorithm" ) is limited when reducing the crest factors of signals transmitted using CA and using component carriers of different bandwidths, as described below in connection with FIG. 6. [0029] FIG. 6 illustrates a block diagram of a prior multi-rate CFR circuit 600. Multi-rate CFR circuit 600 includes, e.g., a first interpolation block 605a associated with a first CC (CC1), a second interpolation block 605b associated with a second CC (CC2), a first frequency shifter 607a, a second frequency shifter 607b, a first delay register 61 la, a second delay register 61 lb, a peak detector 609, a first down sampling block 613a, a second down sampling block 613b, a first window tap 615a, a second window tap 615b, a third interpolator 617a, a fourth interpolator 617b, a first window signal generator 619a, a second window signal generator 619b, a first multiplier 621a, a second multiplier 621b, and an adder 623.

[0030] The prior multi-rate CFR circuit 600 of FIG. 6 may be configured to perform CFR for a first signal 601 associated with a first CC and a second signal 603 associated with a second CC prior to combining the first signal 601 and the second signal 603 into a single transmit signal 625 for transmission via CA. More, specifically, the multi-rate CFR circuit 600 includes a plurality of functional blocks (e.g., 605a, 605b, 607a, 607b, 609, 611a, 611b, 613a, 613b, 615a, 615b, 617a, 617b, 619a, 619b, 621a, 621b, 623) each configured to perform one or more operations that when performed together reduce the crest factor of a first signal 601 of a first CC (CC1) and a second signal 603 associated with a second CC (CC2) prior to combining them into a transmit signal 625 for transmission via CA.

[0031] As illustrated in FIG. 6, the multi-rate CFR circuit 600 includes a first set of functional blocks 605a, 605b, 615a, 615b located in a first sample rate domain 602 and a second set of functional blocks 607a, 607b, 609, 611a, 611b, 613a, 613b, 617a, 617b, 619a, 619b, 621a, 621b, 623 located in a second sample rate domain 604. The first set of functional blocks 605a,

605b, 615a, 615b operate with respective sampling rates of, e.g., 7.68MHz, 30.72MHz, 15.36MHz, and 30.44MHz. The second set of functional blocks 607a, 607b, 609, 61 la, 61 lb, 613a, 613b, 617a, 617b, 619a, 619b, 621a, 621b, 623 operate with a sampling rate of, e.g., 122.88MHz.

[0032] More specifically, the first sample rate domain 602 includes a first interpolation block 605a configured to interpolate the first signal 601 by a first amount (e.g., up-sample by sixteen) and a second interpolation block 605b configured to interpolate the second signal 603 by a second amount (e.g., up-sample by four). The first and second interpolation blocks 605a, 605b operate at low sampling rates (e.g., 7.68MHz and 30.72MHz, respectively) as compared to the functional blocks in the second sample rate domain 604, which operate at 122.88MHz. Hence, the first and second interpolation blocks 605a, 605b (located in the first sample, rate domain 602) use a relatively small amount of power compared to the functional blocks in the second sample rate domain 604.

[0033] As illustrated in FIG. 6, delay registers 611a, 611b and multipliers 621a, 621b, both of which use an undesirable amount of power to begin with, are located in the second sample rate domain 604 to increase the frequency of the multi-carrier CA signal, further increasing the power consumed by these blocks. High sample rate multipliers consume even more power than low sample rate multipliers, and the delay registers 61 la, 61 lb are not configurable for different signal bandwidth. Moreover, delay registers 611a, 611b require an undesirable amount of silicon area and power.

[0034] Consequently, each of these conventional approaches to CFR have significant drawbacks in terms of silicon footprint and power consumption. Particularly, when used in a broadband communication system. Thus, there is an unmet need for a CFR circuit that is configurable for different signal bandwidths and consumes less power, while at the same time using fewer silicon resources.

[0035] To minimize the silicon footprint and enhance peak reduction performance, the present disclosure provides CFR circuits that operate with a sampling rate that is a function of CC bandwidth, thereby limiting the amount of power consumed for CCs of narrower bandwidths. Moreover, the multipliers for the peak reduction and the delay blocks are moved with CFR circuits to the lower sample rate domain. This arrangement (illustrated in FIG. 3A) achieves an increase in peak reduction performance while using a smaller silicon area, while at the same time being configurable for different combinations of CCs used in CA. Additional details of the present approach to CFR are provided below in connection with FIGs. 1-5.

[0036] FIG. 1 illustrates an exemplary wireless network 100, in which certain aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a user equipment (UE) 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Intemet-of-Things (IoT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0037] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0038] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0039] Core network element 106 may connect with a large network, such as the Internet 108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node.

[0040] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0041] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 500 in FIG. 5. Node 500 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 500 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 5, node 500 may include a processor 502, a memory 504, and a transceiver 506. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 500 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 500 may be implemented as a blade in a server system when node 500 is configured as core network element 106. Other implementations are also possible.

[0042] Transceiver 506 may include any suitable device for sending and/or receiving data. Node 500 may include one or more transceivers, although only one transceiver 506 is shown for simplicity of illustration. An antenna 508 is shown as a possible communication mechanism for node 500. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 500 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0043] As shown in FIG. 5, node 500 may include processor 502. Although only one processor is shown, it is understood that multiple processors can be included. Processor 502 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 502 may be a hardware device having one or more processing cores. Processor 502 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0044] As shown in FIG. 5, node 500 may also include memory 504. Although only one memory is shown, it is understood that multiple memories can be included. Memory 504 can broadly include both memory and storage. For example, memory 504 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 502. Broadly, memory 504 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium. [0045] Processor 502, memory 504, and transceiver 506 may be implemented in various forms in node 500 for performing wireless communication functions. In some embodiments, processor 502, memory 504, and transceiver 506 of node 500 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 502 and memory 504 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 502 and memory 504 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can mn a real-time operating system (RTOS). In still another example, processor 502 and transceiver 506 (and memory 504 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 508. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication. [0046] Referring back to FIG. 1, in some embodiments, any suitable node of wireless network 100 (e.g., user equipment 102 or access node 104) in transmitting signals to another node, for example, from user equipment 102 to access node 104 via, or vice versa, may perform harmonic modeling without interpolation to estimate harmonic interference that is then subtracted from an receiver (RX) signal, as described below in detail. As a result, compared with known solutions in which modeling via complex polynomial(s) and/or interpolation, the accuracy of harmonic interference estimation/cancellation may be improved while reducing the computational complexity as well as the power consumption.

[0047] FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip 202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. Apparatus 200 may be an example of any suitable node of wireless network 100 in FIG. 1, such as user equipment 102 or access node 104. As shown in FIG.2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 502 and memory 504, and RF chip 204 is implemented by processor 502, memory 504, and transceiver 506, as described above with respect to FIG. 5. Besides the on-chip memory (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 202, 204, or 206, apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus. Although baseband chip 202 is illustrated as a standalone SoC in FIG.2, it is understood that in one example, baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above.

[0048] In the uplink, host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase pre- shared key (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 202 may send the modulated signal to RF chip 204. RF chip 204, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, up-conversion, or sample-rate conversion. Antenna 210 (e.g., an antenna array) may transmit the

RF signals provided by the transmitter of RF chip 204.

[0049] In the downlink, antenna 210 may receive RF signals and pass the RF signals to the receiver (Rx) of RF chip 204. RF chip 204 may perform any suitable front-end RF functions, such as filtering, down-conversion, or sample-rate conversion, and convert the RF signals into low- frequency digital signals (baseband signals) that can be processed by baseband chip 202. In the downlink, baseband chip 202 may demodulate and decode the baseband signals to extract raw data that can be processed by host chip 206. Baseband chip 202 may perform additional functions, such as error checking, de-mapping, channel estimation, descrambling, etc. The raw data provided by baseband chip 202 may be sent to host chip 206 directly or stored in external memory 208. [0050] In certain implementations, baseband chip 202 may perform operations associated with CFR described below, e.g., in connection with FIGs. 3-5. The operations may be performed by one or more functional blocks and/or circuits of the baseband chip 202. For example, although not illustrated in FIG. 2, the baseband chip 202 may include a multi-carrier peak detection circuit configured to identify a peak amplitude of a combined signal that includes a first signal associated with a first CC and a second signal associated with a second CC. The multi-carrier peak detection circuit may operate at a first sampling rate that is a function of CA bandwidth. The baseband chip may also include at least one CFR circuit (also referred to as a CFR core”) configured to reduce, based at least in part on the peak amplitude identified for the combined signal, a first crest factor associated with the first signal and a second crest factor associated with the second signal. The at least one CFR circuit of the baseband chip 202 may operate at a second sampling rate that is a function of CC bandwidth. As compared with known solutions in which the CFR circuit, the delay block, and multiplier operate in a high sampling rate domain, baseband chip 202 may perform CFR using a significantly reduced amount of power and with a reduced silicon footprint as compared to those conventional approaches discussed above. [0051] FIG. 3A illustrates a block diagram of an expanded view of baseband chip 202 depicted FIG. 2, according to some embodiments of the present disclosure. FIG. 3B illustrates a detailed view of the multi-rate peak detection circuit 305 of FIG. 3A, according to some embodiments of the present disclosure. FIG. 3C illustrates a detailed view of the first CFR circuit 309a of FIG. 3A, according to some embodiments of the present disclosure. FIGs. 3A-3C will be described together.

[0052] Referring to FIG. 3A, baseband chip 202 of the present disclosure may include a plurality of functional blocks configured to perform multi-rate CFR. For example, the plurality of functional blocks includes a multi-rate peak detection circuit 305, a first interpolator 307a, a second interpolator 307b, a first CFR circuit 309a, a second CFR circuit 309b, a third interpolator 31 la, a fourth interpolator 311b, a first frequency shifter 313a, a second frequency shifter 313b, and an adder 315b, just to name a few. As depicted in FIG. 3 A, each of the functional blocks operates with a particular sampling rate in a sampling rate domain. More specifically, any functional block and/or circuit operating with a sample rate less than the highest sampling rate in FIG. 3A (122.88MHz) may be referred to as operating in a first sampling rate domain. On the other hand, the functional blocks operating with a sample rate less than 122.88MHz in FIG.3A may be referred to as operating in a second sampling rate domain.

[0053] More specifically, the functional blocks that operate in the first sample rate domain of baseband chip 202 include, e.g., first interpolator 307a, second interpolator 307b, first CFR circuit 309a, second CFR circuit 309b, third interpolator 311a, and fourth interpolator 311b. The set of functional blocks that operate in the second sample rate domain of baseband chip 202 include, e.g., multi-rate peak detection circuit 305, first frequency shifter 313a, second frequency shifter 313b, and adder 315b. Moreover, the sample rate of the first CFR circuit 309a and second

CFR circuit 309b are configurable based on the bandwidth of the associated CC. [0054] In the example illustrated in FIG. 3A, first CFR circuit 309a may be associated a first component carrier (CC1) and operates at a sampling rate of 15.36MHz, and second CFR circuit 309b is associated with a second component carrier (CC2) and operates at a sampling rate of 61.44MHz. These sample rates may be determined a priori using, for example, a simulation. Moreover, baseband chip 202 includes a first signal path along the top portion of the FIG. 3A that is used to perform CFR for a first signal 301 of a first component carrier (CC1) and a second signal path along the bottom of the FIG. 3A that is used to perform CFR for a second signal 303 of a second CC (CC2). In the example illustrated in FIGs. 3A-3C, the bandwidth of CC1 is 5MHz, and the bandwidth of CC2 is 20MHz. However, CC bandwidths and/or sampling rates other than those depicted in FIGs. 3A-3C may be used without departing from the scope of the present disclosure.

[0055] Referring to FIG. 3B, first signal 301 and second signal 303 are both inputted into multi-rate peak detection circuit 305. Multi-rate peak detection circuit 305 may include a first interpolator 319a configured to interpolate first signal 301 by a first amount (e.g., a factor of sixteen) and a second interpolator 319b configured to interpolate second signal 303 by a second amount (e.g., four). The interpolated first signal 301 may be frequency shifted by a first frequency shifter 321a, and the interpolated second signal 303 may be frequency shifted by a second frequency shifter 321b. Frequency shifting may be performed to shift the center frequency of a CC for the purposes of CA. After frequency shifting, first signal 301 and second signal 303 may be combined by adder 323 (e.g., CA of first signal 301 and second signal 303). The combined signal may be input into envelope detection block 325, which may be configured to identify a peak amplitude of the combined signal. [0056] First clipping function block 327a receives the peak amplitude level of the combined signal and a predetermined CC1 clipping level to generate a first clipping function (also referred to as a “clipping function”) for CC1. Second clipping function block 327b receives the peak amplitude level of the combined signal and a predetermined CC2 clipping level to generate a clipping function for CC2. In some cases, the predetermined clipping level represents a predetermined peak value for the transmit signal 317. In some cases, the first clipping function may represent a scaling function, which may scale down the components in the first signal 301 that are above the clipping level. The second clipping function may represent a scaling function, which may scale down the components in the second signal 303 that are above the clipping level.

[0057] First down sampling block 329a may be configured to down sample the first clipping function associated with CC1 by a first amount (e.g., a factor of eight), and second sampling block 329b may be configured to down sample the second clipping function associated with the CC2 by a second amount (e.g., a factor of two). After down sampling, first clipping function 331a and second clipping function 331b may be sent to the first CFR circuit 309a and second CFR circuit 309b, respectively. [0058] Referring to FIG. 3C, first clipping function 331a may be input into window function block 335. Window function block 335 may receive the first clipping function and generate a windowing signal based on the first clipping function. In some cases, window function block 335 may be implemented using a finite impulse response (FIR) filter. The FIR filter may include N window function units.

[0059] Referring to FIGs. 3A and 3C, first signal 301 may be interpolated by first interpolator 307a by a first amount (e.g., a factor of two) prior to being input into a delay block 333 of first CFR circuit 309a. First signal 301 may be passed through delay block 333, which includes one or more delay registers, prior to being input into multiplier 337. Multiplier 337 may multiply delayed first signal 301 with a windowing signal to generate first output signal 339a. Output signal 339a may have a reduced crest factor compared to first signal 301. Second CFR circuit 309b may perform the same or similar functions to generate a second output signal 339b that has a reduced crest factor as compared to second signal 303.

[0060] Referring to FIG. 3A, first output signal 339a may be interpolated by third interpolator 311a and second output signal may be interpolated by fourth interpolator 311b. After the output signals 339a, 339b have been interpolated, adder 315b may generate a transmit signal 317 by combining the output signal 339a, 339b using CA. Transmit signal 317 may have a reduced crest factor as compared to first signal 301 and second signal 303. As compared with known solutions in which the CFR circuit, the delay block, and multiplier operate in a high sampling rate domain, baseband chip 202 may perform CFR using a significantly reduced amount of power and with a reduced silicon footprint as compared to those conventional approaches discussed above.

[0061] FIG. 4A illustrates a flow chart of a first exemplary method 400 for wireless communication, according to some embodiments of the present disclosure. Examples of the apparatus that can perform operations of method 400 include, for example, apparatus 200, baseband chip 202, multi-rate peak detection circuit 305 operating in a first sample rate domain (e.g., 122.88MHz), or node 500 or any other suitable apparatus disclosed herein. It is understood that the operations shown in method 400 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 4A. [0062] Referring to FIG. 4A, at 402, the multi-rate peak detection circuit may interpolate a first signal associated with a first CC by a first amount. For example, referring to FIG. 3B, multirate peak detection circuit 305 may include a first interpolator 319a configured to interpolate first signal 301 by a first amount (e.g., a factor of sixteen). [0063] At 404, the multi-rate peak detection circuit may interpolate a second signal associated with a second CC by a second amount. For example, referring to FIG. 3B, the multirate peak detection circuit may interpolate second signal 303 by a second amount (e.g., four).

[0064] At 406, the multi-rate peak detection circuit may combine the interpolated first signal and the interpolated second signal to generate a combined signal. For example, referring to FIG. 3B, the multi-rate peak detection circuit may include an adder 323 configured to combine the interpolated first signal and the interpolated second signal to generate a combined signal. In certain implementations, the interpolated first signal and second signal may be frequency shifted prior to being combined. [0065] At 408, the multi-rate peak detection circuit may identify a peak amplitude associated with the combined signal. For example, referring to FIG. 3B, the multi-rate peak detection circuit may include an envelope detection circuit configured to identify the peak amplitude of the combined signal.

[0066] At 410, the multi-rate peak detection circuit may generate a first clipping function for the first CC to reduce the peak amplitude of the combined signal based at least in part on a first predetermined clipping level associated with the first CC. For example, referring to FIG. 3B, the multi-rate peak detection circuit may include a first clipping function block 327a configured to receive the peak amplitude level of the combined signal and a predetermined CC1 clipping level to generate a first clipping function (also referred to as a “clipping function”) for CC1. In some cases, the predetermined clipping level represents a predetermined peak value for the transmit signal 317. In some cases, the clipping function may represent a scaling function, which may scale down the components in the first signal 301 that are above the clipping level.

[0067] At 412, the multi-rate peak detection circuit may generate a second clipping function for the second CC to reduce the peak amplitude of the combined signal based at least in part on a second predetermined clipping level associated with the second CC. For example, referring to FIG. 3B, the multi-rate peak detection circuit may include a second clipping function block 327b configured to receive the peak amplitude level of the combined signal and a predetermined CC2 clipping level to generate a clipping function for CC2. In some cases, the predetermined clipping level represents a predetermined peak value for the transmit signal 317. In some cases, the second clipping function may represent a scaling function, which may scale down the components in the second signal 303 that are above the clipping level. [0068] At 414, the multi-rate peak detection circuit may down sample the first clipping function associated with the first CC. For example, referring to FIG. 3B, the multi-rate peak detection circuit 305 may include first down sampling block 329a configured to down sample the first clipping function associated with CC1 by a first amount (e.g., a factor of eight). [0069] At 416, the multi-rate peak detection circuit may down sample the second clipping function associated with the second CC. For example, referring to FIG. 3B, multi-rate peak detection circuit 305 may include a second sampling block 329b configured to down sample the second clipping function associated with the CC2 by a second amount (e.g., a factor of two). [0070] At 418, the multi-rate peak detection circuit (which operates in first sample rate domain) may send the first clipping function to a first CFR that operates in a second sample rate domain that is slower than the first sample rate domain. For example, referring to FIGs. 3B and 3C, after down sampling, first clipping function 331a and second clipping function 331b may be sent to the first CFR circuit 309a and second CFR circuit 309b, respectively. [0071] FIG. 4B illustrates a flow chart of a second exemplary method 401 for wireless communication, according to some embodiments of the present disclosure. Examples of the apparatus that can perform operations of method 401 include, for example, apparatus 200, baseband chip 202, first CFR circuit 309a operating in a first sample rate domain (e.g., 15.36MHz), second CFR circuit 309b operating in a first sample rate domain (e.g., 61.44MHz), or node 500 or any other suitable apparatus disclosed herein. It is understood that the operations shown in method 400 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 4B.

[0072] Referring to FIG. 4B, at 422, the CFR circuit may receive a clipping function from a multi-rate peak detection circuit that operates in a second sample rate domain (e.g., 122.88MHz) of the baseband chip. For example, referring to FIG. 3C, first CFR circuit 309a may include a window function block 335 configured to receive first clipping function 331a from first clipping function block 327a.

[0073] At 424, the CFR circuit may generate a windowing signal based at least in part on the first clipping function. For example, referring to FIG. 3C, window function block 335 may receive the first clipping function and generate a windowing signal based on the first clipping function. In some cases, window function block 335 may be implemented using a finite impulse response (FIR) filter. The FIR filter may include N window function units. [0074] At 426, the CFR circuit may delay a source signal by a predetermined amount. For example, referring to FIG. 3B, first CFR circuit 309a may include a delay block 333 that may include one or more delay registers through which first signal 301 may be passed through delay block 333, which includes, prior to being input into multiplier 337. [0075] At 428, the CFR circuit may generate an output signal with a reduced crest factor as compared to the source signal by combining the delayed source signal and the windowing signal. For example, referring to FIG. 3C, first CFR circuit 309a may include a multiplier configured to multiply delayed first signal 301 with a windowing signal to generate first output signal 339a. Output signal 339a may have a reduced crest factor compared to first signal 301. [0076] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 500 in FIG. 5. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0077] According to one aspect of the present disclosure, a baseband chip is disclosed. The baseband chip may include a multi-carrier peak detection circuit configured to identify a peak amplitude of a combined signal that includes a first signal associated with a first component carrier

(CC) and a second signal associated with a second CC. The multi-carrier peak detection circuit may operate at a first sampling rate that is a function of carrier aggregation (CA) bandwidth. The baseband chip may also include at least one crest factor reduction (CFR) circuit configured to reduce, based at least in part on the peak amplitude identified for the combined signal, a first crest factor associated with the first signal and a second crest factor associated with the second signal. The at least one CFR circuit operating at a second sampling rate that is a function of CC bandwidth. [0078] The multi-rate peak detection circuit includes a first interpolation block configured to interpolate the first signal associated with the first CC by a first amount. The multi-rate peak detection circuit further includes a second interpolation block configured to interpolate the second signal associated with the second CC by a second amount The multi-rate peak detection circuit also includes an adder configured to combine the interpolated first signal and the interpolated second signal to generate the combined signal. The multi-rate peak detection circuit also includes an envelope detection circuit configured to identify the peak amplitude associated with the combined signal.

[0079] The multi-rate peak detection circuit may also include a first clipping function block configured to generate a first clipping function for the first CC to reduce the peak amplitude of the combined signal based at least in part on a first predetermined clipping level associated with the first CC. The multi-rate peak detection circuit may also include a second clipping function block configured to generate a second clipping function for the second CC to reduce the peak amplitude of the combined signal based at least in part on a second predetermined clipping level associated with the second CC.

[0080] The multi-rate peak detection circuit may also include a first down sampling block configured to down sample the first clipping function associated with the first CC. The multi-rate peak detection circuit may also include a second down sampling block configured to down sample the second clipping function associated with the second CC. [0081] The at least one CFR circuit may include a first CFR circuit associated with the first

CC and a second CFR circuit associated with the second CC.

[0082] The first CFR circuit may include a first window function block configured to receive the first clipping function from the first down sampling block. The first window function block may be further configured to generate a windowing signal based at least in part on the first clipping function. The first CFR circuit may further include a first delay pipeline configured to delay the first signal by a predetermined amount. The first CFR circuit may further include a multiplier configured to generate a first output signal by combining the delayed first signal and the windowing signal, the first output signal having a reduced crest factor as compared to the first signal. [0083] The second CFR circuit may include a second window function block configured to receive the second clipping function from the second down sampling block. The second window function block may be further configured to generate a windowing signal based at least in part on the second clipping function. The second CFR circuit may include a second delay pipeline configured to delay the second signal by a predetermined amount. The second CFR circuit may include a multiplier configured to generate a second output signal by combining the second signal delayed by the predetermined amount and the windowing signal, the second output signal having a reduced crest factor compared to the second signal.

[0084] The baseband chip may further include a third interpolation block configured to interpolate the first output signal. The baseband chip may further include a fourth interpolation block configured to interpolate the second output signal. The baseband chip may further include a second adder configured to combine the first output signal and the second output signal to generate a transmit signal.

[0085] According to another aspect of the present disclosure, an apparatus is disclosed. The apparatus may include a baseband chip. The baseband chip may include a multi-carrier peak detection circuit configured to identify a peak amplitude of a combined signal that includes a first signal associated with a first CC and a second signal associated with a second CC. The multi- carrier peak detection circuit may operate at a first sampling rate that is a function of CA bandwidth. The baseband chip may also include at least one CFR circuit configured to reduce, based at least in part on the peak amplitude identified for the combined signal, a first crest factor associated with the first signal and a second crest factor associated with the second signal. The at least one CFR circuit may operate at a second sampling rate that is a function of CC bandwidth. The apparatus may further include at least one antenna configured to transmit a transmit signal after crest factor reduction. The transmit signal may be transmitted using CA.

[0086] The multi-rate peak detection circuit includes a first interpolation block configured to interpolate the first signal associated with the first CC by a first amount. The multi-rate peak detection circuit further includes a second interpolation block configured to interpolate the second signal associated with the second CC by a second amount. The multi-rate peak detection circuit also includes an adder configured to combine the interpolated first signal and the interpolated second signal to generate the combined signal. The multi-rate peak detection circuit also includes an envelope detection circuit configured to identify the peak amplitude associated with the combined signal. [0087] The multi-rate peak detection circuit may also include a first clipping function block configured to generate a first clipping function for the first CC to reduce the peak amplitude of the combined signal based at least in part on a first predetermined clipping level associated with the first CC. The multi-rate peak detection circuit may also include a second clipping function block configured to generate a second clipping function for the second CC to reduce the peak amplitude of the combined signal based at least in part on a second predetermined clipping level associated with the second CC. [0088] The multi-rate peak detection circuit may also include a first down sampling block configured to down sample the first clipping function associated with the first CC. The multi-rate peak detection circuit may also include a second down sampling block configured to down sample the second clipping function associated with the second CC.

[0089] The at least one CFR circuit may include a first CFR circuit associated with the first CC and a second CFR circuit associated with the second CC.

[0090] The first CFR circuit may include a first window function block configured to receive the first clipping function from the first down sampling block. The first window function block may be further configured to generate a windowing signal based at least in part on the first clipping function. The first CFR circuit may further include a first delay pipeline configured to delay the first signal by a predetermined amount. The first CFR circuit may further include a multiplier configured to generate a first output signal by combining the delayed first signal and the windowing signal, the first output signal having a reduced crest factor as compared to the first signal.

[0091] The second CFR circuit may include a second window function block configured to receive the second clipping function from the second down sampling block. The second window function block may be further configured to generate a windowing signal based at least in part on the second clipping function. The second CFR circuit may include a second delay pipeline configured to delay the second signal by a predetermined amount. The second CFR circuit may include a multiplier configured to generate a second output signal by combining the second signal delayed by the predetermined amount and the windowing signal, the second output signal having a reduced crest factor compared to the second signal.

[0092] The baseband chip may further include a third interpolation block configured to interpolate the first output signal. The baseband chip may further include a fourth interpolation block configured to interpolate the second output signal. The baseband chip may further include a second adder configured to combine the first output signal and the second output signal to generate a transmit signal. [0093] According to yet another aspect of the present disclosure, a multi-carrier peak detection circuit is disclosed. The multi-carrier peak detection circuit may include a first interpolation block configured to interpolate a first signal associated with a first CC by a first amount. The multi-carrier peak detection circuit may also include a second interpolation block configured to interpolate a second signal associated with a second CC by a second amount. The multi-carrier peak detection circuit may further include an adder configured to combine the interpolated first signal and the interpolated second signal to generate a combined signal. The multi-carrier peak detection circuit may also include an envelope detection circuit configured to identify a peak amplitude associated with the combined signal. [0094] The multi-carrier peak detection circuit may also include a first clipping function block configured to generate a first clipping function for the first CC to reduce the peak amplitude of the combined signal based at least in part on a first predetermined clipping level associated with the first CC. The multi-carrier peak detection circuit may also include a second clipping function block configured to generate a second clipping function for the second CC to reduce the peak amplitude of the combined signal based at least in part on a second predetermined clipping level associated with the second CC.

[0095] The multi-carrier peak detection circuit may also include a first down sampling block configured to down sample the first clipping function associated with the first CC. The multi-carrier peak detection circuit may also include a second down sampling block configured to down sample the second clipping function associated with the second CC.

[0096] According to still another aspect of the present disclosure, a CFR circuit configured to operate in a first sample rate domain of a baseband chip is disclosed. The CFR circuit may include a window function block configured to receive a clipping function from a multi-rate peak detection circuit that operates in a second sample rate domain of the baseband chip. The window function block may also include a window signal block configured to generate a windowing signal based at least in part on the first clipping function. The CFR circuit may further include a delay pipeline configured to delay a source signal by a predetermined amount. The CFR circuit may further include a multiplier configured to generate an output signal by combining the delayed source signal and the windowing signal, where the output signal has a reduced crest factor as compared to the source signal, and a first sample rate associated with the first sample rate domain is slower than a second sample rate associated with the second sample rate domain. [0097] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. [0098] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. [0099] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0100] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0101] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A baseband chip, comprising: a multi-carrier peak detection circuit configured to identify a peak amplitude of a combined signal that includes a first signal associated with a first component carrier (CC) and a second signal associated with a second CC, the multi-carrier peak detection circuit operating at a first sampling rate that is a function of carrier aggregation (CA) bandwidth; and at least one crest factor reduction (CFR) circuit configured to reduce, based at least in part on the peak amplitude identified for the combined signal, a first crest factor associated with the first signal and a second crest factor associated with the second signal, the at least one CFR circuit operating at a second sampling rate that is a function of CC bandwidth.

2. The baseband chip of claim 1, wherein the multi-carrier peak detection circuit comprises: a first interpolation block configured to interpolate the first signal associated with the first CC by a first amount; a second interpolation block configured to interpolate the second signal associated with the second CC by a second amount; an adder configured to combine the interpolated first signal and the interpolated second signal to generate the combined signal; and an envelope detection circuit configured to identify the peak amplitude associated with the combined signal.

3. The baseband chip of claim 2, wherein the multi-carrier peak detection circuit further comprises: a first clipping function block configured to generate a first clipping function for the first CC to reduce the peak amplitude of the combined signal based at least in part on a first predetermined clipping level associated with the first CC; and a second clipping function block configured to generate a second clipping function for the second CC to reduce the peak amplitude of the combined signal based at least in part on a second predetermined clipping level associated with the second CC.

4. The baseband chip of claim 3, wherein the multi-carrier peak detection circuit further compnses: a first down sampling block configured to down sample the first clipping function associated with the first CC; and a second down sampling block configured to down sample the second clipping function associated with the second CC.

5. The baseband chip of claim 4, wherein the at least one CFR circuit comprises a first CFR circuit associated with the first CC and a second CFR circuit associated with the second CC.

6. The baseband chip of claim 5, wherein the first CFR circuit comprises: a first window function block configured to: receive the first clipping function from the first down sampling block; and generate a windowing signal based at least in part on the first clipping function; a first delay pipeline configured to delay the first signal by a predetermined amount; and a multiplier configured to generate a first output signal by combining the delayed first signal and the windowing signal, the first output signal having a reduced crest factor as compared to the first signal.

7. The baseband chip of claim 6, wherein the second CFR circuit comprises: a second window function block configured to: receive the second clipping function from the second down sampling block; and generate a windowing signal based at least in part on the second clipping function; a second delay pipeline configured to delay the second signal by a predetermined amount; and a multiplier configured to generate a second output signal by combining the second signal delayed by the predetermined amount and the windowing signal, the second output signal having a reduced crest factor compared to the second signal.

8. The baseband chip of claim 7, further comprising: a third interpolation block configured to interpolate the first output signal; a fourth interpolation block configured to interpolate the second output signal; and a second adder configured to combine the first output signal and the second output signal to generate a transmit signal.

9. An apparatus, comprising: a baseband chip comprising: a multi-carrier peak detection circuit configured to identify a peak amplitude of a combined signal that includes a first signal associated with a first component carrier (CC) and a second signal associated with a second CC, the multi-carrier peak detection circuit operating at a first sampling rate that is a function of carrier aggregation (CA) bandwidth; and at least one crest factor reduction (CFR) circuit configured to reduce, based at least in part on the peak amplitude identified for the combined signal, a first crest factor associated with the first signal and a second crest factor associated with the second signal, the at least one CFR circuit operating at a second sampling rate that is a function of CC bandwidth; and at least one antenna configured to transmit a transmit signal after crest factor reduction, the transmit signal being transmitted using CA.

10. The apparatus of claim 9, wherein the multi-carrier peak detection circuit comprises: a first interpolation block configured to interpolate the first signal associated with the first CC by a first amount; a second interpolation block configured to interpolate the second signal associated with the second CC by a second amount; an adder configured to combine the interpolated first signal and the interpolated second signal to generate the combined signal; and an envelope detection circuit configured to identify the peak amplitude associated with the combined signal.

11. The apparatus of claim 10, wherein the multi-carrier peak detection circuit further comprises: a first clipping fimction block configured to generate a first clipping function for the first CC to reduce the peak amplitude of the combined signal based at least in part on a first predetermined clipping level associated with the first CC; and a second clipping function block configured to generate a second clipping function for the second CC to reduce the peak amplitude of the combined signal based at least in part on a second predetermined clipping level associated with the second CC.

12. The apparatus of claim 11 , wherein the multi-carrier peak detection circuit further comprises: a first down sampling block configured to down sample the first clipping function associated with the first CC; and a second down sampling block configured to down sample the second clipping function associated with the second CC.

13. The apparatus of claim 12, wherein the at least one CFR circuit comprises a first CFR circuit associated with the first CC and a second CFR circuit associated with the second CC.

14. The apparatus of claim 13, wherein the first CFR circuit comprises: a first window fimction block configured to: receive the first clipping function from the first down sampling block; and generate a windowing signal based at least in part on the first clipping function; a first delay pipeline configured to delay the first signal by a predetermined amount; and a multiplier configured to generate a first output signal by combining the first signal delayed by the predetermined amount and the windowing signal, the first output signal having a reduced crest factor as compared to the first signal.

15. The apparatus of claim 14, wherein the second CFR circuit comprises: a second window function block configured to: receive the second clipping function from the second down sampling block; and generate a windowing signal based at least in part on the second clipping fimction; function; a second delay pipeline configured to delay the second signal by a predetermined amount; and a multiplier configured to generate a second output signal by combining the second signal delayed by the predetermined amount and the windowing signal, the second output signal having a reduced crest factor compared to the second signal.

16. The apparatus of claim 15, wherein the baseband chip further comprises: a third interpolation block configured to interpolate the first output signal; a fourth interpolation block configured to interpolate the second output signal; and a second adder configured to combine the first output signal and the second output signal to generate the transmit signal.

17. A multi-carrier peak detection circuit, comprising: a first interpolation block configured to interpolate a first signal associated with a first component carrier (CC) by a first amount; a second interpolation block configured to interpolate a second signal associated with a second CC by a second amount; an adder configured to combine the interpolated first signal and the interpolated second signal to generate a combined signal; and an envelope detection circuit configured to identify a peak amplitude associated with the combined signal.

18. The multi-carrier peak detection circuit of claim 17, further comprising: a first clipping function block configured to generate a first clipping function for the first CC to reduce the peak amplitude of the combined signal based at least in part on a first predetermined clipping level associated with the first CC; and a second clipping function block configured to generate a second clipping function for the second CC to reduce the peak amplitude of the combined signal based at least in part on a second predetermined clipping level associated with the second CC.

19. The multi-carrier peak detection circuit of claim 18, further comprising: a first down sampling block configured to down sample the first clipping function associated with the first CC; and a second down sampling block configured to down sample the second clipping function associated with the second CC.

20. A crest factor reduction (CFR) circuit configured to operate in a first sample rate domain of a baseband chip, the CFR circuit comprising: a window function block configured to: receive a clipping function from a multi-rate peak detection circuit that operates in a second sample rate domain of the baseband chip; and generate a windowing signal based at least in part on the clipping function; a delay pipeline configured to delay a source signal by a predetermined amount; and a multiplier configured to generate an output signal by combining the delayed source signal and the windowing signal, the output signal having a reduced crest factor as compared to the source signal, wherein a first sample rate associated with the first sample rate domain is slower than a second sample rate associated with the second sample rate domain.