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WO2021082119A1 - Low harmonic suppression method for four-quadrant converter device of electric locomotive - Google Patents

Low harmonic suppression method for four-quadrant converter device of electric locomotive Download PDF

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Publication number
WO2021082119A1
WO2021082119A1 PCT/CN2019/119876 CN2019119876W WO2021082119A1 WO 2021082119 A1 WO2021082119 A1 WO 2021082119A1 CN 2019119876 W CN2019119876 W CN 2019119876W WO 2021082119 A1 WO2021082119 A1 WO 2021082119A1
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harmonic
axis
quadrant
voltage
current
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PCT/CN2019/119876
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French (fr)
Chinese (zh)
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于森林
苏鹏程
王力
张巧娟
詹哲军
梁海刚
司军民
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中车永济电机有限公司
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from AC input or output

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  • the invention belongs to the field of control, and particularly relates to a control algorithm for current low-order harmonic suppression of a four-quadrant converter, in particular to a low-harmonic suppression method for a four-quadrant converter device of an electric locomotive.
  • Four-quadrant rectifiers have high power factor and can realize bidirectional flow of energy and are widely used in electric locomotives. Due to the low switching frequency of the four-quadrant rectifier, the AC side current usually has poor harmonic characteristics, which brings harmonic pollution to the power supply network, thereby affecting the power quality of the power supply network and the grid environment when other locomotives are running.
  • four-quadrant converters usually use a variety of methods to reduce the pollution caused by current harmonics.
  • the main circuit topology of the four-quadrant converters of different electric locomotives is different, and different main circuits have different harmonics. Wave suppression method.
  • a software filter can be used to perform multiple filtering methods.
  • the design of the software filter is closely related to the switching frequency, and the four-quadrant converter has a lower switching frequency, which makes the bandwidth of the designed filter narrower.
  • the narrow bandwidth filter will have the risk of divergence, which will cause problems in the control of the entire four-quadrant converter and affect the reliability of locomotive operation.
  • the introduction of the filter will cause the sampled signal to have a certain amplitude attenuation and phase delay, which will reduce the dynamic response performance of the four-quadrant converter.
  • the method of designing hardware filtering can also be used.
  • the hardware filtering is usually designed on the hardware board and has a dedicated hardware circuit design.
  • Hardware filtering has the advantage of corresponding speed, but the device is also susceptible to temperature and humidity, and the hardware design also increases the economic cost.
  • Multiple methods of current paralleling can also be used.
  • the multiplexing of current paralleling is usually double or quadruple, and its multiple harmonic suppression capability is mainly for higher harmonics, and for the 3rd, 5th, etc. Sub-harmonics do not have the ability to suppress harmonics.
  • the present invention provides a harmonic suppression method integrated into the four-quadrant control algorithm, which solves the problems of the low-order harmonics of the four-quadrant converter current affecting the control of the converter and the pollution of the power quality of the power grid. It solves the problem of using software filter to filter out the influence of low-order harmonics. It also solves the low calculation accuracy of the fundamental wave phase angle and low-order harmonic phase angle of the grid voltage signal, which results in the dynamic control of the four-quadrant. Performance and harmonic suppression have a certain impact. This method is mainly to add harmonic extraction and suppression functions to the control algorithm of the four-quadrant converter. It has high adaptability and flexibility, and can achieve the purpose of high precision harmonic suppression.
  • the present invention is realized by adopting the following technical scheme: a low harmonic suppression method for a four-quadrant converter device of an electric locomotive, including a four-quadrant control algorithm, a four-quadrant modulation algorithm and a harmonic suppression algorithm;
  • the harmonic suppression algorithm includes the following steps:
  • the input current of the four-quadrant converter is converted to the harmonic sub-d-axis current and the harmonic sub-q-axis current in the rotating coordinate system, and after filtering by a low-pass filter, the d-axis DC component and the q-axis DC component of the harmonic current are obtained Component, the angle required for the transformation of the rotating coordinate system is calculated through the combination of the network voltage synchronization pulse signal from the hardware board and the DSP high-speed interrupt counting;
  • the d-axis DC component and q-axis DC component of the obtained harmonic currents are used as feedback quantities, and the given quantities form a PI control closed loop.
  • the DC component of the harmonic current is adjusted to zero through the closed-loop control method, and the output is harmonic rotation.
  • the command voltage with harmonic suppression function is obtained, and the command voltage is sent to the four-quadrant pulse modulation module for modulation to obtain the PWM pulse, and the pulse is transmitted to the IGBT of the four-quadrant converter.
  • this method is a four-quadrant current low-order harmonic suppression method realized by using a software control algorithm alone. It uses a hardware architecture composed of a DSP+FPGA control chip and a signal conditioning hardware board.
  • the DSP chip completes the four-quadrant control algorithm, four Quadrant modulation algorithm and harmonic suppression algorithm
  • FPGA completes the data sampling required for four-quadrant rectification, host computer communication, pulse and dead zone settings, and the FPGA is equipped with overcurrent, overvoltage hardware protection and software protection to form a double protection; signal
  • the conditioning hardware board completes the conditioning of the four-quadrant input signal. After the signal conditioning is completed, the signal is transmitted to the FPGA for sampling, and the DSP reads the signal sampling value in the FPGA for control algorithm calculation.
  • the calculation process of the grid voltage phase angle is as follows: when the grid voltage signal changes from negative to positive zero-crossing point, the hardware conditioning circuit on the hardware board will generate a high level with rising edge synchronized with the grid-voltage zero-crossing point. Signal P; when the grid voltage signal is at the zero-crossing point from positive to negative, the hardware board outputs a low-level signal p′ with a falling edge synchronized with the zero-crossing point of the grid voltage; set MKHz high-speed interrupt in the DSP to complete the interrupt count Calculate the angle of the fundamental wave; the number of rising edges of the high-level signal P is counted by Cnt, and Cnt is counted by the increment and decrement method with the maximum value Q; the number of high-speed interrupts is counted by Cnt1 and Cnt2.
  • the harmonic suppression algorithm is to suppress the third and fifth harmonics.
  • the specific calculation process of the d-axis DC component and the q-axis DC component of the third and fifth harmonic currents is as follows:
  • the d-axis and q-axis DC components of the third harmonic As the amount of feedback, and the given amount with The PI control closed loop is formed, and the DC component of the third harmonic current is reduced by the closed loop control method. Adjusted to zero, the output is the d-axis and q-axis error voltage components u d3 , u q3 under the 3rd harmonic rotating coordinate;
  • the d-axis and q-axis DC components of the 5th harmonic As the amount of feedback, and the given amount with A PI control closed loop is formed, and the DC component of the 5th harmonic current is reduced by the closed loop control method. Adjusted to zero, the output is the d-axis and q-axis error voltage components u d5 , u q5 under the 5th harmonic rotation coordinate.
  • the specific calculation process of the harmonic d-axis voltage adjustment total and the harmonic q-axis voltage adjustment total is as follows: add u d3-1 and u d5-1 to form the harmonic d-axis voltage in the fundamental rotation coordinate adjusting the total amount of u 'd; u q3-1 with the sum u q5-1 harmonic constituting the q-axis fundamental voltage regulator total rotational coordinate u' q.
  • the four-quadrant control algorithm adopts id_iq-based dynamic decoupling control, and adopts a voltage and current double closed-loop control strategy;
  • the voltage loop control object is the bus voltage Udc to ensure that the actual value of the bus voltage is equal to the command value, and the actual voltage sampling value is trapped
  • the filter is filtered and compared with the command value.
  • the notch frequency of the notch filter is 100Hz, and the design frequency is twice the four-quadrant switching frequency; the current inner loop is mainly to control the current, and the command value id of the current inner loop is the voltage outer loop.
  • four-quadrant modulation algorithm adopts unipolar frequency multiplication modulation, its composition is flexible and changeable, and can be configured into multiple modes for high-order harmonics in four-quadrant current eliminate.
  • the overall control algorithm has the ability to suppress low-order harmonics and does not require additional hardware circuit design
  • Figure 1 shows the topological diagram of the four-quadrant main circuit.
  • Figure 2 is a schematic diagram of the four-quadrant control algorithm and harmonic suppression algorithm modules.
  • Figure 3 is the algorithm diagram of the harmonic current extraction module and the harmonic current module.
  • Figure 4 shows the timing matching diagram of the high-speed interrupt count Cnt1/Cnt2 when calculating the network voltage angle.
  • Figure 5 is the setting diagram of the rising edge pulse P count Cnt of the grid voltage angle calculation formula.
  • the switching frequency of the four-quadrant rectifier is usually only a few hundred hertz.
  • the current harmonic adopts the filter scheme, it is easy to be affected by the filter to the control performance of the four-quadrant rectifier, so the current harmonic suppression adopts the control closed-loop scheme.
  • the whole scheme is divided into four parts: four-quadrant control algorithm, four-quadrant modulation algorithm, main circuit topology and harmonic suppression algorithm.
  • the four-quadrant control algorithm uses id_iq-based dynamic decoupling control, and the four-quadrant modulation algorithm uses unipolar frequency multiplication modulation, which is flexible and changeable, and can be configured into multiple modes for the elimination of high-order harmonics in the four-quadrant current.
  • Harmonic suppression algorithm adopts PI controller-based closed-loop control of the direct current of the harmonic current, which is mainly composed of a harmonic current extraction module and a harmonic current suppression module.
  • the control hardware adopts the hardware architecture composed of DSP+FPGA control chip and signal conditioning hardware board.
  • the DSP chip completes the four-quadrant control algorithm, the four-quadrant modulation algorithm and the harmonic suppression algorithm, and the FPGA mainly completes the data required for the four-quadrant rectification.
  • the harmonic current extraction module is mainly to complete the extraction of the corresponding sub-harmonics in the four-quadrant current.
  • the main purpose is to complete the extraction of the 3rd and 5th harmonic currents to provide data for the harmonic current suppression module.
  • the acquisition of the 3rd harmonic current and the 5th harmonic current is obtained by transforming the four-quadrant input current through a rotating coordinate.
  • angles 3 ⁇ t and 5 ⁇ t required for the transformation of the rotating coordinate system are calculated through the network voltage synchronization pulse signal from the hardware board and the DSP interrupt count.
  • the four-quadrant input current i s can be obtained by sampling in the FPGA.
  • the hardware conditioning circuit on the hardware board will generate a high-level signal P with a rising edge that is synchronized with the grid-voltage zero-crossing point; the grid voltage signal is changing from positive to positive.
  • the hardware conditioning board outputs a low-level signal p′ with a falling edge synchronized with the zero-crossing point of the network voltage; MKHz high-speed interrupt is set in the DSP to complete the interrupt counting and fundamental wave angle calculation; pulse signal The number of rising edges of P is counted by Cnt, and Cnt is counted with the maximum value of Q.
  • the number of high-speed interrupts is counted by Cnt1 and Cnt2; when the rising edge of the network voltage synchronization pulse signal P is detected and Cnt is an odd number, the high-speed interrupt Count Cnt1 starts to increase, and Cnt2 is cleared when the low-level signal p′ at the falling edge is detected during the increase of Cnt1; when the next rising edge of the pulse signal P arrives, the high-speed interrupt counting Cnt1 count ends, and the Cnt1 count value is assigned to N for angle calculation ; When the Cnt count value is 0 or an even number, the interrupt count Cnt2 starts to increase, Cnt1 is cleared when the low-level signal p′ of the falling edge is detected during the increase of Cnt2; when the next rising edge of the pulse signal P arrives, the high-speed interrupt counting The count of Cnt2 ends, and the count value of Cnt2 is assigned to N for angle calculation.
  • the calculation formula of the fundamental angle ⁇ t is expressed as: In the
  • step 7 As the amount of feedback, and the given amount with The PI control closed loop is formed, and the DC component of the third harmonic current is reduced by the closed loop control method. Adjusted to zero, the output is the d-axis and q-axis error voltage components u d3 , u q3 under the 3rd harmonic rotation coordinate.
  • step 8 Combine what you got in step 8 As the amount of feedback, and the given amount with A PI control closed loop is formed, and the DC component of the 5th harmonic current is reduced by the closed loop control method. Adjusted to zero, the output is the d-axis and q-axis error voltage components u d5 , u q5 under the 5th harmonic rotation coordinate.
  • step 11 u d5-1 in step 11 and step 12 u d3-1 adding the d-axis voltage harmonic constituting the fundamental rotational coordinate adjustment amount u 'd; step 11 u q3-1 and in the step of adding 12 u q5-1 harmonic constituting the q-axis fundamental voltage regulator total rotating coordinate u 'q.
  • the u 'd d-axis into four quadrant control of the amount of adjustment of the fundamental algorithm calculates the grid voltage U s, outer loop regulator output voltage, current decoupling item as the item as a fundamental feedforward d the total amount of the adjustment shaft; after u 'q as a feed-forward term into the four-quadrant control the d-axis adjustment amount of the fundamental algorithm, calculates the q-axis fundamental current regulator output, the fundamental wave current item as a decoupling q The total adjustment of the shaft.
  • step 14 Convert the total adjustment value (DC value) of the d and q axis in step 14 to the AC value under the Cartesian coordinate system, which is the command voltage required to have the 3rd and 5th harmonic suppression function Send it to the pulse modulation module for pulse modulation to obtain the PWM pulse, which is sent to the IGBT of the four-quadrant converter.
  • the above-mentioned harmonic suppression scheme realizes the method of harmonic suppression in a four-quadrant rectifier.
  • the test results show that the AC side current using this method has better harmonic characteristics and achieves the expected purpose.

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Abstract

The present invention relates to the field of control, and in particular, to a control algorithm for current low-order harmonic suppression of a four-quadrant converter, specifically a low harmonic suppression method for a four-quadrant converter device of an electric locomotive. The method is a harmonic suppression method fused in a four-quadrant control algorithm; the problem that the current low-order harmonic of the four-quadrant converter influences the control of the converter and pollutes the power quality of a power grid is solved; the problem of influence caused by low-order harmonic filtering by adopting a software filter method is solved; and the problem of certain influence on four-quadrant control dynamic performance and harmonic suppression capability due to low calculation precision of a fundamental wave phase angle and a low-order harmonic phase angle of a power grid voltage signal is further solved. According to the method, harmonic extraction and suppression functions are mainly added to the four-quadrant converter control algorithm, the method has high adaptability and flexibility, and the purpose of high-precision harmonic suppression can be achieved.

Description

一种电力机车四象限变流装置低谐波抑制方法Low harmonic suppression method for four-quadrant converter device of electric locomotive 技术领域Technical field
本发明属于控制领域，尤其涉及一种四象限变流器的电流低次谐波抑制的控制算法，具体为一种电力机车四象限变流装置低谐波抑制方法。The invention belongs to the field of control, and particularly relates to a control algorithm for current low-order harmonic suppression of a four-quadrant converter, in particular to a low-harmonic suppression method for a four-quadrant converter device of an electric locomotive.
背景技术Background technique
四象限整流器具有高功率因数且能够实现能量的双向流动而在电力机车中广泛使用。因四象限整流器开关频率低，其交流侧电流通常具有较差的谐波特性，给供电网带来了谐波污染，从而影响供电网的电能质量及其他机车运行时的电网环境。Four-quadrant rectifiers have high power factor and can realize bidirectional flow of energy and are widely used in electric locomotives. Due to the low switching frequency of the four-quadrant rectifier, the AC side current usually has poor harmonic characteristics, which brings harmonic pollution to the power supply network, thereby affecting the power quality of the power supply network and the grid environment when other locomotives are running.
在实际应用中四象限变流器通常采用多种方式来降低电流谐波带来的污染，不同电力机车四象限变流器的主电路拓扑结构不同，而针对不同的主电路又有不同的谐波抑制方式。In practical applications, four-quadrant converters usually use a variety of methods to reduce the pollution caused by current harmonics. The main circuit topology of the four-quadrant converters of different electric locomotives is different, and different main circuits have different harmonics. Wave suppression method.
现有技术可采用软件滤波器进行多次滤波的方法，软件滤波器的设计与开关频率密切相关，而四象限变流器开关频率较低，使得设计出的滤波器的带宽较窄，滤波器的设计存在一定的困难，当系统出现冲击时，较窄带宽的滤波器会有发散的风险，导致整个四象限变流器的控制出现问题而影响机车运行的可靠性。控制系统中，滤波器的引入会导致采样信号具有一定的幅值衰减和相位延迟，降低四象限变流器的动态响应性能。In the prior art, a software filter can be used to perform multiple filtering methods. The design of the software filter is closely related to the switching frequency, and the four-quadrant converter has a lower switching frequency, which makes the bandwidth of the designed filter narrower. There are certain difficulties in the design of the system. When the system has an impact, the narrow bandwidth filter will have the risk of divergence, which will cause problems in the control of the entire four-quadrant converter and affect the reliability of locomotive operation. In the control system, the introduction of the filter will cause the sampled signal to have a certain amplitude attenuation and phase delay, which will reduce the dynamic response performance of the four-quadrant converter.
还可采用设计硬件滤波的方法，硬件滤波通常设计在硬件板卡上，且有专门的硬件电路设计。硬件滤波具有相应速度快的优点，但器件也容易受到温度、湿度的影响，同时硬件设计也增加了经济成本。还可采用电流并联的多重化方法，电流并联的多重化通常是两重化或者四重化，其多重化的谐波抑制能力主要是针对高次谐波，而对3次、5次等低次谐波不具备谐波抑制能力。The method of designing hardware filtering can also be used. The hardware filtering is usually designed on the hardware board and has a dedicated hardware circuit design. Hardware filtering has the advantage of corresponding speed, but the device is also susceptible to temperature and humidity, and the hardware design also increases the economic cost. Multiple methods of current paralleling can also be used. The multiplexing of current paralleling is usually double or quadruple, and its multiple harmonic suppression capability is mainly for higher harmonics, and for the 3rd, 5th, etc. Sub-harmonics do not have the ability to suppress harmonics.
发明内容Summary of the invention
本发明提供了一种融合于四象限控制算法中的谐波抑制方法，解决了四象限变流器电流低次谐波对变流器的控制带来影响和对电网电能质量 污染的问题，同时解决了采用软件滤波器的方法滤除低次谐波带来影响的问题，还解决了电网网压信号基波相位角度和低次谐波相位角度的计算精度较低而造成对四象限控制动态性能和谐波抑制能力有一定影响的问题。该方法主要是对四象限变流器控制算法中增加谐波提取和抑制功能，具有较高的适应性和灵活性，能够达到较高精度的谐波抑制目的。The present invention provides a harmonic suppression method integrated into the four-quadrant control algorithm, which solves the problems of the low-order harmonics of the four-quadrant converter current affecting the control of the converter and the pollution of the power quality of the power grid. It solves the problem of using software filter to filter out the influence of low-order harmonics. It also solves the low calculation accuracy of the fundamental wave phase angle and low-order harmonic phase angle of the grid voltage signal, which results in the dynamic control of the four-quadrant. Performance and harmonic suppression have a certain impact. This method is mainly to add harmonic extraction and suppression functions to the control algorithm of the four-quadrant converter. It has high adaptability and flexibility, and can achieve the purpose of high precision harmonic suppression.
本发明是采用如下的技术方案实现的：一种电力机车四象限变流装置低谐波抑制方法，包括四象限控制算法、四象限调制算法和谐波抑制算法；The present invention is realized by adopting the following technical scheme: a low harmonic suppression method for a four-quadrant converter device of an electric locomotive, including a four-quadrant control algorithm, a four-quadrant modulation algorithm and a harmonic suppression algorithm;
其中谐波抑制算法包括以下步骤：The harmonic suppression algorithm includes the following steps:
将四象限变流器输入电流转换到旋转坐标系下的谐波次d轴电流和谐波次q轴电流，经过低通滤波器滤波后，得到谐波电流的d轴直流分量和q轴直流分量，旋转坐标系变换所需要的角度通过来自硬件板卡的网压同步脉冲信号与DSP高速中断计数配合计算获得；The input current of the four-quadrant converter is converted to the harmonic sub-d-axis current and the harmonic sub-q-axis current in the rotating coordinate system, and after filtering by a low-pass filter, the d-axis DC component and the q-axis DC component of the harmonic current are obtained Component, the angle required for the transformation of the rotating coordinate system is calculated through the combination of the network voltage synchronization pulse signal from the hardware board and the DSP high-speed interrupt counting;
将得到的各次谐波电流d轴直流分量和q轴直流分量作为反馈量，与给定量构成PI控制闭环，通过闭环控制方式将谐波电流的直流分量调节为零，输出量为谐波旋转坐标下的d轴和q轴误差电压分量；The d-axis DC component and q-axis DC component of the obtained harmonic currents are used as feedback quantities, and the given quantities form a PI control closed loop. The DC component of the harmonic current is adjusted to zero through the closed-loop control method, and the output is harmonic rotation. The d-axis and q-axis error voltage components under the coordinates;
将谐波旋转坐标下的d轴和q轴误差电压分量转换到基波旋转坐标下的d轴和q轴电压谐波分量，旋转坐标系变换所需要的角度通过来自硬件板卡的网压同步脉冲信号与DSP高速中断计数配合计算获得；Convert the d-axis and q-axis error voltage components in the harmonic rotation coordinate to the d-axis and q-axis voltage harmonic components in the fundamental rotation coordinate. The angle required for the rotation coordinate system transformation is synchronized by the network voltage from the hardware board. The pulse signal is calculated with the DSP high-speed interrupt counting;
将基波旋转坐标下的d轴电压谐波分量相加构成基波旋转坐标下的谐波d轴电压调节总量；将基波旋转坐标下的q轴电压谐波分量相加构成基波旋转坐标下的谐波q轴电压调节总量；谐波d轴电压调节总量和谐波q轴电压调节总量作为前馈项送入到四象限控制算法中进行运算；Add the harmonic components of the d-axis voltage under the fundamental rotation coordinate to form the total harmonic d-axis voltage adjustment under the fundamental rotation coordinate; add the harmonic components of the q-axis voltage under the fundamental rotation coordinate to form the fundamental rotation The harmonic q-axis voltage adjustment total under the coordinate; the harmonic d-axis voltage adjustment total and the harmonic q-axis voltage adjustment total are fed into the four-quadrant control algorithm as a feedforward term for calculation;
四象限控制算法运算后得出具备谐波抑制功能的指令电压，将指令电压送入四象限脉冲调制模块进行调制得到PWM脉冲，将脉冲传递至四象限变流器的IGBT中。After the four-quadrant control algorithm is calculated, the command voltage with harmonic suppression function is obtained, and the command voltage is sent to the four-quadrant pulse modulation module for modulation to obtain the PWM pulse, and the pulse is transmitted to the IGBT of the four-quadrant converter.
进一步的，该方法为单独使用软件控制算法实现的四象限电流低次谐波抑制方法，采用DSP+FPGA控制芯片和信号调理硬件板卡组成的硬件构架，其中DSP芯片完成四象限控制算法、四象限调制算法和谐波抑制算法，FPGA完成四象限整流所需的数据采样，上位机通讯，脉冲及死区设置，其中FPGA中设置了过流、过压硬件保护与软件保护构成双重保护；信号调理硬件板卡 完成四象限输入信号的调理，完成信号调理后将信号传送至FPGA进行采样，DSP读取FPGA中的信号采样值用于控制算法计算。Further, this method is a four-quadrant current low-order harmonic suppression method realized by using a software control algorithm alone. It uses a hardware architecture composed of a DSP+FPGA control chip and a signal conditioning hardware board. The DSP chip completes the four-quadrant control algorithm, four Quadrant modulation algorithm and harmonic suppression algorithm, FPGA completes the data sampling required for four-quadrant rectification, host computer communication, pulse and dead zone settings, and the FPGA is equipped with overcurrent, overvoltage hardware protection and software protection to form a double protection; signal The conditioning hardware board completes the conditioning of the four-quadrant input signal. After the signal conditioning is completed, the signal is transmitted to the FPGA for sampling, and the DSP reads the signal sampling value in the FPGA for control algorithm calculation.
进一步的，电网电压相位角度的计算过程如下：电网电压信号在由负到正过零点时，经过硬件板卡上的硬件调理电路会产生一个与网压过零点同步的具有上升沿的高电平信号P；电网电压信号在由正到负过零点时，硬件板卡输出一个与网压过零点同步的具有下降沿的低电平信号p′；在DSP中设置MKHz的高速中断，完成中断计数和基波角度计算；高电平信号P上升沿个数使用Cnt计数，Cnt采用最大值为Q的增减计数方式；高速中断次数使用Cnt1和Cnt2计数。当检测到网压同步脉冲高电平信号P的上升沿且Cnt为奇数时，高速中断计数Cnt1开始增加，Cnt1增加期间检测到下降沿的低电平信号p′时，Cnt2计数值清零；在下一个脉冲高电平信号P上升沿到来时，高速中断计数Cnt1计数结束，Cnt1计数值赋予N进行角度计算；当Cnt计数值为0或者偶数时，中断计数Cnt2开始增加，Cnt2增加期间检测到下降沿的低电平信号p′时，Cnt1计数清零；在下一个脉冲高电平信号P上升沿到来时，高速中断计数Cnt2计数结束，Cnt2计数值赋予N进行角度计算。基波角度ωt计算公式表示为：
Figure PCTCN2019119876-appb-000001
同理，3次谐波角度3ωt表示为：
Figure PCTCN2019119876-appb-000002
5次谐波角度5ωt表示为：
Figure PCTCN2019119876-appb-000003
Further, the calculation process of the grid voltage phase angle is as follows: when the grid voltage signal changes from negative to positive zero-crossing point, the hardware conditioning circuit on the hardware board will generate a high level with rising edge synchronized with the grid-voltage zero-crossing point. Signal P; when the grid voltage signal is at the zero-crossing point from positive to negative, the hardware board outputs a low-level signal p′ with a falling edge synchronized with the zero-crossing point of the grid voltage; set MKHz high-speed interrupt in the DSP to complete the interrupt count Calculate the angle of the fundamental wave; the number of rising edges of the high-level signal P is counted by Cnt, and Cnt is counted by the increment and decrement method with the maximum value Q; the number of high-speed interrupts is counted by Cnt1 and Cnt2. When the rising edge of the high-level signal P of the network voltage synchronization pulse is detected and Cnt is an odd number, the high-speed interrupt count Cnt1 starts to increase, and when the low-level signal p′ of the falling edge is detected during the increase of Cnt1, the Cnt2 count value is cleared; When the rising edge of the next pulse high level signal P arrives, the high-speed interrupt count Cnt1 count ends, and the Cnt1 count value is assigned to N for angle calculation; when the Cnt count value is 0 or an even number, the interrupt count Cnt2 starts to increase, and it is detected during the increase of Cnt2 At the falling edge of the low-level signal p', the Cnt1 count is cleared; when the next rising edge of the pulse high-level signal P arrives, the high-speed interrupt count Cnt2 counts are over, and the Cnt2 count value is assigned to N for angle calculation. The calculation formula of the fundamental angle ωt is expressed as:
Figure PCTCN2019119876-appb-000001
In the same way, the third harmonic angle 3ωt is expressed as:
Figure PCTCN2019119876-appb-000002
The 5th harmonic angle 5ωt is expressed as:
Figure PCTCN2019119876-appb-000003
进一步的，谐波抑制算法是对三次谐波和五次谐波进行抑制，三次和五次谐波电流的d轴直流分量和q轴直流分量的具体运算过程如下：Further, the harmonic suppression algorithm is to suppress the third and fifth harmonics. The specific calculation process of the d-axis DC component and the q-axis DC component of the third and fifth harmonic currents is as follows:
将四象限输入电流i s与C abc-dq3相乘即可得到在旋转坐标系下的3次谐波d轴电流i d3和3次谐波q轴电流i q3，即，
Figure PCTCN2019119876-appb-000004
经过截止频率为 f c的低通滤波器滤波后，得到3次谐波电流的d轴直流分量
Figure PCTCN2019119876-appb-000005
和q轴直流分量
Figure PCTCN2019119876-appb-000006
Multiply the four-quadrant input current i s and C abc-dq3 to obtain the 3rd harmonic d-axis current i d3 and the 3rd harmonic q-axis current i q3 in the rotating coordinate system, that is,
Figure PCTCN2019119876-appb-000004
After filtering with a low-pass filter with a cut-off frequency of f c , the d-axis DC component of the third harmonic current is obtained
Figure PCTCN2019119876-appb-000005
And q-axis DC component
Figure PCTCN2019119876-appb-000006
将四象限输入电流i s与C abc-dq5相乘即可得到在旋转坐标系下的5次谐波d轴电流i d5和5次谐波q轴电流i q5，
Figure PCTCN2019119876-appb-000007
Figure PCTCN2019119876-appb-000008
经过截止频率为f c的低通滤波器滤波后，得到5次谐波电流的d轴直流量分量
Figure PCTCN2019119876-appb-000009
和q轴直流分量
Figure PCTCN2019119876-appb-000010
Multiply the four-quadrant input current i s and C abc-dq5 to obtain the 5th harmonic d-axis current i d5 and the 5th harmonic q-axis current i q5 in the rotating coordinate system,
Figure PCTCN2019119876-appb-000007
Figure PCTCN2019119876-appb-000008
After filtering by a low-pass filter with a cut-off frequency of f c , the d-axis DC component of the 5th harmonic current is obtained
Figure PCTCN2019119876-appb-000009
And q-axis DC component
Figure PCTCN2019119876-appb-000010
进一步的，谐波旋转坐标下的d轴和q轴误差电压分量的具体运算过程如下：Further, the specific calculation process of the d-axis and q-axis error voltage components under the harmonic rotation coordinate is as follows:
将3次谐波的d轴、q轴直流分量
Figure PCTCN2019119876-appb-000011
作为反馈量，与给定量
Figure PCTCN2019119876-appb-000012
和
Figure PCTCN2019119876-appb-000013
构成PI控制闭环，通过闭环控制方式将3次谐波电流的直流分量
Figure PCTCN2019119876-appb-000014
Figure PCTCN2019119876-appb-000015
调节为零，输出量为3次谐波旋转坐标下的d轴和q轴误差电压分量u d3、u q3； The d-axis and q-axis DC components of the third harmonic
Figure PCTCN2019119876-appb-000011
As the amount of feedback, and the given amount
Figure PCTCN2019119876-appb-000012
with
Figure PCTCN2019119876-appb-000013
The PI control closed loop is formed, and the DC component of the third harmonic current is reduced by the closed loop control method.
Figure PCTCN2019119876-appb-000014
Figure PCTCN2019119876-appb-000015
Adjusted to zero, the output is the d-axis and q-axis error voltage components u d3 , u q3 under the 3rd harmonic rotating coordinate;
将5次谐波的d轴、q轴直流分量
Figure PCTCN2019119876-appb-000016
作为反馈量，与给定量
Figure PCTCN2019119876-appb-000017
和
Figure PCTCN2019119876-appb-000018
构成PI控制闭环，通过闭环控制方式将5次谐波电流的直流分量
Figure PCTCN2019119876-appb-000019
Figure PCTCN2019119876-appb-000020
调节为零，输出量为5次谐波旋转坐标下的d轴和q轴误差电压分量 u d5、u q5。 The d-axis and q-axis DC components of the 5th harmonic
Figure PCTCN2019119876-appb-000016
As the amount of feedback, and the given amount
Figure PCTCN2019119876-appb-000017
with
Figure PCTCN2019119876-appb-000018
A PI control closed loop is formed, and the DC component of the 5th harmonic current is reduced by the closed loop control method.
Figure PCTCN2019119876-appb-000019
Figure PCTCN2019119876-appb-000020
Adjusted to zero, the output is the d-axis and q-axis error voltage components u d5 , u q5 under the 5th harmonic rotation coordinate.
进一步的，基波旋转坐标下的d轴和q轴电压谐波分量具体运算过程如下：Further, the specific calculation process of the d-axis and q-axis voltage harmonic components under the fundamental rotation coordinate is as follows:
将3次谐波旋转坐标下的误差电压分量u d3、u q3转换到基波旋转坐标下的电压谐波分量u d3-1、u q3-1，
Figure PCTCN2019119876-appb-000021
Figure PCTCN2019119876-appb-000022
Convert the error voltage components u d3 and u q3 under the 3rd harmonic rotating coordinate to the voltage harmonic components u d3-1, u q3-1 under the fundamental wave rotating coordinate,
Figure PCTCN2019119876-appb-000021
Figure PCTCN2019119876-appb-000022
将5次谐波旋转坐标下的误差电压分量u d5、u q5转换到基波旋转坐标下的电压谐波分量u d5-1、u q5-1，
Figure PCTCN2019119876-appb-000023
Figure PCTCN2019119876-appb-000024
Convert the error voltage components u d5 and u q5 under the 5th harmonic rotating coordinate to the voltage harmonic components u d5-1 and u q5-1 under the fundamental wave rotating coordinate,
Figure PCTCN2019119876-appb-000023
Figure PCTCN2019119876-appb-000024
进一步的，谐波d轴电压调节总量和谐波q轴电压调节总量的具体运算过程如下：将u d3-1与u d5-1相加构成基波旋转坐标下的谐波d轴电压调节总量u' d；将u q3-1与u q5-1相加构成基波旋转坐标下的谐波q轴电压调节总量u′ q。 Further, the specific calculation process of the harmonic d-axis voltage adjustment total and the harmonic q-axis voltage adjustment total is as follows: add u d3-1 and u d5-1 to form the harmonic d-axis voltage in the fundamental rotation coordinate adjusting the total amount of u 'd; u q3-1 with the sum u q5-1 harmonic constituting the q-axis fundamental voltage regulator total rotational coordinate u' q.
进一步的，四象限控制算法采用基于id_iq的动态解耦控制，采用电压、电流双闭环控制策略；电压环控制对象为母线电压Udc，保证母线电压实际值等于指令值，实际电压采样值经过陷波器滤波后与指令值进行比较计算，陷波器的陷波频率为100Hz，设计频率为四象限开关频率2倍；电流内环主要是对电流的控制，电流内环指令值id为电压外环输出量；四象限运行时，设置iq指令值为零；四象限调制算法采用单极性倍频调制，其构成灵活多变，可配置成多重化方式，用于四象限电流中高次谐波的消除。Further, the four-quadrant control algorithm adopts id_iq-based dynamic decoupling control, and adopts a voltage and current double closed-loop control strategy; the voltage loop control object is the bus voltage Udc to ensure that the actual value of the bus voltage is equal to the command value, and the actual voltage sampling value is trapped The filter is filtered and compared with the command value. The notch frequency of the notch filter is 100Hz, and the design frequency is twice the four-quadrant switching frequency; the current inner loop is mainly to control the current, and the command value id of the current inner loop is the voltage outer loop. Output; when four-quadrant operation, set the iq command value to zero; four-quadrant modulation algorithm adopts unipolar frequency multiplication modulation, its composition is flexible and changeable, and can be configured into multiple modes for high-order harmonics in four-quadrant current eliminate.
本发明技术方案带来的有益效果Beneficial effects brought by the technical scheme of the present invention
1整体控制算法具备低次谐波抑制能力，不需要额外的硬件电路设计；1 The overall control algorithm has the ability to suppress low-order harmonics and does not require additional hardware circuit design;
2提高了变压器原边电流的谐波特性，减少了对电网的污染和干扰。2 Improve the harmonic characteristics of the transformer primary current and reduce the pollution and interference to the power grid.
3通过控制软件实现的低次谐波抑制，避免了电磁干扰的影响。3 The low-order harmonic suppression realized by the control software avoids the influence of electromagnetic interference.
4解决了控制频率低造成的锁相环输出的基波和低次谐波角度计算精度较低的问题。4 It solves the problem of low calculation accuracy of the fundamental wave and low-order harmonic angle of the phase-locked loop output caused by the low control frequency.
附图说明Description of the drawings
图1为四象限主电路拓扑图。Figure 1 shows the topological diagram of the four-quadrant main circuit.
图2为四象限控制算法与谐波抑制算法模块示意图。Figure 2 is a schematic diagram of the four-quadrant control algorithm and harmonic suppression algorithm modules.
图3为谐波电流提取模块和谐波电流一直模块算法图。Figure 3 is the algorithm diagram of the harmonic current extraction module and the harmonic current module.
图4为网压角度计算时高速中断计数Cnt1/Cnt2时序匹配图。Figure 4 shows the timing matching diagram of the high-speed interrupt count Cnt1/Cnt2 when calculating the network voltage angle.
图5为网压角度计算式上升沿脉冲P计数Cnt设置图。Figure 5 is the setting diagram of the rising edge pulse P count Cnt of the grid voltage angle calculation formula.
具体实施方式Detailed ways
1.四象限整流器开关频率通常只有几百赫兹，电流谐波采用滤波器方案时，容易受滤波器影响四象限整流器的控制性能，故而电流谐波抑制采用控制闭环方案。1. The switching frequency of the four-quadrant rectifier is usually only a few hundred hertz. When the current harmonic adopts the filter scheme, it is easy to be affected by the filter to the control performance of the four-quadrant rectifier, so the current harmonic suppression adopts the control closed-loop scheme.
2.整个方案分四象限控制算法、四象限调制算法、主电路拓扑和谐波抑制算法四部分构成。其中四象限控制算法采用基于id_iq的动态解耦控制，四象限调制算法采用单极性倍频调制，其构成灵活多变，可配置成多重化方式，用于四象限电流中高次谐波的消除；谐波抑制算法采用基于PI控制器的谐波电流直流量闭环控制方式，主要由谐波电流提取模块和谐波电流抑制模块构成。2. The whole scheme is divided into four parts: four-quadrant control algorithm, four-quadrant modulation algorithm, main circuit topology and harmonic suppression algorithm. The four-quadrant control algorithm uses id_iq-based dynamic decoupling control, and the four-quadrant modulation algorithm uses unipolar frequency multiplication modulation, which is flexible and changeable, and can be configured into multiple modes for the elimination of high-order harmonics in the four-quadrant current. ; Harmonic suppression algorithm adopts PI controller-based closed-loop control of the direct current of the harmonic current, which is mainly composed of a harmonic current extraction module and a harmonic current suppression module.
3.控制硬件采用DSP+FPGA控制芯片和信号调理硬件板卡组成的硬件构架，其中DSP芯片完成四象限控制算法、四象限调制算法和谐波抑制算法，FPGA主要完成四象限整流所需的数据采样，上位机通讯，脉冲及死区设置，其中FPGA中设置了过流、过压等硬件保护与软件保护构成双重保护，大大提高了故障发生时保护的响应速度和可靠性；信号调理板卡主要完成四象限输入信号的调理，完成信号调理后将信号传送至FPGA进行采样，DSP读取FPGA 中的信号采样值用于控制算法计算。3. The control hardware adopts the hardware architecture composed of DSP+FPGA control chip and signal conditioning hardware board. The DSP chip completes the four-quadrant control algorithm, the four-quadrant modulation algorithm and the harmonic suppression algorithm, and the FPGA mainly completes the data required for the four-quadrant rectification. Sampling, host computer communication, pulse and dead zone settings, in which over-current, over-voltage and other hardware protection and software protection are set in FPGA to form dual protections, which greatly improve the response speed and reliability of the protection when a fault occurs; signal conditioning board It mainly completes the conditioning of the four-quadrant input signal. After the signal conditioning is completed, the signal is transmitted to the FPGA for sampling, and the DSP reads the signal sampled value in the FPGA for control algorithm calculation.
4.谐波电流提取模块主要是完成对四象限电流中对应次谐波的提取，本方案中主要是完成对3次和5次谐波电流的提取，为谐波电流抑制模块提供数据。3次谐波电流和5次谐波电流的获取是对四象限输入电流经过旋转坐标变换得到。4. The harmonic current extraction module is mainly to complete the extraction of the corresponding sub-harmonics in the four-quadrant current. In this scheme, the main purpose is to complete the extraction of the 3rd and 5th harmonic currents to provide data for the harmonic current suppression module. The acquisition of the 3rd harmonic current and the 5th harmonic current is obtained by transforming the four-quadrant input current through a rotating coordinate.
5.旋转坐标系变换所需要的角度3ωt和5ωt通过来自硬件板卡的网压同步脉冲信号与DSP中断计数配合计算获得，四象限输入电流i s可以通过FPGA中采样获得。 5. The angles 3ωt and 5ωt required for the transformation of the rotating coordinate system are calculated through the network voltage synchronization pulse signal from the hardware board and the DSP interrupt count. The four-quadrant input current i s can be obtained by sampling in the FPGA.
6.电网网压信号在由负到正过零点时，经过硬件板卡上的硬件调理电路会产生一个与网压过零点同步的具有上升沿的高电平信号P；电网电压信号在由正到负过零点时，硬件调理板卡输出一个与网压过零点同步的具有下降沿的低电平信号p′；在DSP中设置MKHz的高速中断，完成中断计数和基波角度计算；脉冲信号P上升沿个数使用Cnt计数，Cnt采用最大值为Q的增减计数方式，高速中断次数使用Cnt1和Cnt2计数；当检测到网压同步脉冲信号P的上升沿且Cnt为奇数时，高速中断计数Cnt1开始增加，Cnt1增加期间检测到下降沿的低电平信号p′时，Cnt2清零；在下一个脉冲信号P上升沿到来时，高速中断计数Cnt1计数结束，Cnt1计数值赋予N进行角度计算；当Cnt计数值为0或者偶数时，中断计数Cnt2开始增加，Cnt2增加期间检测到下降沿的低电平信号p′时，Cnt1清零；在下一个脉冲信号P上升沿到来时，高速中断计数Cnt2计数结束，Cnt2计数值赋予N进行角度计算。基波角度ωt计算公式表示为：
Figure PCTCN2019119876-appb-000025
同理，3次谐波角度3ωt表示为：
Figure PCTCN2019119876-appb-000026
5次谐波角度5ωt表示为：
Figure PCTCN2019119876-appb-000027
6. When the grid voltage signal is at the zero-crossing point from negative to positive, the hardware conditioning circuit on the hardware board will generate a high-level signal P with a rising edge that is synchronized with the grid-voltage zero-crossing point; the grid voltage signal is changing from positive to positive. When the negative zero-crossing point is reached, the hardware conditioning board outputs a low-level signal p′ with a falling edge synchronized with the zero-crossing point of the network voltage; MKHz high-speed interrupt is set in the DSP to complete the interrupt counting and fundamental wave angle calculation; pulse signal The number of rising edges of P is counted by Cnt, and Cnt is counted with the maximum value of Q. The number of high-speed interrupts is counted by Cnt1 and Cnt2; when the rising edge of the network voltage synchronization pulse signal P is detected and Cnt is an odd number, the high-speed interrupt Count Cnt1 starts to increase, and Cnt2 is cleared when the low-level signal p′ at the falling edge is detected during the increase of Cnt1; when the next rising edge of the pulse signal P arrives, the high-speed interrupt counting Cnt1 count ends, and the Cnt1 count value is assigned to N for angle calculation ; When the Cnt count value is 0 or an even number, the interrupt count Cnt2 starts to increase, Cnt1 is cleared when the low-level signal p′ of the falling edge is detected during the increase of Cnt2; when the next rising edge of the pulse signal P arrives, the high-speed interrupt counting The count of Cnt2 ends, and the count value of Cnt2 is assigned to N for angle calculation. The calculation formula of the fundamental angle ωt is expressed as:
Figure PCTCN2019119876-appb-000025
In the same way, the third harmonic angle 3ωt is expressed as:
Figure PCTCN2019119876-appb-000026
The 5th harmonic angle 5ωt is expressed as:
Figure PCTCN2019119876-appb-000027
7.将四象限输入电流i s与C abc-dq3相乘即可得到在旋转坐标系下的3次谐波d轴电流i d3和3次谐波q轴电流i q3，经过截止频率为f c的低通滤波器(LPF)滤波后，得到3次谐波电流的d轴直流分量
Figure PCTCN2019119876-appb-000028
和q轴直流分量
Figure PCTCN2019119876-appb-000029
7. Multiply the four-quadrant input current i s and C abc-dq3 to get the 3rd harmonic d-axis current i d3 and the 3rd harmonic q-axis current i q3 in the rotating coordinate system, and the cut-off frequency is f After filtering by the low-pass filter (LPF) of c , the d-axis DC component of the 3rd harmonic current is obtained
Figure PCTCN2019119876-appb-000028
And q-axis DC component
Figure PCTCN2019119876-appb-000029
Figure PCTCN2019119876-appb-000030
Figure PCTCN2019119876-appb-000030
Figure PCTCN2019119876-appb-000031
Figure PCTCN2019119876-appb-000031
Figure PCTCN2019119876-appb-000032
Figure PCTCN2019119876-appb-000032
8.将四象限输入电流i s与C abc-dq5相乘即可得到在旋转坐标系下的5次谐波d轴电流i d5和5次谐波q轴电流i q5，经过截止频率为f c的低通滤波器(LPF)滤波后，得到5次谐波电流的d轴直流量分量
Figure PCTCN2019119876-appb-000033
和q轴直流分量
Figure PCTCN2019119876-appb-000034
8. Multiply the four-quadrant input current i s and C abc-dq5 to get the 5th harmonic d-axis current i d5 and the 5th harmonic q-axis current i q5 in the rotating coordinate system, and the cut-off frequency is f After filtering by the low-pass filter (LPF) of c , the d-axis DC component of the 5th harmonic current is obtained
Figure PCTCN2019119876-appb-000033
And q-axis DC component
Figure PCTCN2019119876-appb-000034
Figure PCTCN2019119876-appb-000035
Figure PCTCN2019119876-appb-000035
Figure PCTCN2019119876-appb-000036
Figure PCTCN2019119876-appb-000036
Figure PCTCN2019119876-appb-000037
Figure PCTCN2019119876-appb-000037
9.将步骤7中得到的
Figure PCTCN2019119876-appb-000038
作为反馈量，与给定量
Figure PCTCN2019119876-appb-000039
和
Figure PCTCN2019119876-appb-000040
构成PI控制闭环，通过闭环控制方式将3次谐波电流的直流分量
Figure PCTCN2019119876-appb-000041
调节为零，输出量为3次谐波旋转坐标下的d轴和q轴误差电压分量u d3、u q3。 9. Combine what you got in step 7
Figure PCTCN2019119876-appb-000038
As the amount of feedback, and the given amount
Figure PCTCN2019119876-appb-000039
with
Figure PCTCN2019119876-appb-000040
The PI control closed loop is formed, and the DC component of the third harmonic current is reduced by the closed loop control method.
Figure PCTCN2019119876-appb-000041
Adjusted to zero, the output is the d-axis and q-axis error voltage components u d3 , u q3 under the 3rd harmonic rotation coordinate.
10.将步骤8中得到的
Figure PCTCN2019119876-appb-000042
作为反馈量，与给定量
Figure PCTCN2019119876-appb-000043
和
Figure PCTCN2019119876-appb-000044
构成PI控制闭环，通过闭环控制方式将5次谐波电流的直流分量
Figure PCTCN2019119876-appb-000045
调节为零，输出量为5次谐波旋转坐标下的d轴和q轴误差电压分量u d5、u q5。 10. Combine what you got in step 8
Figure PCTCN2019119876-appb-000042
As the amount of feedback, and the given amount
Figure PCTCN2019119876-appb-000043
with
Figure PCTCN2019119876-appb-000044
A PI control closed loop is formed, and the DC component of the 5th harmonic current is reduced by the closed loop control method.
Figure PCTCN2019119876-appb-000045
Adjusted to zero, the output is the d-axis and q-axis error voltage components u d5 , u q5 under the 5th harmonic rotation coordinate.
11.将步骤9中得到的3次谐波旋转坐标下的谐波误差电压u d3、u q3，通过公式转换到基波旋转坐标下的电压谐波分量u d3-1、u q3-1。 11. Convert the harmonic error voltage u d3 and u q3 under the third harmonic rotating coordinate obtained in step 9 to the voltage harmonic components u d3-1 , u q3-1 under the fundamental rotating coordinate through the formula.
Figure PCTCN2019119876-appb-000046
Figure PCTCN2019119876-appb-000046
Figure PCTCN2019119876-appb-000047
Figure PCTCN2019119876-appb-000047
Figure PCTCN2019119876-appb-000048
Figure PCTCN2019119876-appb-000048
12.将步骤10中得到的5次谐波旋转坐标下的谐波误差电压u d5、u q5，通过公式转换到基波旋转坐标下的电压谐波分量u d5-1、u q5-1。 12. Convert the harmonic error voltages u d5 and u q5 under the fifth harmonic rotating coordinate obtained in step 10 to the voltage harmonic components u d5-1 and u q5-1 under the fundamental rotating coordinate through the formula.
Figure PCTCN2019119876-appb-000049
Figure PCTCN2019119876-appb-000049
Figure PCTCN2019119876-appb-000050
Figure PCTCN2019119876-appb-000050
Figure PCTCN2019119876-appb-000051
Figure PCTCN2019119876-appb-000051
13.将步骤11中的u d3-1与步骤12中的u d5-1相加构成基波旋转坐标下的谐波d轴电压调节总量u' d；将步骤11中的u q3-1与步骤12中的u q5-1相加构成基波旋转坐标下的谐波q轴电压调节总量u' q。 13. u d5-1 in step 11 and step 12 u d3-1 adding the d-axis voltage harmonic constituting the fundamental rotational coordinate adjustment amount u 'd; step 11 u q3-1 and in the step of adding 12 u q5-1 harmonic constituting the q-axis fundamental voltage regulator total rotating coordinate u 'q.
14.将u' d作为前馈项送入四象限控制算法中的基波d轴调节量，与网压U s、电压外环调节器输出量、电流解耦项进行运算后作为基波d轴总调节量；将u' q作为前馈项送入四象限控制算法中的基波d轴调节量，与q轴基波电流调节器输出量、电流解耦项进行运算后作为基波q轴总调节量。 14. The u 'd d-axis into four quadrant control of the amount of adjustment of the fundamental algorithm, calculates the grid voltage U s, outer loop regulator output voltage, current decoupling item as the item as a fundamental feedforward d the total amount of the adjustment shaft; after u 'q as a feed-forward term into the four-quadrant control the d-axis adjustment amount of the fundamental algorithm, calculates the q-axis fundamental current regulator output, the fundamental wave current item as a decoupling q The total adjustment of the shaft.
15.将步骤14中的d、q轴总调节量(直流量)转换到直角坐标系下的交流量，即为所需具有3次和5次谐波抑制功能的指令电压
Figure PCTCN2019119876-appb-000052
将其送入脉冲调制模块进行脉冲调制得到PWM脉冲，送入四象限变流器的IGBT中。 15. Convert the total adjustment value (DC value) of the d and q axis in step 14 to the AC value under the Cartesian coordinate system, which is the command voltage required to have the 3rd and 5th harmonic suppression function
Figure PCTCN2019119876-appb-000052
Send it to the pulse modulation module for pulse modulation to obtain the PWM pulse, which is sent to the IGBT of the four-quadrant converter.
上述谐波抑制方案实现谐波抑制的方法，在四象限整流器上得到实现，试验结果表明，使用该方法交流侧电流具有较好的谐波特性，达到预期目的。The above-mentioned harmonic suppression scheme realizes the method of harmonic suppression in a four-quadrant rectifier. The test results show that the AC side current using this method has better harmonic characteristics and achieves the expected purpose.

Claims (8)

  1. 一种电力机车四象限变流装置低谐波抑制方法，其特征在于包括四象限控制算法、四象限调制算法和谐波抑制算法；A low harmonic suppression method for a four-quadrant converter device of an electric locomotive, which is characterized by including a four-quadrant control algorithm, a four-quadrant modulation algorithm and a harmonic suppression algorithm;
    其中谐波抑制算法包括以下步骤：The harmonic suppression algorithm includes the following steps:
    将四象限变流器输入电流转换到旋转坐标系下的谐波次d轴电流和谐波次q轴电流，经过低通滤波器滤波后，得到谐波电流的d轴直流分量和q轴直流分量，旋转坐标系变换所需要的角度通过来自硬件板卡的网压同步脉冲信号与DSP高速中断计数配合计算获得；The input current of the four-quadrant converter is converted to the harmonic sub-d-axis current and the harmonic sub-q-axis current in the rotating coordinate system, and after filtering by a low-pass filter, the d-axis DC component and the q-axis DC component of the harmonic current are obtained Component, the angle required for the transformation of the rotating coordinate system is calculated through the combination of the network voltage synchronization pulse signal from the hardware board and the DSP high-speed interrupt counting;
    将得到的各次谐波电流d轴直流分量和q轴直流分量作为反馈量，与给定量构成PI控制闭环，通过闭环控制方式将各次谐波电流的直流分量调节为零，输出量为各次谐波旋转坐标下的d轴和q轴误差电压分量；The d-axis DC component and q-axis DC component of each harmonic current obtained are used as the feedback value, and the given value constitutes a PI control closed loop. The DC component of each harmonic current is adjusted to zero through the closed-loop control method, and the output is each The d-axis and q-axis error voltage components under sub-harmonic rotating coordinates;
    将各次谐波旋转坐标下的d轴和q轴误差电压分量转换到基波旋转坐标下的d轴和q轴电压谐波分量，旋转坐标系变换所需要的角度通过来自硬件板卡的网压同步脉冲信号与DSP高速中断计数配合计算获得；Convert the d-axis and q-axis error voltage components of each harmonic rotation coordinate to the d-axis and q-axis voltage harmonic components of the fundamental rotation coordinate. The angle required for the conversion of the rotating coordinate system is passed through the network from the hardware board. The voltage synchronization pulse signal is calculated in cooperation with the DSP high-speed interrupt counting;
    将基波旋转坐标下的d轴电压谐波分量相加构成基波旋转坐标下的谐波d轴电压调节总量；将基波旋转坐标下的q轴电压谐波分量相加构成基波旋转坐标下的谐波q轴电压调节总量；谐波d轴电压调节总量和谐波q轴电压调节总量作为前馈项送入到四象限控制算法中进行运算；Add the harmonic components of the d-axis voltage under the fundamental rotation coordinate to form the total harmonic d-axis voltage adjustment under the fundamental rotation coordinate; add the harmonic components of the q-axis voltage under the fundamental rotation coordinate to form the fundamental rotation The harmonic q-axis voltage adjustment total under the coordinate; the harmonic d-axis voltage adjustment total and the harmonic q-axis voltage adjustment total are fed into the four-quadrant control algorithm as a feedforward term for calculation;
    四象限控制算法运算出谐波抑制功能的指令电压，将指令电压送入四象限脉冲调制模块进行调制得到PWM脉冲，送入四象限变流器的IGBT中。The four-quadrant control algorithm calculates the command voltage of the harmonic suppression function, and sends the command voltage to the four-quadrant pulse modulation module for modulation to obtain the PWM pulse, which is sent to the IGBT of the four-quadrant converter.
  2. 根据权利要求1所述的一种电力机车四象限变流装置低谐波抑制方法，其特征在于该方法为单独使用控制算法实现的四象限电流低次谐波抑制方法，采用DSP+FPGA控制芯片和信号调理硬件板卡组成的硬件构架，其中DSP芯片完成四象限控制算法、四象限调制算法和谐波抑制算法，FPGA完成四象限整流所需的数据采样，上位机通讯，脉冲及死区设置，其中FPGA中设置了过流、过压硬件保护与软件保护构成双重保护；信号调理硬件板卡完成四象限输入信号的调理，完成信号调理后将信号传送至FPGA进行采样，DSP读取FPGA中的信号采样值用于控制算法计算。The low harmonic suppression method for a four-quadrant converter device for electric locomotives according to claim 1, characterized in that the method is a four-quadrant current low-order harmonic suppression method realized by using a control algorithm alone, using a DSP+FPGA control chip The hardware architecture is composed of signal conditioning hardware boards. The DSP chip completes the four-quadrant control algorithm, the four-quadrant modulation algorithm and the harmonic suppression algorithm, and the FPGA completes the data sampling required for the four-quadrant rectification, host computer communication, pulse and dead zone settings , The FPGA is equipped with over-current, over-voltage hardware protection and software protection to form a double protection; the signal conditioning hardware board completes the conditioning of the four-quadrant input signal. After the signal conditioning is completed, the signal is transmitted to the FPGA for sampling, and the DSP reads the FPGA The sampled value of the signal is used for the calculation of the control algorithm.
  3. 根据权利要求2所述的一种电力机车四象限变流装置低谐波抑制方法，其特征在于坐标变换所需要的角度的计算过程如下：电网网压信号在由负到 正过零点时，经过硬件板卡上的硬件调理电路会产生一个与网压过零点同步的具有上升沿的高电平信号P；电网网压信号在由正到负过零点时，硬件板卡输出一个与网压过零点同步的具有下降沿的低电平信号p′；在DSP中设置MKHz的高速中断，完成中断计数和基波角度计算；高电平信号P上升沿个数使用Cnt计数，Cnt采用最大值为Q的增减计数方式，高速中断次数使用Cnt1和Cnt2计数；当检测到网压同步高电平信号P的上升沿且Cnt为奇数时，高速中断计数Cnt1开始增加，Cnt1增加期间检测到下降沿的低电平信号p′时，Cnt2计数清零；在下一个高电平信号P上升沿到来时，高速中断计数Cnt1计数结束，Cnt1计数值赋予N进行角度计算；当Cnt计数值为0或者偶数时，中断计数Cnt2开始增加，Cnt2增加期间检测到下降沿的低电平信号p′时，Cnt1计数清零；在下一个脉冲信号P上升沿到来时，高速中断计数Cnt2计数结束，Cnt2计数值赋予N进行角度计算。基波角度ωt计算公式表示为：
    Figure PCTCN2019119876-appb-100001
    The low harmonic suppression method of a four-quadrant converter device for electric locomotives according to claim 2, characterized in that the calculation process of the angle required by the coordinate transformation is as follows: the grid voltage signal passes through the zero crossing point from negative to positive The hardware conditioning circuit on the hardware board will generate a high-level signal P with a rising edge that is synchronized with the zero-crossing point of the grid voltage; when the grid-voltage signal goes from positive to negative zero-crossing, the hardware board will output a signal that has crossed the grid voltage. Zero-point synchronous low-level signal p′ with falling edge; set MKHz high-speed interrupt in DSP to complete interrupt counting and fundamental wave angle calculation; the number of rising edges of high-level signal P uses Cnt to count, and Cnt uses the maximum value as Q's increase/decrease counting method, the number of high-speed interrupts is counted by Cnt1 and Cnt2; when the rising edge of the network voltage synchronization high-level signal P is detected and Cnt is an odd number, the high-speed interrupt count Cnt1 starts to increase, and the falling edge is detected during the increase of Cnt1 Cnt2 count is cleared when the low-level signal p′ of the next high-level signal P arrives; when the next high-level signal P rises, the high-speed interrupt count Cnt1 count ends, and the Cnt1 count value is assigned to N for angle calculation; when the Cnt count value is 0 or an even number When the interrupt count Cnt2 starts to increase, the Cnt1 count is cleared when the low-level signal p′ at the falling edge is detected during the Cnt2 increase period; when the next rising edge of the pulse signal P arrives, the high-speed interrupt count Cnt2 count ends, and the Cnt2 count value is assigned N performs angle calculation. The calculation formula of the fundamental angle ωt is expressed as:
    Figure PCTCN2019119876-appb-100001
  4. 根据权利要求3所述的一种电力机车四象限变流装置低谐波抑制方法，其特征在于谐波抑制算法是对三次谐波和五次谐波进行抑制，三次和五次谐波电流的d轴直流分量和q轴直流分量的具体运算过程如下：The low harmonic suppression method for a four-quadrant converter device for electric locomotives according to claim 3, characterized in that the harmonic suppression algorithm suppresses the third and fifth harmonics, and the third and fifth harmonic currents are The specific calculation process of the d-axis DC component and the q-axis DC component is as follows:
    将四象限输入电流i s与C abc-dq3相乘即可得到在旋转坐标系下的3次d轴电流i d3和3次q轴电流i q3，即
    Figure PCTCN2019119876-appb-100002
    Figure PCTCN2019119876-appb-100003
    经过截止频率为f c低通滤波器滤波后，得到3次谐波电流的d轴直流分量
    Figure PCTCN2019119876-appb-100004
    和q轴直流分量
    Figure PCTCN2019119876-appb-100005
    Multiply the four-quadrant input current i s and C abc-dq3 to obtain the 3rd d-axis current i d3 and the 3rd q-axis current i q3 in the rotating coordinate system, namely
    Figure PCTCN2019119876-appb-100002
    Figure PCTCN2019119876-appb-100003
    After filtering by a low-pass filter with a cut-off frequency of f c , the d-axis DC component of the third harmonic current is obtained
    Figure PCTCN2019119876-appb-100004
    And q-axis DC component
    Figure PCTCN2019119876-appb-100005
    将四象限输入电流i s与C abc-dq5相乘即可得到在旋转坐标系下的5次 d轴电流i d5和5次q轴电流i q5，
    Figure PCTCN2019119876-appb-100006
    Figure PCTCN2019119876-appb-100007
    经过截止频率为f c低通滤波器滤波后，得到5次谐波电流的d轴直流量分量
    Figure PCTCN2019119876-appb-100008
    和q轴直流分量
    Figure PCTCN2019119876-appb-100009
    Multiply the four-quadrant input current i s and C abc-dq5 to get the 5th d-axis current i d5 and the 5th q-axis current i q5 in the rotating coordinate system,
    Figure PCTCN2019119876-appb-100006
    Figure PCTCN2019119876-appb-100007
    After filtering by a low-pass filter with a cut-off frequency of f c , the d-axis DC component of the 5th harmonic current is obtained
    Figure PCTCN2019119876-appb-100008
    And q-axis DC component
    Figure PCTCN2019119876-appb-100009
  5. 根据权利要求4所述的一种电力机车四象限变流装置低谐波抑制方法，其特征在于谐波旋转坐标下的d轴和q轴误差电压分量的具体运算过程如下：The low harmonic suppression method for a four-quadrant converter device of an electric locomotive according to claim 4, characterized in that the specific calculation process of the d-axis and q-axis error voltage components under the harmonic rotation coordinate is as follows:
    将d轴、q轴直流分量
    Figure PCTCN2019119876-appb-100010
    作为反馈量，与给定量
    Figure PCTCN2019119876-appb-100011
    构成PI控制闭环，通过闭环控制方式将3次谐波电流的直流分量
    Figure PCTCN2019119876-appb-100012
    调节为零，输出量为3次谐波旋转坐标下的d轴和q轴误差电压分量u d3、u q3；     The d-axis and q-axis DC components
    Figure PCTCN2019119876-appb-100010
    As the amount of feedback, and the given amount
    Figure PCTCN2019119876-appb-100011
    The PI control closed loop is formed, and the DC component of the third harmonic current is reduced by the closed loop control method.
    Figure PCTCN2019119876-appb-100012
    Adjusted to zero, the output is the d-axis and q-axis error voltage components u d3 , u q3 under the 3rd harmonic rotating coordinate;
    将d轴、q轴直流分量
    Figure PCTCN2019119876-appb-100013
    作为反馈量，与给定量
    Figure PCTCN2019119876-appb-100014
    和
    Figure PCTCN2019119876-appb-100015
    构成PI控制闭环，通过闭环控制方式将5次谐波电流的直流分量
    Figure PCTCN2019119876-appb-100016
    调节为零，输出量为5次谐波旋转坐标下的d轴和q轴误差电压分量u d5、u q5。     The d-axis and q-axis DC components
    Figure PCTCN2019119876-appb-100013
    As the amount of feedback, and the given amount
    Figure PCTCN2019119876-appb-100014
    with
    Figure PCTCN2019119876-appb-100015
    A PI control closed loop is formed, and the DC component of the 5th harmonic current is reduced by the closed loop control method.
    Figure PCTCN2019119876-appb-100016
    Adjusted to zero, the output is the d-axis and q-axis error voltage components u d5 , u q5 under the 5th harmonic rotation coordinate.
  6. 根据权利要求5所述的一种电力机车四象限变流装置低谐波抑制方法，其特征在于基波旋转坐标下的d轴和q轴电压谐波分量具体运算过程如下：The low harmonic suppression method for a four-quadrant converter device of an electric locomotive according to claim 5, characterized in that the specific calculation process of the d-axis and q-axis voltage harmonic components under the fundamental wave rotation coordinate is as follows:
    将3次谐波旋转坐标下的误差电压分量u d3、u q3转换到基波旋转坐标 下的电压谐波分量u d3-1、u q3-1，
    Figure PCTCN2019119876-appb-100017
    Figure PCTCN2019119876-appb-100018
    Convert the error voltage components u d3 and u q3 under the 3rd harmonic rotating coordinate to the voltage harmonic components u d3-1, u q3-1 under the fundamental wave rotating coordinate,
    Figure PCTCN2019119876-appb-100017
    Figure PCTCN2019119876-appb-100018
    将5次谐波旋转坐标下的误差电压分量u d5、u q5转换到基波旋转坐标下的电压谐波分量u d5-1、u q5-1，
    Figure PCTCN2019119876-appb-100019
    Figure PCTCN2019119876-appb-100020
    Convert the error voltage components u d5 and u q5 under the 5th harmonic rotating coordinate to the voltage harmonic components u d5-1 and u q5-1 under the fundamental wave rotating coordinate,
    Figure PCTCN2019119876-appb-100019
    Figure PCTCN2019119876-appb-100020
  7. 根据权利要求6所述的一种电力机车四象限变流装置低谐波抑制方法，其特征在于谐波d轴电压调节总量和谐波q轴电压调节总量的具体运算过程如下：将u d3-1与u d5-1相加构成基波旋转坐标下的谐波d轴电压调节总量u' d；将u q3-1与u q5-1相加构成基波旋转坐标下的谐波q轴电压调节总量u′ q。 The method for suppressing low harmonics of a four-quadrant converter device for electric locomotives according to claim 6, characterized in that the specific calculation process of the total harmonic d-axis voltage adjustment and the total harmonic q-axis voltage adjustment is as follows: u d5-1 and d3-1 adding the d-axis voltage harmonic constituting the fundamental rotational coordinate adjustment amount u 'd; constituting the harmonics of the fundamental rotational coordinate u q3-1 and adding u q5-1 The total amount of q-axis voltage adjustment u′ q .
  8. 根据权利要求1或2所述的一种电力机车四象限变流装置低谐波抑制方法，其特征在于四象限控制算法采用基于id_iq的动态解耦控制，采用电压、电流双闭环控制策略；电压环控制对象为母线电压Udc，保证母线电压实际值等于指令值，实际电压采样值经过陷波器滤波后与指令值进行比较计算；电流内环是对电流的控制，电流内环指令值id为电压外环输出量；四象限运行时，设置iq指令值为零；四象限调制算法采用单极性倍频调制。The low harmonic suppression method for a four-quadrant converter device of an electric locomotive according to claim 1 or 2, characterized in that the four-quadrant control algorithm adopts id_iq-based dynamic decoupling control, and adopts a voltage and current double closed-loop control strategy; The control object of the loop is the bus voltage Udc to ensure that the actual value of the bus voltage is equal to the command value. The actual voltage sampling value is filtered by the notch filter and compared with the command value; the current inner loop is the control of the current, and the current inner loop command value id is The output of the voltage outer loop; when the four-quadrant is running, set the iq command value to zero; the four-quadrant modulation algorithm adopts unipolar frequency multiplication modulation.
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