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WO2021008262A1 - 扫描设备、图像形成装置、扫描方法及存储介质 - Google Patents

扫描设备、图像形成装置、扫描方法及存储介质 Download PDF

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Publication number
WO2021008262A1
WO2021008262A1 PCT/CN2020/093992 CN2020093992W WO2021008262A1 WO 2021008262 A1 WO2021008262 A1 WO 2021008262A1 CN 2020093992 W CN2020093992 W CN 2020093992W WO 2021008262 A1 WO2021008262 A1 WO 2021008262A1
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WO
WIPO (PCT)
Prior art keywords
image data
data
low
voltage differential
differential signal
Prior art date
Application number
PCT/CN2020/093992
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English (en)
French (fr)
Inventor
余成柱
张军
Original Assignee
珠海奔图电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from CN201921099789.5U external-priority patent/CN210640937U/zh
Priority claimed from CN201910634273.4A external-priority patent/CN110233948B/zh
Application filed by 珠海奔图电子有限公司 filed Critical 珠海奔图电子有限公司
Publication of WO2021008262A1 publication Critical patent/WO2021008262A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/04—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa

Definitions

  • This application relates to the field of image forming technology, and in particular to a scanning device, an image forming device, a scanning method and a storage medium.
  • FIG. 1 is a schematic diagram of the structure of an image forming apparatus for double-sided scanning in the prior art.
  • the scanning device of the image forming apparatus in the prior art is provided with a matching set to support the double-sided function.
  • Hardware modules such as ADF (Automatic Document Feeder) scanning unit 110, FB (Flat Panel, flat panel) scanning unit 120 and ports, etc., but due to the existing SoC (System on Chip, system on chip) for The number of ports receiving scan data cannot completely match the number of output ports of the configured scanning unit, and increasing the number of SoC ports will put forward higher requirements on the hardware design and chip area of the SoC, and may even affect other modules of the SoC Therefore, it is not conducive to the development of scanning technology.
  • ADF Automatic Document Feeder
  • FB Breast Panel, flat panel
  • SoC System on Chip, system on chip
  • the embodiments of the application provide a scanning device, an image forming apparatus, a scanning method, and a storage medium, which can solve the problem that the number of ports through which the imaging controller receives scan data in the prior art cannot completely match the number of output interfaces of the configured scanning unit .
  • an embodiment of the present application provides a scanning device, including:
  • Two image readers respectively configured to read a document to be scanned and output image data corresponding to the document to be scanned;
  • a data processor connected to the image reader through a first signal transmission line, and the data processor is configured to obtain the image data through the first signal transmission line and cache it in its internal buffer unit;
  • the imaging controller is configured to read the image data of the buffer unit through a second signal transmission line, wherein the number of lines corresponding to the second signal transmission line is smaller than the number of lines corresponding to the first signal transmission line.
  • an embodiment of the present application provides an image forming apparatus, including the scanning device described in any one of the above, and an imaging device connected to the scanning device.
  • an embodiment of the present application provides a scanning method, including:
  • Two image readers respectively read the document to be scanned and output image data corresponding to the document to be scanned;
  • the data processor obtains the image data through the first signal transmission line and caches it in its internal cache unit;
  • the imaging controller reads the image data of the buffer unit through a second signal transmission line, wherein the number of lines corresponding to the second signal transmission line is smaller than the number of lines corresponding to the first signal transmission line.
  • an embodiment of the present application provides a storage medium, the storage medium includes a stored program, and the device where the storage medium is located is controlled to execute the above method when the program runs.
  • an embodiment of the present application provides a scanning device, including a memory and a processor, the memory is used to store information including program instructions, the processor is used to control the execution of the program instructions, and the program instructions are processed The steps of the above method are implemented when the processor is loaded and executed.
  • a data processor is provided between the image reader and the imaging controller, and the scan data conversion processing is completed through the data processor, so that the number of ports through which the imaging controller receives the scan data can match the configured data processing
  • the number of output interfaces of the imaging controller solves the problem that the number of ports for the imaging controller to receive scan data in the prior art cannot completely match the number of output interfaces of the configured scanning unit, and makes full use of the existing second signal of the imaging controller
  • the transmission line corresponds to the resource of the port, and the data processor does not need to be configured with additional memory, which reduces the development and production cost and is conducive to the further development of scanning technology.
  • FIG. 1 is a schematic diagram of the structure of an image forming apparatus in the prior art
  • FIG. 2 is a cross-sectional view of a scanning device in an image forming apparatus of the related art
  • FIG. 3 is a schematic block diagram of a scanning device provided by an embodiment of the application.
  • FIG. 4 is a further schematic block diagram of the scanning device in FIG. 3;
  • FIG. 5 is a schematic block diagram of a scanning device provided by another embodiment of this application.
  • FIG. 6 is a schematic block diagram of a scanning device provided by another embodiment of this application.
  • FIG. 7 is a signal timing diagram of image data output by an image reader provided by an embodiment of the application.
  • FIG. 8 is a schematic block diagram of a scanning device provided by another embodiment of this application.
  • FIG. 9 is a schematic diagram of a process of processing the second image data by the imaging controller in the scanning device provided in FIG. 8;
  • FIG. 10 is a schematic block diagram of an image forming apparatus according to an embodiment of the application.
  • FIG. 11 is a flowchart of a scanning method provided by an embodiment of the application.
  • FIG. 12 is a schematic block diagram of a scanning device provided by another embodiment of this application.
  • the prior art provides an image forming device.
  • the image forming device includes a scanning device and an imaging device located below the scanning device.
  • the scanning device includes, but is not limited to, ADF (Automatic Document Feeder, An automatic document feeder) scanning unit 110 and an FB (Flat Bed) scanning unit 120.
  • the imaging device includes, but is not limited to, an imaging unit (such as a developing cartridge), a fixing unit, a paper transport unit, and a paper cassette 130.
  • the image forming apparatus further includes a touch screen 140, on which the user can click or press the scan or copy icon to perform scanning or copying operations, and the imaging parameters of the image forming apparatus (such as scanning resolution, paper tray, etc.) can also be set through the touch screen. 130 paper size, etc.).
  • the ADF scanning unit 110 includes a paper inlet 112, two paper web adjustment sheets 111, and a pickup roller 113.
  • the distance between the two paper web adjustment sheets 111 it can be adjusted to be allowed to be placed in the paper inlet 112.
  • the size of the paper For example, if the paper to be scanned or copied is A4, adjust the distance between the two paper web adjustment sheets 111 to correspond to the size of A4.
  • the motor will drive the pickup roller 113.
  • the pickup roller 113 feeds the paper to be scanned into the paper path in the ADF scanning unit 110, and the paper will be conveyed to the first sensor 116 or the second sensor 116 by the two transfer rollers (114, 115) on the paper path.
  • the first sensor 116 obtains the image on the paper, and then the paper continues to move along the transfer roller 117, and the paper is discharged to the paper tray by the paper discharge roller 118.
  • the models of the first sensor 116 and the second sensor 121 are not particularly limited.
  • the first sensor 116 and the second sensor 121 may be configured as a contact image sensor (Contact Image Sensor, CIS); or, the first sensor 116 and the second sensor 121 may also be partially or completely configured as a charge coupled device (Charge Coupled Device, CCD).
  • CCD Charge Coupled Device
  • the FB scanning unit 120 is provided with a document cover, a glass document table 122 is arranged under the document cover, and a second sensor 121 that can be driven by a motor is arranged under the glass document table 122. After the document cover is opened, the paper to be scanned or copied Placed on the glass document table 122, the motor drives the second sensor to move from left to right to complete scanning.
  • the first sensor 116 and the second sensor 121 are all lit. After the paper enters the paper path, the first sensor 116 and the second sensor 121 simultaneously acquire data on the front and back sides of the paper to realize double-sided scanning.
  • an embodiment of the present application provides a scanning device, including:
  • Two image readers 1 are respectively configured to read a document to be scanned and output image data corresponding to the document to be scanned;
  • the data processor 2 is connected to the image reader 1 through a first signal transmission line, and the data processor 2 is configured to obtain image data through the first signal transmission line and cache it in its internal buffer unit 21;
  • the imaging controller 3 is configured to read the image data of the buffer unit 21 through the second signal transmission line, wherein the number of lines corresponding to the second signal transmission line is smaller than the number of lines corresponding to the first signal transmission line.
  • the “first signal transmission line” mentioned above refers to the transmission line corresponding to the first signal transmission protocol.
  • the corresponding type of the first signal transmission protocol includes but is not limited to the “low voltage differential signal” mentioned below. Voltage Differentia Signaling, LVDS)", the specific form of the first signal transmission line includes but is not limited to “flexible cable” and “wire harness”.
  • the “second signal transmission line” mentioned above refers to the transmission line corresponding to the second signal transmission protocol.
  • the corresponding type of the second signal transmission protocol can be the same as or different from the corresponding type of the first signal transmission protocol.
  • LVDS Low Voltage Differential Signaling
  • the specific form of the second signal transmission line includes but is not limited to the signal transmission line in the PCB board (for example, a microstrip line or a strip
  • the same signal transmission protocol is used, so the data processor 2 does not need to undergo complex signal conversion, nor does it need to configure additional memory to assist the data processor 2 in completing the signal protocol conversion; only the data processor 2 is used
  • the internal buffer can complete the adjustment and transmission of image data.
  • the number of lines corresponding to the first signal transmission line mentioned above refers to the number of image data ports (or channels) and clock control set by the data processor 2 in order to receive the image data output by the image reader 1 Number of signal ports (or channels).
  • the number of lines corresponding to the second signal transmission line refers to the number of image data ports (or channels) and the number of clock control signal ports (or channels) set by the imaging controller 3 in order to receive the image data output by the data processor 2.
  • the image reader 1 is sold as a separate component, which has been prefabricated in advance and needs to output scanned image data through a first number (for example, X) of ports, and the first number of ports need to use the first signal transmission protocol Output the signal.
  • the imaging controller 3 is sold as a separate component, and the second number (for example, Y) of ports has been prefabricated in advance to receive the scanned image data, and the second number of ports need to receive signals through the second signal transmission protocol; but the prefabricated The first number X ⁇ the second number Y.
  • a data processor 2 is provided between the image reader 1 and the imaging controller 3, and the scan data conversion processing is completed by the data processor 2, so that the number of ports through which the imaging controller 3 receives the scan data can match
  • the configured number of output interfaces of the data processor 2 solves the problem that the number of ports for the imaging controller 3 to receive scan data in the prior art cannot completely match the number of output interfaces of the configured scanning unit, and makes full use of imaging control
  • the existing second signal transmission line of the device 3 corresponds to the resource of the port, and the data processor 2 does not need to be configured with additional memory, which reduces the development and production cost and is beneficial to the further development of scanning technology.
  • the two image readers 1 can read the front image data and the back image data of the document to be scanned respectively, or both image readers 1 can read the front image data or two images of the document to be scanned.
  • the reader 1 reads the reverse side image data of the document to be scanned.
  • the scanning device provided in the embodiment of the present application can also be used for single-sided scanning.
  • two image readers 1 are located in the document to be scanned. The same side of the document.
  • the image data output by the two image readers 1 are both the front image data of the document to be scanned, or the two image readers 1 output
  • the image data is the reverse image data of the document to be scanned.
  • the document to be scanned may include, but is not limited to: at least one of a document, a certificate, an image, and a photo, which is not particularly limited in the embodiment of the present application.
  • the imaging controller 3 is an SoC (System on Chip).
  • the SoC is a miniature system composed of multiple system components and is configured to control the imaging processing operations of the scanned image of the scanning device, such as The data is processed by linear correction, noise reduction, dead pixel removal, detail enhancement, etc., thereby improving the quality of image output.
  • the imaging controller 3 is also used to perform data transmission and reception, command transmission and reception, and engine control related processing operations for printing images, such as through Interface units (including but not limited to USB ports, wired network ports, wireless network ports or other interfaces, etc.) to send and receive data, print engine control commands, status, etc.
  • the imaging controller 3 simultaneously controls the scanning operation of the scanning device and the imaging operation of the imaging device, but this embodiment is not limited to this.
  • an independent imaging controller may be configured for the scanning device and the imaging device. It belongs to the protection scope of this embodiment.
  • the number of data processors 2 is two, and the two data processors 2 are connected to the two image readers 1 through two sets of first signal transmission lines, and are connected to the imaging device through two sets of second signal transmission lines.
  • the controller 3 is connected, and the two data processors 2 respectively process the image data output by the two image readers 1.
  • the data processor 2 may also be composed of two or more data processors 2 integrated together.
  • the data processor 2 is a programmable logic device, specifically an FPGA (Field-Programmable Gate Array, Field Programmable Gate Array).
  • the data processor 2 may also be a CPLD. (Complex Programmable Logic Device, Complex Data Processor 2) and other programmable devices.
  • the data processor 2 is configured to obtain image data through the first signal transmission line and perform a remapping process on each image data to obtain second image data, and cache the second image data to the buffer unit 21 in.
  • the image data needs to be remapped to obtain the second image data with the preset format, so that the imaging The controller 3 can obtain continuous and uninterrupted image data under the premise of meeting its own receiving frequency, and process the image data.
  • the image data output by the image reader in one output period is referred to as the first image data
  • the image data obtained by the imaging controller 3 in one acquisition period is referred to below. It is called the second image data.
  • the image reader 1 includes:
  • the sensor 11 is configured to read a document to be scanned and output image data corresponding to the document to be scanned, wherein the image data includes at least one first image data;
  • the first Low Voltage Differential Signaling (LVDS) transmitter 12 connected to the sensor 11, is configured to receive at least one piece of first image data and transmit it differentially through the first signal transmission line in each first period.
  • One piece of first image data is output in the method, where each piece of first image data corresponds to one pixel point data.
  • the two sensors 11 may be the first sensor (for example, CIS or CCD) 116 and the second sensor (for example, CIS or CCD) 121 described above, respectively.
  • the sensor 11 is configured to scan line by line. The method converts each pixel into a corresponding analog signal, where a line of image includes several pixels, such as 1024 pixels.
  • the image reader 1 further includes an analog-to-digital conversion unit (not shown).
  • the analog-to-digital conversion unit is connected between the sensor 11 and the first low-voltage differential signal transmitter 12 for transmitting the analog signal output by the sensor 11 It is converted into a digital signal and output to the first low-voltage differential signal transmitter 12. More specifically, the image reader 1 outputs image data line by line according to the line synchronization signal, and is also provided with an image data transmission clock (TCLK), and each image data transmission clock (TCLK) outputs data corresponding to one pixel.
  • TCLK image data transmission clock
  • the first low-voltage differential signal transmitter 12 is used to output the received digital signal to the data processor 2 through the first signal transmission line in a pixel-by-pixel manner according to a preset clock cycle, that is, the first low-voltage differential signal transmitter 12
  • the first image data corresponding to one pixel is output to the data processor 2 in each clock pulse period (in this document, the clock pulse period of the first low-voltage differential signal transmitter 12 is the “first period”).
  • first image data and the generated second image data may have a one-to-one correspondence, or the first image data may generate multiple second image data correspondingly, or the multiple first image data may generate one first image data correspondingly. Two image data, or multiple first image data corresponding to multiple second image data.
  • the data processor 2 also includes a first low voltage differential signal (Low Voltage Differential Signaling, LVDS) receiver 22 and a second low voltage differential signal (Low Voltage Differential Signaling, LVDS) transmitter 23, imaging control
  • the device 3 includes a second low voltage differential signal (Low Voltage Differential Signaling, LVDS) receiver 31.
  • the first low voltage differential signal receiver 22 is connected to the first low voltage differential signal transmitter 12 through a first signal transmission line, and the data processor 2 receives the first image data through the first low voltage differential signal receiver 22.
  • the second low voltage differential signal transmitter 23 is connected to the buffer unit 21 and connected to the second low voltage differential signal receiver 31 through a second signal transmission line, and the second low voltage differential signal transmitter 23 is configured to pass through the second signal transmission line.
  • the second image data buffered in the buffer unit 21 is output to the imaging controller 3 in a differential transmission manner, and the imaging controller 3 receives the second image data through the second low-voltage differential signal receiver 31.
  • the first low-voltage differential signal transmitter is configured to output the first image data generated by the sensor 11 on a pixel-by-pixel basis.
  • a pixel is represented by 24-bit RGB data.
  • the 24-bit RGB data includes 8-bit R (red) pixel data (R7, R6, R5, R4, R3, R2, R1, R0), 8-bit G (Blue) pixel data (G7, G6, G5, G4, G3, G2, G1, G0) and 8-bit B (green) pixel data (B7, B6, B5, B4, B3, B2, B1, B0),
  • the first image data corresponding to a pixel is composed of 24-bit RGB data and control signals.
  • LVDS converts parallel pixel signals and control signals into serial bit streams, which are transmitted through multiple sets of wires , The clock pulse signal is transmitted by a set of wires alone.
  • each first low-voltage differential signal transmitter 12 Since each data channel of the first low-voltage differential signal transmitter 12 outputs a 7-bit serial data signal in one clock pulse period, each first low-voltage differential signal transmitter 12 corresponds to a group of transmission lines, and each group The transmission line requires 5 pairs of data lines and 1 pair of clock lines.
  • the first image data is transmitted through the first signal transmission line composed of the data line and the clock line.
  • each first low voltage The differential signal transmitter 12 has 6 pairs of low-voltage differential signal ports (the number of data transmission ports is 5 and the number of clock signal transmission ports is 1, because the LVDS signal output lines are arranged in pairs, and each channel corresponds to 1 pair of signal lines, so the number of ports can also be "pairs"); each data processor needs 6 pairs of low-voltage differential signal receiving ports, and the data processor of the entire scanning device needs at least 12 pairs of low-voltage differential Signal receiving port.
  • the remapping process is specifically a process of rearranging the sequence of the RGB pixel data, clock signals, and control signals corresponding to the first image data according to a preset mapping rule.
  • the preset rule in this embodiment is mainly set to meet the requirement that the number of LVDS input ports of the data processor is greater than the number of LVDS output ports, and to meet this requirement, the preset rule includes the image output by the data processor.
  • the data amount (number of bits) of the data is less than or equal to the data (number of bits) of the input image data, and rearrangement is performed according to the number of output ports is less than the number of input ports.
  • the first image data corresponding to one pixel is composed of 24-bit RGB data and control signals, and the three colors each correspond to 8 bits; and each 8-bit data synthesizes the pixel value of one color, and the pixels of three colors The value is then synthesized as the pixel value of the pixel; the rearrangement in the preset rules includes: only valid control signals and valid image data are retained.
  • the valid image data includes, but is not limited to, the output of RGB colors arranged out of order, Arrange according to the data sequence (also called the sequence) that can correctly reflect the different color pixel values of each pixel; therefore, the image data can be arranged in sequence according to the preset rules, and then input to the imaging controller 3 for The imaging controller 3 can complete subsequent image processing operations more efficiently.
  • the number of data processors 2 is two, correspondingly, the number of second low-voltage differential signal receivers 31 of the imaging controller 3 is two, and two second low-voltage
  • the differential signal receiver 31 is connected to two second low voltage differential signal transmitters 23 through two sets of second signal transmission lines, or the second low voltage differential signal receiver 31 is composed of two or more second low voltage
  • the differential signal receiver 31 is integrated together.
  • the remapping processing of the image data by the data processor 2 includes but not limited to the following three methods:
  • the data processor 2 (the data processor 2 can have multiple types, the FPGA shown in FIG. 5 is one of them) is configured to pass through the first signal transmission line (attached) in each first cycle (LVDS1-TA, LVDS1-TB, LVDS1-TC, LVDS1-TD, LVDS1-TE, and TCLK shown in Figure 5) receive the first image data once and compare the first image data in the order in which the first image data is received. Perform a first remapping process and a quantization compression process to sequentially obtain second image data having a first preset format and a first preset number of bits, and cache the second image data in the buffer unit 21, where each The second image data corresponds to one pixel data.
  • Table 1 is a data format table of the first image data received by the first low-voltage differential signal receiver 23 within one clock pulse period.
  • the first low-voltage differential signal transmitter 12 In a clock pulse period, the TCLK line transmission signal corresponding to the first signal transmission line is expressed as: H, H, L, L, L, H, H; the LVDS1-TA line transmission data corresponding to the first signal transmission line is expressed as: R4, R5, R6, R7, 0, 0, HSYHQ; LVDS1-TB line transmission data corresponding to the first signal transmission line is expressed as: B3, B4, B5, B6, B7, 0, 0; LVDS1-TC corresponding to the first signal transmission line
  • the line transmission data is expressed as: 0, VD, HD, R0, R1, R2, R3; the LVDS1-TD line transmission data corresponding to the first signal transmission line is expressed as: G6, G7, 0, 0, B0, B1, B2;
  • R represents red pixel data
  • G represents blue pixel data
  • B represents green pixel data
  • 0 represents no data
  • HSYHQ, VD, and HD represent control signals, respectively, where HSYHQ represents line synchronization signal, VD represents a valid data enable signal, and HD represents a page synchronization signal.
  • HSYHQ represents line synchronization signal
  • VD represents a valid data enable signal
  • HD represents a page synchronization signal.
  • the arrangement of the output data of the first low-voltage differential signal transmitter 12 produced by different manufacturers may be different.
  • Table 1 only represents an exemplary arrangement format of the first image data.
  • the first image data output by the low-voltage differential signal transmitter 12 can also be arranged in other ways, and different data arrangements match different remapping rules, specifically according to the preset of the manufacturer of the first low-voltage differential signal transmitter 12 According to the transmission protocol, this application does not limit it.
  • Table 2 is the data format of a second image data generated after the data processor 2 in this embodiment performs the first remapping processing and quantization compression processing on the first image data listed in Table 1. table.
  • the number of low-voltage differential signal ports corresponding to the second low-voltage differential signal transmitter 23 is 4 groups, and the second signal transmission line includes 3 For data lines (such as LVDS2-TA, LVDS2-TB and LVDS2-TC in Figure 5) and a pair of clock lines (such as TCLK in Figure 5), a clock in the second low-voltage differential signal receiver 31
  • the TCLK line transmission signal corresponding to the second signal transmission line is expressed as: H, H, L, L , L, H, H
  • the LVDS2-TA line transmission data corresponding to the second signal transmission line is expressed as: HSYHQ, R7, R6, R5, R4, R3
  • the LVDS2-TB line transmission data corresponding to the second signal transmission line is expressed as: VD , G7, G6, G5, G4, G3, G2;
  • LVDS2-TA line transmission data corresponding to the second signal transmission line is expressed as: VD , G7, G6, G5, G4, G3, G2;
  • the quantization compression process specifically converts 24-bit RGB data into 16-bit RGB data, that is, it will have the RGB888 format (that is, including 8-bit R pixel data, 8-bit G pixel data And 8-bit B pixel data) the first image data is converted into RGB565 format (that is, including 5-bit R pixel data, 6-bit G pixel data and 5-bit B pixel data) second image data, in other embodiments, also The first image data in the RGB888 format can be converted into the second image data in the RGB555 format (that is, including 5-bit R pixel data, 5-bit G pixel data, and 5-bit B pixel data), because the second low-voltage differential signal transmitter 23 Including 3 pairs of data lines.
  • each pair of data lines transmits 7 bits of data, that is, the second low-voltage differential signal transmitter 23 supports the transmission of up to 21 bits in addition to the clock signal.
  • Data the first image data is quantized and compressed, so that the second low-voltage differential signal transmitter 23 also outputs the second image data corresponding to one pixel to the second low-voltage differential signal of the imaging controller 3 in the first cycle Receiver 31 (not shown in Figure 5).
  • the first image data is subjected to first remapping processing and quantization compression processing, so that the second low-voltage differential signal transmitter 23 can output the second image data corresponding to one pixel under one clock pulse, and the first low
  • the clock frequency of the voltage differential signal transmitter 12 and the second low voltage differential signal transmitter 23 can be set to be the same. Therefore, the first low voltage differential signal transmitter 12 and the second low voltage differential signal transmitter 23 can achieve the same frequency.
  • the clock frequency of the first low-voltage differential signal transmitter 12 is 66.38Mhz, while the clock frequency of the low-voltage differential signal port prefabricated by the second low-voltage differential signal receiver 31 of the imaging controller 3 currently supports a maximum of 100Mhz. So it fully meets business needs.
  • the data processor 2 sequentially performs the first remapping process and the quantization compression process on the first image data, then sequentially generates the second image data, and sequentially converts the second image data into
  • the second low-voltage differential signal transmitter 23 ( Figure 5) is buffered into the internal buffer unit 21 (such as Buffer A shown in FIG. 5). (Not shown in) start to send the second image data to the second low-voltage differential signal receiver 31 (not shown in FIG. 5) through the second signal transmission line, where N is the number of pixels corresponding to a row of images, and That is, the buffer unit 21 buffers the second image data in rows.
  • N is 1024
  • the second low voltage difference The signal receiver 31 sequentially outputs the second image data in the second cycle.
  • the imaging controller 3 further includes a control module (the control module may be of multiple types, and the CPU shown in FIG. 5 is one of them) and an image data processor.
  • the image data processor includes, but is not limited to, the CISX module (the CISX module is configured to separate R, G, and B image data), PIC (Pixel Image Correction, image pixel correction) module, PIE (Pixel Image Enhancement, image pixel enhancement) ) Modules and memory modules (the memory modules can be multiple, as shown in Figure 5, DDR (Double Data Rate SDRAM, double rate SDRAM) is one of them), the CIXX module is connected to the second low voltage differential Between the signal receiver 31 and the PIC module, the PIC module is connected with the PIE module, and the PIC module and the PIE module are respectively connected with the storage module.
  • the control module of the imaging controller 3 is configured to generate control instructions, and the image data processor is configured to read the second image data buffered in the buffer unit 21 through the second signal transmission line once in each second cycle, and according to the control The instruction performs quantization compensation processing on the second image data, where the second cycle is equal to the first cycle.
  • the current PC personal computer, personal computer
  • the second image data needs to be quantified and compensated by the image data processor.
  • the data format of the second image data is RGB888 format.
  • the PIC module receives the second image data through the second low-voltage differential signal receiver 31 and the CISX module.
  • the PIC module is used to perform quantization compensation processing on the second image data under the intervention of the CPU, and quantize compensation
  • the processed second image data is stored in the DDR, and then the CPU processes the second image data stored in the storage module into a plane format, and then controls the DDR to send the quantized and compensated second image data to the plane format.
  • the PIE module performs further processing. After the PIE module processes the processed image data, it saves the processed image data into the DDR, and then the image data processor uses the USB interface (in other embodiments, it may also be other interfaces, such as a network interface).
  • the image data is sent to a PC (personal computer) to complete the scanning operation.
  • performing quantization and compensation processing on the second image data according to the control instruction is specifically converting the second image data from RGB565 format or RGB555 format to RGB888 format.
  • the specific implementation process is to add 0 to the low bits of each second image data.
  • the format of the second image data after 0 is added is shown in Table 3.
  • the data processor 2 sequentially remaps and quantizes and compresses the received first image data, so that the imaging controller 3 can continuously and continuously receive the two images under the premise of insufficient interface resources.
  • the image data output by each image reader 1 does not need to change the existing structure of the imaging controller 3 and fully utilizes the existing resources of the imaging controller 3, which is beneficial to the further development of scanning technology.
  • the number of buffer units 21 (such as Buffer B and Buffer C shown in FIG. 6) is two, and the two buffer units 21 are constructed as a ping-pong buffer (double buffer) structure
  • the data processor 2 (the control module can be of multiple types, the FPGA shown in Figure 6 is one of them) is configured to pass the first signal transmission line (as shown in Figure 6) in each first cycle LVDS1-TA, LVDS1-TB, LVDS1-TC, LVDS1-TD, LVDS1-TE and TCLK) receive the first image data once and remap the first image data according to the order in which the first image data is received Processing to sequentially obtain second image data having a second preset format and a second preset number of bits, and cache the generated second image data in one of the two cache units 21, where: Every three second image data corresponds to two first image data.
  • Table 4 is a data format table of the two first image data received by the first low-voltage differential signal receiver 22 in two adjacent clock pulse cycles (1TCLK and 2TCLK).
  • the TCLK line transmission signal corresponding to the first signal transmission line is expressed as: H, H, L, L, L, H, H;
  • the LVDS1-TA line transmission data corresponding to the first signal transmission line is expressed as: R4, R5, R6, R7, 0, 0, HSYHQ;
  • the LVDS1-TB line transmission data corresponding to the first signal transmission line is expressed as: B3, B4, B5, B6, B7, 0, 0;
  • LVDS1-TC line transmission data corresponding to the first signal transmission line is expressed as: 0, VD, HD, R0, R1, R2, R3; LVDS1-TD line transmission corresponding to the first signal transmission line
  • the data is expressed as: G6, G7, 0, 0, B0, B1, B2;
  • the LVDS1-TE line transmission data corresponding to the first signal transmission line is expressed as: 0, G0, G1, G2, G3, G4, G5.
  • R represents red pixel data
  • G represents blue pixel data
  • B represents green pixel data
  • 0 represents no data
  • HSYHQ, VD, and HD represent control signals, respectively, where HSYHQ represents line synchronization signal, VD represents a valid data enable signal, and HD represents a page synchronization signal.
  • VD represents a valid data enable signal
  • HD represents a page synchronization signal.
  • the arrangement of the output data of the first low-voltage differential signal transmitter 12 produced by different manufacturers may be different.
  • Table 1 only represents an exemplary arrangement format of the first image data.
  • the first image data output by the low-voltage differential signal transmitter 12 can also be arranged in other ways, and different data arrangements match different remapping rules, specifically according to the preset of the manufacturer of the first low-voltage differential signal transmitter 12 According to the transmission protocol, this application does not limit it.
  • Table 5 is a data format table of three second image data generated after the data processor 2 in this embodiment performs the second remapping process on the first image data in Table 4, where the first The second low-voltage differential signal transmitter 23 sends a second image data to imaging in each clock pulse period (in this embodiment, the second low-voltage differential signal transmitter 23 uses each clock pulse period as the second period). Controller 3.
  • the ping-pong buffer (double buffer) structure means that when one of the buffer units 21 is writing data, the other buffer unit 21 is outputting data at the same time, and the buffer unit 21 that has written the data in the next cycle outputs data, and The other buffer unit 21 buffers the written data.
  • the two buffer units 21 alternately output and send data.
  • one of the cache units 21 caches the second image data corresponding to a row of pixels and then switches to the other cache unit 21 to cache the data, and so on.
  • the number of low-voltage differential signal ports corresponding to the second low-voltage differential signal transmitter 23 is 4 pairs, and the second signal transmission line includes 3 pairs of data lines (as shown in FIG. 8).
  • LVDS2-TA, LVDS2-TB and LVDS2-TC) and a pair of clock lines (such as TCLK in Figure 6),
  • the imaging controller 3 is configured to obtain the second image data of one of the two buffer units 21 once in each third period, where the first period may be 1.5 times the third period .
  • the number of corresponding lines of the first signal transmission line is greater than the number of corresponding lines of the second signal transmission line, the number of data bits transmitted by the second signal transmission line in the same time is less than the number of data bits transmitted by the first signal transmission line.
  • the second remapping process is performed on the first data so that the bit number of the second image data can be 2/3 times the bit number of the first image data.
  • the output frequency of the second low-voltage differential signal transmitter 23 is increased. In this way, the number of ports of the second low-voltage differential signal receiver 31 corresponding to the imaging controller 3 is reduced, thereby ensuring the normal reception and processing of image data.
  • the output frequency of the second low-voltage differential signal transmitter 23 is 3/2 times the output frequency of the first low-voltage differential signal transmitter 12.
  • the second method does not need to perform quantization and compression processing on the first image data, so that the formed image can have higher accuracy.
  • the data processor 2 further includes a data screening unit (not shown in the figure).
  • the data screening unit is used to remove useless data (invalid data).
  • the data filtering unit removing useless data may include but not limited to the following two methods:
  • the first type extract the first control signal (VD) in the first image data, when the first control signal is a preset signal (for example, "0"), confirm that the first image data is useless data, and set the One image data is deleted.
  • VD first control signal
  • the second type determine the first time and the second time; and delete the first image data obtained by one of the two sensors 11 at the first time, and delete the other sensor of the two sensors after the second time The acquired first image data is deleted.
  • the two sensors 11 may be in a positional relationship that is not completely up and down, so as to prevent the two sensors 11 from causing interference to each other when acquiring image data. Interference.
  • This design of staggering the layout of the two sensors 11 makes the time when the two sensors 11 acquire the first image data of the document to be scanned are different.
  • the front data of the document to be processed is scanned first. , It is necessary to delete the useless data collected after scanning the front data from the image data collected by the sensor 11, and it is also necessary to remove the redundant data collected before scanning the back data from the image data collected by the sensor 11.
  • the first moment is the moment when the document to be scanned leaves one of the sensors 11, and the second moment is the moment when the document to be scanned reaches the other sensor 11.
  • the data obtained by the first low-voltage differential signal receiver 22 is screened by the data screening unit, and the first image data retained after screening can be subjected to remapping processing, and then the generated second image data Cached in the cache unit 21.
  • the space of the buffer unit 21 can be saved, and the clock frequency of the second low-voltage differential signal receiver 31 of the imaging controller 3 can be reduced to satisfy the second low voltage of the imaging controller 3.
  • the voltage differential signal receiver 31 requires the clock frequency. What you need to know is that the low voltage differential signal port in the second low voltage differential signal receiver 31 of the current imaging controller 3 only supports a speed of 100Mhz, without reducing the existing image Under the premise of the output frequency of the reader (66.38MHz), the first image data is filtered by the data filtering unit, so that the clock frequency of the second low-voltage differential signal receiver 31 of the imaging controller 3 can be equal to or lower than Requires 100Mhz.
  • FIG. 7 shows a signal timing diagram of the image data output by the image reader 1 in an embodiment of the present application.
  • the output data of the first low-voltage differential signal transmitter 12 includes a pixel signal (DATA). , Control signal (HCYNC, HD and VD) and clock signal (TCLK), as the effective data enable signal HD, when it is low, the pixel signal is the effective signal, combined with Table 6 and attached Figure 6, Image reading
  • DATA pixel signal
  • Control signal HYNC, HD and VD
  • TCLK clock signal
  • data screening unit is not limited to be applied to the second method above, and may also be applied to any one of the first, third, and other embodiments of the present application.
  • the imaging controller 3 is configured to obtain the second image data of one of the two buffer units 21 once in each third period, where the first period may be 1.5 times the third period It can be understood that, after the data screening unit is adopted, the first period can also be 1 times, 1.2 times, or other times the third period.
  • the imaging controller 3 further includes a control module (the control module can be of multiple types, and the CPU shown in FIG. 6 is one of them) and an image data processor, etc.
  • a control module the control module can be of multiple types, and the CPU shown in FIG. 6 is one of them
  • an image data processor etc.
  • the CISX module the CISX module is configured to separate R, G, and B image data
  • PIC Pixel Image Correction, image pixel correction
  • PIE Panel Image Enhancement, image pixel enhancement
  • storage module There can be multiple storage modules.
  • the DDR (Double Data Rate SDRAM) shown in Figure 6 is one of them.
  • the CISX module is connected to the second low-voltage differential signal receiver 31 (not shown in Figure 6). (Shown) and the PIC module, the PIC module is connected with the PIE module, and the PIC module and the PIE module are respectively connected with the storage module.
  • the PIC module obtains the second image data through the second low-voltage differential signal receiver 31. After receiving the second image data, the PIC module performs pixel correction processing on the second image data, and then the processed The second image data is stored in the DDR, and then the CPU processes the second image data stored in the DDR into a plane format, and then controls the DDR to send the quantized and compensated second image data to the PIE in the plane format The module performs further processing. After processing, the PIE module saves the processed image data in the DDR, and then the second image data processor uses the USB interface (in other embodiments, it may also be other interfaces, such as a network interface). The image data is sent to a PC (personal computer) to complete the scanning operation.
  • PC personal computer
  • the number of buffer units 21 is three, and the three buffer units 21 are respectively a first buffer unit (such as Buffer D shown in FIG. 8) and a second buffer unit (such as Buffer E shown in Figure 8 and the third buffer unit (such as Buffer F shown in Figure 8);
  • the data processor 2 (the data processor 2 can have multiple types, the FPGA shown in FIG. 8 is one of them) is specifically configured to pass through the first signal transmission line (as shown in FIG. 8) in each first cycle.
  • LVDS1-TA, LVDS1-TB, LVDS1-TC, LVDS1-TD, LVDS1-TE, and TCLK shown) receive the first image data and perform the third remapping of the first image data according to the order in which the first image data is received Processing to sequentially obtain second image data having a third preset format and a third preset number of bits, where the second image data includes red pixel data, blue pixel data, and green pixel data; and red pixels to be obtained
  • the data, blue pixel data and green pixel data are respectively buffered in the first buffer unit, the second buffer unit and the third buffer unit.
  • Table 1 is a data format table of the first image data received by the first low-voltage differential signal receiver 22 in one clock pulse period.
  • the first low-voltage differential signal transmitter 12 In a clock pulse period, the TCLK line transmission signal corresponding to the first signal transmission line is expressed as: H, H, L, L, L, H, H; the LVDS1-TA line transmission data corresponding to the first signal transmission line is expressed as: R4, R5, R6, R7, 0, 0, HSYHQ; LVDS1-TB line transmission data corresponding to the first signal transmission line is expressed as: B3, B4, B5, B6, B7, 0, 0; LVDS1-TC corresponding to the first signal transmission line
  • the line transmission data is expressed as: 0, VD, HD, R0, R1, R2, R3; the LVDS1-TD line transmission data corresponding to the first signal transmission line is expressed as: G6, G7, 0, 0, B0, B1, B2;
  • R represents red pixel data
  • G represents blue pixel data
  • B represents green pixel data
  • 0 represents no data
  • HSYHQ, VD, and HD represent control signals, respectively, where HSYHQ represents line synchronization signal, VD represents a valid data enable signal, and HD represents a control page synchronization signal.
  • VD represents a valid data enable signal
  • HD represents a control page synchronization signal.
  • the arrangement of the output data of the first low-voltage differential signal transmitter 12 produced by different manufacturers may be different.
  • Table 1 only represents an exemplary arrangement format of the first image data.
  • the first image data output by the low-voltage differential signal transmitter 12 can also be arranged in other ways, and different data arrangements match different remapping rules, specifically according to the preset of the manufacturer of the first low-voltage differential signal transmitter 12 According to the transmission protocol, this application does not limit it.
  • Table 8 is a data format table for generating the second image data after the data processor 2 in this embodiment performs the third remapping process on one of the first image data listed in Table 1.
  • the number of low-voltage differential signal ports corresponding to the second low-voltage differential signal transmitter 23 is 3 groups, and the second signal transmission line includes two pairs of data lines (as shown in FIG. 8).
  • LVDS2-TA and LVDS2-TB) and a pair of clock lines such as TCLK in FIG. 8
  • each pair of data lines transmits 7 bits of data
  • the second low-voltage differential signal transmitter 23 can support the transmission of up to 14 bits of data in one transmission period.
  • the data processor 2 remaps each first image data to generate Generate red pixel data, blue pixel data, and green pixel data, respectively, so that the second low-voltage differential signal transmitter 23 sends the red pixel data, blue pixel data, and green pixel data corresponding to one pixel in turn according to the transmission cycle, wherein, Red pixel data includes: HSYHQ, R7, R6, R5, R4, R3, R2, VD, R1, R0, 0, 0, 0, 0; blue pixel data includes: HSYHQ, B7, B6, B5, B4, B3 , B2, VD, B1, B0, 0, 0, 0, 0; Green pixel data includes HSYHQ, G7, G6, G5, G4, G3, G2, G0, G0, 0, 0, 0, 0.
  • the second low-voltage differential signal transmitter 23 transmits three in turn according to its clock pulse period (in mode three, the clock pulse period of the second low-voltage differential signal transmitter 23 is the third period)
  • the red pixel data, blue pixel data, and green pixel data are respectively buffered in the buffer unit 21.
  • the TCLK line transmission signal corresponding to the second signal transmission line is expressed as: H, H, L, L, L, H, H;
  • the second signal transmission line corresponds to LVDS2 -TA line transmission data is expressed as: HSYHQ, R7, R6, R5, R4, R3, R2;
  • the LVDS2-TB line transmission data corresponding to the second signal transmission line is expressed as: VD, R1, R0, 0, 0, 0, 0 ;
  • the TCLK line transmission signal corresponding to the second signal transmission line is expressed as: H, H, L, L, L, H, H;
  • the transmission data of the LVDS2-TA line corresponding to the second signal transmission line is expressed as: HSYHQ, B7, B6, B5, B4, B3, B2;
  • the transmission data of the LVDS2-TB line corresponding to the second signal transmission line is expressed as: VD, B1, B0, 0 , 0,
  • the imaging controller 3 is configured to receive the red pixel data of the first buffer unit, the blue pixel data of the second buffer unit, and the second buffer unit in turn once in each first cycle through the second low-voltage differential signal receiver 31 Three buffer unit green pixel data.
  • the data processor 2 does not limit the receiving order of the red pixel data, blue pixel data, and blue pixel data in this application.
  • the first period is three times the third period.
  • the clock frequency of the second low-voltage differential signal receiver 31 is three times that of the first low-voltage differential signal receiver 22.
  • the data processor 2 sequentially performs the third remapping process on the first image data, remaps one piece of first image data to obtain red pixel data, blue pixel data, and green pixel data, and then converts the red The pixel data, the blue pixel data, and the green pixel data are respectively buffered in the three buffer units 21.
  • the three buffer units 21 respectively buffer the red pixel data, blue pixel data and green pixel data corresponding to a row of pixels, the three The buffer unit 21 starts to output data in turn.
  • this embodiment obtains red pixel data, blue pixel data, and green pixel data by performing the third remapping process on the first image data, and buffers the red pixel data, blue pixel data, and green pixel data respectively.
  • the data processor 2 may further include a data screening unit (not shown in the figure).
  • a data screening unit please refer to the corresponding content in the second mode, which will not be repeated here.
  • the space of the buffer unit 21 can be saved, and the clock frequency of the second low-voltage differential signal receiver 31 of the imaging controller 3 can be reduced to satisfy the second low voltage of the imaging controller 3.
  • the voltage differential signal receiver 31 requires clock frequency.
  • the image reader 1 scans one line each time, the image reader 1 outputs 11218 pixels through the first low-voltage differential signal transmitter 12. Pixel) data, but the actual useful data is only 7500 pixels.
  • the frequency of the LVDS CLK the clock signal of the first low-voltage differential signal receiver 22
  • the LVDS CLK from the data processor 2 to the imaging controller 3 It can be determined according to the number of effective data actually transmitted.
  • the frequency of LVDS CLK from image reader 1 to data processor 2 is reduced, and LVDS CLK is set to 99Mhz (10.1ns), then the time of 24000 LVDS CLK is 242.4us, and there are 11218 points in one TR cycle.
  • the imaging controller 3 also includes a control module (the control module can be multiple, the CPU shown in FIG. 8 is one of them) and an image data processor, etc.
  • a control module the control module can be multiple, the CPU shown in FIG. 8 is one of them
  • an image data processor etc.
  • the CISX module the CISX module is configured to separate R, G, and B image data
  • PIC Pixel Image Correction, image pixel correction
  • PIE Pixel Image Enhancement, image pixel enhancement
  • storage module There can be multiple storage modules.
  • the DDR (Double Data Rate SDRAM) shown in Figure 8 is one of them.
  • the CISX module is connected to the second low-voltage differential signal receiver 31 (not shown in Figure 8). (Shown) and the PIC module, the PIC module is connected with the PIE module, and the PIC module and the PIE module are respectively connected with the storage module.
  • the CIXX module is configured to receive red pixel data, blue pixel data, and green pixel data in turn through the second low-voltage differential signal receiver 31, and combine the red pixel data, blue pixel data, and
  • the green pixel data is stored in a buffer (not shown in FIG. 8) inside the imaging controller 3; then the red pixel data, blue pixel data, and green pixel data in the buffer unit are separated and separated into planes.
  • the formats are sent to the PIC module for pixel correction processing.
  • the red pixel data, blue pixel data, and green pixel data are combined and sent to the PIE module for further processing.
  • the PIE module saves the processed image data after processing.
  • the image data processor then sends the processed image data to a PC (personal computer, personal computer) through a USB interface (in other embodiments, other interfaces, such as a network interface) to complete the scanning operation.
  • the CIXX module receives X, Y and Z data in turn and passes 3
  • the ODMA (Output Dynamic Memory Access) controller stores the received X, Y, and Z in the internal buffer of the imaging controller 3, where, as shown in Figure 9, the buffer unit is set To store X, Y, and Z in a non-interleaved manner, that is, first store all X components, then store all Y components, and finally store all Z components.
  • the module performs pixel correction processing.
  • the data processor 2 separately stores the red pixel data, the blue pixel data and the green pixel data into different buffer units and outputs them in turn, so that the CISX module can Separate the RGB data so that the PIC module can separate the separated and planar format red pixel data, blue pixel data and green pixel data, and then make full use of it compared to the first and second methods
  • the CISX module and PIC module in the imaging controller 3 have higher processing accuracy, so the output image quality is effectively improved.
  • mode three does not require a control module (such as CPU) to control the separation of RGB data, so it can effectively reduce the load of the CPU, and it also makes the CPU do not need to store the corresponding code, effectively avoiding the CPU in the code is not robust or inefficient In this case, data loss or confusion occurs due to untimely data processing.
  • a control module such as CPU
  • an embodiment of the present application provides an image forming apparatus, including a scanning device 50 in any embodiment and an imaging device 60 connected to the scanning device 50.
  • the imaging device includes but It is not limited to including an image forming unit (for example, a developing cartridge), a fixing unit, a paper transport unit, and a paper cassette.
  • an embodiment of the present application provides a scanning method, which includes:
  • Step S01 Two image readers respectively read the document to be scanned and output image data corresponding to the document to be scanned;
  • Step S02 The data processor obtains the image data through the first signal transmission line and caches it in its internal cache unit;
  • Step S03 The imaging controller reads the image data of the buffer unit through the second signal transmission line, where the number of lines corresponding to the second signal transmission line is less than the number of lines corresponding to the first signal transmission line.
  • this application uses the data processor to convert the scan data, so that the number of ports through which the imaging controller receives the scan data can match the number of configured data processor output interfaces, which solves the problem of the imaging controller receiving scans in the prior art.
  • the data processor does not need to be configured with additional memory, which reduces Reduce the development and production costs, which is conducive to the further development of scanning technology.
  • the two image readers can read the front side image data and the back side image data of the document to be scanned respectively, or both image readers can read the front side image data of the document to be scanned or two image readings. Both image readers read the reverse side image data of the document to be scanned.
  • the scanning device provided in the embodiment of the application can also be used for single-sided scanning.
  • the two image readers are located on the same side of the document to be scanned.
  • the image data output by the two image readers are both the front image data of the document to be scanned, or the image data output by the two image readers are both to be scanned The back image data of the file.
  • the document to be scanned may include, but is not limited to: at least one of a document, a certificate, an image, and a photo, which is not particularly limited in the embodiment of the present application.
  • the imaging controller 3 is an SoC (System on Chip).
  • the SoC is a miniature system composed of multiple system components and is configured to control the imaging processing operations of the scanned image of the scanning device, such as The data is processed by linear correction, noise reduction, dead pixel removal, detail enhancement, etc., thereby improving the quality of image output.
  • the imaging controller 3 is also used to perform data transmission and reception, command transmission and reception, and engine control related processing operations for printing images, such as through Interface units (including but not limited to USB ports, wired network ports, wireless network ports or other interfaces, etc.) to send and receive data, print engine control commands, status, etc.
  • the imaging controller 3 simultaneously controls the scanning operation of the scanning device and the imaging operation of the imaging device, but this embodiment is not limited to this.
  • an independent imaging controller may be configured for the scanning device and the imaging device. It belongs to the protection scope of this embodiment.
  • the data processor is a programmable logic device, specifically an FPGA (Field-Programmable Gate Array).
  • the data processor may also be a CPLD (Complex Programmable Logic Device, complex data processor) and other programmable devices.
  • the data processor obtains the image data through the first signal transmission line and caches the image data in the internal cache unit, which specifically includes:
  • the data processor obtains image data through the first signal transmission line and performs remapping processing on each image data to obtain second image data, and caches the second image data in the buffer unit.
  • the image data needs to be remapped to obtain the second image data with the preset format, so that the imaging The controller can obtain the second image data continuously and uninterruptedly and process the second image data under the premise of meeting its own receiving frequency.
  • the image reader includes a sensor and a first low-voltage differential signal transmitter.
  • the two image readers respectively read the document to be scanned and output image data corresponding to the document to be scanned, specifically including:
  • the sensor reads the document to be scanned and outputs image data corresponding to the document to be scanned, where the image data includes at least one first image data;
  • the first low-voltage differential signal transmitter receives at least one piece of first image data and outputs one piece of first image data through the first signal transmission line in a differential transmission manner in each first period, where each piece of first image data corresponds to one Pixel data.
  • the two sensors may be the first sensor (for example, CIS or CCD) and the second sensor (for example, CIS or CCD) mentioned above.
  • the sensors are configured to scan each line by line. Pixels are converted into corresponding analog signals, where a line of image includes several pixels, such as 1024 pixels.
  • the image reader further includes an analog-to-digital conversion unit, which is connected between the sensor and the first low-voltage differential signal transmitter, and is used to convert the analog signal output by the sensor into a digital signal and output it to the first low-voltage differential signal transmitter.
  • a low-voltage differential signal transmitter is used to output the received digital signal to the data processor through the first signal transmission line in a pixel-by-pixel manner according to a preset clock cycle, that is, the first low-voltage differential signal
  • the signal transmitter outputs the first image data corresponding to one pixel to the data processor in each clock pulse period (in this document, the clock pulse period of the first low-voltage differential signal transmitter is the "first period").
  • first image data and the generated second image data may have a one-to-one correspondence, or the first image data may generate multiple second image data correspondingly, or the multiple first image data may generate one first image data correspondingly. Two image data, or multiple first image data corresponding to multiple second image data.
  • the data processor further includes a first low voltage differential signal (LVDS) receiver and a second low voltage differential signal (LVDS) transmitter, and the imaging controller includes a second low voltage signal.
  • LVDS low voltage differential signal
  • LVDS Low Voltage Differential Signaling
  • the first low voltage differential signal receiver is connected to the first low voltage differential signal transmitter through a first signal transmission line, and the data processor receives the first image data through the first low voltage differential signal receiver.
  • the second low-voltage differential signal transmitter is connected to the buffer unit and connected to the second low-voltage differential signal receiver through the second signal transmission line, and the second low-voltage differential signal transmitter is configured to transmit differentially through the second signal transmission line
  • the second image data buffered in the buffer unit is output to the imaging controller, and the imaging controller receives the second image data through the second low-voltage differential signal receiver.
  • the first low-voltage differential signal transmitter is configured to output the first image data generated by the sensor in a pixel-by-pixel manner.
  • a pixel is represented by 24-bit RGB data.
  • the 24-bit RGB data includes 8-bit R (red) pixel data (R7, R6, R5, R4, R3, R2, R1, R0), 8-bit G (Blue) pixel data (G7, G6, G5, G4, G3, G2, G1, G0) and 8-bit B (green) pixel data (B7, B6, B5, B4, B3, B2, B1, B0),
  • the first image data corresponding to a pixel is composed of 24-bit RGB data and control signals.
  • LVDS converts parallel pixel signals and control signals into serial bit streams, which are transmitted through multiple sets of wires , The clock pulse signal is transmitted by a set of wires alone.
  • each first low-voltage differential signal transmitter 12 Since each data channel of the first low-voltage differential signal transmitter 12 outputs a 7-bit serial data signal in one clock pulse period, each first low-voltage differential signal transmitter 12 corresponds to a group of transmission lines, and each group The transmission line requires 5 pairs of data lines and 1 pair of clock lines.
  • the first image data is transmitted through the first signal transmission line composed of the data line and the clock line.
  • each first low voltage The differential signal transmitter 12 has 6 pairs of low-voltage differential signal ports (the number of data transmission ports is 5 and the number of clock signal transmission ports is 1, because the LVDS signal output lines are arranged in pairs, and each channel corresponds to 1 pair of signal lines, so the number of ports can also be "pairs"); each data processor needs 6 pairs of low-voltage differential signal receiving ports, and the data processor of the entire scanning device needs at least 12 pairs of low-voltage differential signals. Signal receiving port.
  • the remapping process is specifically a process of rearranging the sequence of the RGB pixel data, clock signals, and control signals corresponding to the first image data according to a preset mapping rule.
  • the data processor obtains the image data through the first signal transmission line and remaps each image data to obtain the second image data, and caches the second image data in the buffer unit, including but not limited to the following three Ways:
  • Method 1 The data processor receives the first image data once through the first low-voltage differential signal receiver in each first cycle and performs the first remapping process on the first image data according to the order in which the first image data is received And quantization compression processing to sequentially obtain the second image data having the first preset format and the first preset number of bits, and cache the second image data in the buffer unit, wherein the second image data and the first image data It is a one-to-one correspondence.
  • the imaging controller includes a controller and an image data processor, and the imaging controller reads the image data of the buffer unit through the second signal transmission line, which specifically includes:
  • the control module generates control instructions
  • the image data processor receives the second image data buffered in the buffer unit through the second signal transmission line once in each second cycle, and performs quantization and compensation processing on the second image data according to the control instruction, where the first cycle is equal to the second cycle.
  • Method 2 The number of buffer units is two, and the two buffer units are constructed as a ping-pong buffer structure;
  • Obtaining image data through the first signal transmission line and performing remapping processing on each image data to obtain second image data, and buffering the second image data in the buffer unit specifically includes:
  • the data processor receives the first image data once through the first low-voltage differential signal receiver in each first cycle, and performs the second remapping process on the first image data according to the order in which the first image data is received, so as to sequentially Obtain second image data having a second preset format and a second preset number of bits, and buffer the generated second image data into one of the buffer units, and every three second image data corresponds to two first image data .
  • the imaging controller reads the image data of the buffer unit through the second signal transmission line, which specifically includes:
  • the imaging controller receives the second image data buffered by one of the two buffer units once in each third period, where the first period is 1.5 times the third period.
  • Manner 3 The number of cache units is three, and the three cache units are respectively a first cache unit, a second cache unit, and a third cache unit;
  • the data processor obtains the image data through the first signal transmission line, performs remapping processing on each image data to obtain the second image data, and caches the second image data in the buffer unit, which specifically includes:
  • the data processor receives the first image data through the first signal transmission line in each first cycle and performs the third remapping process on the first image data according to the order in which the first image data is received, so as to sequentially obtain the Set the format and the third preset number of second image data, where the second image data includes red pixel data, blue pixel data, and green pixel data; and separate the red pixel data, blue pixel data, and green pixel data. Cached in the first cache unit, the second cache unit and the third cache unit.
  • reading the image data of the buffer unit through the second signal transmission line specifically includes:
  • the imaging controller receives the red pixel data buffered in the first buffer unit, the blue pixel data buffered in the second buffer unit, and the third buffer unit in turn in each first cycle through the second low-voltage differential signal receiver. Cached green pixel data.
  • mode 1, mode 2, and mode 3 can be referred to the above, and the details are not repeated here.
  • This embodiment provides a computer-readable storage medium with a computer program stored on the computer-readable storage medium.
  • the scanning method in the embodiment is implemented. To avoid repetition, we will not repeat them here. .
  • the computer program is executed by the processor, the function of each module/unit in the image forming apparatus in the embodiment is realized. In order to avoid repetition, it will not be repeated here.
  • an embodiment of the present application provides a scanning device 50.
  • the scanning device 50 of this embodiment includes: a processor 51, a memory 52, and a computer program 53 stored in the memory 52 and running on the processor 51
  • the computer program 53 is executed by the processor 51, the scanning method in the embodiment is implemented. To avoid repetition, it will not be repeated here.
  • the computer program is executed by the processor 51, the function of each model/unit in the scanning device in the embodiment is realized. In order to avoid repetition, it will not be repeated here.
  • the scanning device 50 can be a computing device such as a desktop computer, a notebook, a palmtop computer, and a cloud server.
  • the scanning device 50 may include but is not limited to a processor 51 and a memory 52.
  • FIG. 8 is only an example of the scanning device 50, and does not constitute a limitation on the scanning device 50. It may include more or less components than shown in the figure, or combine certain components, or different components.
  • computer equipment may also include input and output devices, network access devices, buses, and so on.
  • the processor 51 may be a central processing unit (Central Processing Unit, CPU), other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (ASIC), and on-site Field-Programmable Gate Array (FPGA) or other data processors, discrete gates or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the memory 52 may be an internal storage unit of the scanning device 50, such as a hard disk or a memory of the scanning device 50.
  • the memory 52 may also be an external storage device of the scanning device 50, such as a plug-in hard disk equipped on the scanning device 50, a smart memory card (Smart Media Card, SMC), a Secure Digital (SD) card, and a flash memory card (Flash). Card) etc.
  • the memory 52 may also include both an internal storage unit of the scanning device 50 and an external storage device.
  • the memory 52 is used to store computer programs and other programs and data required by the scanning device.
  • the memory 52 can also be used to temporarily store data that has been output or will be output.

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Abstract

本申请涉及一种扫描设备、图像形成装置、扫描方法及存储介质，该扫描设备包括：两个图像读取器，分别被配置为读取待扫描文件并输出与待扫描文件对应的图像数据；数据处理器，与图像读取器通过第一信号传输线连接，数据处理器被配置为通过第一信号传输线获取图像数据并缓存至其内部的缓存单元中；及成像控制器，被配置为通过第二信号传输线读取缓存单元的图像数据，其中，第二信号传输线对应的线的数量小于第一信号传输线对应的线的数量。该扫描设备的成像控制器接收扫描数据的端口数量能够匹配所配置的扫描单元的输出接口的数量。

Description

扫描设备、图像形成装置、扫描方法及存储介质
本申请要求于2019年07月15日提交中国专利局、申请号为201910634273.4、申请名称为“扫描设备、图像形成装置、扫描方法及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中；及要求于2019年7月15日提交中国专利局、申请号为201921099789.5、申请名称为“扫描设备及图像形成装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及图像形成技术领域，具体涉及一种扫描设备、图像形成装置、扫描方法及存储介质。
背景技术
目前，为了提高读取文件的生产率和改进安静性等，现有技术中采用了具有双面扫描功能的扫描设备。
请参阅图1，其为现有技术中用于双面扫描的图像形成装置的结构示意图，如图1所示，现有技术中的图像形成装置的扫描设备为了支持双面功能对应设置了配套的硬件模块，例如ADF(Automatic Document Feeder，自动进纸器)扫描单元110、FB(Flat Panel，平板)扫描单元120及端口等，但是由于现有的SoC(System on Chip，片上系统)用于接收扫描数据的端口数量不能完全匹配所配置的扫描单元输出端口的数量，而增加SoC的端口数量会对SoC的硬件设计及芯片面积提出了更高的要求，甚至可能对SoC的其他模块造成影响，因此，不利于扫描技术的发展。
申请内容
本申请实施例提供一种扫描设备、图像形成装置、扫描方法及存储介质，能够解决现有技术中成像控制器接收扫描数据的端口数量不能完全匹配所配置的扫描单元的输出接口的数量的问题。
第一方面，本申请实施例提供了一种扫描设备，包括：
两个图像读取器，分别被配置为读取待扫描文件并输出与所述待扫描文件对应的图像数据；
数据处理器，与所述图像读取器通过第一信号传输线连接，所述数据处理器被配置为通过所述第一信号传输线获取所述图像数据并缓存至其内部的缓存单元中；及
成像控制器，被配置为通过第二信号传输线读取所述缓存单元的图像数据，其中，所述第二信号传输线对应的线的数量小于所述第一信号传输线对应的线的数量。
第二方面，本申请实施例提供了一种图像形成装置，包括上述任一项所述的扫描设备，以及与所述扫描设备连接的成像设备。
第三方面，本申请实施例提供了一种扫描方法，包括：
两个图像读取器分别读取待扫描文件并输出与所述待扫描文件对应的图像数据；
数据处理器通过第一信号传输线获取所述图像数据并缓存至其内部的缓存单元中；
成像控制器通过第二信号传输线读取所述缓存单元的图像数据，其中，所述第二信号传输线对应的线的数量小于所述第一信号传输线对应的线的数量。
第四方面，本申请实施例提供了一种存储介质，所述存储介质包括存储的程序，其中，在所述程序运行时控制所述存储介质所在设备执行上述方法。
第五方面，本申请实施例提供了一种扫描设备，包括存储器和处理器，所述存储器用于存储包括程序指令的信息，所述处理器用于控制程序指令的执行，所述程序指令被处理器加载并执行时实现上述方法的步骤。
可以理解，本申请通过在图像读取器与成像控制器之间设置数据处理器，通过数据处理器完成扫描数据的转换处理，使得成像控制器接收扫描数据的端口数量能够匹配所配置的数据处理器输出接口的数量，解决了现有技术中成像控制器接收扫描数据的端口数量不能完全匹配所配置的扫描单元的输出接口的数量的问题，并且充分利用了成像控制器的现有第二信号传输线对应端口 的资源，同时数据处理器不需要额外配置存储器，减少了开发生产成本，有利于扫描技术的进一步发展。
附图说明
下面结合附图和实施例对本申请进一步说明。
图1为现有技术中图像形成装置的结构示意图；
图2为现有技术的图像形成装置中的扫描设备的剖视图；
图3为本申请一实施例提供的扫描设备的示意性框图；
图4为图3中的扫描设备进一步的示意性框图；
图5为本申请又一实施例提供的扫描设备的示意性框图；
图6为本申请又一实施例提供的扫描设备的示意性框图；
图7为本申请实施例提供的图像读取器输出的图像数据的信号时序图；
图8为本申请又一实施例提供的扫描设备的示意性框图；
图9为图8中提供的扫描设备中的成像控制器对第二图像数据进行处理的过程示意图；
图10为本申请实施例提供的图像形成装置的示意性框图；
图11为本申请实施例提供的扫描方法的流程图；
图12为本申请又一实施例提供的扫描设备的示意性框图。
具体实施方式
为了更好的理解本申请的技术方案，下面结合附图对本申请实施例进行详细描述。
请参阅附图1-2，现有技术提供了一种图像形成装置，图像形成装置包括扫描设备及位于所述扫描设备下方的成像设备，其中，扫描设备包括但不限于ADF(Automatic Document Feeder，自动进纸器)扫描单元110和FB(Flat Bed，平板)扫描单元120，成像设备包括但不限于包括成像单元(例如显影盒)、定影单元、纸张搬动单元以及纸盒130。
进一步地，图像形成装置还包括触摸屏140，用户可以在上面点击或按压扫描或者复印图标以进行扫描或者复印操作，也可以通过该触摸屏设置图像形成装置的成像参数(例如扫描的分辨率、纸盒130内纸张的尺寸等)。
进一步地，ADF扫描单元110包括进纸口112、两个纸幅调整片111及搓纸轮113，通过调整两个纸幅调整片111之间的距离，可以调整允许放入进纸口112内纸张的尺寸，例如如果需要扫描或复印的纸张是A4，那么就把两个纸幅调整片111之间的距离调整成对应为A4的尺寸，扫描命令发送后，马达会带动搓纸轮113，搓纸轮113按张将需要扫描的纸张送入到ADF扫描单元110中的纸路通道，纸张就会被纸路上的两个传递辊轮(114，115)传送到第一传感器116或者第二传感器121的位置，第一传感器116获取到纸张上的图像，然后将纸张沿着传递辊轮117继续移动，通过排纸辊118将纸张排除到纸盘中。
本申请实施例中，对第一传感器116和第二传感器121的型号不做特别限定。优选地，第一传感器116和第二传感器121可以设置为接触式图像传感器(Contact Image Sensor，CIS)；或者，第一传感器116和第二传感器121也可以部分或者全部设置为电荷耦合器件(Charge Coupled Device，CCD)。
进一步地，FB扫描单元120设置有文稿盖，文稿盖下方设置有玻璃文稿台122，玻璃文稿台122下方有可被马达带动的第二传感器121，把文稿盖打开之后，将要扫描或者复印的纸张放在玻璃文稿台122上，马达带动第二传感器从左往右移动，进而完成扫描。
双面扫描时，第一传感器116和第二传感器121全部点亮，纸张进入纸路后，第一传感器116和第二传感器121同时获取纸张的正反面数据，以实现双面扫描。
请参阅附图3，本申请实施例提供一种扫描设备，包括：
两个图像读取器1，分别被配置为读取待扫描文件并输出与待扫描文件对应的图像数据；
数据处理器2，与图像读取器1通过第一信号传输线连接，数据处理器2被配置为通过第一信号传输线获取图像数据并缓存至其内部的缓存单元21中；及
成像控制器3，被配置为通过第二信号传输线读取缓存单元21的图像数据，其中，第二信号传输线对应的线的数量小于第一信号传输线对应的线的数量。
本实施例中，上述提及“第一信号传输线”是指第一种信号传输协议对应的传输线，第一种信号传输协议对应类型包括但不限于下文中提及的“低电压差分信号(Low Voltage Differentia l Signaling，LVDS)”，第一信号传输线具体地形式包括但不限于“软排线”、“束线”。上述提及的“第二信号传输线”是指第二种信号传输协议对应的传输线，第二种信号传输协议对应类型可以是与第一种信号传输协议对应类型相同，也可以不同，本实施例优选的实施方式为相同，例如都是“低电压差分信号(Low Voltage Differential Signaling，LVDS)；而第二信号传输线具体地形式包括但不限于PCB板中的信号传输线(例如，微带线或带状线)。优选的方式中，采用相同的信号传输协议，所以数据处理器2无需经过复杂的信号转换，也无需额外配置存储器来协助数据处理器2完成信号协议转换；仅仅使用数据处理器2内部的缓存即可完成图像数据的调整和传输。
本实施例中，上述提及第一信号传输线对应的线的数量是指：数据处理器2为了接收图像读取器1输出的图像数据，而设置的图像数据端口(或通道)数量和时钟控制信号端口(或通道)数量。第二信号传输线对应的线的数量是指：成像控制器3为了接收数据处理器2输出的图像数据，而设置的图像数据端口(或通道)数量和时钟控制信号端口(或通道)数量。而且本实施例中，图像读取器1作为单独部件销售，已经提前预制需要通过第一数量(例如X)的端口来输出扫描图像数据，并且第一数量的端口需要用第一种信号传输协议将信号输出。而成像控制器3作为单独部件销售，也已经提前预制了第二数量(例如Y)的端口来接收扫描图像数据，并且第二数量的端口需要通过第二种信号传输协议接收信号；但是预制的第一数量X<第二数量Y。
可以理解，本申请通过在图像读取器1与成像控制器3之间设置数据处理器2，通过数据处理器2完成扫描数据的转换处理，使得成像控制器3接收扫描数据的端口数量能够匹配所配置的数据处理器2输出接口的数量，解决了现有技术中成像控制器3接收扫描数据的端口数量不能完全匹配所配置的扫描单元的输出接口的数量的问题，并且充分利用了成像控制器3的现有第二信号传输线对应端口的资源，同时数据处理器2不需要额外配置存储器，减少了开发生产成本，有利于扫描技术的进一步发展。
具体地，两个图像读取器1可以分别读取待扫描文件的正面图像数据及反面图像数据，也可以是两个图像读取器1均读取待扫描文件的正面图像数据或者两个图像读取器1均读取待扫描文件的反面图像数据，可以理解的是，本申请实施例所提供的扫描设备还可以用于单面扫描，此时，两个图像读取器1位于待扫描文件的同侧，此时，根据待扫描文件需要进行扫描的一面，两个图像读取器1输出的图像数据均为待扫描文件的正面图像数据，或者，两个图像读取器1输出的图像数据均为待扫描文件的反面图像数据。
具体地，本申请实施例中，待扫描文件可以包括但不限于：文档、证件、图像和照片中至少一个，本申请实施例对此不进行特别限定。
具体地，成像控制器3为SoC(System on Chip，片上系统)，SoC是一个微型的系统，由多个系统的部件组成，被配置为控制扫描设备的扫描图像的成像处理操作，例如对图像数据进行线性纠正、降噪、坏点去除、细节增强等处理，从而提高图像输出的质量，成像控制器3还用于执行数据收发、命令收发、打印画像的引擎控制相关的处理操作，例如通过接口单元(包括但不限于USB端口、有线网络端口、无线网络端口或者其他接口等)来收发数据、打印引擎不见控制命令、状态等。本实施例中，成像控制器3同时控制扫描设备的扫描操作和成像设备的成像操作，但是本实施不限于此，例如，可以为扫描设备和成像设备分别配置一个独立的成像控制器，这些都属于本实施例的保护范围。
在本实施方式中，数据处理器2的数量为两个，两个数据处理器2分别通过两组第一信号传输线与两个图像读取器1连接以及分别通过两组第二信号传输线与成像控制器3连接，两个数据处理器2分别处理两个图像读取器1输出的图像数据。在其它实施方式中，数据处理器2还可以为由两个或者多个数据处理器2集成在一起构成，当然，数据处理器2的设置还有其它实施方式，只要符合本申请的技术方案均在本申请的保护范围内。
具体地，在本实施例中，数据处理器2为可编程逻辑器件，具体为FPGA(Field-Programmable Gate Array，现场可编程门阵列)，在其它实施方式中，数据处理器2还可以为CPLD(Complex Programmable Logic Device，复杂数据处理器2)等可编程器件。
进一步地，数据处理器2被配置为通过第一信号传输线获取图像数据并对每个图像数据进行重映射(Remapping)处理，以获得第二图像数据，并将第二图像数据缓存至缓存单元21中。
需要理解的是，由于第二信号传输线对应的线的数量小于第一信号传输线对应的线的数量，因此需要对图像数据进行重映射处理，以获得具有预设格式的第二图像数据，使得成像控制器3能够在满足自身接收频率的前提下获得连续、不间断地获得图像数据，并对图像数据进行处理。为了本领域技术人员更容易理解本实施例，下文中将图像读取器在一个输出周期内输出的图像数据称为第一图像数据，将成像控制器3在一个获得周期内获得的图像数据，称为第二图像数据。
请参阅附图4，进一步地，图像读取器1包括：
传感器11，被配置为读取待扫描文件并输出与待扫描文件对应的图像数据，其中，图像数据包括至少一个第一图像数据；及
第一低电压差分信号(Low Voltage Differential Signaling，LVDS)发送器12，与传感器11连接，被配置为接收至少一个第一图像数据并在每个第一周期内通过第一信号传输线以差分传输的方式输出一个第一图像数据，其中，每个第一图像数据对应一个像素点数据。
具体地，两个传感器11可以分别为上文的第一传感器(例如CIS或者CCD)116及第二传感器(例如CIS或者CCD)121，在本实施方式中，传感器11被构造为以逐行扫描的方式将各个像素转化为对应的模拟信号，其中，一行图像包括若干个像素点，例如1024个像素点。
具体地，图像读取器1还包括模数转换单元(图未示)，模数转换单元连接于传感器11与第一低电压差分信号发送器12之间，用于将传感器11输出的模拟信号转换为数字信号并输出给第一低电压差分信号发送器12。更具体地，图像读取器1按照行同步信号逐行输出图像数据，同时还设置有图像数据发送时钟(TCLK)，每个图像数据发送时钟(TCLK)输出一个像素点对应的数据。第一低电压差分信号发送器12用于将接收到的数字信号按照预设的时钟周期以逐像素的方式通过第一信号传输线输出给数据处理器2，即第一低电压差分信号发送器12在每个时钟脉冲周期(在本文中，第一低电压差分信号发送器12的时钟脉冲周期为“第一周期”)内输出一个像素点对应的第一图像数据至数据处理器2。
需要知道的是，第一图像数据与生成的第二图像数据可以是一一对应关系，或者，第一图像数据对应生成多个第二图像数据，或者，多个第一图像数据对应生成一个第二图像数据，或者，多个第一图像数据对应生成多个第二图像数据。
请参阅附图4，数据处理器2还包括第一低电压差分信号(Low Voltage Differential Signaling，LVDS)接收器22及第二低电压差分信号(Low Voltage Differential Signaling，LVDS)发送器23，成像控制器3包括第二低电压差分信号(Low Voltage Differential Signaling，LVDS)接收器31。
第一低电压差分信号接收器22通过第一信号传输线与第一低电压差分信号发送器12连接，数据处理器2通过第一低电压差分信号接收器22接收第一图像数据。
第二低电压差分信号发送器23与缓存单元21连接以及通过第二信号传输线与第二低电压差分信号接收器31连接，第二低电压差分信号发送器23被配置为通过第二信号传输线以差分传输的方式输出缓存单元21内缓存的第二图像数据至成像控制器3，成像控制器3通过第二低电压差分信号接收器31接收第二图像数据。
需要知道的是，第一信号传输线的数量与第一图像数据的数据位数相关联，第二信号传输线的数量与第二图像数据的数据位数相关联。第一低电压差分信号发送器被配置为以逐像素的方式输出传感器11生成的第一图像数据。
在本实施方式中，一个像素点采用24位RGB数据表示，24位RGB数据包括8位R(红色)像素数据(R7、R6、R5、R4、R3、R2、R1、R0)、8位G(蓝色)像素数据(G7、G6、G5、G4、G3、G2、G1、G0)及8位B(绿色)像素数据(B7、B6、B5、B4、B3、B2、B1、B0)，在本实施方式中，一个像素点对应的第一图像数据由24位RGB数据及控制信号构成，根据LVDS传输机制，LVDS将并行像素信号和控制信号转换为串行比特流，通过多组导线传输，时钟脉冲信号单独采用一组导线传输。由于第一低电压差分信号发送器12在一个时钟脉冲周期内，每个数据通道都输出7bit的串行数据信号，因此，每个第一低电压差分信号发送器12对应一组传输线，每组传输线需要数据线的数量为5对及时钟线的数量为1对，通过数据线和时钟线组成的第一信号传输线对第一图像数据进行传输，在本实施方式中，每个第一低电压差分信号发送器12具有6对低电压差分信号端口(数据传输端口的数量为5及时钟信号传输端口的数量为1，因为LVDS信号输出线是按照“对”来排布的，每个通道对应1对信号线，所以端口的数量单位也可以为“对”)； 每个数据处理器分别需要6对低电压差分信号接收端口，整个扫描设备的数据处理器就至少对应需要12对低电压差分信号接收端口。
还需要知道的是，在本实施方式中，重映射处理具体为将第一图像数据对应的RGB像素数据、时钟信号及控制信号的排列顺序按照预设映射规则进行重新排列的过程。
还需要知道的是，成像控制器3的第二低电压差分信号接收器31预制的低电压差分信号端口的数量小于第一信号传输线对应的线的数量，两个图像读取器1的第一低电压差分信号发送器12预制的低电压差分信号端口的数量大于或等于第一信号传输线对应的线的数量。因此，本实施例中的预设规则主要是为了满足数据处理器的LVDS输入端口数量大于LVDS输出端口数量的需求而设置的，并且为了满足这种需求，预设规则包括数据处理器输出的图像数据的数据量(bit位数)小于或等于输入的图像数据的数据(bit位数)，并且按照输出端口数量小于输入端口数量，进行重新排列。本实施例中，一个像素点对应的第一图像数据由24位RGB数据及控制信号构成，三种颜色各自对应8位；并且每8位数据合成一种颜色的像素值，三种颜色的像素值再进行合成作为该像素点的像素值；预设规则中进行重新排列包括：仅保留有效的控制信号和有效的图像数据，有效的图像数据包括但不限于把RGB颜色错序排列的输出，按照能够正确反映每个像素点不同颜色像素值对应的数据顺序(也称先后顺序)进行排列；因此，能够按照预设规则将图像数据按照先后顺序依次排列，再输入至成像控制器3，以便成像控制器3能更高效完成后续的图像处理操作。
还需要知道的是，在本实施方式中，数据处理器2的数量为2，对应地，成像控制器3的第二低电压差分信号接收器31的数量为两个，两个第二低电压差分信号接收器31分别通过两组第二信号传输线与两个第二低电压差分信号发送器23连接，或者，第二低电压差分信号接收器31由两个或两个以上的第二低电压差分信号接收器31集成在一起构成。
进一步地，数据处理器2对图像数据的重映射处理包括但不限于以下三种方式：
方式一：
请参阅附图5，数据处理器2(数据处理器2可以有多种，附图5中所示的FPGA为其中一种)被配置为在每个第一周期内通过第一信号传输线(附图5中所示的LVDS1-TA、LVDS1-TB、LVDS1-TC、LVDS1-TD、LVDS1-TE及TCLK)接收一次第一图像数据并按照其对第一图像数据的接收顺序对第一图像数据进行第一重映射处理及量化压缩处理，以依次获得具有第一预设格式及第一预设位数的第二图像数据，并将第二图像数据缓存至缓存单元21中，其中，每个第二图像数据对应一个像素点数据。
举例来说，请参见下文的表一、表二及表三：
表一：
    bit5 bit4 bit3 bit2 bit1 bit0
TLCK H H L L L H H
LVDS1-TA R4 R5 R6 R7 0 0 HSYHQ
LVDS1-TB B3 B4 B5 B6 B7 0 0
LVDS1-TC 0 VD HD R0 R1 R2 R3
LVDS1-TD G6 G7 0 0 B0 B1 B2
LVDS1-TE 0 G0 G1 G2 G3 G4 G5
表二：
  bit6 bit5 bit4 bit3 bit2 bit1 bit0
TLCK H H L L L H H
LVDS2-TA HSYHQ R7 R6 R5 R4 R3  
LVDS2-TB VD G7 G6 G5 G4 G3 G2
LVDS2-TC HD B7 B6 B5 B4 B3  
表三：
  bit6 bit5 bit4 bit3 bit2 bit1 bit0
TLCK H H L L L H H
LVDS2-TA HSYHQ R7 R6 R5 R4 R3 0
LVDS2-TB VD G7 G6 G5 G4 G3 G2
LVDS2-TC HD B7 B6 B5 B4 B3 0
如表一所示，表一为第一低电压差分信号接收器23在一个时钟脉冲周期内接收到的第一图像数据的数据格式表，可以知道，在第一低电压差分信号发送器12的一个时钟脉冲周期内，第一信号传输线对应的TCLK线传输信号表示为：H、H、L、L、L、H、H；第一信号传输线对应的LVDS1-TA线传输数据表示为：R4、R5、R6、R7、0、0、HSYHQ；第一信号传输线对应的LVDS1-TB线传输数据表示为：B3、B4、B5、B6、B7、0、0；第一信号传输线对应的LVDS1-TC线传输数据表示为：0、VD、HD、R0、R1、R2、R3；第一信号传输线对应的LVDS1-TD线传输数据表示为：G6、G7、0、0、B0、B1、B2；第一信号传输线对应的LVDS1-TE线传输数据表示为：0、G0、G1、G2、G3、G4、G5。
需要说明的是，表一中R表示红色像素数据、G表示蓝色像素数据、B表示绿色像素数据，0表示没有数据，HSYHQ、VD及HD分别表示控制信号，其中，HSYHQ表示行同步信号，VD表示有效数据使能信号，HD表示页同步信号。例如，当HSYHQ对应的信号为“1”时，表示该第一图像数据对应的像素为一个像素行中的起始像素点或者末端像素点，当VD对应的信号为“0”时，表示该第一图像数据对应的像素为有效像素。以上仅为示例，在其它实施方式中，一个第一图像数据对应的控制信号不限于以上几种。
还需要说明的是，不同厂家生产的第一低电压差分信号发送器12输出数据的排列方式可能是不同的，表一仅代表其中的一种示例性的第一图像数据的排列格式，第一低电压差分信号发送器12的输出的第一图像数据还可以是其他的排列方式，不同的数据排列方式匹配不同的重映射规则，具体根据第一低电压差分信号发送器12生产厂家的预设的传输协议来定，本申请对此不做限定。
如表二所示，表二为本实施例中的数据处理器2对表一中列举的一个第一图像数据进行第一重映射处理及量化压缩处理之后生成的一个第二图像数据的数据格式表。
结合表二及附图5，在本实施方式中，第二低电压差分信号发送器23(图5中未示出)对应的低电压差分信号端口的数量为4组，第二信号传输线包括3对数据线(如附图5中的LVDS2-TA、LVDS2-TB及LVDS2-TC)及1对时钟线(如附图5中的TCLK)，在第二低电压差分信号接收器31的一个时钟脉冲周期(在方式一中，第一低电压差分信号发送器12的时钟脉冲周期为“第一周期”)内，第二信号传输线对应的TCLK线传输信号表示为：H、H、L、L、L、H、H；第二信号传输线对应的LVDS2-TA线传输数据表示为：HSYHQ、R7、R6、R5、R4、R3；第二信号传输线对应的LVDS2-TB线传输数据表示为：VD、G7、G6、G5、G4、G3、G2；第二信号传输线对应的LVDS3-TC线传输数据表示为：HD、B7、B6、B5、B4、B3。
需要说明的是，在本实施方式中，量化压缩处理具体为将24位的RGB数据转化为16位的RGB数据，即，将具有RGB888格式(即包括8位R像素数据、8位G像素数据及8位B像素数据)的第一图像数据转换为RGB565格式(即包括5位R像素数据、6位G像素数据及5位B像素数据)的第二图像数据，在其它实施方式中，也可以由RGB888格式的第一图像数据转换为RGB555格式(即包括5位R像素数据、5位G像素数据及5位B像素数据)的第二图像数据，由于第二低电压差分信号发送器23包括3对数据线，在第二低电压差分信号发送器23的一个发送周期中，每对数据线传输7bit的数据，即第二低电压差分信号发送器23除时钟信号以外最多支持传输21bit的数据，因此对第一图像数据进行量化压缩处理，使得第二低电压差分信号发送器23同样以第一周期输出一个像素点对应的第二图像数据至成像控制器3的第二低电压差分信号接收器31(图5中未示出)。
可以理解，由于第一信号传输线对应线的数量大于第二信号传输线对应线的数量，因此，第二信号传输线在相同时间内传输的数据位数少于第一信号传输线传输的数据位数，而本申请通过将第一图像数据进行第一重映射处理及量化压缩处理，使得第二低电压差分信号发送器23能够 在一个时钟脉冲下输出一个像素点对应的第二图像数据，且第一低电压差分信号发送器12与第二低电压差分信号发送器23的时钟频率可以设置为相同，因此，第一低电压差分信号发送器12与第二低电压差分信号发送器23可以做到同频传输，并且，第一低电压差分信号发送器12的时钟频率为66.38Mhz，而目前成像控制器3的第二低电压差分信号接收器31预制的低电压差分信号端口的时钟频率最大支持100Mhz，因此完全满足业务需求。
在本实施方式中，数据处理器2依次对第一图像数据进行第一重映射处理及量化压缩处理后，依次生成第二图像数据，并按照第二图像数据的生成顺序依次将第二图像数据缓存至其内部的缓存单元21(如附图5中所示的Buffer A)里，待缓存单元21缓存的第二图像数据的数量到N时，第二低电压差分信号发送器23(图5中未示出)开始通过第二信号传输线发送第二图像数据至第二低电压差分信号接收器31(图5中未示出)，其中，N为一行图像对应的像素点的个数，也就是说，缓存单元21按行缓存第二图像数据，当第二图像数据对应的像素点的个数到达一行图像对应的像素点的个数时(例如，N为1024)，第二低电压差分信号接收器31按第二周期依次输出第二图像数据。
请继续参阅附图5，在本实施方式中，成像控制器3还包括控制模块(控制模块可以为多种，附图5中所示的CPU为其中的一种)及图像数据处理器，其中，图像数据处理器包括但不限于CISX模块(CISX模块被配置以对R、G、B图像数据进行分离)、PIC(Pixel Image Correction，图像像素修正)模块、PIE(Pixel Image Enhancement，图像像素增强)模块及存储模块(存储模块可以为多种，如附图5中所示的DDR(Double Data Rate SDRAM，双倍速率SDRAM))为其中的一种)，CISX模块连接于第二低电压差分信号接收器31与PIC模块之间，PIC模块与PIE模块连接且PIC模块与PIE模块分别与存储模块连接。
成像控制器3的控制模块被配置为生成控制指令，图像数据处理器被配置为在每个第二周期内通过第二信号传输线读取一次缓存单元21内缓存的第二图像数据，并根据控制指令对第二图像数据进行量化补偿处理，其中，第二周期等于第一周期。可以理解地，目前PC(personal computer，个人计算机)的显示端只支持输入RGB888格式的图像数据，因此在将图像数据发送给PC之前，需要通过图像数据处理器对第二图像数据进行量化补偿处理，使得第二图像数据的数据格式为RGB888格式。
在本实施方式中，PIC模块通过第二低电压差分信号接收器31及CISX模块接收第二图像数据，PIC模块用于在CPU的干预下对第二图像数据进行量化补偿处理，并将量化补偿处理后的第二图像数据存储于DDR中，然后CPU将存储模块内存储的第二图像数据处理为平面(plane)格式，然后控制DDR以平面格式将量化补偿处理后的第二图像数据发送给PIE模块进行进一步处理，PIE模块处理后将处理后的图像数据保存至DDR内，接着图像数据处理器通过USB接口(在其它实施方式中，还可以是其它接口，例如网络接口)将处理后的图像数据发送给PC(personal computer，个人计算机)完成扫描操作。
具体地，根据控制指令对第二图像数据进行量化补偿处理具体为将第二图像数据进行RGB565格式或者RGB555格式到RGB888格式的转换，具体实现过程为在每个第二图像数据的低位进行补0，补0后的第二图像数据的格式如表3所示。
可以理解，本实施方式通过数据处理器2依次对接收到的第一图像数据进行重映射及量化压缩处理，使得成像控制器3在接口资源不够的前提下，能够不间断地、连续地接收两个图像读取器1输出的图像数据，无需改变成像控制器3的现有构造且充分利用了成像控制器3的现有资源，有利于扫描技术的进一步发展。
方式二：
请参阅附图6，在本实施方式中，缓存单元21(如附图6中所示的Buffer B及Buffer C)数量为两个，两个缓存单元21被构建为乒乓Buffer(双缓存)结构；数据处理器2(控制模块可以为多种，附图6中所示的FPGA为其中的一种)被配置为在每个第一周期内通过第一信号传输线(如附图6中所示的LVDS1-TA、LVDS1-TB、LVDS1-TC、LVDS1-TD、LVDS1-TE及TCLK)接收一次第一图像数据并按照其对第一图像数据的接收顺序对第一图像数据进行第二重映射处理，以依次获得具有第二预设格式及第二预设位数的第二图像数据，并将生成的第二图像数据缓存至两个缓存单元21中的其中一个缓存单元21内，其中，每三个第二图像数据对应两个第一图像数据。
举例来说，请参见下文的表四及表五：
表四：
Figure PCTCN2020093992-appb-000001
表五：
Figure PCTCN2020093992-appb-000002
如表四所示，表四为第一低电压差分信号接收器22在相邻的两个时钟脉冲周期(1TCLK及2TCLK)内接收到的两个第一图像数据的数据格式表。
结合表四及附图6，在第一低电压差分信号发送器12的一个时钟脉冲周期内，第一信号传输线对应的TCLK线传输信号表示为：H、H、L、L、L、H、H；第一信号传输线对应的LVDS1-TA线传输数据表示为：R4、R5、R6、R7、0、0、HSYHQ；第一信号传输线对应的LVDS1-TB线传输数据表示为：B3、B4、B5、B6、B7、0、0；第一信号传输线对应的LVDS1-TC线传输数据表示为：0、VD、HD、R0、R1、R2、R3；第一信号传输线对应的LVDS1-TD线传输数据表示为：G6、G7、0、0、B0、B1、B2；第一信号传输线对应的LVDS1-TE线传输数据表示为：0、G0、G1、G2、G3、G4、G5。
需要说明的是，表一中R表示红色像素数据、G表示蓝色像素数据、B表示绿色像素数据，0表示没有数据，HSYHQ、VD及HD分别表示控制信号，其中，HSYHQ表示行同步信号，VD表示有效数据使能信号，HD表示页同步信号。例如，当HSYHQ对应的信号为“1”时，表示该第一图像数据对应的像素为一个像素行中的起始像素或者末端像素，当VD对应的信号为“0”时，表示该第一图像数据对应的像素为有效像素。以上仅为示例，在其它实施方式中，一个第一图像数据对应的控制信号不限于以上几种。
还需要说明的是，不同厂家生产的第一低电压差分信号发送器12输出数据的排列方式可能是不同的，表一仅代表其中的一种示例性的第一图像数据的排列格式，第一低电压差分信号发送器12的输出的第一图像数据还可以是其他的排列方式，不同的数据排列方式匹配不同的重映射规则，具体根据第一低电压差分信号发送器12生产厂家的预设的传输协议来定，本申请对此不做限定。
如表五所示，表五为本实施例中的数据处理器2对表四中的第一图像数据进行第二重映射处理之后生成的三个第二图像数据的数据格式表，其中，第二低电压差分信号发送器23在每个时钟脉冲周期(在本实施方式中，第二低电压差分信号发送器23在每个时钟脉冲周期为第二周期)内发送一个第二图像数据给成像控制器3。
具体地，乒乓Buffer(双缓存)结构意指当其中一个缓存单元21在写入数据的时候，另一个缓存单元21同时在输出数据，到下一个周期写好数据的缓存单元21输出数据，而另一个缓存单元21缓存写入数据，总而言之，两个缓存单元21交替输出和发送数据。在本实施方式中，当其中一个缓存单元21缓存一行像素点对应的第二图像数据后切换至另一个缓存单元21缓存数据，如此反复。
在本实施方式中，第二低电压差分信号发送器23(附图6中未示)对应的低电压差分信号端口的数量为4对，第二信号传输线包括3对数据线(如附图8中的LVDS2-TA、LVDS2-TB及LVDS2-TC)及1对时钟线(如附图6中的TCLK)，
进一步地，成像控制器3被配置为在每个第三周期内获取一次两个缓存单元21中的其中一个缓存单元21的第二图像数据，其中，第一周期可以为第三周期的1.5倍。
可以理解，由于第一信号传输线对应线的数量大于第二信号传输线对应线的数量，因此，第二信号传输线在相同时间内传输的数据位数少于第一信号传输线传输的数据位数，通过对第一数据进行第二重映射处理使得第二图像数据的位数可以为第一图像数据位数的2/3倍，本实施例通过提高第二低电压差分信号发送器23的输出频率的方式来减少成像控制器3对应的第二低电压差分信号接收器31的端口数量，进而保证图像数据的正常接收和处理。在本实施方式中，第二低电压差分信号发送器23的输出频率为第一低电压差分信号发送器12的输出频率的3/2倍。
可以理解，方式二相较于方式一而言，无需对第一图像数据进行量化压缩处理，可以使得所形成的图像具有更高的精度。
在其它实施方式中，数据处理器2还包括数据筛选单元(图未示)，具体地，数据筛选单元用于去除无用数据(无效数据)。具体地，数据筛选单元去除无用数据可以包括但不限于以下两种方式：
第一种：提取第一图像数据中的第一控制信号(VD)，当第一控制信号为预设信号(例如为“0”)时，确认该第一图像数据为无用数据，将该第一图像数据删除。
第二种：确定第一时刻和第二时刻；以及，将第一时刻两个传感器11中的一个传感器获取到的第一图像数据删除，以及将第二时刻后两个传感器中的另一个传感器获取到的第一图像数据删除。
需要说明的是，本申请实施例提供的扫描设备用于双面扫描时，两个传感器11可以为上下不完全正对的位置关系，这样可以避免两个传感器11在获取图像数据时对彼此造成的干扰。这种将两个传感器11错开布局的设计，使得两个传感器11在获取待扫描文件的第一图像数据的时刻不同，用于双面扫描时，假设首先对扫描待处理文件的正面数据进行扫描，则需要将传感器11采集到的图像数据中扫描正面数据之后采集到的无用数据进行删除，还需要将传感器11采集到的图像数据中扫描背面数据前采集到的多余数据去掉。
基于以上所述，第一时刻为待扫描文件离开其中一个传感器11的时刻，第二时刻为待扫描文件达到另一个传感器11的时刻。
本申请实施例中，经数据筛选单元对第一低电压差分信号接收器22获取到的数据进行筛选，可以将筛选后保留的第一图像数据进行重映射处理，进而将生成的第二图像数据缓存至缓存单元21中。
可以理解，通过对第一图像数据进行筛选，可以节约缓存单元21的空间，同时降低成像控制器3的第二低电压差分信号接收器31的时钟频率，以满足成像控制器3的第二低电压差分信号接收器31时钟频率要求，需要知道的是，目前的成像控制器3的第二低电压差分信号接收器 31中低电压差分信号端口只支持100Mhz的速度，在不减少现有的图像读取器的输出频率(66.38MHz)的前提下，通过数据筛选单元对第一图像数据进行筛选，可以使得成像控制器3的第二低电压差分信号接收器31的时钟频率能够满足等于或低于100Mhz的要求。
举例来说，请参见下文的表六：
表六：
Figure PCTCN2020093992-appb-000003
请参阅附图7，附图7示出了本申请实施例中图像读取器1输出的图像数据的信号时序图，其中，第一低电压差分信号发送器12输出数据包括像素信号(DATA)、控制信号(HCYNC、HD及VD)及时钟信号(TCLK)，作为有效数据使能信号的HD，当为低电平时，像素信号为有效信号，结合表六及附图6，、图像读取器1每扫描一行，图像读取器1通过第一低电压差分信号发送器12输出11218个Pixel(像素)的数据，而实际有用的数据只有7500个pixel。这样在图像读取器1到数据处理器2(FPGA)的LVDS CLK(第一低电压差分信号接收器22的时钟信号)频率一定的情况下，数据处理器2到成像控制器3的LVDS CLK可以根据实际传输的有效数据个数来决定。假设实际传输的有效数据点数是8000个点，一个TR(repetition time，回波时间)的周期是11218*15.1ns＝169.4us，在一个TR的周期内需要传输的数据是8000个点，每个像素点为24bit RGB数据(3Byte)，则一行像素需要传输的总数据量为8000*3＝24000Byte，按1个LVDS CLK传输2个Byte计算，则需要24000/2＝12000个LVDS CLK，一行像素传输的时间是169.4uS，因此LVDS CLK的频率为169.4/12000＝14.1nS，即70.9Mhz，图像读取器1到数据处理器2的LVDS CLK频率是66.38Mhz，这样成像控制器3的LVDS CLK的频率完全满足小于100Mhz的需求。
需要知道的是，数据筛选单元不限于应用在如上的方式二中，还可以应用方式一、方式三以及本申请的其他实施例中的任一实施例中。
进一步地，成像控制器3被配置为在每个第三周期内获取一次两个缓存单元21中的其中一个缓存单元21的第二图像数据，其中，第一周期可以为第三周期的1.5倍，可以理解，在采用了数据筛选单元后，第一周期还可以为第三周期1倍、1.2倍或者其它。
请再次参阅附图6，进一步地，成像控制器3还包括控制模块(控制模块可以为多种，附图6中所示的CPU为其中一种)及图像数据处理器等，图像数据处理器包括但不限于CISX模块(CISX模块被配置以对R、G、B图像数据进行分离)、PIC(Pixel Image Correction，图像像素修正)模块、PIE(Pixel Image Enhancement，图像像素增强)模块及存储模块(存储模块可以有多种，附图6所示的DDR(Double Data Rate SDRAM，双倍速率SDRAM)为其中一种)，CISX模块连接于第二低电压差分信号接收器31(图6中未示出)与PIC模块之间，PIC模块与PIE模块连接且PIC模块与PIE模块分别与存储模块连接。
在本实施方式中，PIC模块通过第二低电压差分信号接收器31获得第二图像数据，PIC模块接收到第二图像数据后，对第二图像数据进行像素效正处理，然后将处理后的第二图像数据存储于DDR中，然后CPU将DDR内存储的第二图像数据处理为平面(plane)格式，然后控制DDR以平面(plane)格式将量化补偿处理后的第二图像数据发送给PIE模块进行进一步处理，PIE模块处理后将处理后的图像数据保存至DDR内，然后第二图像数据处理器通过USB接口(在其它实施方式中，还可以是其它接口，例如网络接口)将处理后的图像数据发送给PC(personal computer，个人计算机)完成扫描操作。
方式三：
请参阅附图8，在本实施方式中，缓存单元21的数量为三个，三个缓存单元21分别为第一缓存单元(如附图8中所示的Buffer D)、第二缓存单元(如附图8中所示的Buffer E)及第三缓存单元(如附图8中所示的Buffer F)；
数据处理器2(数据处理器2可以有多种，附图8中所示的FPGA为其中一种)具体被配置为在每个第一周期内通过第一信号传输线(如附图8中所示的LVDS1-TA、LVDS1-TB、LVDS1-TC、LVDS1-TD、LVDS1-TE及TCLK)接收第一图像数据并按照其对第一图像数据的接收顺序对第一图像数据进行第三重映射处理，以依次获得具有第三预设格式及第三预设位数的第二图像数据，其中，第二图像数据包括红色像素数据、蓝色像素数据及绿色像素数据；以及将获得的红色像素数据、蓝色像素数据及绿色像素数据分别缓存至第一缓存单元、第二缓存单元及第三缓存单元内。
举例来说，请参见下文的表七及表八：
表七：
  bit6 bit5 bit4 bit3 bit2 bit1 bit0
TLCK H H L L L H H
LVDS1-TA R4 R5 R6 R7 0 0 HSYHQ
LVDS1-TB B3 B4 B5 B6 B7 0 0
LVDS1-TC 0 VD HD R0 R1 R2 R3
LVDS1-TD G6 G7 0 0 B0 B1 B2
LVDS1-TE 0 G0 G1 G2 G3 G4 G5
表八：
Figure PCTCN2020093992-appb-000004
Figure PCTCN2020093992-appb-000005
如表七所示，表一为第一低电压差分信号接收器22在一个时钟脉冲周期内接收到的第一图像数据的数据格式表，可以知道，在第一低电压差分信号发送器12的一个时钟脉冲周期内，第一信号传输线对应的TCLK线传输信号表示为：H、H、L、L、L、H、H；第一信号传输线对应的LVDS1-TA线传输数据表示为：R4、R5、R6、R7、0、0、HSYHQ；第一信号传输线对应的LVDS1-TB线传输数据表示为：B3、B4、B5、B6、B7、0、0；第一信号传输线对应的LVDS1-TC线传输数据表示为：0、VD、HD、R0、R1、R2、R3；第一信号传输线对应的LVDS1-TD线传输数据表示为：G6、G7、0、0、B0、B1、B2；第一信号传输线对应的LVDS1-TE线传输数据表示为：0、G0、G1、G2、G3、G4、G5。
需要说明的是，表一中R表示红色像素数据、G表示蓝色像素数据、B表示绿色像素数据，0表示没有数据，HSYHQ、VD及HD分别表示控制信号，其中，HSYHQ表示行同步信号，VD表示有效数据使能信号，HD表示控制页同步信号。例如，当HSYHQ对应的信号为“1”时，表示该第一图像数据对应的像素为一个像素行中的起始像素或者末端像素，当VD对应的信号为“0”时，表示该第一图像数据对应的像素为有效像素。以上仅为示例，在其它实施方式中，一个第一图像数据对应的控制信号不限于以上几种。
还需要说明的是，不同厂家生产的第一低电压差分信号发送器12输出数据的排列方式可能是不同的，表一仅代表其中的一种示例性的第一图像数据的排列格式，第一低电压差分信号发送器12的输出的第一图像数据还可以是其他的排列方式，不同的数据排列方式匹配不同的重映射规则，具体根据第一低电压差分信号发送器12生产厂家的预设的传输协议来定，本申请对此不做限定。
如表八所示，表八为本实施例中的数据处理器2对表一中列举的一个第一图像数据进行第三重映射处理之后生成第二图像数据的数据格式表。
在本实施方式中，第二低电压差分信号发送器23(附图8中未示)对应的低电压差分信号端口的数量为3组，第二信号传输线包括2对数据线(如附图8中的LVDS2-TA及LVDS2-TB)及1对时钟线(如附图8中的TCLK)，由于在第二低电压差分信号发送器23的一个发送周期中，每对数据线传输7bit的数据，可以知道，第二低电压差分信号发送器23在一个发送周期内最多可支持传输14bit的数据，因此，在本实施方式中，数据处理器2对每个第一图像数据进行重映射后生成分别生成红色像素数据、蓝色像素数据及绿色像素数据，使得第二低电压差分信号发送器23按照发送周期轮流发送一个像素点对应的红色像素数据、蓝色像素数据及绿色像素数据，其中，红色像素数据包括：HSYHQ、R7、R6、R5、R4、R3、R2、VD、R1、R0、0、0、0、0；蓝色像素数据包括：HSYHQ、B7、B6、B5、B4、B3、B2、VD、B1、B0、0、0、0、0；绿色像素数据包括HSYHQ、G7、G6、G5、G4、G3、G2、G0、G0、0、0、0、0。
结合表八及附图8，第二低电压差分信号发送器23按照其时钟脉冲周期(在方式三中，第二低电压差分信号发送器23的时钟脉冲周期为第三周期)轮流发送三个缓存单元21内分别缓存的红色像素数据、蓝色像素数据及绿色像素数据。
在本实施方式中，在一个时钟脉冲周期(1TCLK)内，第二信号传输线对应的TCLK线传输信号表示为：H、H、L、L、L、H、H；第二信号传输线对应的LVDS2-TA线传输数据表示为：HSYHQ、R7、R6、R5、R4、R3、R2；第二信号传输线对应的LVDS2-TB线传输数据表示为：VD、R1、R0、0、0、0、0；在第二低电压差分信号接收器31的下一个时钟脉冲周期(2TCLK)内，第二信号传输线对应的TCLK线传输信号表示为：H、H、L、L、L、H、H；第二信号传输线对应的LVDS2-TA线传输数据表示为：HSYHQ、B7、B6、B5、B4、B3、B2；第二信号传输线对应的LVDS2-TB线传输数 据表示为：VD、B1、B0、0、0、0、0；在第二低电压差分信号接收器31的再下一个时钟脉冲周期(3TCLK)内，第二信号传输线对应的TCLK线传输信号表示为：H、H、L、L、L、H、H；第二信号传输线对应的LVDS2-TA线传输数据表示为：HSYHQ、G7、G6、G5、G4、G3、G2；第二信号传输线对应的LVDS2-TB线传输数据表示为：VD、G1、G0、0、0、0、0，再下一个时钟脉冲周期内，第二信号传输线对应的TCLK线传输信号表示为：H、H、L、L、L、H、H；第二信号传输线对应的LVDS2-TA线传输数据表示为：HSYHQ、R7、R6、R5、R4、R3、R2；第二信号传输线对应的LVDS2-TB线传输数据表示为：VD、R1、R0、0、0、0、0，如此循环。
进一步地，成像控制器3被配置为通过第二低电压差分信号接收器31在每个第一周期内轮流接收一次第一缓存单元的红色像素数据、第二缓存单元的蓝色像素数据及第三缓存单元的绿色像素数据。在每个第一周期内，数据处理器2对红色像素数据、蓝色像素数据及蓝色像素数据的接收顺序本申请不做限定。
在本实施方式中，第一周期为第三周期的三倍，对应地，第二低电压差分信号接收器31的时钟频率为第一低电压差分信号接收器22的三倍。
在本实施方式中，数据处理器2依次对第一图像数据进行第三重映射处理，将一个第一图像数据重映射后分别获得红色像素数据、蓝色像素数据及绿色像素数据，然后将红色像素数据、蓝色像素数据及绿色像素数据分别缓存至三个缓存单元21中，当三个缓存单元21分别缓存有一行像素对应的红色像素数据、蓝色像素数据及绿色像素数据时，三个缓存单元21开始轮流输出数据。
可以理解，本实施方式通过对第一图像数据进行第三重映射处理，分别获得红色像素数据、蓝色像素数据及绿色像素数据，并将红色像素数据、蓝色像素数据及绿色像素数据分别缓存至三个缓存单元21中，然后在第一周期(即三个第三周期)内轮流输出一次红色像素数据、蓝色像素数据及绿色像素数据，使得成像控制器3在接口资源不够的前提下，能够不间断地、连续地接收两个图像读取器1输出的图像数据，无需改变成像控制器3的现有构造且充分利用了成像控制器3的现有资源，有利于扫描技术的进一步发展。
在其它实施方式中，数据处理器2还可以包括数据筛选单元(图未示)，数据筛选单元具体可参见方式二中对应的内容，在此不重复赘述。
可以理解，通过对第一图像数据进行筛选，可以节约缓存单元21的空间，同时降低成像控制器3的第二低电压差分信号接收器31的时钟频率，以满足成像控制器3的第二低电压差分信号接收器31时钟频率要求。
举例来说，请再次参见方式二中所示的表六及附图7，当图像读取器1每扫描一行，图像读取器1通过第一低电压差分信号发送器12输出11218个Pixel(像素)的数据，而实际有用的数据只有7500个pixel。这样在图像读取器1到数据处理器2(FPGA)的LVDS CLK(第一低电压差分信号接收器22的时钟信号)频率一定的情况下，数据处理器2到成像控制器3的LVDS CLK可以根据实际传输的有效数据个数来决定。假设实际传输的有效数据点数是8000个点，一个TR(repetition time，回波时间)的周期是11218*15.1ns＝169.4us，在一个TR的周期内需要传输的数据是8000个点，每个像素点为24bit RGB数据(3Byte)，则一行像素需要传输的总数据量为8000*3＝24000Byte，按1个LVDS CLK传输1个Byte计算，则需要24000/1＝24000个LVDS CL K，一行像素传输的时间是169.4uS，因此LVDS CLK的频率为169.4/24000＝7.05nS，即141.8Mhz。若降低图像读取器1到数据处理器2的LVDS CLK频率，将LVDS CLK设置为99Mhz(10.1ns)，那么24000个LVDS CLK的时间是242.4us，一个TR周期内还是11218个点，则每个像素点的时间为242.4/11218＝21.6ns，那么图像读取器1到数据处理器2的LVDS CLK频率是46.3Mhz，这样成像控制器3的LVDS CLK的频率完全满足小于100Mhz的需求。
请继续参阅附图8，进一步地，成像控制器3还包括控制模块(控制模块可以为多种，附图8中所示的CPU为其中一种)及图像数据处理器等，图像数据处理器包括但不限于CISX模块(CISX模块被配置以对R、G、B图像数据进行分离)、PIC(Pixel Image Correction，图像像素修正)模块、PIE(Pixel Image Enhancement，图像像素增强)模块及存储模块(存储模块可以有多种，附图8所示的DDR(Double Data Rate SDRAM，双倍速率SDRAM)为其中一种)，CISX模块连接于第二低电压差分信号接收器31(图8中未示出)与PIC模块之间，PIC模块与PIE模块连接且PIC模块与PIE模块分别与存储模块连接。
在本实施方式中，CISX模块被配置为：通过第二低电压差分信号接收器31轮流接收红色像素数据、蓝色像素数据及绿色像素数据，按照接收顺序将红色像素数据、蓝色像素数据及绿色像素数据保存在成像控制器3内部的缓存器(附图8未示出)内；然后将缓存单元内的红色像素数据、蓝色像素数据及绿色像素数据各自分离出来并以平面(plane)格式分别发送给PIC模块进行像素校正处理，PIC模块处理后将红色像素数据、蓝色像素数据及绿色像素数据合并在一起发送给PIE模块进行进一步处理，PIE模块处理后将处理后的图像数据保存至DDR内，接着图像数据处理器通过USB接口(在其它实施方式中，还可以是其它接口，例如网络接口)将处理后的图像数据发送给PC(personal computer，个人计算机)完成扫描操作。
请参阅附图9，举例来说，若一个像素点对应的红色像素数据、蓝色像素数据及绿色像素数据分别为X、Y、Z；CISX模块轮流接收X、Y及Z数据并通过3个ODMA(Output Dynamic Memory Access，输出动态内存访问)控制器分别将接收到的X、Y及Z存储在在成像控制器3内部的缓存器内，其中，如附图9所示，缓存单元被设置为以非交错方式对X、Y及Z进行储存，即，先存放所有的X分量，然后存储所有的Y分量，最后存储所有的Z分量。然后通过IDMA(Internal Dynamic Memory Access，输出动态内存访问)控制器将X、Y及Z数据进行分离，并以平面(plane)格式将一个平面对应的X数据、Y数据及Z数据分别发送给PIC模块进行像素校正处理。
可以理解，方式三相对于方式一及方式二而言，数据处理器2通过将红色像素数据、蓝色像素数据及绿色像素数据分开存储至不同的缓存单元中，并轮流输出，使得CISX模块能够对RGB数据进行分离，进而使得PIC模块能够对分离后的且为平面格式的红色像素数据、蓝色像素数据及绿色像素数据进行分开处理，进而相较于方式一及方式二而言，充分利用了成像控制器3内的CISX模块及PIC模块，处理精度更高，因此有效的提升输出图像质量。除此之外，方式三不需要控制模块(例如CPU)控制RGB数据分离，因此可以有效的减少CPU的负载，也使得CPU不需要存储相应的代码，有效避免CPU在代码不够健壮或效率低下的情况下，出现数据处理不及时而导致数据丢失或错乱的情况发生。
请参阅附图10，本申请实施例提供了一种图像形成装置，包括任一实施例中的扫描设备50及以及与扫描设备50连接的成像设备60，在本实施方式中，成像设备包括但不限于包括成像单元(例如显影盒)、定影单元、纸张搬动单元以及纸盒。
请参阅附图11，本申请实施例提供了一种扫描方法，该方法包括：
步骤S01：两个图像读取器分别读取待扫描文件并输出与待扫描文件对应的图像数据；
步骤S02：数据处理器通过第一信号传输线获取图像数据并缓存至其内部的缓存单元中；
步骤S03：成像控制器通过第二信号传输线读取缓存单元的图像数据，其中，第二信号传输线对应的线的数量小于第一信号传输线对应的线的数量。
可以理解，本申请通过数据处理器对扫描数据进行转换处理，使得成像控制器接收扫描数据的端口数量能够匹配所配置的数据处理器输出接口的数量，解决了现有技术中成像控制器接收扫描数据的端口数量不能完全匹配所配置的扫描单元的输出接口的数量的问题，并且充分利用了成像控制器的现有第二信号传输线对应端口的资源，同时数据处理器不需要额外配置存储器，减少了开发生产成本，有利于扫描技术的进一步发展。
具体地，两个图像读取器可以分别读取待扫描文件的正面图像数据及反面图像数据，也可以是两个图像读取器均读取待扫描文件的正面图像数据或者两个图像读取器均读取待扫描文件的反面图像数据，可以理解的是，本申请实施例所提供的扫描设备还可以用于单面扫描，此时，两个图像读取器位于待扫描文件的同侧，此时，根据待扫描文件需要进行扫描的一面，两个图像读取器输出的图像数据均为待扫描文件的正面图像数据，或者，两个图像读取器输出的图像数据均为待扫描文件的反面图像数据。
具体地，本申请实施例中，待扫描文件可以包括但不限于：文档、证件、图像和照片中至少一个，本申请实施例对此不进行特别限定。
具体地，成像控制器3为SoC(System on Chip，片上系统)，SoC是一个微型的系统，由多个系统的部件组成，被配置为控制扫描设备的扫描图像的成像处理操作，例如对图像数据进行线性纠正、降噪、坏点去除、细节增强等处理，从而提高图像输出的质量，成像控制器3还用于执行数据收发、命令收发、打印画像的引擎控制相关的处理操作，例如通过接口单元(包括但不限于USB端口、有线网络端口、无线网络端口或者其他接口等)来收发数据、打印引擎不见控制 命令、状态等。本实施例中，成像控制器3同时控制扫描设备的扫描操作和成像设备的成像操作，但是本实施不限于此，例如，可以为扫描设备和成像设备分别配置一个独立的成像控制器，这些都属于本实施例的保护范围。
具体地，在本实施例中，数据处理器为可编程逻辑器件，具体为FPGA(Field-Programmable Gate Array，现场可编程门阵列)，在其它实施方式中，数据处理器还可以为CPLD(Complex Programmable Logic Device，复杂数据处理器)等可编程器件。
进一步地，数据处理器通过第一信号传输线获取图像数据并缓存至其内部的缓存单元中，具体包括：
数据处理器通过第一信号传输线获取图像数据并对每个图像数据进行重映射处理，以获得第二图像数据，并将第二图像数据缓存至缓存单元中。
需要理解的是，由于第二信号传输线对应的线的数量小于第一信号传输线对应的线的数量，因此需要对图像数据进行重映射处理，以获得具有预设格式的第二图像数据，使得成像控制器能够在满足自身接收频率的前提下获得连续、不间断地获得第二图像数据并对第二图像数据进行处理。
进一步地，图像读取器包括传感器及第一低电压差分信号发送器，两个图像读取器分别读取待扫描文件并输出与待扫描文件对应的图像数据，具体包括：
传感器读取待扫描文件并输出与待扫描文件对应的图像数据，其中，图像数据包括至少一个第一图像数据；
第一低电压差分信号发送器接收至少一个第一图像数据并在每个第一周期内通过第一信号传输线以差分传输的方式输出一个第一图像数据，其中，每个第一图像数据对应一个像素点数据。
具体地，两个传感器可以分别为上文的第一传感器(例如CIS或者CCD)及第二传感器(例如CIS或者CCD)，在本实施方式中，传感器被构造为以逐行扫描的方式将各个像素转化为对应的模拟信号，其中，一行图像包括若干个像素点，例如1024个像素点。
具体地，图像读取器还包括模数转换单元，模数转换单元连接于传感器与第一低电压差分信号发送器之间，用于将传感器输出的模拟信号转换为数字信号并输出给第一低电压差分信号发送器，第一低电压差分信号发送器用于将接收到的数字信号按照预设的时钟周期以逐像素的方式通过第一信号传输线输出给数据处理器，即第一低电压差分信号发送器在每个时钟脉冲周期(在本文中，第一低电压差分信号发送器的时钟脉冲周期为“第一周期”)内输出一个像素点对应的第一图像数据至数据处理器。
需要知道的是，第一图像数据与生成的第二图像数据可以是一一对应关系，或者，第一图像数据对应生成多个第二图像数据，或者，多个第一图像数据对应生成一个第二图像数据，或者，多个第一图像数据对应生成多个第二图像数据。
进一步地，数据处理器还包括第一低电压差分信号(Low Voltage Differential Signaling，LVDS)接收器及第二低电压差分信号(Low Voltage Differential Signaling，LVDS)发送器，成像控制器包括第二低电压差分信号(Low Voltage Differential Signaling，LVDS)接收器。
第一低电压差分信号接收器通过第一信号传输线与第一低电压差分信号发送器连接，数据处理器通过第一低电压差分信号接收器接收第一图像数据。
第二低电压差分信号发送器与缓存单元连接以及通过第二信号传输线与第二低电压差分信号接收器连接，第二低电压差分信号发送器被配置为通过第二信号传输线以差分传输的方式输出缓存单元内缓存的第二图像数据至成像控制器，成像控制器通过第二低电压差分信号接收器接收第二图像数据。
需要知道的是，第一信号传输线的数量与第一图像数据的数据位数相关联，第二信号传输线的数量与第二图像数据的数据位数相关联。第一低电压差分信号发送器被配置为以逐像素的方式输出传感器生成的第一图像数据。
在本实施方式中，一个像素点采用24位RGB数据表示，24位RGB数据包括8位R(红色)像素数据(R7、R6、R5、R4、R3、R2、R1、R0)、8位G(蓝色)像素数据(G7、G6、G5、G4、G3、G2、G1、G0)及8位B(绿色)像素数据(B7、B6、B5、B4、B3、B2、B1、B0)，在本实施方式中，一个像素点对应的第一图像数据由24位RGB数据及控制信号构成，根据LVDS传输机制，LVDS将并行像素信号和控制信号转换为串行比特流，通过多组导线传输，时钟脉冲信号单独采 用一组导线传输。由于第一低电压差分信号发送器12在一个时钟脉冲周期内，每个数据通道都输出7bit的串行数据信号，因此，每个第一低电压差分信号发送器12对应一组传输线，每组传输线需要数据线的数量为5对及时钟线的数量为1对，通过数据线和时钟线组成的第一信号传输线对第一图像数据进行传输，在本实施方式中，每个第一低电压差分信号发送器12具有6对低电压差分信号端口(数据传输端口的数量为5及时钟信号传输端口的数量为1，因为LVDS信号输出线是按照“对”来排布的，每个通道对应1对信号线，所以端口的数量单位也可以为“对”)；每个数据处理器分别需要6对低电压差分信号接收端口，整个扫描设备的数据处理器就至少对应需要12对低电压差分信号接收端口。
还需要知道的是，在本实施方式中，重映射处理具体为将第一图像数据对应的RGB像素数据、时钟信号及控制信号的排列顺序按照预设映射规则进行重新排列的过程。
进一步地，数据处理器通过第一信号传输线获取图像数据并对每个图像数据进行重映射处理，以获得第二图像数据，并将第二图像数据缓存至缓存单元中，包括但不限于以下三种方式：
方式一：数据处理器在每个第一周期内通过第一低电压差分信号接收器接收一次第一图像数据并按照其对第一图像数据的接收顺序对第一图像数据进行第一重映射处理及量化压缩处理，以依次获得具有第一预设格式及第一预设位数的第二图像数据，并将第二图像数据缓存至缓存单元中，其中，第二图像数据与第一图像数据为一一对应关系。
进一步地，成像控制器包括控制器及图像数据处理器，成像控制器通过第二信号传输线读取缓存单元的图像数据，具体包括：
控制模块生成控制指令；
图像数据处理器在每个第二周期内通过第二信号传输线接收一次缓存单元内缓存的第二图像数据，并根据控制指令对第二图像数据进行量化补偿处理，其中，第一周期等于第二周期。
方式二：缓存单元数量为两个，两个缓存单元被构建为乒乓Buffer结构；
通过第一信号传输线获取图像数据对每个图像数据进行重映射处理，以获得第二图像数据，并将第二图像数据缓存至缓存单元中，具体包括：
数据处理器在每个第一周期内通过第一低电压差分信号接收器接收一次第一图像数据并按照其对第一图像数据的接收顺序对第一图像数据进行第二重映射处理，以依次获得具有第二预设格式及第二预设位数的第二图像数据，并将生成的第二图像数据缓存至其中一个缓存单元内，每三个第二图像数据对应两个第一图像数据。
进一步地，成像控制器通过第二信号传输线读取缓存单元的图像数据，具体包括：
成像控制器在每个第三周期内接收一次两个缓存单元中的其中一个缓存单元缓存的第二图像数据，其中，第一周期为第三周期的1.5倍。
方式三：缓存单元的数量为三个，三个缓存单元分别为第一缓存单元、第二缓存单元及第三缓存单元；
数据处理器通过第一信号传输线获取图像数据对每个图像数据进行重映射处理，以获得第二图像数据，并将第二图像数据缓存至缓存单元中，具体包括：
数据处理器在每个第一周期内通过第一信号传输线接收第一图像数据并按照其对第一图像数据的接收顺序对第一图像数据进行第三重映射处理，以依次获得具有第三预设格式及第三预设位数的第二图像数据，其中，第二图像数据包括红色像素数据、蓝色像素数据及绿色像素数据；及将红色像素数据、蓝色像素数据及绿色像素数据分别缓存至第一缓存单元、第二缓存单元及第三缓存单元内。
进一步地，通过第二信号传输线读取缓存单元的图像数据，具体包括：
成像控制器通过第二低电压差分信号接收器在每个第一周期内轮流接收一次第一缓存单元内缓存的红色像素数据、第二缓存单元内缓存的蓝色像素数据及第三缓存单元内缓存的绿色像素数据。
方式一、方式二及方式三的具体实现过程可参见上文，在此不重复赘述。
本实施例提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器执行时实现实施例中的扫描方法，为避免重复，此处不一一赘述。或者，该计算机程序被处理器执行时实现实施例中图像形成装置中各模块/单元的功能，为避免重复，此处不一一赘述。
请参阅附图12，本申请实施例提供一种扫描设备50，该实施例的扫描设备50包括：处理器51、存储器52以及存储在存储器52中并可在处理器51上运行的计算机程序53，该计算机程序53被处理器51执行时实现实施例中的扫描方法，为避免重复，此处不一一赘述。或者，该计算机程序被处理器51执行时实现实施例中扫描设备中各模型/单元的功能，为避免重复，此处不一一赘述。
扫描设备50可以是桌上型计算机、笔记本、掌上电脑及云端服务器等计算设备。扫描设备50可包括但不仅限于处理器51、存储器52。本领域技术人员可以理解，图8仅仅是扫描设备50的示例，并不构成对扫描设备50的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件，例如计算机设备还可以包括输入输出设备、网络接入设备、总线等。
处理器51可以是中央处理单元(Central Processing Unit，CPU)，还可以是其它通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)或者其它数据处理器、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
存储器52可以是扫描设备50的内部存储单元，例如扫描设备50的硬盘或内存。存储器52也可以是扫描设备50的外部存储设备，例如扫描设备50上配备的插接式硬盘，智能存储卡(Smart Media Card,SMC)，安全数字(Secure Digital,SD)卡，闪存卡(Flash Card)等。进一步地，存储器52还可以既包括扫描设备50的内部存储单元也包括外部存储设备。存储器52用于存储计算机程序以及扫描设备所需的其它程序和数据。存储器52还可以用于暂时地存储已经输出或者将要输出的数据。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述方法的具体工作过程，可以参考前述装置实施例中的对应过程，在此不再赘述。

Claims (18)

  1. 一种扫描设备，其特征在于，包括：
    两个图像读取器，分别被配置为读取待扫描文件并输出与所述待扫描文件对应的图像数据；
    数据处理器，与所述图像读取器通过第一信号传输线连接，所述数据处理器被配置为通过所述第一信号传输线获取所述图像数据并缓存至其内部的缓存单元中；及
    成像控制器，被配置为通过第二信号传输线读取所述缓存单元的图像数据，其中，所述第二信号传输线对应的线的数量小于所述第一信号传输线对应的线的数量。
  2. 如权利要求1所述的扫描设备，其特征在于，所述数据处理器为可编程逻辑器件，并且所述可编程逻辑器件具体被配置为通过所述第一信号传输线获取所述图像数据并对每个所述图像数据进行重映射处理，以获得第二图像数据，并将所述第二图像数据缓存至所述缓存单元中。
  3. 如权利要求2所述的扫描设备，其特征在于，所述图像读取器包括：
    传感器，被配置为读取所述待扫描文件并输出与所述待扫描文件对应的图像数据，其中，所述图像数据包括至少一个第一图像数据；及
    第一低电压差分信号发送器，与所述传感器连接，被配置为接收所述至少一个第一图像数据并在每个第一周期内通过所述第一信号传输线以差分传输的方式输出一个所述第一图像数据，其中，每个第一图像数据对应一个像素点数据。
  4. 如权利要求3所述的扫描设备，其特征在于，所述可编程逻辑器件还包括第一低电压差分信号接收器及第二低电压差分信号发送器，所述成像控制器包括第二低电压差分信号接收器；
    所述第一低电压差分信号接收器通过所述第一信号传输线与所述第一低电压差分信号发送器连接，所述可编程逻辑器件通过所述第一低电压差分信号接收器接收所述第一图像数据；
    所述第二低电压差分信号发送器与所述缓存单元连接以及通过所述第二信号传输线与所述第二低电压差分信号接收器连接，所述第二低电压差分信号发送器被配置为通过所述第二信号传输线以差分传输的方式输出所述缓存单元内缓存的第二图像数据至所述成像控制器，所述成像控制器通过所述第二低电压差分信号接收器接收所述第二图像数据。
  5. 如权利要求4所述的扫描设备，其特征在于，所述可编程逻辑器件具体被配置为在每个所述第一周期内通过所述第一低电压差分信号接收器接收一次所述第一图像数据并按照其对所述第一图像数据的接收顺序对所述第一图像数据进行第一重映射处理及量化压缩处理，以依次获得具有第一预设格式及第一预设位数的所述第二图像数据，并将所述第二图像数据缓存至所述缓存单元中，其中，所述第二图像数据与所述第一图像数据为一一对应关系。
  6. 如权利要求5所述的扫描设备，其特征在于，所述成像控制器还包括：
    控制模块，被配置以生成控制指令；及
    图像数据处理器，被配置为在每个所述第二周期内通过所述第二低电压差分信号接收器接收一次所述缓存单元内缓存的第二图像数据，并根据所述控制指令对所述第二图像数据进行量化补偿处理，其中，所述第一周期等于所述第二周期。
  7. 如权利要求4所述的扫描设备，其特征在于，所述缓存单元数量为两个，两个缓存单元被构建为乒乓Buffer结构；
    所述可编程逻辑器件具体被配置为在每个所述第一周期内通过所述第一低电压差分信号接收器接收一次所述第一图像数据并按照其对所述第一图像数据的接收顺序对所述第一图像数据进行第二重映射处理，以依次获得具有第二预设格式及第二预设位数的所述第二图像数据，并将生成的所述第二图像数据缓存至两个缓存单元中的其中一个缓存单元内，每三个第二图像数据对应两个第一图像数据。
  8. 如权利要求7所述的扫描设备，其特征在于，所述成像控制器具体被配置为通过所述第二低电压差分信号接收器在每个第三周期内接收一次两个缓存单元中的其中一个缓存单元缓存的第二图像数据，其中，所述第一周期为所述第三周期的1.5倍。
  9. 如权利要求4所述的扫描设备，其特征在于，所述缓存单元的数量为三个，三个缓存单元分别为第一缓存单元、第二缓存单元及第三缓存单元；
    所述可编程逻辑器件具体被配置为在每个第一周期内通过所述第一信号传输线接收所述第一图像数据并按照其对所述第一图像数据的接收顺序对所述第一图像数据进行第三重映射处理，以依次获得具有第三预设格式及第三预设位数的所述第二图像数据，其中，所述第二图像数据包括红色 像素数据、蓝色像素数据及绿色像素数据；及将获得的所述红色像素数据、所述蓝色像素数据及所述绿色像素数据分别缓存至所述第一缓存单元、所述第二缓存单元及所述第三缓存单元内。
  10. 如权利要求9所述的扫描设备，其特征在于，所述成像控制器具体被配置为通过第二低电压差分信号接收器在每个所述第一周期内轮流接收一次所述第一缓存单元内缓存的红色像素数据、所述第二缓存单元内缓存的蓝色像素数据及所述第三缓存单元内缓存的绿色像素数据。
  11. 如权利要求1-10任意一种所述的扫描设备，其特征在于，所述成像控制器的第二低电压差分信号接收器预制的低电压差分信号端口的数量小于所述第一信号传输线对应的线的数量，两个所述图像读取器的第一低电压差分信号发送器预制的低电压差分信号端口的数量大于或等于所述第一信号传输线对应的线的数量。
  12. 一种图像形成装置，包括如权利要求1-11任一项所述的扫描设备，以及与所述扫描设备连接的成像设备。
  13. 一种扫描方法，其特征在于，所述方法包括：
    两个图像读取器分别读取待扫描文件并输出与所述待扫描文件对应的图像数据；
    数据处理器通过第一信号传输线获取所述图像数据并缓存至其内部的缓存单元中；
    成像控制器通过第二信号传输线读取所述缓存单元的图像数据，其中，所述第二信号传输线对应的线的数量小于所述第一信号传输线对应的线的数量。
  14. 如权利要求13所述的扫描方法，其特征在于，所述数据处理器为可编程逻辑器件，所述数据处理器通过第一信号传输线获取所述图像数据并缓存至其内部的缓存单元中，具体包括：
    所述可编程逻辑器件通过所述第一信号传输线获取所述图像数据并对每个所述图像数据进行重映射处理，以获得第二图像数据，并将所述第二图像数据缓存至所述缓存单元中。
  15. 如权利要求14所述的扫描方法，其特征在于，所述图像读取器包括传感器及第一低电压差分信号发送器，所述两个图像读取器分别读取待扫描文件并输出与所述待扫描文件对应的图像数据，具体包括：
    所述传感器读取所述待扫描文件并输出与所述待扫描文件对应的图像数据，其中，所述图像数据包括至少一个第一图像数据；
    所述第一低电压差分信号发送器接收所述至少一个第一图像数据并在每个第一周期内通过所述第一信号传输线以差分传输的方式输出一个所述第一图像数据，其中，每个第一图像数据对应一个像素点数据。
  16. 如权利要求15所述的扫描方法，其特征在于，所述可编程逻辑器件还包括第一低电压差分信号接收器及第二低电压差分信号发送器，所述成像控制器包括第二低电压差分信号接收器；
    所述第一低电压差分信号接收器通过所述第一信号传输线与所述第一低电压差分信号发送器连接，所述可编程逻辑器件通过所述第一低电压差分信号接收器接收所述第一图像数据；
    所述第二低电压差分信号发送器与所述缓存单元连接以及通过所述第二信号传输线与所述第二低电压差分信号接收器连接，所述第二低电压差分信号发送器被配置为通过所述第二信号传输线以差分传输的方式输出所述缓存单元内缓存的第二图像数据至所述成像控制器，所述成像控制器通过所述第二低电压差分信号接收器接收所述第二图像数据。
  17. 一种存储介质，所述存储介质包括存储的程序，其中，在所述程序运行时控制所述存储介质所在设备执行13至16任意一项所述的方法。
  18. 一种扫描设备，包括存储器和处理器，所述存储器用于存储包括程序指令的信息，所述处理器用于控制程序指令的执行，其特征在于：所述程序指令被处理器加载并执行时实现权利要求13至16任意一项所述的方法的步骤。
PCT/CN2020/093992 2019-07-15 2020-06-02 扫描设备、图像形成装置、扫描方法及存储介质 WO2021008262A1 (zh)

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