WO2020264109A1

WO2020264109A1 - Dual-step printed circuit board test, and associated systems and methods

Info

Publication number: WO2020264109A1
Application number: PCT/US2020/039546
Authority: WO
Inventors: Harry JIN; Daniel Benjamin CARSON; David Gill
Original assignee: Checksum, Llc
Priority date: 2019-06-28
Filing date: 2020-06-25
Publication date: 2020-12-30

Abstract

The inventive technology is directed to testing of printed circuit boards (PCBs). Contact resistance can be increased or become intermittent in presence of flux (e.g., Organic Solderability Preservative or OSP) over the test points. Therefore, prior to testing a relatively high current is applied to the test pad for a duration of time. In response, the flux heats up and/or becomes less viscous, thereby creating less contact resistance. After the contact resistance is reduced, the real test commences. In some embodiments, false high contact resistance are reduced.

Description

DUAL-STEP PRINTED CIRCUIT BOARD TEST, AND ASSOCIATED SYSTEMS

AND METHODS

CROSS-REFERENCE TO REPLAETD APPLICATION(S)

This application claims the benefit of U.S. Provisional Application No. 62/868,757 filed June 28, 2019, which is incorporated herein by reference.

FIELD OF THE INVENTION

The inventive technology relates generally to printed circuit board (PCB) testers. More particularly, the inventive technology improves testability of the PCB components when soldering flux or other contamination is present on the PCB.

BACKGROUND

Printed circuit boards are tested before shipping to customers. PCBs typically include internal routing (traces) distributed over several metallization layers. The horizontal metallization layers are interconnected with vertical vias. The electrical components (resistors, capacitors, integrated circuits (ICs), connectors, etc.) are attached to the surface of the PCB through the pads or through-holes. These components are electrically interconnected through the traces of the PCB. The external electrical connections to the PCB are typically provided through edge connectors or other connectors mounted on the PCB.

The PCB and associated electrical components are sometimes collectively called a printed circuit board assembly (PCB A). Generally, the terms PCB and PCB A are used interchangeably, i.e., the term PCB can denote the board itself, as well as an assembly of the board and the electrical components that are carried by the board.

Testing of the PCBs (or the PCBAs) can be in-circuit or functional. In-circuit testing performs a "schematic verification" by testing individual components of the PCB one at a time. For example, resistance, voltage drop, polarity, etc., of the individual electrical components are measured and compared against expected values for that component. The in-circuit test may detect solder shorts, missing components, wrong components, improperly attached components (e.g., a diode that is rotated 180°), or open connections. Functional testing is designed to assure that circuitry functions within the specifications. Such testing may be done "at speed" through the PCB connectors (e.g., edge connectors on the PCB) and/or a bed-of-nails (BON) fixture. Functional tests can identify functional defects within the PCB as well as the defects in the components.

During the in-circuit or functional testing, tester connectors (e.g., pins of the BON fixture) make contact with the electrical components on the PCB. Next, predetermined electrical signals and/or power are sent through the components of the PCB and the PCB itself, thus generating return voltages/currents that are routed back to the tester through the pins of the tester connectors. The tester analyzes these return signals to identify defects, if any, either on the PCB itself or on the electrical components of the PCB.

Electrical components are typically attached to the PCB by soldering. Prior to soldering the electrical components on the PCB, leads of these electrical components and soldering pads of the PCB are treated with soldering flux to remove impurities (e.g., organic contamination, oxidation layer, etc.), thus improving solderability of the components onto the PCB. Generally, soldering flux (also referred to as flux for simplicity and brevity) evaporates during the soldering. The remaining flux residue, if any, is cleaned after the soldering as a part of normal manufacturing process. However, some flux may remain on the PCB after the soldering and cleaning operations, and may cover test points, on the PCB and/or on the electrical components. Since the flux is generally poor electrical conductor, as the tester pins (e.g., pins of the BON) contact these components, the residual layer of flux may prevent or reduce electrical contact between the tester pins and the components. As a result, the test may result in erroneous readings. For example, a correctly functioning resistor may be declared "fail open" or "resistance out of spec" by the tester because of the additional electrical resistance caused by flux.

Some operators on the test floor attempt to retest the failing component several times, which may ultimately succeed in breaking through the layer of flux, establishing the required electrical contact, and ultimately correctly testing the components. In some cases, a test program automatically attempts a retest, which, again, may lead to a successful test after several attempts. However, these retests will not always succeed in breaking through the layer of flux and establishing required electrical contact. Furthermore, even when ultimately successful, repeated testing slows down the test process, may damage the components under test and/or increase the cost of testing. Accordingly, systems and methods are required for improved testability of PCBs having residual flux. SUMMARY

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In some embodiments, the inventive technology is directed to electrical testing of printed circuit boards (PCBs). After soldering electrical components on the PCB, contact resistance between the test points on the PCB and test pins of the tester may increase or become intermittent because of residual soldering flux over the test points. A non limiting example of such soldering flux is Organic Solderability Preservative (OSP). Therefore, in some embodiments, a relatively high electrical current is applied to the test pad for a duration of time when high contact resistance is detected. In response, residual flux heats up and/or becomes less viscous, enabling the contact pin to penetrate through the weakened/softened flux to contact the test point. As a result, the contact resistance between the test point and contact pin is reduced. After the contact resistance is reduced, the electrical test commences. In some embodiments, the incidence of false high resistance reading is reduced, because high contact resistance is eliminated or at least reduced.

In one embodiment, an apparatus for testing printed circuit boards (PCBs) that are units under test (UUTs) includes: a tester configured for sending test signals to a UUT and for acquiring test data from the UUT; and a test fixture electrically connected with the tester. The test fixture carries a plurality of contact pins configured for contacting corresponding test pads of the UUT. The tester includes a non-volatile memory that carries instructions, which, when executed, cause the tester to:

(i) send a first test signal at a first test voltage VI to a test pad of the UUT ;

(ii) measure a resistance of a circuit of the UUT that is connected to the test pad;

(iii) compare the resistance to a predetermined threshold level; and

(iv) if the resistance exceeds the predetermined threshold level, cause the tester to:

(a) send a second test signal at a second test voltage to the test pad, where the second test voltage is higher than the first test voltage by a predetermined amount AV making the second test voltage VI +AV;

(b) heat the test pad for a predetermined amount of time tl by applying the second test voltage VI +AV to the test pad; (c) after the predetermined amount of time tl elapses, send a third test signal at a third test voltage V2 to the test pad; and

(d) measure the resistance of the circuit of the UUT that is connected to the test pad.

In one aspect, the third test voltage V2 and the first test voltage VI are the same.

In another aspect, the predetermined amount of time tl is between 1 millisecond and 1 second.

In yet another aspect, the third test signal at the second voltage V2 is sent within 1 milisecond from the end of the predetermined amount of time tl.

In one aspect, during applying the first test signal at the first voltage VI, the test pad of the UUT is separated from the corresponding contact pin of the test fixture by a layer of contamination. In one aspect, the layer of contamination comprises soldering flux. In one aspect, the soldering flux is organic solderability preservative (OSP).

In one aspect, during applying the third test signal at the third test voltage V2, the test pad of the UUT makes a direct mechanical contact with the corresponding pin of the test fixture.

In one aspect, the non-volatile memory includes further instructions, which, when executed, cause the tester to:

(e) send a fourth test signal to the test pad, wherein a fourth test voltage is higher than the second test voltage by a predetermined amount AVI making the fourth test voltage V l+AV+AV 1 ;

(f) heat the test pad for a predetermined amount of time t2 by applying the fourth test voltage Vl+AV+AV 1 ;

(g) after the predetermined amount of time t2 elapses, send a fifth test signal at the second test voltage V2 to the test pad of the UUT; and

(h) measure the resistance of the circuit of the UUT that is connected to the test pad.

In another aspect, AY and AY 1 are the same.

In one aspect, the contact pins are Pogo pins.

In one aspect, the tester includes: a first source of voltage; a second source of voltage that is different from the first source of voltage; and a relay configured to electrically couple the test fixture to one of the first source of voltage and the second source of voltage. In one aspect, the first source of voltage is configured to supply the first test voltage VI, and the second source of voltage is configured to supply the second test voltage Vl+Dn.

In one embodiment, a method for testing printed circuit boards (PCBs) that are units under test (UUTs) includes:

(i) sending a first test signal at a first voltage VI to a test pad of the UUT ;

(ii) measuring a resistance of a circuit of the UUT that is connected to the test pad;

(iii) comparing the resistance to a predetermined threshold level; and

(iv) if the resistance exceeds the predetermined threshold level:

(a) sending a second test signal at a second test voltage to the test pad, wherein the second test voltage is higher than the first test voltage by a predetermined amount AY making the second test voltage VI +AV;

(b) heating the test pad for a predetermined amount of time tl by applying the second test voltage Vl+AV to the test pad;

(c) after the predetermined amount of time tl elapses, sending a third test signal at a third test voltage V2 to a test pad of a UUT; and

(d) measuring the resistance of the circuit of the UUT that is connected to the test pad.

In one aspect, the method of also includes:

(e) sending a fourth test signal to the test pad, wherein the fourth test voltage is higher than the second test voltage by a predetermined amount AVI making the fourth test voltage Vl+AV+AV 1 ;

(f) heating the test pad for a predetermined amount of time t2 by applying the fourth voltage V l+AV+AV 1 ;

(g) after the predetermined amount of time t2 elapses, sending the fifth test signal at the third test voltage V2 to the test pad of the UUT; and

(h) measuring the resistance of the circuit of the UUT that is connected to the test pad.

In one aspect, the method also includes switching, by a relay, between the first test signal at the first test voltage V 1 and the second test signal at the second test voltage Vl+AV. The first test voltage VI is provided by a first source of voltage, and the second test voltage Vl+AV is provided by a second source of voltage that is different from the first source of voltage. DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIGURE 1 is a partially schematic, isometric view of a PCB tester in accordance with an embodiment of the present technology;

FIGURE 2 is a partially schematic view of a test fixture in accordance with an embodiment of the present technology;

FIGURES 3A, 3B and 3C are schematic diagrams of pin/test pad contact in accordance with an embodiment of the present technology;

FIGURE 4 is a graph of contact parameters in accordance with an embodiment of the present technology;

FIGURES 5 A, 5B and 5C are schematic diagrams of pin/test pad contact in accordance with an embodiment of the present technology;

FIGURE 6 is a block diagram of a test apparatus in accordance with an embodiment of the present technology; and

FIGURE 7 is a flow chart of a test method in accordance with an embodiment of the present technology.

DETAILED DESCRIPTION

While illustrative embodiments have been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

FIGURE 1 is a partially schematic, isometric view of a PCB tester 10 in accordance with an embodiment of the present technology. In some embodiments, the PCB tester 10 includes a mainframe 13 and a test fixture 18 that is built as a mechanical "bed of nails" (BON) fixture specifically for a given PCB layout. The mainframe 13 includes electronics that sends test vectors and power to a PCB under test, also referred to as a unit under test (UUT) 16. For example, the mainframe 13 may include test instruments 13a for checking opens/shorts on the UUT 16, and a power supply 13b for powering components 22 on the UUT 16. The test fixture 18 includes contact pins 20 (e.g., pogo pins) that electrically connect electronics in the mainframe 13 with test pads, traces 21, and further with components 22 of the UUT 16. Additional electrical connectivity between the test fixture 20 and the UUT 16 may be provided by a cable 17.

Test cables 14 may connect the test instruments 13a and power supplies 13b of the mainframe 13 with the test fixture 18. In some embodiments, a host computer 11 controls the operation of the mainframe 13 (e.g., sending the test vectors through the cables 14) and interprets the results of the test (e.g., presence/absence of defective components on the UUT 16). In some embodiments, after detecting unexpectedly high electrical resistance (or other out-of-spec value) on the UUT, the host computer 11 may cause the mainframe 13 to apply a sequence of electrical signals as described in more detail with respect to Figures 2-7 below.

FIGURE 2 is a partially schematic view of a test fixture in accordance with an embodiment of the present technology. The test fixture 18 can include an assembly of boards 18a and 18b for improved alignment of the contact pins 20. The mainframe tester 13 provides test vectors/power through test cables 14. In operation, the contact pins 20 contact the components 22 or the test pads of the UUT 16 to provide electrical connectivity to/from the mainframe tester 13. After completing testing of the UUT 16, the tested UUT is removed and the next UUT is loaded to contact the test fixture 18. However, residual flux or other impurities may prevent or degrade electrical contact between the pins 20 and the test points on the UUT 16.

FIGURES 3A, 3B and 3C are schematic diagrams of pin/test pad contact in accordance with an embodiment of the present technology. Figure 3A represents an initial contact between the test pin 20 and a test pad 30. However, the initial contact may be impaired by a layer of residual flux 30-f over the contact surface of the test pad 30. The parameters of the initial contact are denoted as time ti, electrical resistance Ri that is sensed by the tester, and voltage V) that is applied by the by the tester to the test pin 20. In the illustrated scenario, the presence of flux 30-f increases the electrical resistance Ri that is sensed by the tester. In the context of this application, terms "residual flux" and "flux" also encompass other electrical contact-impairing impurities that may be present over the components or test points on the UUT.

In operation, electrical resistance of residual flux 30-f is additive to any other resistance in the current path that the tester 10 senses as Ri. In many situations, measured value of Ri is relatively high, but still finite. Therefore, some electrical current, albeit out-of-spec low current, passes through the residual flux 30-f between the test pad 30 and the test pin 20. Electrical resistance of the residual flux may push the overall resistance of tested components or traces beyond the expected or "pass" value for a given UUT test scenario.

Figure 3B illustrates test conditions at time t2. In some embodiments, after detecting an unexpectedly high or out-of-spec resistance Ri, the tester increases voltage to V2 at the test pin 20. As a result, more current passes through residual flux 30-f, which, in turn, may heat up the flux. In some embodiments, this heating of the flux reduces its electrical resistance to R2. Without being bound to theory, it is believed that increased temperature of the flux may reduce its surface tension, viscosity and/or density, therefore promoting better penetration of the test pin 20 through the flux and toward the test pad 30. In turn, a separation between the test pin 20 and the test pad 30 is reduced, thus reducing the electrical resistance of the flux and a contact resistance between the test pin 20 and the test pad 30 to R2, where R2 is less than Ri.

In the context of this disclosure, a person of ordinary skill will understand that heating the soldering flux in practice means heating both the flux and the test pad that carries the flux. Therefore, the terms "heating the flux" and "heating the test pad" may be used interchangeably in this specification.

Figure 3C illustrates test conditions at time t3. In some embodiments, at this point in the test the flux 30-f is already sufficiently heated, therefore less dense, less viscous and/or softer. Therefore, the test pin 20 may mechanically contact the test pad 30. As a result, the resistance R3 is not elevated anymore, and may be reduced to a value that is more representative of the within-the-spec test condition. Therefore, in at least some embodiments, Figure 3C represents test conditions where both R3 and V3 are reduced in comparison with Ri and Vi. Changes in resistance R and test voltage V as a function of time are further discussed with respect to Figure 4 below.

FIGURE 4 is a graph of contact parameters in accordance with an embodiment of the present technology. Some examples of relevant contact parameters are resistance R, temperature T, voltage V and surface tension g of the residual flux. Other contact parameters are also possible, for example, density, viscosity and hardness/softness of the flux. In the context of this application, the tester generally senses the resistance and voltage for the entire electrical path under the test (including, e.g., cables, test pin, layer of flux, test pad, component under test, electrical trace of the PCB, etc.). However, for simplicity and brevity the parameters of the flux itself are also referred to as, for example, resistance R, voltage V, without specifically attributing a portion of the overall resistance R or voltage drop V to the flux itself. It is to be understood that, generally, flux contributes some portion of the resistance R and/or voltage drop V as sensed by the tester, whereas other components in the circuit contribute the remainder.

At time t _j , tester senses a relatively high resistance R, while providing a spec test voltage V. In some embodiments, such a combination of R and V may indicate a presence of the residual flux at the test point. At time t _j , the residual flux may be characterized by relatively high surface tension g and relatively low temperature T. In the context of Figure 4, surface tension g may also represent other physical parameters of the flux, for example, hardness, viscosity or density of the flux.

At time t₂, tester increases the voltage V. As a result, electrical current through the flux is increased, therefore resistively heating the flux. In turn, temperature T of the flux over the test pad increases, causing the surface tension g (and/or density, viscosity, hardness of the flux) to decrease. In some embodiments, a decreased surface tension g of the flux enables better penetration of the test pin through the flux, leading to a reduction in resistance R.

At time t₃, resistance R in the tested circuit is reduced based on reducing or eliminating separation between the test pin and the test pad. Accordingly, the tester may reduce test voltage V down to its spec value to proceed with testing the UUT.

In some embodiments, the remaining layer of flux that separates the test pad from the test pin may start to cool down due to the reduction in the electrical current passing through the flux. As a result, temperature T may start to decrease during the test, causing surface tension g and electrical resistance R to increase. However, for many practical applications, the rate of change of these parameters (e.g., T, g, R, etc.) may be too slow to negatively affect the accuracy and reliability of the tester measurements.

FIGURES 5A, 5B and 5C are schematic diagrams of pin/test pad contact in accordance with an embodiment of the present technology. Figure 5A corresponds to time t_j, when a relatively cold residual flux 30-f separates the test pad 30 from the test pin 20. Figure 5B corresponds to time t₂, when Ohmic heating reduces surface tension g of the flux 30-f. Consequently, a separation between the test pin 20 and the test pad 30 may be eliminated or at least reduced. Figure 5C corresponds to time t₃, when the test pin 20 and the test pad 30 establish contact that may be sufficient for valid testing. For example, in some embodiments, the test pin 20 may penetrate into the surface of the test pad 30. This condition is sometimes referred to as a "scrub" in the test industry.

FIGURE 6 is a block diagram of a test apparatus in accordance with an embodiment of the present technology. In operation, a test instrument 13c (e.g., power supply, voltage source, etc.) may provide required test voltage V to the test pin 20. As explained above, the test voltage V may be changed by the test instrument 13c during different phases of the test. Therefore, in some embodiments the test instrument 13c may provide multiple voltages to a given test point during different phases of the test. In other embodiments, a relay 40 may connect test instruments 13c, 13d to the test pin 20 during different phases of the test. For example, one voltage (e.g., V_j) may be provided by the test instrument 13c, while another voltage (e.g., V₂) may be provided by the test instrument 13d.

FIG. 7 is a flow chart of a test method in accordance with an embodiment of the present technology. In some embodiments, the method may include additional steps or may be practiced without all steps illustrated in the flow chart. The method starts in block 70, and proceeds to block 72 where the tester applies voltage V and measures electrical resistance R of the circuit under the test.

In block 74, the tester verifies whether the measured resistance R is smaller than a predetermined threshold electrical resistance RTHRESHOLD· ^ the measured resistance R is smaller than the threshold resistance, the tester accepts the test results, and the method ends in block 80. If, however, the measured resistance R is larger than the threshold electrical resistance RTHRESHOLD’ the method proceeds to block 76, where the tester applies an increased voltage V+AV to the test pad. In some embodiments, the incremental increase AV may range from sub-Volt range to several Volts. In some embodiments, this increased voltage may be applied for the period of time ranging from, for example, 1 ms to several ms, or from 1 second to several seconds. In other embodiments, different incremental increases AV and/or periods of time may apply.

In block 78, the tester verifies whether the newly increased voltage exceeds a predetermined maximum allowed voltage V_MAX. If it does, the method ends in block 80.

If, on the other hand, the new increased voltage still did not reach the maximum allowed voltage V_MAX, the method proceeds to block 72 where the resistance is measured again and block 74 where the measured resistance is compared with the predetermined threshold resistance. Therefore, under different scenarios, the tester may apply voltages V+Dn, n+Dn+ AVI, n+Dn+ Dnΐ+ AV2, etc., if the measured resistance R is larger than a predetermined threshold electrical resistance RTHRESHOLD’ ^uP ^to the point where the maximum allowed voltage V_MAX is reached.

Many embodiments of the technology described above may take the form of computer- or controller-executable instructions, including routines executed by a programmable computer or controller. Those skilled in the relevant art will appreciate that the technology can be practiced on computer/controller systems other than those shown and described above. The technology can be embodied in a special-purpose computer, application specific integrated circuit (ASIC), controller or data processor that is specifically programmed, configured or constructed to perform one or more of the computer-executable instructions described above. Of course, any logic or algorithm described herein can be implemented in software or hardware, or a combination of software and hardware.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Moreover, while various advantages and features associated with certain embodiments have been described above in the context of those embodiments, other embodiments may also exhibit such advantages and/or features, and not all embodiments need necessarily exhibit such advantages and/or features to fall within the scope of the technology. As used herein, the term "about" indicates that the subject value can be modified by plus or minus 5% and still fall within the disclosed embodiment.

Where methods are described, the methods may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. Accordingly, the disclosure can encompass other embodiments not expressly shown or described herein.

Claims

CLAIMS I/We claim:

1. An apparatus for testing printed circuit boards (PCBs) that are units under test (UUTs), comprising:

a tester configured for sending test signals to a UUT and for acquiring test data from the UUT ; and

a test fixture electrically connected with the tester, wherein the test fixture carries a plurality of contact pins configured for contacting corresponding test pads of the UUT, wherein the tester includes a non-volatile memory that carries instructions, which, when executed, cause the tester to:

(ii) measure a resistance of a circuit that is connected to the test pad;

(iii) compare the resistance to a predetermined threshold level; and

(a) send a second test signal at a second test voltage to the test pad, wherein the second test voltage is higher than the first test voltage by a predetermined amount AV making the second test voltage Vl+AV

(b) heat the test pad for a predetermined amount of time tl by applying the second test voltage Vl+AV to the test pad;

(c) after the predetermined amount of time tl elapses, send a third test signal at a third test voltage V2 to the test pad; and

2. The apparatus of claim 1, wherein the third test voltage V2 and the first test voltage VI are the same.

3. The apparatus of claim 1, wherein the predetermined amount of time tl is between 1 millisecond and 1 second.

4. The apparatus of claim 1, wherein the third test signal at the second voltage V2 is sent within 1 milisecond from the end of the predetermined amount of time tl.

5. The apparatus of claim 1, wherein, during applying the first test signal at the first voltage VI , the test pad of the UUT is separated from the corresponding contact pin of the test fixture by a layer of contamination·

6. The apparatus of claim 5, wherein the layer of contamination comprises soldering flux.

7. The apparatus of claim 6, wherein the soldering flux is organic solderability preservative (OSP).

8. The apparatus of claim 5, wherein, during applying the third test signal at the third test voltage V2, the test pad of the UUT makes a direct mechanical contact with the corresponding pin of the test fixture.

9. The apparatus of claim 1, wherein the non-volatile memory includes further instructions, which, when executed, cause the tester to:

(e) send a fourth test signal to the test pad, wherein a fourth test voltage is higher than the second test voltage by a predetermined amount AVI making the fourth test voltage Vl+AV+AVl·,

(f) heat the test pad for a predetermined amount of time t2 by applying the fourth test voltage Vl+AV+AVl ;

(g) after the predetermined amount of time t2 elapses, send a fifth test signal at the second test voltage V2 to the test pad of the UUT ; and

10. The apparatus of claim 1, wherein AV and AVI are the same.

11. The apparatus of claim 1, wherein the contact pins are Pogo pins.

12. The apparatus of claim 1, wherein the tester comprises:

a first source of voltage; a second source of voltage that is different from the first source of voltage; and a relay configured to electrically couple the test fixture to one of the first source of voltage and the second source of voltage.

13. The apparatus of claim 12, wherein the first source of voltage is configured to supply the first test voltage VI , and wherein the second source of voltage is configured to supply the second test voltage Vl+AV.

14. A method for testing printed circuit boards (PCBs) that are units under test (UUTs), the method comprising:

(iii) comparing the resistance to a predetermined threshold level; and

(iv) if the resistance exceeds the predetermined threshold level:

(a) sending a second test signal at a second test voltage to the test pad, wherein the second test voltage is higher than the first test voltage by a predetermined amount AV making the second test voltage Vl+AV ;

(c) after the predetermined amount of time tl elapses, sending a third test signal at a third test voltage V2 to a test pad of a UUT ; and

15. The method of claim 14, wherein the third test voltage V2 and the first test voltage VI are the same.

16. The method of claim 14, wherein, during applying the first test signal at the first voltage VI , the test pad of the UUT is separated from the corresponding contact pin of the test fixture by a layer of contamination·

17. The method of claim 16, wherein, the layer of contamination comprises soldering flux.

18. The method of claim 14, further comprising: (e) sending a fourth test signal to the test pad, wherein the fourth test voltage is higher than the second test voltage by a predetermined amount AVI making the fourth test voltage Vl+AV+AVl·,

(f) heating the test pad for a predetermined amount of time t2 by applying the fourth voltage Vl+AV+AVl·,

(g) after the predetermined amount of time t2 elapses, sending the fifth test signal at the third test voltage V2 to the test pad of the UUT ; and

19. The method of claim 18, wherein AV and AVI are the same.

20. The method of claim 14, further comprising:

switching, by a relay, between the first test signal at the first test voltage VI and the second test signal at the second test voltage Vl+AV,

wherein the first test voltage VI is provided by a first source of voltage, and wherein the second test voltage Vl+AV is provided by a second source of voltage that is different from the first source of voltage.