WO2020199490A1 - Dual-mode error detection memory and dual-mode error detection method - Google Patents
Dual-mode error detection memory and dual-mode error detection method Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- the invention relates to storage technology, in particular to a dual-mode error detection memory method.
- Cache devices and memory devices serve as data buffers and are one of the basic conditions for the normal operation of some complex hardware systems. It assumes the function of buffering data. Like any memory, it must be ensured that the storage is reliable and will not become unstable (for example, data errors on SRAM due to voltage surges or memory cell damage). Therefore, storage must be associated with error detection (and error correction) mechanisms.
- parity check is relatively simple, saves power, and can meet the general error detection requirements of storage devices.
- Extended Hamming code is generated by the extended Hamming coding mechanism to generate a code table, which has It has dual functions of error detection and correction, but it is more complicated and consumes a lot of power.
- storage devices adopt an error correction mechanism, but the probability of errors in the initial stage of use of storage devices is very low. If a more complex error correction mechanism is used, resources will be wasted, and at the end of its life, the probability of errors is high. Increased, the simpler error correction mechanism cannot detect errors in time, resulting in frequent device restarts and crashes.
- the purpose of the present invention is to overcome the shortcomings of the prior art, provide a dual-mode error detection memory, introduce parity check and extended Hamming code at the same time, and use error correction code switching flags to switch between the two modes to meet the use requirements and improve at the same time Error correction rate to avoid frequent restart of the device.
- a dual-mode error detection memory including:
- An instruction processing module that communicates with an external circuit and receives a new instruction sent by the external circuit. It has an error correction code switch flag switch_flag inside.
- the error correction code switch flag has two states of 0 and 1, and 0 means parity is selected.
- Check code, 1 means to select extended Hamming code:
- a storage module storing physical words
- a control signal module which is respectively connected to the instruction processing module and the storage module, controls the storage module to perform storage or read operations according to the control signal sent by the instruction processing module, and feeds back the completion signal to the instruction processing module at the same time;
- An encoding module respectively connected with the instruction processing module and the storage module, encodes the logical words input by the instruction processing module, generates corresponding error correction codes and logical words to form physical words and sends them to the storage module;
- a decoding module is respectively connected with the instruction processing module and the storage module, reads the physical words from the storage module for error checking or error correction to generate error correction codes, and transmits the decoded logical words and error correction codes to the instruction processing module.
- the physical words include logical words and error correction codes.
- the error correction code is a parity check bit and an extended Hamming code.
- a dual-mode error detection method including the following:
- step b Detect the value of the error correction code switch flag switch_flag in the instruction processing module. If the error correction code switch flag is 0, use the parity check code as the error correction code, and the instruction processing module performs normal read and write operations, and run step b.
- the error code switching flag is 1, the extended Hamming code is used as the error correction code, the instruction processing module performs read and write operations, and step g is executed;
- the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;
- the encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;
- the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;
- the decoding module decodes the read physical words, and outputs the error detection results and data words to the instruction processing module;
- the instruction processing module judges whether there is an error according to the error detection result. If there is no error, it sends the read data word. If there is an error, it sets the error correction code flag switch_flag to 1, and returns to step a;
- the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;
- the encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;
- the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;
- the decoding module decodes the read physical word, and at the same time uses the extended Hamming code for error correction, and outputs the error detection result and the corrected data word to the instruction processing module;
- the instruction processing module sends the read data word and returns to step a.
- control signals in the steps b and g include a write signal and an address signal
- control signals in the steps d and i include a read signal and an address signal
- the dual-mode error detection memory disclosed in the present invention has the following beneficial effects:
- the simple error detection mechanism of parity check is used to meet the data security requirements at the early stage of memory life that is not prone to errors. At the same time, it can save power and reduce the delay of the memory in the cycle. After an error occurs at the end of the life, it will switch to the extended Hamming code mechanism to realize the synchronous error detection and correction of the memory, effectively avoiding the spread of storage errors and causing the system to crash.
- Figure 1 is a block diagram of a memory in an embodiment of the present invention.
- Figure 2 is a block diagram of organizing physical words in an embodiment of the present invention.
- Figure 3 is an error detection process in an embodiment of the present invention.
- a dual-mode error detection memory disclosed in the present invention includes an instruction processing module, a storage module, a control signal module, an encoding module, and a decoding module, wherein:
- the instruction processing module communicates with the external circuit and receives the read and write instructions sent by the external circuit.
- the error correction code switch flag switch_flag is set in the instruction processing module to select which error correction mechanism to use.
- the error correction code switch flag has 0 And 1 two states, 0 indicates that the parity bit is selected, and 1 indicates that the extended Hamming code is selected.
- the storage module is used to store relevant instruction information in the circuit.
- the control signal module is respectively connected with the instruction processing module and the storage module, and according to the control signal (including read/write, address) sent by the instruction processing module, the storage module is controlled to perform storage or read operations, and the completion signal (including read completion) And address) to the instruction processing module.
- the encoding module is respectively connected with the instruction processing module and the storage module, encodes the logical words input by the instruction processing module, generates corresponding parity bits and logical words to form physical words and sends them to the storage module;
- the decoding module is respectively connected with the instruction processing module and the storage module, reads the physical word from the storage module for decoding, and outputs the data word after error detection or correction and the error detection result (with 0/1/2 bit Error), if the current error correction mechanism of the memory is a parity check code, the decoding module only performs error detection on physical words, and if the current error correction mechanism of the memory is an extended Hamming code, the decoding module will only check physical words. Error, error correction processing is also performed at the same time, the error correction code is generated and the logic word is sent to the instruction processing module.
- the physical word in the storage module has a total of 13 bits, including 8 data bits (d0 ⁇ d7), 4 error correction codes (h0 ⁇ h3) and 1 parity bit (p).
- the bits b0 to b7 in the 13-bit physical word are the bits d0 to d7 of the logical word, and the bits b8 to b11 remain zero; the bit b12 is the parity bit P.
- the bits b0 to b7 are the bits d0 to d7 of the logical word
- the bits b8 to b11 are the bits h0 to h3 of the error correction code
- the bit b12 is the parity bit P.
- the coding efficiency is only 0.615.
- the characteristic of Hamming code is that as the length of the logical word increases, the coding efficiency also increases, while maintaining the error detection and correction capabilities constant. For example, when a 64-bit logical word corresponds to a 72-bit physical word, the coding efficiency reaches 0.889.
- the selection of the error correction code depends on the error correction code switch flag stored in the instruction processing module, in fact, it depends on the health status of the storage module.
- the present invention discloses a dual-mode error detection method, including the following contents:
- step b Detect the value of the error correction code switch flag switch_flag in the instruction processing module. If the error correction code switch flag is 0, use the parity check code as the error correction code, and the instruction processing module performs normal read and write operations, and run step b.
- the error code switching flag is 1, the extended Hamming code is used as the error correction code, the instruction processing module performs read and write operations, and step g is executed;
- the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;
- the encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;
- the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;
- the decoding module decodes the read physical words, and outputs the error detection results and data words to the instruction processing module;
- the instruction processing module judges whether there is an error according to the error detection result. If there is no error, it sends the read data word. If there is an error, it sets the error correction code flag switch_flag to 1, and returns to step a;
- the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;
- the encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;
- the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;
- the decoding module decodes the read physical word, and at the same time uses the extended Hamming code for error correction, and outputs the error detection result and the corrected data word to the instruction processing module;
- the instruction processing module sends the read data word and returns to step a.
- control signals in steps b and g include write signals and address signals
- control signals in steps d and i include read signals and address signals.
- the present invention improves the error correction code mode in the ECC memory, so that during the normal use period of the storage device, it uses a more power-saving and low-delay parity error correction mechanism to meet the error detection requirements of the storage device; for storage device error codes At the end of life with greatly improved rate, the extended Hamming code error correction method with single error correction and double error detection capabilities is used to protect data.
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Abstract
A dual-mode error detection memory, comprising an instruction processing module, a storage module, a control signal module, an encoding module, and a decoding module, wherein an error correction code switch flag is provided inside the instruction processing module, the error correction code switch flag has two states of 0 and 1, 0 represents selection of a parity check code, and 1 represents selection of an extended Hamming code; the control signal module controls, according to a control signal sent by the instruction processing module, the storage module to perform a storage or reading operation, and further feeds a completion signal back to the instruction processing module; the encoding module encodes a logical word input by the instruction processing module, and the decoding module reads a physical word from the storage module to perform debugging or error correction to generate an error correction code. According to the apparatus, parity check and extended Hamming codes are introduced at the same time, and switching between two modes is achieved by using an error correction code switch flag, so that the error correction rate is increased while the use requirement is met, and frequent device restart is avoided.
Description
本发明涉及存储技术，尤其涉及一种双模式检错内存的方法。The invention relates to storage technology, in particular to a dual-mode error detection memory method.
缓存装置和内存装置作为数据的缓冲区，是一些复杂硬件系统的正常工作的基础条件之一。其承担着缓冲数据的职能，与任何存储器一样，必须确保存储是可靠的并且不会变得不稳定(例如SRAM上由于电压突波或存储单元损坏导致的数据错误)。因此，存储必须与检错(和纠错)机制相关联。Cache devices and memory devices serve as data buffers and are one of the basic conditions for the normal operation of some complex hardware systems. It assumes the function of buffering data. Like any memory, it must be ensured that the storage is reliable and will not become unstable (for example, data errors on SRAM due to voltage surges or memory cell damage). Therefore, storage must be associated with error detection (and error correction) mechanisms.
一般的纠错机制包括奇偶校验和扩展汉明码，其中奇偶校验较为简单，且省电，可以满存储设备的一般检错需求，扩展汉明码由扩展汉明编码机制生成编码表，其具有检错和纠错双功能，但其较为复杂，且耗电大。General error correction mechanisms include parity check and extended Hamming code. Among them, parity check is relatively simple, saves power, and can meet the general error detection requirements of storage devices. Extended Hamming code is generated by the extended Hamming coding mechanism to generate a code table, which has It has dual functions of error detection and correction, but it is more complicated and consumes a lot of power.
目前存储设备上都采用的是一种纠错机制，但是存储设备在使用初期出错的概率很低，若采用较为复杂的纠错机制会导致资源浪费，而在寿命尾期，其出错的概率大大增加，较为简单的纠错机制无法及时检错，导致设备频繁重启而出现崩溃的情况。At present, storage devices adopt an error correction mechanism, but the probability of errors in the initial stage of use of storage devices is very low. If a more complex error correction mechanism is used, resources will be wasted, and at the end of its life, the probability of errors is high. Increased, the simpler error correction mechanism cannot detect errors in time, resulting in frequent device restarts and crashes.
发明内容Summary of the invention
本发明的目的在于克服现有技术的缺陷，提供一种双模式检错内存，同时引入奇偶校验和扩展汉明码，采用纠错码切换标志来实现两种模式的切换，满足使用需求同时提升纠错率，避免设备频繁重启。The purpose of the present invention is to overcome the shortcomings of the prior art, provide a dual-mode error detection memory, introduce parity check and extended Hamming code at the same time, and use error correction code switching flags to switch between the two modes to meet the use requirements and improve at the same time Error correction rate to avoid frequent restart of the device.
为实现上述目的，本发明提出如下技术方案：一种双模式检错内存，包括：In order to achieve the above objective, the present invention proposes the following technical solution: a dual-mode error detection memory, including:
一指令处理模块，与外部电路进行通信，接收外部电路发送过来的新指令，其内部设有纠错码切换标志switch_flag，所述纠错码切换标志具有0和1两种状态，0表示选择奇偶校验码，1表示选择扩展汉明码：An instruction processing module that communicates with an external circuit and receives a new instruction sent by the external circuit. It has an error correction code switch flag switch_flag inside. The error correction code switch flag has two states of 0 and 1, and 0 means parity is selected. Check code, 1 means to select extended Hamming code:
一存储模块，存储有物理字；A storage module, storing physical words;
一控制信号模块，分别与指令处理模块及存储模块连接，根据指令处理模块发送的控制信号，控制存储模块进行存储或读取操作，同时反馈完成信号给指令处理模块；A control signal module, which is respectively connected to the instruction processing module and the storage module, controls the storage module to perform storage or read operations according to the control signal sent by the instruction processing module, and feeds back the completion signal to the instruction processing module at the same time;
一编码模块，分别与指令处理模块及存储模块连接，对指令处理模块输入的逻辑字编码，生成对应的纠错码与逻辑字组成物理字送入存储模块；An encoding module, respectively connected with the instruction processing module and the storage module, encodes the logical words input by the instruction processing module, generates corresponding error correction codes and logical words to form physical words and sends them to the storage module;
一译码模块，分别与指令处理模块及存储模块连接，从存储模块中读取物理字进行查错或纠错生成纠错码，将解码后的逻辑字和纠错码传送给指令处理模块。A decoding module is respectively connected with the instruction processing module and the storage module, reads the physical words from the storage module for error checking or error correction to generate error correction codes, and transmits the decoded logical words and error correction codes to the instruction processing module.
优选的，所述物理字包括逻辑字和纠错码。Preferably, the physical words include logical words and error correction codes.
优选的，所述纠错码为奇偶校验位和扩展汉明码。Preferably, the error correction code is a parity check bit and an extended Hamming code.
一种双模式检错方法，包括如下内容：A dual-mode error detection method, including the following:
a、指令处理模块中检测纠错码切换标志switch_flag的值，若纠错码切换标志为0，采用奇偶校验码作为纠错码，指令处理模块进行正常读写操作，运行步骤b，若纠错码切换标志为1，采用扩展汉明码作为纠错码，指令处理模块进行读写操作，运行步骤g；a. Detect the value of the error correction code switch flag switch_flag in the instruction processing module. If the error correction code switch flag is 0, use the parity check code as the error correction code, and the instruction processing module performs normal read and write operations, and run step b. The error code switching flag is 1, the extended Hamming code is used as the error correction code, the instruction processing module performs read and write operations, and step g is executed;
b、若指令处理模块接收到写指令，将写指令中的控制信号发送给控制信号模块控制存储模块，而写指令中的逻辑字送入编码模块中；b. If the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;
c、编码模块对逻辑字进行编码生成对应的奇偶校验位，然后将原始逻辑字和对应的奇偶校验位组合成物理字写入存储模块；c. The encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;
d、若指令处理模块接收到读指令，将读指令中的控制信号送给控制信号模块控制存储模块，同时译码模块读取存储模块中相应的物理字；d. If the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;
e、译码模块对读取的物理字进行译码，输出检错结果及数据字给指令处理模块；e. The decoding module decodes the read physical words, and outputs the error detection results and data words to the instruction processing module;
f、指令处理模块根据检错结果判断是否存在错误，若不存在错误就将读取的数据字送出，若存在错误，则将纠错码标志位switch_flag设为1，返回步骤a；f. The instruction processing module judges whether there is an error according to the error detection result. If there is no error, it sends the read data word. If there is an error, it sets the error correction code flag switch_flag to 1, and returns to step a;
g、若指令处理模块接收到写指令，将写指令中的控制信号发送给控制信号模块控制存储模块，而写指令中的逻辑字送入编码模块中；g. If the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;
h、编码模块对逻辑字进行编码生成对应的奇偶校验位，然后将原始逻辑字和对应的奇偶校验位组合成物理字写入存储模块；h. The encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;
i、若指令处理模块接收到读指令，将读指令中的控制信号送给控制信号模块控制存储模块，同时译码模块读取存储模块中相应的物理字；i. If the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;
j、译码模块对读取的物理字进行译码，同时利用扩展汉明码进行纠错，输出检错结果及纠错后的数据字给指令处理模块；j. The decoding module decodes the read physical word, and at the same time uses the extended Hamming code for error correction, and outputs the error detection result and the corrected data word to the instruction processing module;
k、指令处理模块将读取的数据字送出，返回步骤a。k. The instruction processing module sends the read data word and returns to step a.
优选的，所述步骤b、g中控制信号包括写信号及地址信号，而步骤d、i中控制信号包括读信号及地址信号。Preferably, the control signals in the steps b and g include a write signal and an address signal, and the control signals in the steps d and i include a read signal and an address signal.
与现有技术相比，本发明所揭示的一种双模式检错内存，具有如下有益效果：Compared with the prior art, the dual-mode error detection memory disclosed in the present invention has the following beneficial effects:
同时引入奇偶校验位和扩展汉明码两种纠错机制，配合纠错码切换标志，在存储器寿命前期不易出错的阶段，通过奇偶校验这种简单的检错机制来满足数据安全性要求，同时可以达到省电和降低周期内存储器的延迟，而在寿命后期出现错误后，就切换至扩展汉明码机制，实现对存储器同步检错和纠错，有效避免存储错误扩散导致系统崩溃。At the same time, two error correction mechanisms, parity bit and extended Hamming code are introduced, and with the error correction code switching flag, the simple error detection mechanism of parity check is used to meet the data security requirements at the early stage of memory life that is not prone to errors. At the same time, it can save power and reduce the delay of the memory in the cycle. After an error occurs at the end of the life, it will switch to the extended Hamming code mechanism to realize the synchronous error detection and correction of the memory, effectively avoiding the spread of storage errors and causing the system to crash.
图1是本发明实施例中内存的模块图；Figure 1 is a block diagram of a memory in an embodiment of the present invention;
图2是本发明实施例中组织物理字的框图；Figure 2 is a block diagram of organizing physical words in an embodiment of the present invention;
图3是本发明实施例中检错流程。Figure 3 is an error detection process in an embodiment of the present invention.
下面将结合本发明的附图，对本发明实施例的技术方案进行清楚、完整的描述。The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.
如图1所示，本发明所揭示的一种双模式检错内存，包括指令处理模块，存储模块，控制信号模块，编码模块及译码模块，其中：As shown in Figure 1, a dual-mode error detection memory disclosed in the present invention includes an instruction processing module, a storage module, a control signal module, an encoding module, and a decoding module, wherein:
指令处理模块，与外部电路进行通信，接收外部电路发送过来的读写指令，该指令处理模块中设置了纠错码切换标志switch_flag来选择采用何种纠错机制，该纠错码切换标志具有0和1两个状态，0表示选择奇偶校验位，而1表示选择扩展汉明码。The instruction processing module communicates with the external circuit and receives the read and write instructions sent by the external circuit. The error correction code switch flag switch_flag is set in the instruction processing module to select which error correction mechanism to use. The error correction code switch flag has 0 And 1 two states, 0 indicates that the parity bit is selected, and 1 indicates that the extended Hamming code is selected.
所述存储模块用于存储电路中的相关指令信息。The storage module is used to store relevant instruction information in the circuit.
所述控制信号模块分别与指令处理模块及存储模块连接，根据指令处理模块发送的控制信号(包括读/写，地址)，控制存储模块进行存储或读取操作，同时反馈完成信号(包括读完成和地址)给指令处理模块。The control signal module is respectively connected with the instruction processing module and the storage module, and according to the control signal (including read/write, address) sent by the instruction processing module, the storage module is controlled to perform storage or read operations, and the completion signal (including read completion) And address) to the instruction processing module.
所述编码模块分别与指令处理模块及存储模块连接，对指令处理模块输入的逻辑字进行编码，生成对应的奇偶校验位与逻辑字组成物理字送入存储模块；The encoding module is respectively connected with the instruction processing module and the storage module, encodes the logical words input by the instruction processing module, generates corresponding parity bits and logical words to form physical words and sends them to the storage module;
所述译码模块分别与指令处理模块及存储模块连接，从存储模块中读取物理字进行译码，输出经过检错或纠错的数据字及其检错结果(有0/1/2比特出错)，若当前内存的纠错机制为奇偶校验码，译码模块仅仅对物理字进行检错，而若当前内存的纠错机制为扩展汉明码，则译码模块除了对物理字进行检错，同时还进行纠错处理，生成纠错码连同逻辑字送入指令处理模块。The decoding module is respectively connected with the instruction processing module and the storage module, reads the physical word from the storage module for decoding, and outputs the data word after error detection or correction and the error detection result (with 0/1/2 bit Error), if the current error correction mechanism of the memory is a parity check code, the decoding module only performs error detection on physical words, and if the current error correction mechanism of the memory is an extended Hamming code, the decoding module will only check physical words. Error, error correction processing is also performed at the same time, the error correction code is generated and the logic word is sent to the instruction processing module.
如图2所示，存储模块中物理字总共13位，包括8位数据位(d0～d7)，4位纠错码(h0～h3)及1位奇偶校验位(p)。As shown in Figure 2, the physical word in the storage module has a total of 13 bits, including 8 data bits (d0 ~ d7), 4 error correction codes (h0 ~ h3) and 1 parity bit (p).
当纠错机制为奇偶校验位时，13位物理字中位b0～b7为逻辑字的位d0～d7，位b8～b11保持为零；位b12为奇偶校验位P。When the error correction mechanism is the parity bit, the bits b0 to b7 in the 13-bit physical word are the bits d0 to d7 of the logical word, and the bits b8 to b11 remain zero; the bit b12 is the parity bit P.
当纠错机制为扩展汉明码，在这种情况下：When the error correction mechanism is extended Hamming code, in this case:
13位物理字中位b0～b7为逻辑字的位d0～d7，位b8～b11为纠错码的位h0～h3；位b12为奇偶校验位P。In the 13-bit physical word, the bits b0 to b7 are the bits d0 to d7 of the logical word, the bits b8 to b11 are the bits h0 to h3 of the error correction code; the bit b12 is the parity bit P.
在上面的13位物理字和8位逻辑字的示例中，编码效率仅为0.615，然而，汉明码的特点是随逻辑字长度增加，编码效率亦随之提高，同时维 持检错与纠错能力不变。例如64位逻辑字对应72位物理字时，编码效率达到0.889。而纠错码的选择取决于指令处理模块内部存储的纠错码切换标志，事实上，取决于存储模块的健康状况。In the above example of 13-bit physical words and 8-bit logical words, the coding efficiency is only 0.615. However, the characteristic of Hamming code is that as the length of the logical word increases, the coding efficiency also increases, while maintaining the error detection and correction capabilities constant. For example, when a 64-bit logical word corresponds to a 72-bit physical word, the coding efficiency reaches 0.889. The selection of the error correction code depends on the error correction code switch flag stored in the instruction processing module, in fact, it depends on the health status of the storage module.
如图3所示，本发明揭示一种双模式检错方法，包括如下内容：As shown in Figure 3, the present invention discloses a dual-mode error detection method, including the following contents:
a、指令处理模块中检测纠错码切换标志switch_flag的值，若纠错码切换标志为0，采用奇偶校验码作为纠错码，指令处理模块进行正常读写操作，运行步骤b，若纠错码切换标志为1，采用扩展汉明码作为纠错码，指令处理模块进行读写操作，运行步骤g；a. Detect the value of the error correction code switch flag switch_flag in the instruction processing module. If the error correction code switch flag is 0, use the parity check code as the error correction code, and the instruction processing module performs normal read and write operations, and run step b. The error code switching flag is 1, the extended Hamming code is used as the error correction code, the instruction processing module performs read and write operations, and step g is executed;
b、若指令处理模块接收到写指令，将写指令中的控制信号发送给控制信号模块控制存储模块，而写指令中的逻辑字送入编码模块中；b. If the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;
c、编码模块对逻辑字进行编码生成对应的奇偶校验位，然后将原始逻辑字和对应的奇偶校验位组合成物理字写入存储模块；c. The encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;
d、若指令处理模块接收到读指令，将读指令中的控制信号送给控制信号模块控制存储模块，同时译码模块读取存储模块中相应的物理字；d. If the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;
e、译码模块对读取的物理字进行译码，输出检错结果及数据字给指令处理模块；e. The decoding module decodes the read physical words, and outputs the error detection results and data words to the instruction processing module;
f、指令处理模块根据检错结果判断是否存在错误，若不存在错误就将读取的数据字送出，若存在错误，则将纠错码标志位switch_flag设为1，返回步骤a；f. The instruction processing module judges whether there is an error according to the error detection result. If there is no error, it sends the read data word. If there is an error, it sets the error correction code flag switch_flag to 1, and returns to step a;
g、若指令处理模块接收到写指令，将写指令中的控制信号发送给控制信号模块控制存储模块，而写指令中的逻辑字送入编码模块中；g. If the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;
h、编码模块对逻辑字进行编码生成对应的奇偶校验位，然后将原始逻辑字和对应的奇偶校验位组合成物理字写入存储模块；h. The encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;
i、若指令处理模块接收到读指令，将读指令中的控制信号送给控制信号模块控制存储模块，同时译码模块读取存储模块中相应的物理字；i. If the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;
j、译码模块对读取的物理字进行译码，同时利用扩展汉明码进行纠错，输出检错结果及纠错后的数据字给指令处理模块；j. The decoding module decodes the read physical word, and at the same time uses the extended Hamming code for error correction, and outputs the error detection result and the corrected data word to the instruction processing module;
k、指令处理模块将读取的数据字送出，返回步骤a。k. The instruction processing module sends the read data word and returns to step a.
所述步骤b、g中控制信号包括写信号及地址信号，而步骤d、i中控制信号包括读信号及地址信号。The control signals in steps b and g include write signals and address signals, and the control signals in steps d and i include read signals and address signals.
本发明改进了ECC存储器中纠错码的方式，使其在存储设备的正常使用周期，用更省电并且低延迟的奇偶校验纠错机制满足存储设备的检错需求；对于存储设备误码率大大提高的寿命尾期，使用具有单错校正双错检测能力的扩展汉明码纠错方法来保护数据。The present invention improves the error correction code mode in the ECC memory, so that during the normal use period of the storage device, it uses a more power-saving and low-delay parity error correction mechanism to meet the error detection requirements of the storage device; for storage device error codes At the end of life with greatly improved rate, the extended Hamming code error correction method with single error correction and double error detection capabilities is used to protect data.
本发明的技术内容及技术特征已揭示如上，然而熟悉本领域的技术人员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰，因此，本发明保护范围应不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请权利要求所涵盖。The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention should not be limited The content disclosed in the embodiments should include various substitutions and modifications that do not deviate from the present invention, and are covered by the claims of this patent application.
Claims (5)
- 一种双模式检错内存，其特征在于包括：A dual-mode error detection memory, which is characterized by including:一指令处理模块，与外部电路进行通信，接收外部电路发送过来的新指令，其内部设有纠错码切换标志switch_flag，所述纠错码切换标志具有0和1两种状态，0表示选择奇偶校验码，1表示选择扩展汉明码：An instruction processing module that communicates with an external circuit and receives a new instruction sent by the external circuit. It has an error correction code switch flag switch_flag inside. The error correction code switch flag has two states of 0 and 1, and 0 means parity is selected. Check code, 1 means to select extended Hamming code:一存储模块，存储有物理字；A storage module, storing physical words;一控制信号模块，分别与指令处理模块及存储模块连接，根据指令处理模块发送的控制信号，控制存储模块进行存储或读取操作，同时反馈完成信号给指令处理模块；A control signal module, which is respectively connected to the instruction processing module and the storage module, controls the storage module to perform storage or read operations according to the control signal sent by the instruction processing module, and feeds back the completion signal to the instruction processing module at the same time;一编码模块，分别与指令处理模块及存储模块连接，对指令处理模块输入的逻辑字编码，生成对应的纠错码与逻辑字组成物理字送入存储模块；An encoding module, respectively connected with the instruction processing module and the storage module, encodes the logical words input by the instruction processing module, generates corresponding error correction codes and logical words to form physical words and sends them to the storage module;一译码模块，分别与指令处理模块及存储模块连接，从存储模块中读取物理字进行查错或纠错生成纠错码，将解码后的逻辑字和纠错码传送给指令处理模块。A decoding module is respectively connected with the instruction processing module and the storage module, reads the physical words from the storage module for error checking or error correction to generate error correction codes, and transmits the decoded logical words and error correction codes to the instruction processing module.
- 根据权利要求1所述的双模式检错内存，其特征在于：所述物理字包括逻辑字和纠错码。The dual-mode error detection memory according to claim 1, wherein the physical words include logical words and error correction codes.
- 根据权利要求1所述的双模式检错内存，其特征在于：所述纠错码为奇偶校验位和扩展汉明码。The dual-mode error detection memory according to claim 1, wherein the error correction code is a parity bit and an extended Hamming code.
- 一种双模式检错方法，基于权利要求1所述双模式内存实现，其特征在于包括如下内容：A dual-mode error detection method based on the dual-mode memory implementation of claim 1, characterized in that it includes the following content:a、指令处理模块中检测纠错码切换标志switch_flag的值，若纠错码切换标志为0，采用奇偶校验码作为纠错码，指令处理模块进行正常读写操作，运行步骤b，若纠错码切换标志为1，采用扩展汉明码作为纠错码，指令处理模块进行读写操作，运行步骤g；a. Detect the value of the error correction code switch flag switch_flag in the instruction processing module. If the error correction code switch flag is 0, use the parity check code as the error correction code, and the instruction processing module performs normal read and write operations, and run step b. The error code switching flag is 1, the extended Hamming code is used as the error correction code, the instruction processing module performs read and write operations, and step g is executed;b、若指令处理模块接收到写指令，将写指令中的控制信号发送给控制信号模块控制存储模块，而写指令中的逻辑字送入编码模块中；b. If the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;c、编码模块对逻辑字进行编码生成对应的奇偶校验位，然后将原始逻辑字和对应的奇偶校验位组合成物理字写入存储模块；c. The encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;d、若指令处理模块接收到读指令，将读指令中的控制信号送给控制信号模块控制存储模块，同时译码模块读取存储模块中相应的物理字；d. If the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;e、译码模块对读取的物理字进行译码，输出检错结果及数据字给指令处理模块；e. The decoding module decodes the read physical words, and outputs the error detection results and data words to the instruction processing module;f、指令处理模块根据检错结果判断是否存在错误，若不存在错误就将读取的数据字送出，若存在错误，则将纠错码标志位switch_flag设为1，返回步骤a；f. The instruction processing module judges whether there is an error according to the error detection result. If there is no error, it sends the read data word. If there is an error, it sets the error correction code flag switch_flag to 1, and returns to step a;g、若指令处理模块接收到写指令，将写指令中的控制信号发送给控制信号模块控制存储模块，而写指令中的逻辑字送入编码模块中；g. If the instruction processing module receives the write instruction, it sends the control signal in the write instruction to the control signal module to control the storage module, and the logic word in the write instruction is sent to the encoding module;h、编码模块对逻辑字进行编码生成对应的奇偶校验位，然后将原始逻辑字和对应的奇偶校验位组合成物理字写入存储模块；h. The encoding module encodes the logical word to generate the corresponding parity check bit, and then combines the original logical word and the corresponding parity check bit into a physical word and writes it into the storage module;i、若指令处理模块接收到读指令，将读指令中的控制信号送给控制信号模块控制存储模块，同时译码模块读取存储模块中相应的物理字；i. If the instruction processing module receives the read instruction, it sends the control signal in the read instruction to the control signal module to control the storage module, and the decoding module reads the corresponding physical word in the storage module at the same time;j、译码模块对读取的物理字进行译码，同时利用扩展汉明码进行纠错，输出检错结果及纠错后的数据字给指令处理模块；j. The decoding module decodes the read physical word, and at the same time uses the extended Hamming code for error correction, and outputs the error detection result and the corrected data word to the instruction processing module;k、指令处理模块将读取的数据字送出，返回步骤a。k. The instruction processing module sends the read data word and returns to step a.
- 根据权利要求4所述的双模式检错方法，其特征在于：所述步骤b、g中控制信号包括写信号及地址信号，而步骤d、i中控制信号包括读信号及地址信号。The dual-mode error detection method according to claim 4, wherein the control signals in steps b and g include write signals and address signals, and the control signals in steps d and i include read signals and address signals.
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| CN109903806A (en) * | 2019-04-01 | 2019-06-18 | 江苏华存电子科技有限公司 | A kind of double mode error detection memory and double mode error-detecting method |
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| US12225126B2 (en) | 2021-12-21 | 2025-02-11 | Silicon Motion, Inc. | Apparatus and method for detecting errors during data encryption |
| US12348630B2 (en) | 2021-12-21 | 2025-07-01 | Silicon Motion, Inc. | Apparatus and method for detecting errors during data encryption |
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| US12273108B2 (en) | 2023-03-20 | 2025-04-08 | Silicon Motion, Inc. | Apparatus and method for expanding round keys during data encryption |
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