WO2020188168A1 - Method for transferring a useful layer onto a support substrate - Google Patents
Method for transferring a useful layer onto a support substrate Download PDFInfo
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- WO2020188168A1 WO2020188168A1 PCT/FR2020/050368 FR2020050368W WO2020188168A1 WO 2020188168 A1 WO2020188168 A1 WO 2020188168A1 FR 2020050368 W FR2020050368 W FR 2020050368W WO 2020188168 A1 WO2020188168 A1 WO 2020188168A1
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- bonded structure
- buried
- support substrate
- plane
- transfer method
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- 239000000758 substrate Substances 0.000 title claims abstract description 91
- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000000977 initiatory effect Effects 0.000 claims abstract description 38
- 238000000137 annealing Methods 0.000 claims abstract description 32
- 238000010438 heat treatment Methods 0.000 claims description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 239000001307 helium Substances 0.000 claims description 7
- 229910052734 helium Inorganic materials 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 230000002269 spontaneous effect Effects 0.000 claims description 4
- 238000011282 treatment Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000001902 propagating effect Effects 0.000 claims description 2
- 230000003313 weakening effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 49
- 230000035882 stress Effects 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000001788 irregular Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000002513 implantation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006355 external stress Effects 0.000 description 3
- 238000009499 grossing Methods 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000012512 characterization method Methods 0.000 description 2
- 238000004320 controlled atmosphere Methods 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 230000010070 molecular adhesion Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 238000004971 IR microspectroscopy Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- -1 helium ions Chemical class 0.000 description 1
- 230000001976 improved effect Effects 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
Definitions
- TITLE PROCESS FOR TRANSFERRING A USEFUL LAYER ON A
- the present invention relates to the field of microelectronics. It relates in particular to a method of transferring a useful layer onto a support substrate.
- a method of transferring a useful layer 3 onto a support substrate 4, shown in FIG. 1, is known from the state of the art; this process described in particular in documents WO2005043615 and WO2005043616 comprises the following steps:
- the species implanted at the level of the buried fragile plane 2 are at the origin of the development of microcavities.
- the thermal embrittlement treatment has the effect of promoting the growth and pressurization of these microcavities.
- additional external forces energy pulse
- the initiation of a fracture wave in the buried fragile plane 2 is operated, which wave propagates in a self-sustaining manner, leading the transfer of the useful layer 3 by detachment at the level of the buried fragile plane 2.
- This process can be used for the manufacture of silicon on insulator substrates (SOI - “Silicon on insulator”).
- the donor substrate 1 and the support substrate 4 are each formed from a silicon wafer, the standardized diameter of which is typically 200mm, 300mm, or even 450 mm for the next generations.
- One and / or the other of the donor substrate 1 and of the support substrate 4 are oxidized at the surface.
- SOI substrates must meet very precise specifications. This is particularly the case for the average thickness and the uniformity of thickness of the useful layer 3. Compliance with these specifications is required for the proper functioning of the semiconductor devices which will be formed in and on this useful layer 3. .
- the architecture of these semiconductor devices requires the availability of SOI substrates having a very low average thickness of the useful layer 3, for example less than 50 nm, and having very good uniformity of thickness of the layer. useful 3.
- the expected thickness uniformity can be of the order of 5% at most, corresponding to variations typically ranging from +/- 0.3nm to +/- lnm over the entire surface of the useful layer 3.
- additional finishing steps such as etching or heat treatments for surface smoothing, are carried out after the useful layer 3 is transferred to the support substrate 4, it is important that the surface morphological properties (in particular, thickness uniformity and surface roughness) are as favorable as possible after transfer, to ensure that specifications are maintained finals.
- certain useful layers 3 may comprise, after transfer, irregular patterns of the marbling type resulting in local variations in thickness, the amplitude of which is of the order of one nm or half a nanometer. These mottles can be distributed over the whole of the useful layer 3, or over only a part. They contribute to the non-uniformity of the useful layer 3.
- This type of non-uniformity of thickness of the useful layer 3 is very difficult to eliminate by the usual finishing techniques (etching, sacrificial oxidation, heat treatment of smoothing) because the latter are not effective in erasing irregular patterns of this. amplitude.
- document EP2933828 proposes to put in contact with the assembly to be fractured, an absorbing element to dissipate the acoustic vibrations emitted during initiation and the self-sustaining propagation of the fracture wave.
- the present invention relates to a method of transferring a useful layer onto a support substrate.
- the process offers a alternative solution to those of the state of the art, aimed in particular at improving the uniformity of thickness of the useful layers after transfer.
- the invention relates to a method of transferring a useful layer onto a support substrate, comprising the following steps:
- a donor substrate comprising a buried fragile plane, the useful layer being delimited by a front face of the donor substrate and the buried fragile plane;
- the transfer process is remarkable in that the initiation of the fracture wave is carried out while the bonded structure undergoes, at least in its hottest region, a maximum temperature of between 150 ° and 250 ° C.
- the maximum temperature is between 180 ° C and 220 ° C;
- step d • the annealing of step d) reaches a maximum plateau temperature of between 300 ° C and 600 ° C;
- the thermal embrittlement budget is between 40% and 95% of a thermal fracture budget, the thermal fracture budget leading to spontaneous initiation of the fracture wave in the brittle plane buried during annealing;
- step e • the initiation of step e) is carried out directly after the annealing of step d), before the hottest region of the bonded structure is subjected to a temperature below 150 ° C .;
- step d) • the annealing of step d) is carried out in heat treatment equipment of horizontal or vertical configuration, suitable for the collective treatment of a plurality of bonded structures, and the initiation of step e) is carried out during removal of glued structures from the equipment;
- the donor substrate and the support substrate are made of monocrystalline silicon, and in which the buried fragile plane is formed by ionic implantation of light species in the donor substrate, said light species being chosen from hydrogen and helium or a combination hydrogen and helium.
- FIG. 1 shows a method of transferring a thin film according to the state of the art
- FIG. 2 presents a transfer method according to the invention
- FIGS. 3a to 3c show “haze” maps on the surface of useful layers comprising non-uniformities of thickness after transfer;
- FIG. 4 shows a “haze” map on the surface of a useful layer transferred by a transfer method in accordance with the invention
- FIG. 5 shows a step of a transfer method according to the invention
- FIG. 6 presents a graph showing the temperatures and the thermal gradient seen by a bonded structure in a step of a transfer process according to the invention
- FIG. 7 shows a step of a transfer method according to the invention.
- the invention relates to a method of transferring a useful layer 3 onto a support substrate 4.
- the useful layer 3 is so named because it is intended to be used for the manufacture of. components in the fields of microelectronics or microsystems.
- the useful layer and the support substrate can be of various types depending on the type of component and the intended application. Since silicon is the semiconductor material most used at present, the useful layer and the support substrate can in particular be made of monocrystalline silicon but are of course not limited to this material.
- the transfer method according to the invention first of all comprises a step a) of supplying a donor substrate 1, from which the useful layer 3 will be obtained.
- the donor substrate 1 comprises a buried fragile plane 2 (FIG. 2 - a). ).
- the latter is advantageously formed by ion implantation of light species in the donor substrate 1, at a defined depth.
- the light species are preferably chosen from hydrogen and helium, or a combination of hydrogen and helium, because these species are favorable to the formation of microcavities around the defined depth of implantation, giving rise to the fragile plane.
- the useful layer 3 is delimited by a front face 1a of the donor substrate 1 and the buried fragile plane 2.
- the donor substrate 1 can be formed by at least one material chosen from among silicon, germanium, silicon carbide, compound semiconductors IV-IV, III-V or II-VI, piezoelectric materials (for example, LiNb03 , LiTa03, ...), etc. It may also include one or more surface layer (s) arranged on its front face 1a and / or on its rear face 1b, of all kinds, for example dielectric (s).
- the transfer process also comprises a step b) of providing a support substrate 4 (FIG. 2 - b)).
- the support substrate can for example be formed by at least one material chosen from among silicon, silicon carbide, glass, sapphire, aluminum nitride, or any other material capable of being available in the form of a substrate. he can also comprise one or more surface layer (s) of all kinds, for example dielectric (s).
- the transfer method according to the invention is the manufacture of SOI substrates.
- the donor substrate 1 and the support substrate 4 are made of monocrystalline silicon, and one and / or the other of said substrates comprises a surface layer of silicon oxide 6 on its front face.
- the transfer method then comprises a step c) of assembly, according to a bonding interface 7, of the donor substrate 1, at its front face 1a, and of the support substrate 4, to form a bonded structure 5 (FIG. 2 - vs) ) .
- the assembly can be carried out by any known method, in particular by direct bonding by molecular adhesion, or by thermocompression, or even by electrostatic bonding. These techniques, which are well known from the state of the art, will not be described in detail here. It is nevertheless recalled that, prior to assembly, the donor 1 and support 4 substrates will have undergone cleaning and / or surface activation sequences, so as to guarantee the quality of the bonding interface 7 in terms of defectivity. and bonding energy.
- a step d) of annealing the bonded structure 5 is then carried out, to apply to said structure 5 a thermal embrittlement budget and bring the buried fragile plane to a defined level of embrittlement. (figure 2 - d)).
- the time / temperature pairs applied during annealing determine the thermal budget undergone by the bonded structure 5.
- the temperature range in which annealing can be carried out for this embrittlement of the buried plane 2 depends on essentially of the type of bonded structure 5 (homo-structure or hetero-structure) and of the nature of the donor substrate 1.
- the annealing of step d) reaches a maximum plateau temperature typically between 200 ° C and 600 ° C, advantageously between 300 and 500 ° C, and even more advantageously between 350 ° C and 450 ° C.
- the maximum plateau temperature may more generally, for materials used for the donor substrate 1 and / or for the support substrate 4 other than silicon, typically be between 200 ° C and 800 ° C.
- Annealing may include a temperature rise ramp (typically between 200 ° C. and the maximum plateau temperature) and a plateau at the maximum temperature. In general, such an annealing will have a duration of between a few tens of minutes and several hours, depending on the maximum stage temperature of the annealing.
- the level of embrittlement of the buried brittle plane 2 is defined by the surface occupied by the microcavities present in the buried brittle plane 2.
- the characterization of this surface occupied by the microcavities can be perform by infrared microscopy.
- the level of embrittlement can increase from a low level ( ⁇ 1%, below the detection threshold of the characterization instruments) to more than 80%, depending on the thermal budget applied to the bonded structure 5 during annealing.
- the thermal embrittlement budget is always kept below a thermal fracture budget, for which the spontaneous initiation of the fracture wave in the buried fragile plane 2 is obtained during annealing.
- the thermal budget for embrittlement is between 40% and 95% of the thermal budget for fracture.
- a step e) of initiation of a fracture wave along the buried brittle plane 2 is then carried out, by applying a stress to the buried brittle plane 2 of the bonded structure 5 (figure 2 - e)).
- the fracture wave After initiation, the fracture wave propagates in a self-sustaining manner, leading to the separation of the bonded structure 5 at the level of the buried fragile plane 2.
- a self-sustaining propagation reflects the fact that once initiated, the wave of The fracture propagates by itself, without the application of any external stress and over the entire extent of the buried fragile plane 2, so as to completely detach the useful layer 3 from the donor substrate 1 and to transfer it to the support substrate 4. We obtain thus a transferred set 5a and the remainder 5b of the donor substrate 1 (FIG. 2 - f)).
- the external stress is advantageously local and can be of mechanical origin or of any other origin such as, for example, localized heating carried out by a laser or an input of energy by ultrasound.
- the transfer method provides that the initiation of the fracture wave in step e) is performed by application of 'a external stress to the buried brittle plane 2 while the bonded structure 5 is subjected, at least in its hottest region (or typically, in its hottest point), to a maximum temperature of between 150 ° and 250 ° C.
- the invention therefore provides that the region of the bonded structure 5 undergoing the highest temperatures (its hottest region) sees a temperature between 150 ° C. and 250 ° C.
- the initiation of the fracture is effected when the maximum temperature to which the bonded structure 5 is subjected, locally in its hottest region or uniformly over its entire extent, is within this temperature range.
- the aforementioned maximum temperature is between 180 ° C and 220 ° C, preferably around 200 ° C.
- the energy stored in the system is sufficient to guarantee a self-sustaining and stable propagation of the fracture wave.
- the Applicant has observed that when the excess energy released during the fracture is too great, regular patterns of large amplitude can appear and degrade the uniformity of thickness of the useful layer 3 after transfer. This can be for example the case, when the fracture budget is applied to a bonded structure 5 and that a fracture wave initiates spontaneously at the annealing stage temperature (eg 400 ° C). Too much energy stored and released during the propagation of the fracture wave is therefore also problematic with respect to the uniformity of thickness of the useful layer 3 after transfer.
- the energy stored in the system depends on the one hand on the level of embrittlement of the buried fragile plane 2 and on the other hand on the temperature at which the fracture wave is initiated and will propagate.
- the transfer method according to the invention makes it possible to initiate the fracture wave when the energy stored in the system is, on the one hand, sufficient to guarantee a self-sustaining and stable propagation (thus limiting the appearance of patterns irregular), and secondly, little excess to limit the amplitude of regular patterns also degrading the uniformity of thickness.
- FIGS. 3a, 3b and 3c show "haze" maps on the surface of useful layers 3 after a fracture, respectively spontaneous, mechanical initiated at room temperature and mechanical initiated with a maximum temperature undergone by the bonded structure. of 100 ° C. Note that the initiation of the aforementioned mechanical fractures was made by local mechanical stress exerted on the bonded structures 5 and generating a stress in the buried brittle plane 2. In each case, regular (figure 3a) or irregular patterns are noted. ( Figures 3b and 3c) of the marbling type which degrade the thickness uniformity of the useful layer 3 after transfer (between 0.5 and 1.5 nm in amplitude).
- FIG. 4 shows a “haze” map on the surface of a useful layer 3 transferred by a transfer process according to the invention: that is to say after a fracture initiated while the bonded structure 5 is undergoing, at less in its hottest region, a temperature of 200 ° C, by a local mechanical stress exerted on the bonded structure 5 generating a stress in the buried fragile plane 2. No pattern, neither regular nor irregular of the marbling type is present, the thickness uniformity of the useful layer 3 is thus greatly improved.
- the initiation of step e) is carried out directly after the annealing of step d), before the hottest region of the bonded structure 5 is subjected to a temperature below 150 ° C.
- the initiation is carried out when the bonded structure 5 (at least at the level of its hottest region) experiences a maximum temperature less than or equal to 250 ° C and before it experiences a maximum temperature of 150 ° C.
- step e) of initiation of the fracture wave when the bonded structure 5 leaves the heat treatment equipment 20 used for annealing, in a controlled exit zone 23 in which the bonded structure 5 is subjected to a maximum temperature greater than 150 ° C. and less than or equal to 250 ° C. (FIG. 2 - e)).
- the annealing of step d) can be carried out in heat treatment equipment 20 of horizontal or vertical configuration, suitable for the collective treatment of a plurality of bonded structures 5; the initiation of step e) is then carried out when the bonded structures 5 leave the equipment 20, in the exit zone 23 where the maximum temperature undergone by the structures 5 is controlled within the range required for initiation of the fracture wave.
- the external constraint to trigger the initiation of the fracture wave is advantageously applied to the bonded structures 5 successively, as they pass through the controlled exit zone 23.
- the initiation of step e) is carried out after the hottest region of the bonded structure 5 has undergone a temperature below 150 ° C.
- the bonded structure 5 is maintained in a controlled atmosphere between the end of the annealing of step d) and the moment of the initiation of the fracture wave which will require that the bonded structure 5 is brought back to a maximum temperature. between 150 ° C and 250 ° C.
- controlled atmosphere is meant here a dry atmosphere having less than 0.1% humidity.
- step d) when the annealing of step d) exhibits a temperature rise ramp up to 400 ° C, then a temperature drop ramp down to 150 ° C before the bonded structure returns to ambient temperature 5 , the latter is maintained in a dry atmosphere until step e) of initiation of the fracture wave.
- the application of a stress to the buried fragile plane 2 corresponds to the application of a local mechanical stress on the bonded structure 5, in particular on the periphery. of said structure, so as to initiate the fracture wave.
- the local mechanical stress can be achieved by inserting a bevel 10, facing the bonding interface 7 of the bonded structure 5, between chamfered edges respectively of the donor substrate 1 and of the support substrate 4 of said bonded structure 5. This has for effect of generating a stress in tension in the buried brittle plane 2.
- the local mechanical stress is exerted in a region of the bonded structure 5 undergoing lower temperatures, when a temperature gradient exists on the bonded structure 5 during step e). Said region is hereinafter called the cold region, as opposed to the hottest region of the bonded structure 5 mentioned above.
- a thermal gradient exists in general on each bonded structure 5 ( Figures 5 and 6). This gradient is generally due to the geometry of the furnace and to the presence of a system for maintaining the bonded structures 5, which influence the heat dissipation. For example, in the case of a furnace of horizontal configuration 20, in which the bonded structures
- the local mechanical stress is exerted on the bonded structure 5 when the temperature gradient is of the order of 80 ° C, ie 80 ° C +/- 15 ° C.
- the Applicant has observed that a temperature gradient of 80 ° C + / - 10 ° C undergone by the bonded structure 5 at the time of initiation of the fracture wave helped to improve the uniformity of thickness of the useful layer 3 after transfer.
- the transfer method according to the invention can be used for the manufacture of SOI substrates in which the useful layer 3 is very thin, in particular between a few nanometers and 50 nm.
- donor 1 and support 4 substrates in monocrystalline silicon each in the form of a wafer 300 mm in diameter.
- the donor substrate is covered with a layer of silicon oxide 6 50 nm thick.
- the buried fragile plane 2 is formed in the donor substrate 1 by co-implantation of hydrogen and helium ions under the following conditions:
- H implantation energy 38 keV, dose 1E16 H / cm2,
- He implantation energy 25 keV, dose 1E16 He / cm2.
- the buried fragile plane 2 is located at a depth of approximately 290 nm, from the surface 1a of the donor substrate 1. It delimits, with the oxide layer 6, a useful layer 3 of approximately 240 nm.
- the assembly of the donor substrate 1 and the support substrate 4 is made by direct bonding by molecular adhesion, to form the bonded structure 5.
- the donor 1 and support 4 substrates Prior to assembly, will have undergone cleaning and / or sequences. known surface activation, so as to guarantee the quality of the bonding interface 7 in terms of defectivity and bonding energy.
- a furnace 20 of horizontal configuration is used to collectively perform the annealing of a plurality of bonded structures such as that described above.
- This type of equipment heat treatment 20 comprises a loading shovel 21 which supports nacelles 22 in which the bonded structures 5 are positioned (FIG. 7).
- the loading shovel 21 moves between a retracted position, in which the bonded structures 5 are inside the oven 20, and an extended position, in which they are outside the oven 20.
- a system of bevels 10 can be positioned on each nacelle 22, below the bonded structures 5.
- the loading shovel 21 moves in the retracted position for carrying out the annealing.
- the annealing includes a temperature rise ramp from 200 ° C to 380 ° C, a plateau at 380 ° C for 2 minutes and a temperature drop ramp down to 225 ° C.
- the loading shovel 21 moves to its extended position.
- each bonded structure 5 will pass through an outlet zone 23 in which it will see a maximum temperature (in its hottest region) of between 150 ° C and 250 ° C.
- a support device 11 located above the bonded structures 5 will exert a supporting force successively on each bonded structure 5, so that the bevel 10 below it s 'inserts, facing the bonding interface 7, between the chamfered edges of the assembled substrates of the bonded structure 5 (FIG. 7).
- the insertion of the bevel 10 generates a local stress and in tension at the level of the buried fragile plane 2 making it possible to initiate the fracture wave in each bonded structure 5, successively, as they pass under the device. support 11.
- the initiation of the fracture wave is thus carried out for each bonded structure 5 while the latter is subjected to a maximum temperature of between 150 ° C and 250 ° C, preferably around 200 ° C.
- the exit zone 23 in which the initiation of the fracture wave is operated corresponds to a zone in which each bonded structure 5 undergoes, in its hottest region (the upper region H) a maximum temperature of the order of 200 ° C, its central region C seeing an intermediate temperature of the order of 180 ° C and its lower region B seeing a temperature of the order of 130 ° C.
- the bevel 10 being, in the example illustrated in FIG. 7, placed in the lower part of each bonded structure 5, the initiation also takes place in the cold region (lower region B: that which is subjected to the lowest temperatures) of the bonded structure 5.
- the SOI substrate is obtained after transfer (transferred assembly 5a) and the remainder 5b of the donor substrate 1. A very good uniformity of thickness of the useful layers 3 transferred is obtained.
- Finishing steps applied to the transferred assemblies 5a include chemical cleanings and at least one high temperature smoothing heat treatment.
- the SOI substrates comprise a useful layer 3 with a thickness of 50 nm, the non-uniformity of final thickness of which is of the order of 0.45 nm.
- SOI substrates in which the useful layer 3 comprises regular or irregular patterns after fracture may have final thickness non-uniformities greater than or equal to 0.7 nm.
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Abstract
Description
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Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021555271A JP7510434B2 (en) | 2019-03-15 | 2020-02-26 | Process for transferring a useful layer onto a carrier substrate - Patent application |
EP20713947.8A EP3939077A1 (en) | 2019-03-15 | 2020-02-26 | Method for transferring a useful layer onto a support substrate |
US17/439,300 US11881429B2 (en) | 2019-03-15 | 2020-02-26 | Method for transferring a useful layer onto a support substrate |
KR1020217032934A KR20210134783A (en) | 2019-03-15 | 2020-02-26 | The process of transferring the useful layer to the carrier substrate |
SG11202109929X SG11202109929XA (en) | 2019-03-15 | 2020-02-26 | Process for transferring a useful layer to a carrier substrate |
CN202080016818.6A CN113491005A (en) | 2019-03-15 | 2020-02-26 | Method for transferring a useful layer to a carrier substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR1902671 | 2019-03-15 | ||
FR1902671A FR3093860B1 (en) | 2019-03-15 | 2019-03-15 | Method of transferring a useful layer onto a support substrate |
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US (1) | US11881429B2 (en) |
EP (1) | EP3939077A1 (en) |
JP (1) | JP7510434B2 (en) |
KR (1) | KR20210134783A (en) |
CN (1) | CN113491005A (en) |
FR (1) | FR3093860B1 (en) |
SG (1) | SG11202109929XA (en) |
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WO (1) | WO2020188168A1 (en) |
Citations (4)
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WO2005043616A1 (en) | 2003-10-28 | 2005-05-12 | S.O.I. Tec Silicon On Insulator Technologies | Method for the catastrophic transfer of a thin layer after co-implantation |
EP2802001A1 (en) * | 2012-01-06 | 2014-11-12 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded silicon-on-insulator (soi) wafer |
EP2933828A1 (en) | 2014-04-16 | 2015-10-21 | Soitec | Method for transferring a useful layer |
US9914233B2 (en) * | 2012-09-07 | 2018-03-13 | Soitec | Device for separating two substrates |
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US20070277269A1 (en) * | 2006-04-17 | 2007-11-29 | Ceres, Inc. | Nucleotide sequences and polypeptides encoded thereby useful for modifying plant characteristics |
US20060014363A1 (en) * | 2004-03-05 | 2006-01-19 | Nicolas Daval | Thermal treatment of a semiconductor layer |
FR2910179B1 (en) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING THIN LAYERS OF GaN BY IMPLANTATION AND RECYCLING OF A STARTING SUBSTRATE |
JP5703853B2 (en) | 2011-03-04 | 2015-04-22 | 信越半導体株式会社 | Manufacturing method of bonded wafer |
FR2982071B1 (en) | 2011-10-27 | 2014-05-16 | Commissariat Energie Atomique | METHOD FOR SMOOTHING A SURFACE BY THERMAL TREATMENT |
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2019
- 2019-03-15 FR FR1902671A patent/FR3093860B1/en active Active
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- 2020-02-24 TW TW109105910A patent/TWI851665B/en active
- 2020-02-26 WO PCT/FR2020/050368 patent/WO2020188168A1/en active Application Filing
- 2020-02-26 KR KR1020217032934A patent/KR20210134783A/en active Pending
- 2020-02-26 US US17/439,300 patent/US11881429B2/en active Active
- 2020-02-26 CN CN202080016818.6A patent/CN113491005A/en active Pending
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005043616A1 (en) | 2003-10-28 | 2005-05-12 | S.O.I. Tec Silicon On Insulator Technologies | Method for the catastrophic transfer of a thin layer after co-implantation |
WO2005043615A1 (en) | 2003-10-28 | 2005-05-12 | S.O.I.Tec Silicon On Insulator Technologies | Method for self- supported transfer of a fine layer by pulsation after implantation or co-implantation |
EP2802001A1 (en) * | 2012-01-06 | 2014-11-12 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded silicon-on-insulator (soi) wafer |
US9914233B2 (en) * | 2012-09-07 | 2018-03-13 | Soitec | Device for separating two substrates |
EP2933828A1 (en) | 2014-04-16 | 2015-10-21 | Soitec | Method for transferring a useful layer |
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TW202036783A (en) | 2020-10-01 |
EP3939077A1 (en) | 2022-01-19 |
SG11202109929XA (en) | 2021-10-28 |
CN113491005A (en) | 2021-10-08 |
TWI851665B (en) | 2024-08-11 |
US20220157651A1 (en) | 2022-05-19 |
JP7510434B2 (en) | 2024-07-03 |
US11881429B2 (en) | 2024-01-23 |
JP2022525162A (en) | 2022-05-11 |
KR20210134783A (en) | 2021-11-10 |
FR3093860A1 (en) | 2020-09-18 |
FR3093860B1 (en) | 2021-03-05 |
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