WO2020090166A1 - Signal processing device, image sensor, image capture device, and information processing device - Google Patents

Abstract

Provided is a signal processing device for performing a single-slope type of A/D conversion. The signal processing device is provided with: an amplifier that amplifies an analog signal; a determination unit that determines higher-order bits of the analog signal; an adjustment unit that, on the basis of a determination result of the determination unit, adjusts the level of the analog signal to be input to the amplifier; and a single-slope type of A/D conversion unit that A/D converts lower-order bits of the analog signal by use of the level-adjusted output signal. The determination unit that is constituted by an inverter, a capacitor and a switching element determines the higher-order bits of the analog signal that is to be input to the amplifier.

Description

Signal processing device, image sensor, imaging device, and information processing device

The technology disclosed in the present specification relates to a signal processing apparatus that performs single-slope AD conversion, an image sensor used as a column ADC using the signal processing apparatus, an imaging apparatus, and an information processing apparatus.

Known solid-state imaging devices include amplification type solid-state imaging devices represented by MOS image sensors such as CMOS (Complementary Metal Oxide Semiconductor) and charge transfer type solid-state imaging devices represented by CCD (Charge Coupled Device) image sensors. ing. These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and various information terminals such as smartphones and tablets.

Recently, CMOS image sensors are widely used because of their low power supply voltage and power consumption. The CMOS image sensor also has an advantage that various functional circuits can be integrated in the same element. In particular, by mounting the AD converter in the same element and performing digital output, it is possible to reduce the influence of noise mixed during the processing of the pixel signal.

The CMOS image sensor has an AD converter (AD Converter: ADC) that performs AD (Analog to Digital) conversion of an analog electric signal output by a pixel having a photoelectric conversion element such as a PD (Photo Diode) that performs photoelectric conversion. In order to reduce the waiting time after shooting, a column AD conversion method is generally used in which AD converters are mounted in parallel in the row direction and the analog signals photoelectrically converted by pixels are AD-converted for each row and read. In addition, a single-slope AD converter (SSADC) is often used because the circuit configuration of the AD converter is required to be simple.

In the SSADC, a comparator compares a reference signal called a ramp signal whose level changes with a constant slope with an electric signal output from a pixel, and a counter makes the levels of the reference signal and the electric signal coincide with each other. The electric signals output from the pixels are AD-converted by counting the time required to change the level of the reference signal up to. Then, the CDS for obtaining the difference between the AD conversion result of the reset level which is the electric signal immediately after the pixel is reset and the AD conversion result of the signal level which is the electric signal corresponding to the charges accumulated in the PD of the pixel after the reset (Correlated Double Sampling: Correlated double sampling) is performed, and the difference obtained as a result of the CDS is output as a pixel value (for example, see Patent Document 1).

However, it has become difficult for the conventional SSADC to meet all the requirements of high precision (or multi-bit), high speed (or high frame rate), and low power consumption. For example, as the resolution becomes higher as the number of bits increases, the count period increases, so that the AD conversion time becomes longer, the signal reading from the pixel becomes slower, and eventually high-speed imaging cannot be performed.

The resolution of the SSADC is determined by the number of clocks that generate the ramp, but considering that the clock speed has already reached the upper limit, the AD conversion period doubles each time the resolution increases by 1 bit, resulting in higher accuracy. There is a limit to the compatibility of high speed operation with. If an attempt is made to improve the accuracy of the current 12 bits to 14 bits, the AD processing time will be quadrupled, resulting in a strict frame rate and increased power consumption of the ADC. As a solution for speeding up, there is AD cascading (or parallel processing), but further power consumption increases and there is a mounting problem.

JP, 2007-59991, A Japanese Patent Laid-Open No. 2012-19410

The object of the technique disclosed in the present specification is a signal processing device that performs single slope type AD conversion that realizes high accuracy, high speed, and low power consumption, and column AD conversion that enables high accuracy and high speed conversion. An object of the present invention is to provide an image sensor, an image pickup apparatus, and an information processing apparatus including a container.

The technology disclosed in this specification has been made in consideration of the above problems,
An amplifier that amplifies the analog signal,
A determination unit that determines the higher-order bits of the analog signal,
An adjustment unit that adjusts the level of the analog signal input to the amplifier based on the determination result of the determination unit;
A single-slope AD converter that AD-converts the lower bits of the analog signal using the level-adjusted output signal;
It is a signal processing device provided with.

The judging unit is composed of an inverter, a capacitor, and a switch element, and judges the upper bit of the analog signal before being input to the amplifier.

The determining unit determines the upper bit of the analog signal during D-phase settling in AD conversion of the analog signal. Further, the upper bit determined by the determination unit and the lower bit output from the AD conversion unit are connected to output a digital signal obtained by AD converting the analog signal.

According to the technology disclosed in the present specification, a signal processing device that performs single-slope AD conversion that achieves high accuracy, high speed, and low power consumption, and column AD conversion that enables high accuracy and high speed conversion. It is possible to provide an image sensor including a container, an imaging device, and an information processing device.

The effects described in this specification are merely examples, and the effects of the present invention are not limited to these. In addition to the above effects, the present invention may have additional effects.

Further objects, features, and advantages of the technology disclosed in the present specification will be clarified by a more detailed description based on the embodiments described below and the accompanying drawings.

FIG. 1 is a diagram showing a configuration example of the image sensor 100. FIG. 2 is a diagram showing a main configuration example of the pixel array 101. FIG. 3 is a diagram showing an example of a main circuit configuration of the unit pixel 141. FIG. 4 is a diagram schematically showing a configuration example of the AD conversion unit 103. FIG. 5 is a diagram schematically illustrating an internal configuration example of the column AD conversion unit 161 that performs AD conversion by the single slope method. FIG. 6 is a diagram showing a timing chart when AD conversion is performed by the correlated double sampling method. FIG. 7 is a diagram showing each processing phase of AD conversion when the D-phase period is shortened. FIG. 8 is a diagram for explaining the D-phase comparison process in the multi-lamp method. FIG. 9 is a diagram for explaining the D phase comparison processing in the VSL shift method. FIG. 10 is a diagram showing a schematic configuration example of a signal processing circuit 1000 for AD converting the pixel signal VSL by the VSL shift method. FIG. 11 is a diagram showing a specific circuit configuration example of the adjusting unit 1002 and the column amplifier 160. FIG. 12 is a diagram showing an operation example of the adjusting unit 1002. FIG. 13 is a diagram showing an example of the level shift operation of the pixel signal VSL by the adjustment unit 1002. FIG. 14 is a diagram showing a circuit configuration example of the determination unit 1001. FIG. 15 is a diagram showing an operation timing chart of the determination unit 1001 in each processing phase of AD conversion. FIG. 16 is a diagram showing an operation example of the determination unit 1001. FIG. 17 is a diagram showing an operation example of the determination unit 1001. FIG. 18 is a diagram showing the relationship between the 4-bit determination result of the inverter 1401 and the upper 2 bits output from the determination unit 1001. FIG. 19 is a diagram showing a configuration example of the image pickup apparatus 1900. FIG. 20 is a diagram showing a configuration example of the information processing device 2000.

Hereinafter, embodiments of the technology disclosed in the present specification will be described in detail with reference to the drawings.

A. Schematic Configuration of Image Sensor FIG. 1 shows a configuration example of an image sensor 100 to which the technique disclosed in this specification is applied. The image sensor 100 is a device that photoelectrically converts light from a subject and outputs it as image data, and is configured as a CMOS image sensor, a CCD image sensor, or the like. The illustrated image sensor 100 includes a pixel array 101, a reference voltage generation unit 102, an AD conversion unit 103, a horizontal transfer unit 104, a control unit 111, and a vertical scanning unit 112.

The pixel array 101 is a pixel region in which unit pixels each having a photoelectric conversion element such as a PD are arranged in a plane or a curved surface. The analog signal read from each unit pixel is transmitted to the AD conversion unit 103 via any of the vertical signal lines 121-1 to 121-N. Hereinafter, the vertical signal lines 121-1 to 121-N will be collectively referred to as the vertical signal lines 121 unless it is necessary to distinguish them from each other.

The reference voltage generator 102 generates a reference signal (also referred to as a reference voltage) that serves as a reference signal for AD conversion by the AD converter 103. In the present embodiment, a ramp (Ramp) signal composed of a ramp wave (sawtooth wave) is used as a reference signal. The reference voltage generator 102 has, for example, a DA (Digital to Analog) converter (not shown), and the DA converter generates a ramp signal. This ramp signal is supplied to the AD conversion unit 103 via the reference signal line 122.

The AD conversion unit 103 uses the reference signal to AD convert each analog signal read from each unit pixel in the pixel array 101 via the vertical signal lines 121-1 to 121-N. , And outputs the digital data for each column to the horizontal transfer unit 104 via the corresponding signal line of the signal lines 123-1 to 123-N. Hereinafter, the signal lines 123-1 to 123-N are collectively referred to as the signal line 123 unless it is necessary to distinguish them from each other.

The horizontal transfer unit 104 transfers the digital data supplied from the AD conversion unit 103 via the signal line 123 to the outside of the image sensor 100 via the signal line 124.

The control unit 111 controls the operation of the entire image sensor 100 by controlling each unit of the image sensor 100. Specifically, the control unit 111 controls an operation such as generation of a ramp signal by the reference voltage generation unit 102 by supplying a control signal via the control line 131. In addition, the control unit 111 controls the AD conversion operation of the pixel signal (VSL) by the AD conversion unit 103 by supplying the control signal via the control line 132. The control unit 111 also controls the digital data transfer operation by the horizontal transfer unit 104 by supplying a control signal via the control line 133. Further, the control unit 111 controls the vertical scanning of the pixel array 101 by the vertical scanning unit 112 by supplying a control signal via the control line 134.

The vertical scanning unit 112 controls the operation of the transistor of each unit pixel of the pixel array 101 by being controlled by the control unit 111 and supplying a control signal via the control lines 125-1 to 125-M. .. In the following, the control lines 125-1 to 125-M are collectively referred to as the control lines 125 unless it is necessary to distinguish them from each other.

FIG. 2 shows a main configuration example of the pixel array 101. The pixel array 101 includes a plurality of unit pixels arranged in a plane. In the example illustrated in FIG. 2, M × N unit pixels 141 (unit pixels 141-11 to unit pixels 141-MN) are arranged side by side in a matrix of M rows and N columns (array). However, M and N are arbitrary natural numbers). Hereinafter, the unit pixels 141-11 to 141-MN are collectively referred to as the unit pixel 141 unless it is necessary to distinguish them from each other. The arrangement of the unit pixels 141 is arbitrary, and may be arranged other than the matrix, such as a so-called honeycomb structure.

A vertical signal line 121 (vertical signal line 121-1 to vertical signal line 121-N) is formed for each column of the unit pixel 141 (hereinafter, also referred to as a unit pixel column). Then, each vertical signal line 121 is connected to each unit pixel of a column (unit pixel row) corresponding to itself, and a signal read from each unit pixel is sent to the AD conversion unit 103 (not shown in FIG. 2). To transmit. A control line 125 (control line 125-1 to control line 125-M) is formed for each row of unit pixels 141 (hereinafter, also referred to as a unit pixel row). Then, each control line 125 is connected to each unit pixel 141 of the unit pixel row corresponding to itself, and transmits the control signal supplied from the vertical scanning unit 112 to each unit pixel 141.

In other words, the unit pixel 141 is connected to the vertical signal line 121 assigned to the column to which it belongs (unit pixel column) and the control line 125 assigned to the unit pixel row to which it belongs, and the control line 125 thereof. Driven on the basis of a control signal supplied via, the electric signal obtained by itself is supplied to the AD conversion unit 103 via the vertical signal line 121.

B. Pixel Configuration FIG. 3 shows a main circuit configuration example of the unit pixel 141. The unit pixel 141 shown in the figure includes a photodiode (PD) 151, a transfer transistor 152, a reset transistor 153, an amplification transistor 154, and a select transistor 155. Basically, the unit pixels 141-11 to 141-MN have the same configuration.

The photodiode 151 photoelectrically converts the received light into a photocharge having a charge amount corresponding to the light amount, and accumulates the photocharge. The accumulated photocharge is read at a predetermined timing. The anode electrode of the photodiode 151 is connected to the ground of the pixel region (pixel ground), and the cathode electrode is connected to the floating diffusion (FD) via the transfer transistor 152. Of course, the cathode electrode of the photodiode 151 may be connected to a power source (pixel power source) in the pixel region, the anode electrode may be connected to the FD via the transfer transistor 152, and photocharges may be read out as photoholes.

The transfer transistor 152 controls the reading of photocharges from the photodiode 151. The transfer transistor 152 has a drain electrode connected to the FD and a source electrode connected to the cathode electrode of the photodiode 151. A transfer control line (TRG) that transfers a transfer control signal supplied from the vertical scanning unit 112 is connected to the gate electrode of the transfer transistor 152. This TRG is included in the control line 125 in FIG.

When the TRG signal (that is, the gate potential of the transfer transistor 152) is in the off state, the photoelectric charge is not transferred from the photodiode 151 (the photoelectric charge is accumulated in the photodiode 151). On the other hand, when the signal of TRG is on, the photocharges accumulated in the photodiode 151 are transferred to the FD.

The reset transistor 153 resets the FD potential. The reset transistor 153 has a drain electrode connected to the power supply potential and a source electrode connected to the FD. A reset control line (RST) that transmits a reset control signal supplied from the vertical scanning unit 112 is connected to the gate electrode of the reset transistor 153. This RST is included in the control line 125 in FIG.

FD is disconnected from the power supply potential when the signal of RST (that is, the gate potential of the reset transistor 153) is in the off state. On the other hand, when the RST signal is in the ON state, the electric charge of the FD is discarded in the power supply potential and the FD is reset.

The amplification transistor 154 amplifies the potential change of the FD and outputs it as an electric signal (analog signal). The amplification transistor 154 has a gate electrode connected to the FD, a drain electrode connected to the source follower power supply voltage, and a source electrode connected to the drain electrode of the select transistor 155.

For example, the amplification transistor 154 outputs the potential of the FD reset by the reset transistor 153 to the select transistor 155 as a reset signal (reset level). Further, the amplification transistor 154 outputs the potential of the FD to which the photocharge is transferred by the transfer transistor 152 to the select transistor 155 as a pixel signal (light accumulation signal level).

The select transistor 155 controls the output of the electric signal supplied from the amplification transistor 154 to the vertical signal line (VSL) 121 (that is, the AD conversion unit 103). The select transistor 155 has a drain electrode connected to the source electrode of the amplification transistor 154 and a source electrode connected to the vertical signal line 121. A select control line (SEL) that transmits a select control signal supplied from the vertical scanning unit 112 is connected to the gate electrode of the select transistor 155. This SEL is included in the control line 125 in FIG.

When the SEL signal (that is, the gate potential of the select transistor 155) is in the off state, the amplification transistor 154 and the vertical signal line 121 are electrically disconnected. Therefore, in this state, the reset signal or the pixel signal is not output from the unit pixel 141. On the other hand, when the SEL is in the on state, the unit pixel 141 is in the selected state. That is, the amplification transistor 154 and the vertical signal line 121 are electrically connected, and the signal output from the amplification transistor 154 is supplied to the vertical signal line 121 as the pixel signal VSL of the unit pixel 141. That is, the reset signal and the pixel signal VSL are read from the unit pixel 141.

C. Configuration of Single-Slope Type AD Converter FIG. 4 schematically shows a configuration example of the AD converter 103. The illustrated AD conversion unit 103 has N column AD conversion units 161-1 to 161-N corresponding to the number of columns of the unit pixel 141 of the pixel array 101. In the following, the column AD conversion units 161-1 to 161-N are collectively referred to as the column AD conversion unit 161, unless it is necessary to distinguish them from each other. The column AD converter 161 is provided for each column (unit pixel row) of the pixel array 101.

Each column AD conversion unit 161 (column AD conversion unit 161-1 to column AD conversion unit 161-N) has a vertical signal line 121 (vertical signal line 121-1 to vertical signal line 121-N) of a column corresponding to itself. ) And the reference signal line 122 are connected. Further, column amplifiers 160-1 to 160-N for amplifying pixel signals are inserted on the vertical signal lines 121-1 to 121-N of each column. Hereinafter, the column amplifiers 160-1 to 160-N are collectively referred to as the column amplifier 160 unless it is necessary to distinguish them from each other. In the column amplifier 160, before the pixel signal VSL transferred through the vertical signal line 121 is input to the column AD conversion unit 161, VSL is low-noise amplified and inverted output is performed.

The column AD conversion unit 161 performs AD conversion by the single slope method. That is, each column AD converter 161 reads out the signal read from the unit pixel 141 of the column corresponding to itself and supplied through the vertical signal line 121 of the column (after being amplified by the column amplifier 160). AD conversion is performed using the reference signal supplied from the reference voltage generation unit 102 via the reference signal line 122.

The signal line 123 (signal line 123-1 to signal line 123-N) of the column corresponding to the column AD conversion unit 161 is connected to each column AD conversion unit 161. Each column AD conversion unit 161 supplies the AD conversion result obtained by itself to the horizontal transfer unit 104 (not shown in FIG. 4) via the signal line 123 corresponding to itself.

A control line 132 (control lines 132-1 to 132-N) is connected to each column AD converter 161. Each column AD converter 161 is driven based on a control signal (that is, control of the controller 111) supplied from the controller 111 (not shown in FIG. 4) via the control line 132 corresponding to itself.

FIG. 5 schematically shows an internal configuration example of the column AD conversion unit 161 that performs AD conversion by the single slope method. The illustrated column AD converter 161 includes a comparator 171, a counter 172, a capacitor 173, and a capacitor 174.

One input terminal of the 2-input 1-output comparator 171 is connected to the vertical signal line 121 of the column corresponding to itself via the capacitor 174, and is read from each unit pixel of the column corresponding to itself. The pixel signal VSL is subjected to low noise amplification by the corresponding column amplifier 160, and then input via the capacitor 174. Further, the other input terminal of the comparator 171 is connected to the reference signal line 122 via the capacitor 173, and the ramp signal generated as the reference signal by the reference voltage generation unit 102 is input. The output terminal VCO of the comparator 171 is connected to the counter 172.

The capacitors 173 and 174 are capacitors having a fixed capacity (having a predetermined capacity). Note that the comparator 171, the capacitors 173, and 174 may be integrated into a comparator 181 (in other words, the capacitors 173 and 174 may be included in the configuration of the comparator 181).

The comparator 171 receives the VSL signal (however, after low noise amplification by the column amplifier 160) input to one input terminal via the vertical signal line 121 and the capacitor 174, and the reference signal line 122 and the capacitor 173. The signal levels of the ramp signal input to the other input terminal are compared, and the comparison result is output to the counter 172. That is, the comparator 171 outputs a signal indicating which of the VSL signal and the ramp signal has the higher signal level from the output terminal VCO and supplies the signal to the counter 172.

The signal output by the comparator 171 is, for example, 1-bit digital data. When the signal level of the ramp signal is higher than the signal level of the VSL signal, the value output by the comparator 171 becomes "0". Conversely, when the signal level of the VSL signal is higher than the signal level of the ramp signal, the comparator 171 The value output by is "1". Of course, the method of taking the value of this signal may be reversed. The bit length of the signal indicating the comparison result is arbitrary and may be information composed of a plurality of bits.

The counter 172 has an input terminal connected to the output terminal VCO of the comparator 171, and an output terminal connected to the signal line 123 of the column corresponding to itself. The comparison result is supplied from the comparator 171 to the counter 172. The counter 172 counts the number of clocks of the clock signal from the start of counting until the comparison result of the comparator 171 is inverted (that is, the signal level of the output terminal VCO changes), and thus the time until the comparison result is inverted To measure. Then, the counter 172 converts the count value up to that point when the comparison result is inverted into the AD conversion result of the VSL signal input to one input terminal of the comparator 171 (that is, the signal read from the unit pixel 141). Of the digital data) is output to the horizontal transfer unit 104 via the signal line 123.

D. Operation of Single-Slope Type AD Converter FIG. 6 shows a timing chart when the AD conversion by the correlated double sampling method is performed in the column AD converter 161. In the illustrated AD conversion period, the auto zero (AZ) period (time t0 to time t1) of the correlated double sampling (comparator 171) and the reset signal and the ramp signal read from the pixel are compared P ( It includes a precharge phase period (time t1 to time t2) and a D (data) phase period (time t2 to time t3) in which the VSL signal read from the pixel and the ramp signal are compared.

The analog image signal VSL read by the vertical signal line 121 is compared with a ramp signal which is a reference signal in signal level (voltage) by a comparator 171 in the column AD converter 103 arranged for each column. .. At this time, the counter 172 in the same column AD converter 161 operates. By changing the ramp signal and the count value of the counter 172 in a one-to-one correspondence, the analog pixel signal VSL of the vertical signal line 121 is converted into a digital pixel signal. The change in the reference voltage V _slop is to convert the change in voltage into a change in time, and by counting the time with a predetermined clock, the analog value is converted into a digital value. Then, when the potential VSL of the vertical signal line 121, which is an analog signal, and the reference voltage V _{slop of the} ramp signal intersect, the output of the comparator 171 (or the comparator 181) is inverted. As a result, the input clock of the counter 172 is stopped and AD conversion is completed.

When the potential of the pixel signal VSL input from the vertical signal line 121 and the reference voltage V _{slop of the} ramp signal become equal in the P-phase period, the output of the comparator 171 is inverted from high level to low level. Then, in response to the polarity reversal of the comparator 171, the counter 171 stops the counting operation and temporarily holds the count value τ _P corresponding to the P-phase output (ΔV).

Next, in the D-phase period, when the potential of the pixel signal VSL input from the vertical signal line 121 that is an analog signal becomes equal to the reference voltage V _{Ramp of the} ramp signal, the output of the comparator 171 changes from high level to low level. Invert. Then, in response to the polarity reversal of the comparator 171, the counter 172 stops the counting operation and temporarily holds the count value τ _D corresponding to the D-phase output.

Next, correlated double sampling, that is, subtracting the count value τ _P of the P phase period from the count value τ _D of the D phase period, it is possible to obtain the output voltage V _out which is the difference between the D phase output and the P phase output. it can.

E. When the speed-up image sensor of the single slope type AD conversion unit has multiple bits, the D phase period, that is, the count value τ _D increases. For example, when increasing the accuracy of the current 12 bits to 14 bits, if a full scale measurement is performed over the entire range of AD conversion, the D phase period will be quadrupled, and the frame rate will be severe, and the ADC Increases power consumption.

Therefore, in this specification, a technique for realizing the speedup of the single slope type AD conversion unit by shortening the D phase period is proposed below. In addition, the power consumption is reduced in proportion to the reduction in AD processing time.

The multi-ramp method and the VSL shift method can be mentioned as the method for realizing the speedup of the single slope type AD conversion unit. In either method, the upper bit of the pixel signal VSL is determined in the upper determination period provided during the D-phase settling, and then the level comparison between the VSL and the ramp signal is performed in detail only in the lower level of VSL. Therefore, the D-phase period is shortened (see FIG. 7).

The former multi-ramp method is, for example, a method of determining the upper bits of VSL in the D phase in N stages and generating N ramp signals having different levels corresponding to the upper bits (see, for example, Patent Document 2). See). Specifically, one corresponding ramp signal is selected from N based on the determination result of the upper bit, the comparison with VSL is performed, and the lower bit is measured.

FIG. 8 shows how the D-phase full scale (FS) is divided into four to generate ramp signals for each of the four voltage regions. In the upper determination period, it is determined which of the four voltage ranges the VSL level of the D phase corresponds to. Then, in the subsequent D-phase period, the ramp signal corresponding to the determination result of the upper bit is selected and compared with the pixel signal VSL. The D-phase period can be shortened to 1/4 as compared with the case where the comparison with VSL is performed on a full scale.

For example, when the pixel signal VSL expanded from 12 bits to 14 bits is AD-converted by the multi-ramp method shown in FIG. 8, the same ramp-shaped waveform signal for 12 bits is used as the multi-ramp and the upper bit ( 00, 01, 10, 11), four types of ramp signals having different levels can be generated. First, the upper 2 bits are determined in the upper determination period. Then, based on whether the determination result of the upper bit is 00, 01, 10, or 11, the ramp signal of the corresponding level is selected and compared with the D-phase pixel signal VSL to determine the correlation of the lower 12 bits. Perform double sampling. Then, 2 bits acquired in the upper determination period can be concatenated with the obtained upper 12 bits of the lower 12 bits to be converted into 14-bit digital data. The D-phase period can be shortened to 1/4 as compared with the case where the comparison with VSL is performed on a full scale.

In short, the multi-lamp is a system that selects the ramp signal according to the pixel level read out, and can be realized with a simple circuit configuration. However, in the multi-ramp method, since the number of column AD conversion units 161 that select each ramp signal changes due to a change in the image, the load capacitance applied to each ramp generation circuit changes, resulting in a delay, and as a result, There is a problem that the A / D conversion value shifts. Further, in order to correct the delay error, calibration for every 1H is necessary, and the circuit scale increases.

On the other hand, the latter VSL shift method is a method of shifting the VSL level in the D-phase period. Specifically, the level of VSL in the D phase is determined in N steps, and the level of VSL in the D phase is shifted based on the determination result so that the input signal to the comparator 171 corresponds to N minutes of the D phase period. The D-phase period is shortened to 1 / N so that the voltage falls within the voltage range of 1. In the VSL shift method, since the number of lamps used is one, the delay problem as in the case of the multi-lamp method does not occur.

FIG. 9 shows a state in which the D-phase comparison is performed by the VSL shift method with a single ramp signal having a length of ¼ of the full-scale (FS) of the D-phase. In the high-order determination period, it is determined which voltage region the D-phase VSL level corresponds to, and in the subsequent D-phase period, the VSL level is shifted according to the determination result of the high-order bit, and the comparison is performed. The D-phase period can be shortened to a quarter by making the input signal to the device 171 fall within the voltage range of a quarter of the D-phase period.

For example, when the pixel signal VSL expanded from 12 bits to 14 bits is AD-converted by the VSL shift method shown in FIG. 9, one kind of ramp signal for 12 bits (or P phase comparison) is used as the ramp signal. Use only. First, in the upper determination period, the upper 2 bits of the pixel signal VSL are determined. Then, based on which of the determination results of the upper bits is 00, 01, 10, 11, the pixel signal VSL of the D phase is shifted to the level of the P phase or the upper 2 bits “00”, and Perform correlated double sampling of the lower 12 bits compared to the ramp signal. Then, 2 bits acquired in the upper determination period can be concatenated with the obtained upper 12 bits of the lower 12 bits to be converted into 14-bit digital data. The D-phase period can be shortened to 1/4 as compared with the case where the comparison with VSL is performed on a full scale.

In this specification, in view of the problems such as load fluctuations and circuit scale that the multi-ramp system has, we propose a technology that realizes the speedup of the single slope AD converter by the VSL shift system.

FIG. 10 shows a schematic configuration example of a signal processing circuit 1000 for AD converting the pixel signal VSL by the VSL shift method. The signal processing circuit 1000 shown in the drawing is, with respect to the column AD conversion unit 161 shown in FIGS. 4 to 5, a determination unit 1001 that determines the upper bit of the pixel signal VSL, and a pixel signal VSL based on the determination result of the upper bit. The adjustment unit 1002 for adjusting the shift amount is added.

The determination unit 1001 inputs the pixel signal VSL (before being input to the amplifier 202) transferred from the unit pixel 141 via the vertical signal line 121 during the D-phase settling, and determines the upper 2 bits thereof. To do. The determination result of the determination unit 1001 is written as the upper 2 bits of the counter 172 (described above) and is output to the adjustment unit 1002.

The determination unit 1001 can be realized by a simple circuit using an inverter, a capacitor, and a switch element, for example, but the detailed configuration will be described later.

The adjusting unit 1002 shifts the level of the pixel signal VSL by adding a DC offset voltage based on the determination result of the determining unit 1001 to the pixel signal VSL input to the column amplifier 160.

The column amplifier 160 low-noise amplifies and inverts the level-shifted pixel signal VSL based on the upper bits, and outputs the pixel signal VSL to the column AD converter 161 in the subsequent stage.

The reference voltage generation unit 102 generates a ramp signal in the ramp voltage range of 1 / N for the lower bit (excluding the upper bit) of the pixel signal VSL (where N is a positive integer). And) to the column AD converter 161.

In the column AD converter 161, the comparator 181 compares the level-shifted pixel signal VSL input from the column amplifier 160 with the signal level of the ramp signal in the ramp voltage range that is 1 / N, and A signal indicating which signal level is higher is output from the output terminal VCO and supplied to the counter 172.

The counter 172 counts the number of clocks of the clock signal from the start of counting until the comparison result of the comparator 171 is inverted (that is, the signal level of the output terminal VCO changes), and when the comparison result is inverted, the count is reached. The count value of is the AD conversion result of the lower bits of the pixel signal VSL. Then, the upper bits of the AD conversion result of the lower bits are connected to the upper bits determined by the determination unit 1001 and output to the horizontal transfer unit 104 (not shown in FIG. 10) via the signal line 123.

A specific operation of the signal processing circuit 1000 shown in FIG. 10 will be described by taking as an example the case where the pixel signal VSL expanded from 12 bits to 14 bits is AD-converted.

The determination unit 1001 determines the upper 2 bits of the pixel signal VSL during the upper determination period during the D-phase settling. Then, the adjustment unit 1002 shifts the DC signal for shifting the D-phase pixel signal VSL to the level of the upper bit “00” based on which of the determination results of the upper two bits is 00, 01, 10, or 11. The offset voltage is added to the pixel signal VSL input to the column amplifier 160. Further, the reference voltage generation unit 102 generates a ramp signal in a ramp voltage range that is a quarter, for example, for 14 bits, and supplies the ramp signal to the comparator 181 in the column AD conversion unit 161.

The comparator 181 compares the level-shifted pixel signal VSL with the signal level of the ramp signal in the pump voltage range that is ¼, and outputs a signal indicating which signal level is larger from the output terminal VCO. And supplies it to the counter 172. The counter 172 counts the number of clocks of the clock signal from the start of counting until the comparison result of the comparator 171 is inverted, and sets the count value as the AD conversion result of the lower 12 bits of the pixel signal VSL. Then, the upper 2 bits determined by the determination unit 1001 can be connected to the upper 12 bits of the AD conversion result, and the 14-bit AD conversion result of the pixel signal VSL can be obtained.

According to the signal processing circuit 1000 shown in FIG. 10, the upper bit is determined based on the voltage value of the pixel signal VSL at the time of D-phase settling, and the level shift amount of VSL is set, so that the lamp voltage range is reduced to 1 / N. The AD processing time can be shortened by pulling in the pixel signal VSL.

Note that it is also possible to mount one or both functions of the determination unit 1001 and the adjustment unit 1002 in the column amplifier 160.

FIG. 11 shows a specific circuit configuration example of the adjusting unit 1002 and the column amplifier 160 in the signal processing circuit 1000 shown in FIG.

The column amplifier 160 is originally a low noise amplifier that amplifies VSL before inputting the pixel signal VSL transferred by the vertical signal line 121 to the column AD converter 161. The illustrated column amplifier 160 is a switched capacitor amplifier, and the column amplifier 160 includes a capacitor 1101 as C _IN , an amplifier 1102, a capacitor 1103 as C _FB , and a switch 1104, and two capacitors C _IN and The gain for amplifying the input pixel signal VSL is determined by C _FB .

The pixel signal VSL transferred via the vertical signal line 121 is input to and accumulated in the first terminal of the capacitor 1101. As a result, a voltage signal having a voltage corresponding to the accumulated charge signal is output from the second terminal of the capacitor 1101 and input to the inverting input terminal of the amplifier 1102. The non-inverting input terminal of the amplifier 1102 is grounded. Then, the amplifier 1102 amplifies the voltage of the input voltage signal, and inverts and outputs the amplified voltage signal as the output of the column amplifier 160 to the column AD conversion unit 161 in the subsequent stage.

The voltage signal inverted and output by the amplifier 1102 is input to the first terminal of the capacitor 1103 and accumulated. As a result, the voltage signal corresponding to the accumulated voltage signal is output from the second terminal of the capacitor 1103 to the amplifier 1102 as a feedback signal. Then, the amplifier 1102 continues to output a voltage signal of a constant voltage according to the voltage of the feedback signal. That is, the amplifier 1102 continues to output the voltage signal of the voltage corresponding to the charge signal input to the column amplifier 160 to the column AD conversion unit 161 in the subsequent stage.

The voltage signal output from the amplifier 1102 represents the magnitude of the pixel signal VSL generated by the corresponding unit pixel 141 of the pixel array 101, which is increased or decreased according to the ratio between the capacitance C _{IN of the} capacitor 1101 and the capacitance C _FB of the capacitor 1103. This is a voltage inversion signal. For example, the capacitance C _{IN of the} capacitor 1101 is 200 fF, and the capacitance C _{FB of the} capacitor 1103 is variable among 200 fF, 100 fF, 50 fF, and 25 fF.

The output terminal of the amplifier 1102 (which is also the first terminal of the capacitor 1103) is connected to the first terminal of the switch 1104, and the input terminal of the amplifier 1102 (which is also the second terminal of the capacitor 1103) is connected to the switch. It is connected to the second terminal of 1104. Then, the switch 1104 short-circuits or opens the first terminal and the second terminal of the capacitor 1103. When both terminals of the capacitor 1103 are short-circuited, the voltages of both terminals of the capacitor 1103 become the same voltage and are reset, and the amplification operation of the voltage signal by the amplifier 1102 is also reset.

As described above, the signal processing circuit 1000 determines the upper bit of the VSL directly from the pixel signal VSL input via the vertical signal line 121, and the VSL of the VSL based on the determination result of the determination unit 1001. An adjustment unit 1002 for adjusting (shifting) the level is further provided. Although the determination unit 1001 and the adjustment unit 1002 are arranged outside the column amplifier 160 in FIG. 11, one or both of the functions of the determination unit 1001 and the adjustment unit 1002 can be installed in the column amplifier 160. is there.

FIG. 11 shows a circuit configuration example of the adjusting unit 1002 in the case of shifting the VSL level by dividing the full scale of the D-phase VSL into four. When the D-phase VSL full scale is divided by a power of 2 other than 4, the adjusting unit 1002 can be configured as in FIG. 11. It is also possible for those skilled in the art to configure the adjusting unit 1002 so as to divide the full scale of the D-phase VSL by a value other than a power of two.

The determination unit 1001 determines the upper 2 bits of the pixel signal VSL (before being input to the amplifier 202) transferred via the vertical signal line 121. The determination result of the determination unit 1001 is written as the upper 2 bits of the counter 172 (described above) and is output to the adjustment unit 1001. The determination unit 1001 can be realized by a simple circuit using, for example, an inverter, a capacitor, and a switch element, but the detailed configuration thereof will be described later.

The adjustment unit 1002 inputs the DC offset voltage ΔV _SH based on the determination result of the upper 2 bits of the pixel signal VSL by the determination unit 1001 to the inverting input terminal of the amplifier 1102 (or the column amplifier 160) to output the upper 2 bits. The level of the pixel signal VSL is shifted by a shift amount according to the determination result.

In the example illustrated in FIG. 11, the adjustment unit 1002 is configured by a DA conversion circuit that generates a DC offset voltage. Specifically, the adjustment unit 1002 has switches 1111 to 1113 (SW1, SW2, SW3), one end of which is commonly connected to the inverting input terminal of the amplifier 1102 and the other end of which is switched between the ground and the reference voltage signal V _FSR. ) Are respectively connected to each other and have three capacitors 1114 to 1116 having the same capacitance C _SH .

The reference voltage signal V _FSR is, for example, a 14-bit voltage signal corresponding to the full scale of the pixel signal VSL, and is supplied from the DA converter 1110. The capacitance of each of the capacitors 1114 to 1116 is assumed to be a quarter of the capacitance of the capacitor 201 forming the column amplifier 160 (that is, C _SH = ¼ · C _IN = 50 fF). However, the capacities of the capacitors 1114 to 1116 do not have to be uniform, and the adjustment unit 1002 can be configured in a binary type by weighting each capacitor such as C, 2C, and 4C.

The switches SW1, SW2, and SW3 denoted by reference numerals 1111 to 1113 are turned on / off based on the determination result of the upper 2 bits of the pixel signal VSL by the determination unit 1001, and the pixel signal VSL corresponding to the number of switches in the on state is changed. The level shift amount ΔV _SH can be applied to the inverting input terminal of the amplifier 1102 (or the column amplifier 160). For example, the shift amount ΔV _SH is 1/4 · V _FSR when only the switch SW1 is in the on state, and the shift amount ΔV _SH is 1/2 · V _{FSR when} the two switches SW1 and SW2 are in the on state. If all the switches SW1 to SW3 are in the ON state, the shift amount ΔV _SH is 3/4 · V _FSR . FIG. 12 illustrates the relationship between the determination result of the upper 2 bits of the pixel signal VSL, the on / off states of the switches SW1 to SW3, and the level shift amount ΔV _SH of the pixel signal VSL.

FIG. 13 shows an example in which the level of the pixel signal VSL is shifted by the adjustment unit 1002 when the upper bit determined by the determination unit 1001 is “11”. However, the pixel signal VSL is in a state before being input to the column amplifier 160, that is, before being inverted and output by the column amplifier 160. As shown in FIG. 13, the level of the pixel signal VSL is shifted from “11” to “00”. Further, although not shown, whether the upper level of the pixel signal VSL is “10” or “01” is similarly shifted to the level “00” by the adjusting unit 1002.

Therefore, the column AD conversion unit 161 in the subsequent stage compares the lower 12 bits of the pixel signal VSL expanded to 14 bits with one kind of ramp signal for 12 bits (or for P phase comparison), and determines the comparison result. Correlated double sampling can be performed to obtain digital data. That is, the D-phase period or the AD processing time can be shortened to 1/4 by pulling the pixel signal VSL into the lamp voltage range of 1/4.

FIG. 14 shows a circuit configuration example of the determination unit 1001. Further, FIG. 15 shows an operation timing chart of the determination unit 1001 in each processing phase of AD conversion. The determination unit 1001 performs a high-order determination using the pixel signal VSL before input to the column amplifier 160, and is composed of simple elements such as an inverter, a capacitor, and a switch element, as will be described later. The main feature is that it is short.

The determination unit 1001 shown in FIG. 14 includes an inverter 1401, a first capacitor 1402 and a second capacitor 1403, a switch 1404, and a latch 1405. However, the capacitance C1 of the first capacitor 1402 and the capacitance C2 of the second capacitor 1403 are equal, and C1 = C2 = C.

The pixel signal VSL transferred via the vertical signal line 121 is input to and accumulated in the first terminal of the first capacitor 1402. As a result, a voltage signal having a voltage corresponding to the accumulated charge signal is output from the second terminal of the first capacitor 1402.

The DA converter 1406 generates a full-scale DC voltage of V-phase VSL as a reference voltage V _FSR . This reference voltage V _FSR is divided by a voltage dividing circuit composed of four resistance elements connected in series with the same resistance value, and four types of reference voltages 0/4 · V _FSR and 1/4 with different voltage levels are obtained. _{· V FSR, 2/4 ·} V FSR, 3/4 · V FSR can be generated. Then, by turning on the switches SW1, SW2, SW3, and SW4 in this order, the first terminal of the second capacitor 1403 has reference voltages 0/4 · V _FSR , 1/4 · V _FSR , and 2 / 4 · V _FSR and 3/4 · V _FSR are sequentially input. As a result, a voltage signal having a voltage corresponding to the accumulated charge signal is output from the second terminal of the second capacitor 1403.

The second terminals of the first capacitor 1402 and the second capacitor 1403 are commonly connected to the inverter 1401. The voltage of the input terminal of the inverter 1401 is Va. The output of the inverter 1401 is input to the latch 1405.

In order to perform the determination process using the inverter 1401 with high accuracy (or stably), it is necessary to temporarily remove the offset between the input and the output of the inverter 1401. Therefore, the calibration (T _cal ) is performed using the auto-zero period and the P-phase period in which the level of the pixel signal VSL is constant. Specifically, the switch 1404 is turned on, the output of the inverter 1401 is short-circuited to the input of the inverter 1401, and the input / output offset is removed. This corrects the absolute deviation between the level V _SP of the pixel signal VSL at the end of the P-phase period or the start of the D-phase period and the reference voltage V _rP output from the second terminal of the second capacitor 1403. At the time of calibration, the switch SW1 is turned on, and the reference voltage 0/4 · V _FSR is input to the first terminal of the second capacitor 1403. Then, as a result of the calibration, the voltage Va at the input terminal of the inverter 1401 becomes equal to the logical voltage threshold value (logical V _th (threshold value determined in the inverter 1401): VB) of the inverter 1401 (that is, Va = VB). .. In the subsequent upper determination period (T _CM ), the output of the inverter 1401 is inverted every time the input terminal voltage Va of the inverter 1401 becomes higher or lower than VB.

Then, when the P-phase period ends and the D-phase period starts, the switch 1404 is turned off and the determination process of the upper bit of the pixel signal VSL is started. During the D-phase period, the level of the pixel signal VSL changes. During the upper bit determination period (T _CM ) during D-phase settling, the switches SW1, SW2, SW3, and SW4 are turned on in this order, so that the first terminal of the second capacitor 1403 receives the reference voltage as a reference voltage. _{0/4 · V FSR, 1/4} · V FSR, 2/4 · V FSR, 3/4 · V FSR is inputted in order. As a result, the voltage signal output from the second terminal of the second capacitor 1403 changes. Further, the pixel signal VSL also drops in the D-phase period, and the voltage signal output from the second terminal of the first capacitor 1402 also changes.

Here, the amount of change in the voltage level of the pixel signal VSL from the end of the P-phase period is ΔV _S. Further, the unit of the amount of change from the reference voltage V _rP in the voltage level output from the second terminal of the second capacitor 1403 is ΔV _ref . The input terminal voltage Va of the inverter 1401 changes in accordance with the changes ΔV _S and ΔV _ref of the voltage levels input to the first terminals of the first capacitor 1402 and the second capacitor 1403, respectively. Va in the determination period (T _CM ) of the upper bits can be expressed by the following equation (1). However, n in the formula (1) is an integer of 0 to 3. Further, it is assumed that the capacitance C1 of the first capacitor 1402 and the capacitance C2 of the second capacitor 1403 are equal (that is, C1 = C2 = C).

By the above calibration, the difference value between the voltage level change amount ΔV _S of the pixel signal VSL and the reference voltage change amount ΔV _ref is determined based on the logical threshold value (logical V _th ): VB of the inverter 1401. It is composed. This makes it possible to absorb the deviation of the logical threshold value of each element of the inverter 1401 and accurately determine the upper bit of the D-phase pixel signal VSL.

During the determination period (T _CM ) of the upper bits, the switches SW1, SW2, and SW3 are sequentially turned on / off. On / off of each of the switches SW1, SW2, and SW3 is controlled by a 4-bit switch control signal. When the switch control signal is "0000", the switch SW1 is on, "0001" is the switch SW2 on, "0011" is the switch SW3 on, and "0111" is the switch SW3 on. The 4-bit switch control signal is also input to the latch 1405.

In addition, when the switches SW1, SW2, SW3, and SW4 are sequentially switched on and off in the determination period (T _CM ) of the upper bit, the change amount ΔV _S of the voltage level of the pixel signal VSL and the change from the reference voltage V _rP. The output of the inverter 1401 changes according to the amount ΔV _ref × n.

The latch 1405 temporarily holds the 4-bit switch control signal input when the output of the inverter 1401 is inverted as a determination result. 16 and 17 show examples of determination results of the inverter 1401 as operation examples of the determination unit 1001.

In the example shown in FIG. 16, the change amount ΔV _S of the voltage level of the pixel signal VSL is small, and the output of the inverter 1401 is output regardless of the voltage level ΔV _ref × n output from the second terminal of the second capacitor 1403. Is not inverted, the determination result by the determination unit 1001 is “0000”.

Further, in the example shown in FIG. 17, the amount of change ΔV _S of the voltage level of the pixel signal VSL is rather large, and the output of the inverter 1401 is at the voltage level ΔV _ref × 3 output from the second terminal of the second capacitor 1403. Since it is inverted, the determination result by the determination unit 1001 is “0011”.

Although illustration is omitted, when the output of the inverter 1401 is inverted at the voltage level ΔV _ref × 2 output from the second terminal of the second capacitor 1403, the determination result by the determination unit 1001 is “0010”. When the output of the inverter 1401 is inverted at the voltage level ΔV _ref × 4 output from the second terminal of the second capacitor 1403, the determination result by the determination unit 1001 is “0111”.

The 4-bit determination result by the inverter 1401 corresponds to the on / off control of the switches SW1, SW2, and SW3. Then, the determination result of the upper 2 bits of the pixel signal VSL by the determination unit 1001 is acquired by using 3 bits of the determination result of 4 bits by the inverter 1401. FIG. 18 shows the relationship between the 4-bit determination result of the inverter 1401 and the high-order 2 bits output from the determination unit 1001. The determination result of the determination unit 1001 is written as the upper 2 bits of the counter 172 (described above) and is output to the adjustment unit 1002.

Summarizing the signal processing circuit 1000 shown in FIG. 10, the level of the VSL of the D phase is determined in N steps, the level of the VSL of the D phase is shifted based on the determination result, and the input to the comparator 171 is performed. By setting the signal to fall within the voltage range of 1 / N of the D phase period, the D phase period in the AD conversion process can be shortened to 1 / N. When the D-phase period is shortened to 1/4, the 14-bit AD conversion processing time can be shortened by 60%. There is also a power consumption reduction effect in proportion to the reduction of the AD processing time.

The signal processing circuit 1000 is configured to determine the upper bit of the pixel signal VSL during the D-phase settling and adjust the shift amount of the pixel signal VSL input to the column amplifier 160 based on the determination result of the upper bit. .. The circuits of the determination unit 1001 that determines the higher-order bits of the pixel signal VSL and the adjustment unit 1002 that adjusts the shift amount of the pixel signal VSL can be implemented in the circuit of the column amplifier 160 for the purpose of low noise amplification.

The determination unit 1001 is configured to perform high-order determination using the pixel signal VSL before input to the column amplifier 160 (see FIGS. 10 and 11), and includes simple elements such as an inverter, a capacitor, and a switch element. Therefore (see FIG. 14), the main feature is that the determination time is short.

When the VSL shift method is implemented using the signal processing circuit 1000, the relationship between the AD conversion unit 161 and the ramp signal is the same as the conventional AD conversion processing (without VSL shift). Therefore, there are no problems such as load capacity fluctuations and circuit scales that occur in the multi-lamp method, and calibration for every 1H is also unnecessary.

According to the signal processing circuit 1000, the implied characteristic at the time of a small signal (when the light is shielded or at the black level) that most affects the image quality is similar to the conventional AD conversion processing (without VSL shift), and is a good characteristic. It is possible to shorten the AD conversion processing time while maintaining the above.

E. Configuration Example of Imaging Device FIG. 19 shows a configuration example of an imaging device 1900 configured by applying the technology disclosed in this specification. The imaging device 1900 corresponds to, for example, a digital still camera or a digital video camera. The illustrated image pickup apparatus 1900 includes an optical system 1901, an image sensor 1902, a signal processing unit 1903, a recording / reproducing unit 1904, a recording unit 1905, and a control unit 1906.

The optical system 1901 includes a mechanical shutter, a lens, a diaphragm mechanism, and the like. When the shutter is opened, the lens collects the reflected light from the subject and makes it enter the pixel area of the image sensor 1902 through the diaphragm mechanism.

The image sensor 1902 has the configuration shown in FIG. 1, but in the AD conversion unit 103, it is configured by a column amplifier 160 and a column AD conversion unit 161 to which the signal processing circuit 1000 shown in FIG. 10 is applied. And The image sensor 1902 generates an image signal corresponding to the light from the optical system 1901, performs digital conversion, and outputs the image signal to the signal processing unit 1903.

The signal processing unit 1903 performs digital processing such as digital gain processing and gamma processing on the digital image signal output from the image sensor 1902 to generate a signal suitable for recording in the recording unit 1905.

The recording / reproducing unit 1904 records the signal supplied from the signal processing unit 1904 in the recording unit 1905. Further, the recording / reproducing unit 1904 reproduces the signal recorded in the recording unit 1905 and displays it on a display device (not shown) that is equipped with the imaging device 1900 or is externally connected. The recording unit 1905 is composed of a recording medium such as a hard disk or a semiconductor memory, and the recording / reproducing unit 1904 records and reproduces signals.

The control unit 1906 is composed of, for example, a microprocessor, and controls the operation of each unit in the imaging apparatus 1900 in a centralized manner. For example, the control unit 1906 comprehensively controls the operation of each unit in the image capturing apparatus 1900 according to an instruction from the user input via a user interface (not shown) included in the image capturing apparatus 1900. Further, the control unit 1906 drives and controls the mechanical shutter and the diaphragm mechanism in the optical system 1901 to realize automatic exposure processing and the like.

F. Configuration Example of Information Processing Device FIG. 20 shows a configuration example of an information processing device 2000 equipped with an image sensor configured by applying the technology disclosed in this specification. The information processing device 2000 corresponds to, for example, a smartphone, a tablet, or another type of information terminal, but with respect to the control unit 2010, a display unit 2020, a voice processing unit 2030, a communication unit 2040, a storage unit 2050, an imaging unit 2060. , The sensor unit 2070, etc. are connected.

The control unit 2010 includes a CPU 2011, a ROM (Read Only Memory) 2012, a RAM (Random Access Memory) 20613, and the like. The ROM 2012 stores program codes executed by the CPU 2011, information essential to the information processing apparatus 2000, and the like.

The CPU 2011 loads the program code from the ROM 2012 or the storage unit 2050 into the RAM 2013 and executes it. Examples of the program executed by the CPU 2011 include an operating system (OS) such as Android and iOS, and various application programs operating under the execution environment provided by the OS.

The display unit 2020 includes a display panel 2021 including a liquid crystal element, an organic EL (Electro Luminescence) element, and the like, and a transparent touch panel 2023 attached to the upper surface of the display panel 2021. The display panel 2021 is connected to the control unit 2010 via the display interface 2022, and displays and outputs the image information generated by the control unit 610. In addition, the touch panel 2023 is connected to the control unit 2010 via the touch interface 2024, and outputs coordinate information, which the user operates on the display panel 2021 with a fingertip, to the control unit 2010. On the control unit 2010 side, a touch operation by the user (tap, long press, flick, swipe, etc.) is detected based on the input coordinate information, and a process corresponding to the user operation is activated.

The audio processing unit 2030 includes an audio output unit 2031 such as a speaker, an audio input unit 2032 such as a microphone, and an audio codec (CODEC) 2033 that encodes and decodes input and output audio signals. The audio processing unit 2030 may further include an audio output terminal 2034 for outputting an audio signal to headphones (not shown).

The communication unit 2040 performs communication processing of information between an application executed by the control unit 2010 and an external device (not shown). Examples of the external device mentioned here include an information terminal handled by another user, a server existing on the Internet, and the like. The communication unit 2040 is equipped with physical layer modules such as Wi-Fi (registered trademark), NFC (Near Field Communication), and Bluetooth (registered trademark) communication depending on the communication medium used, and via the physical layer module. Modulation / demodulation processing and coding / decoding processing of transmitted / received communication signals are performed.

The storage unit 2050 is composed of a large-capacity storage device such as SSD (Solid State Drive) or HDD (Hard Disc Drive). For example, application programs and contents downloaded via the communication unit 2040, image data such as still images and moving images captured by the image capturing unit 2060, and the like are stored in the storage unit 2050.

The image capturing unit 2060 corresponds to the image capturing apparatus 1900 shown in FIG. 19 and applies the technology disclosed in this specification. The imaging unit 2060 outputs the generated image data to the control unit 2010 via a camera interface (not shown).

The sensor unit 2070 is a GPS (Global Positioning System) sensor for acquiring the position information of the information processing apparatus 2000, a gyro sensor for detecting the posture or acting force of the information processing apparatus 2000 main body, and an acceleration sensor. Etc. are included.

The technology disclosed in this specification has been described in detail above with reference to the specific embodiments. However, it is obvious that a person skilled in the art can modify or substitute the embodiment without departing from the gist of the technique disclosed in the present specification.

The technology disclosed in this specification can be suitably applied mainly to a column AD conversion unit of an image sensor such as CMOS or CCD. Of course, the technique disclosed in this specification can be similarly applied to an AD conversion circuit that is required to have a simple configuration.

Further, the image sensor to which the technology disclosed in this specification is applied can be widely used for digital still cameras, digital video cameras, vehicle-mounted cameras, and various information terminals such as smartphones and tablets.

In short, although the technology disclosed in this specification has been described in the form of exemplification, the contents described in this specification should not be interpreted in a limited manner. In order to determine the gist of the technology disclosed in this specification, the claims should be taken into consideration.

Note that the technology disclosed in this specification may have the following configurations.
(1) An amplifier that amplifies an analog signal,
A determination unit that determines the higher-order bits of the analog signal,
An adjustment unit that adjusts the level of the analog signal input to the amplifier based on the determination result of the determination unit;
A single-slope AD converter that AD-converts the lower bits of the analog signal using the level-adjusted output signal;
A signal processing device comprising:
(2) The determination unit is configured to determine a higher-order bit of the analog signal before being input to the amplifier.
The signal processing device according to (1) above.
(3) The determination unit includes an inverter, a capacitor, and a switch element,
The signal processing device according to any one of (1) and (2) above.
(4) The determination unit includes a first capacitor to which the analog signal is input to a first terminal and a second capacitor to which a reference signal is input to the first terminal, and the inverter includes the first capacitor. The second terminals of the first and second capacitors are input, and the switching element shorts the output of the inverter to the input during the auto-zero period,
The signal processing device according to (3) above.
(5) The determination unit determines a higher-order bit of the analog signal during D-phase settling in AD conversion of the analog signal,
The signal processing device according to any one of (1) to (4) above.
(6) A high-order bit determined by the determination unit and a low-order bit output from the AD conversion unit are connected to output a digital signal obtained by AD-converting the analog signal.
The signal processing device according to any one of (1) to (5) above.
(7) The amplifier is composed of a switched capacitor amplifier,
The signal processing device according to any one of (1) to (6) above.
(8) At least one of the determination unit and the adjustment unit is mounted in the circuit of the amplifier.
The signal processing device according to (7) above.
(9) The analog signal is a pixel signal output from a pixel,
The signal processing device according to any one of (1) to (8) above.
(10) The amplifier is a column amplifier, the AD converter is a column AD converter, and the signal processing apparatus according to any one of (1) to (9) is used.
Image sensor.
(11) An imaging device including the image sensor according to (10).
(12) An information processing device equipped with the imaging device according to (11).

100 ... Image sensor 101 ... Pixel array, 102 ... Reference voltage generation part, 103 ... AD conversion part 104 ... Horizontal transfer part, 111 ... Control part, 112 ... Vertical scanning part 121 ... Vertical signal line, 122 ... Reference signal line, 123 ... signal line 125 ... control line 131, 132, 133, 134 ... control line 141 ... unit pixel 151 ... photodiode, 152 ... transfer transistor 153 ... reset transistor, 154 ... amplification transistor 155 ... select transistor 160 ... column amplifier, 161 Column AD converter 171 Comparator 172 Counter 173 Capacitor 174 Capacitor 181 Comparator 1000 Signal processing circuit 1001 Judgment unit 1002 Adjustment unit 1101 Capacitor (C _IN ) 1102 ... Amplifier 1103 ... Capacitor (C _FB ) 1104 ... Switch 1110 ... DA converter, 1111-1113 ... Switch 1114-11116 ... Capacitor 1401 ... Inverter, 1402 ... First capacitor (C1)
1403 ... 2nd capacitor (C2), 1404 ... Switch 1405 ... Latch, 1406 ... DA converter 1900 ... Imaging device, 1901 ... Optical system, 1902 ... Image sensor 1903 ... Signal processing part, 1904 ... Recording / reproducing part, 1905 ... Recording Unit 1906 ... Control unit 2000 ... Information processing device, 2010 ... Control unit, 2020 ... Display unit 2021 ... Display panel, 2022 ... Display interface 2023 ... Touch panel, 2024 ... Touch interface 2030 ... Voice processing unit, 2031 ... Voice output unit 2032 ... Audio input unit, 2033 ... Audio codec 2034 ... Audio output terminal, 2040 ... Communication unit, 2050 ... Storage unit 2060 ... Imaging unit, 2070 ... Sensor unit

Claims (12)

An amplifier that amplifies the analog signal,
A determination unit that determines the higher-order bits of the analog signal,
An adjustment unit that adjusts the level of the analog signal input to the amplifier based on the determination result of the determination unit;
A single-slope AD converter that AD-converts the lower bits of the analog signal using the level-adjusted output signal;
A signal processing device comprising: The determination unit is configured to determine a high-order bit of the analog signal before being input to the amplifier.
The signal processing device according to claim 1. The determination unit includes an inverter, a capacitor, and a switch element,
The signal processing device according to claim 1. The determination unit includes a first capacitor to which the analog signal is input to a first terminal and a second capacitor to which a reference signal is input to the first terminal, and the inverter includes the first and second capacitors. The second terminal of the second capacitor is input, and the switching element shorts the output of the inverter to the input during the auto-zero period,
The signal processing device according to claim 3. The determination unit determines the upper bit of the analog signal during D-phase settling in AD conversion of the analog signal,
The signal processing device according to claim 1. Connecting the upper bit determined by the determination unit and the lower bit output from the AD conversion unit to output a digital signal obtained by AD converting the analog signal;
The signal processing device according to claim 1. The amplifier is composed of a switched capacitor amplifier,
The signal processing device according to claim 1. At least one of the determination unit and the adjustment unit is mounted in the circuit of the amplifier,
The signal processing device according to claim 7. The analog signal is a pixel signal output from a pixel,
The signal processing device according to claim 1. The signal processing device according to claim 1, wherein the amplifier is a column amplifier, and the AD converter is a column AD converter.
Image sensor. An imaging device equipped with the image sensor according to claim 10. An information processing device equipped with the image pickup device according to claim 11.

Images