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WO2020052024A1 - 阵列基板及其制备方法和显示器件 - Google Patents

阵列基板及其制备方法和显示器件 Download PDF

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Publication number
WO2020052024A1
WO2020052024A1 PCT/CN2018/113397 CN2018113397W WO2020052024A1 WO 2020052024 A1 WO2020052024 A1 WO 2020052024A1 CN 2018113397 W CN2018113397 W CN 2018113397W WO 2020052024 A1 WO2020052024 A1 WO 2020052024A1
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WIPO (PCT)
Prior art keywords
layer
source
buffer layer
array substrate
drain
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PCT/CN2018/113397
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Priority to US16/312,311 priority Critical patent/US20200083259A1/en
Publication of WO2020052024A1 publication Critical patent/WO2020052024A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application belongs to the field of display technology, and particularly relates to an array substrate, a method for manufacturing the same, and a display device.
  • AMLCD Active Liquid Crystal Display
  • AMOLED Active Organic Light Emitting Diode Display
  • the two display modes coexist with each other with their own advantages.
  • the active liquid crystal display includes an active array substrate, a color filter substrate, and a liquid crystal layer located between the two substrates.
  • the active organic light emitting diode display includes an active array substrate and an organic light emitting diode layer. Both display methods require a stable and reliable array substrate.
  • the array substrate includes one or more thin-film transistors (TFTs).
  • TFTs thin-film transistors
  • the conductive layer, insulating layer materials, and process methods of the formed thin-film transistors are similar. Began to change than the traditional. For example, from traditional Al / Mo to Cu / Mo, Cu / Mo-Ti, ITO, etc., or silicon nitride to silicon oxide and other organic or inorganic insulating materials.
  • the source / drain of the conductive layer and the passivation layer often have poor adhesion, which not only reduces the yield of the finished product, but also affects the display quality.
  • the Source / Drain is a Cu wire and the PV is silicon oxide
  • the adhesion between the Source / Drain and the silicon oxide is poor, and gas bulging will occur, which greatly reduces the panel yield.
  • the purpose of this application is to overcome the above-mentioned shortcomings of the prior art, and to provide an array substrate, a method for manufacturing the same, and a display device, which are intended to include, but not limited to, an array substrate composed of a conventional thin film transistor. Technical problems with poor adhesion between them.
  • An array substrate includes:
  • a gate insulating layer formed on the substrate and covering the gate
  • Source and drain formed on the active layer
  • a buffer layer for improving adhesion between the source and drain electrodes and the passivation layer is provided between the source and drain electrodes and the passivation layer, and the buffer layer is coated on the buffer layer Source-drain surface.
  • the buffer layer is composed of a conductive material, and the conductive material is indium tin oxide, a molybdenum-containing alloy, or a titanium-containing alloy.
  • the buffer layer is composed of a semiconductor material, and the semiconductor material is a metal oxide semiconductor material.
  • the buffer layer is composed of an insulating material, and the insulating material is an organic insulating material or an inorganic insulating material.
  • the organic insulating material is a resin.
  • the inorganic insulating material includes at least one of silicon nitride, silicon oxynitride, and alumina.
  • a method for preparing an array substrate includes the following steps:
  • the buffer layer covers the source and drain surfaces, and the buffer layer is used to improve the adhesion between the source and drain and the passivation layer.
  • the buffer layer is composed of a conductive material, a semiconductor material, or an insulating material.
  • the thickness of the buffer layer is 10-200 nm.
  • the present application provides a display device.
  • the display device includes an array substrate.
  • the array substrate includes:
  • a gate insulating layer formed on the substrate and covering the gate
  • Source and drain formed on the active layer
  • a buffer layer for improving adhesion between the source and drain electrodes and the passivation layer is provided between the source and drain electrodes and the passivation layer, and the buffer layer is coated on the buffer layer Source-drain surface
  • the buffer layer is composed of an insulating material, and the insulating material is an organic insulating material or an inorganic insulating material; the organic insulating material is a resin, and the inorganic insulating material includes silicon nitride, silicon oxynitride, and aluminum oxide. At least one.
  • the display device is a liquid crystal display device or an organic light emitting diode display device.
  • a buffer layer is added between the source and drain and the passivation layer.
  • the buffer layer covers the surface of the source and drain, and has a good effect on both the source and drain and the passivation layer. This can improve the adhesion between the source and drain electrodes and the passivation layer.
  • the array substrate provided with a buffer layer in the present application has good flatness and uniformity, which can improve There are bubbles in the display process of the display panel and uneven display of bright or dark spots.
  • a buffer layer for improving adhesion between the source and drain electrodes and the passivation layer is directly added between the source and drain electrodes and the passivation layer.
  • the source and drain electrodes are covered completely to cover the source and drain electrodes.
  • the display device provided in the embodiment of the present application is provided with an array substrate unique to the present application, and the array substrate has good flatness and uniformity, which can improve the presence of air bubbles during the display process of the display panel and the occurrence of bright or dark spots.
  • the display is uneven, so the display device having the array substrate has a good display effect.
  • FIG. 1 is an abnormal effect diagram caused by poor adhesion between a source and a drain and a passivation layer of an existing array substrate:
  • FIG. 2 is a structural diagram of a buffer layer added between a source and a drain and a passivation layer of an array substrate according to an embodiment of the present application;
  • each reference numeral in the figure is:
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality” is two or more, unless specifically defined otherwise.
  • an embodiment of the present application provides an array substrate, whose structure is shown in FIG. 2 and includes:
  • the gate 2 is formed on the substrate 1;
  • An active layer 4 is formed on the gate insulating layer 3;
  • Source and drain 5 are formed on the active layer 4;
  • a buffer layer 7 is provided between the source and drain electrodes 5 and the passivation layer 6 to improve adhesion between the source and drain electrodes 5 and the passivation layer 6, and the buffer layer 7 covers the surface of the source and drain electrodes 5.
  • FIG. 1 is a schematic structural diagram of an existing array substrate, in which the adhesion between the source and drain electrodes 5 (such as Cu) and the passivation layer 6 (such as silicon oxide) is poor, and gas bulging occurs: and the array substrate provided in the embodiment of the present application (As shown in FIG. 2), a buffer layer 7 is added between the source and drain electrodes 5 and the passivation layer 6, and the buffer layer 7 covers the surface of the source and drain electrodes 5 and passes through the source and drain electrodes 5 and the passivation layer.
  • the source and drain electrodes 5 such as Cu
  • the passivation layer 6 such as silicon oxide
  • the layer 6 also has good adhesion, which can improve the adhesion between the source and drain electrodes 5 and the passivation layer 6; therefore, the array substrate provided with the buffer layer 7 provided in the embodiment of the present application has a good
  • the flatness and uniformity can improve the air bubbles existing in the display process of the display panel and the uneven display of bright or dark spots.
  • the buffer layer 7 is composed of any one of a conductive material, a semiconductor material, or an insulating material, that is, the buffer layer 7 may be a conductive layer made of a conductive material, or A semiconductor layer composed of a semiconductor material may also be an insulating layer composed of an insulating material.
  • the buffer layer is composed of a conductive material, and the conductive material is indium tin oxide (ITO), a molybdenum (Mo) -containing alloy, or a titanium (Ti) -containing alloy.
  • the buffer layer is composed of a semiconductor material, and the semiconductor material is a metal oxide semiconductor material, such as zinc oxide, tin oxide, indium oxide, molybdenum oxide, or the like, or a mixture thereof.
  • the buffer layer is composed of an insulating material, and the insulating material is an organic insulating material or an inorganic insulating material; wherein the inorganic insulating material includes at least one of silicon nitride, silicon oxynitride, and alumina.
  • the organic insulating material is resin
  • Resins include various natural resins and artificial resins, such as phenolic resin, urea resin, aniline resin, melamine formaldehyde resin, glycerin resin, silicone resin, polyester film, unsaturated polyester resin, epoxy resin, and the like.
  • the reason for the poor adhesion between the passivation layer made of silicon oxide material and the source and drain made of copper material is that silicon oxide (SiO x ) has fewer surface defects, and the suspended Si- is relatively small, so there are fewer The dangling Si-bonds have a small bond with the Cu surface of the face-centered cubic structure, which is prone to poor adhesion.
  • Conductive materials and semiconductor materials are connected by ionic bonds and can make good contact with Cu surfaces; organic materials such as resins can also make good contact with Cu surfaces due to their special thermal expansion coefficients and possible van der Waals forces. Therefore, the buffer layer composed of the above materials can increase the adhesion between the passivation layer and the source and drain.
  • the source and drain electrodes 5 are made of copper.
  • the source and drain electrodes 5 are provided with channels above the active layer 4.
  • the source and drain electrodes 5 are divided into source and drain electrodes and are distributed in the active layer.
  • the passivation layer 6 is silicon oxide, and the buffer layer 7 may be an ITO layer. Adding an oxide conductor ITO layer on the copper surface can solve the problem of poor adhesion between copper and silicon oxide;
  • the wet-etched line width Loss of 5 metal wires (such as Cu) is larger than the oxide conductive material ITO. Therefore, the metal wires of source and drain electrodes 5 and the ITO layer (buffer layer 7) can use the same mask.
  • the metal surface of the source and drain electrodes 5 may be covered to form a protective layer of the source and drain electrodes 5.
  • the thickness of the buffer layer 7 is 10-200 nm. Within this thickness range, the adhesion between the source and drain electrodes 5 and the passivation layer 6 can be increased without affecting the display performance of the display panel, and the overall effect is the best.
  • an embodiment of the present application further provides a method for preparing an array substrate, including the following steps:
  • the buffer layer 7 covers the surface of the source and drain electrodes 5, and the buffer layer 7 is used to improve the adhesion between the source and drain electrodes 5 and the passivation layer 6.
  • a buffer layer 7 is directly added between the source and drain electrodes 5 and the passivation layer 6 to improve the adhesion between the source and drain electrodes 5 and the passivation layer 6.
  • the buffer layer 7 is covered on the surface of the source and drain electrodes 5 to completely cover the source and drain electrodes.
  • the preparation process does not need to add extra mask expenses. Therefore, the process is simple, the cost is low, and the array substrate is finally manufactured. It has good flatness and uniformity, and can significantly improve the phenomenon of air bubbles in the display process of the display panel and uneven display of bright or dark spots.
  • the substrate 1 is a glass substrate, and the prepared gate insulating layer 3 (GI) may be silicon nitride or silicon oxide.
  • the prepared active layer 4 is an etch stop structure (ESL), which may be an a-Si layer.
  • the prepared buffer layer 7 is composed of a conductive material, a semiconductor material or an insulating material, and the thickness of the buffer layer is 10-200 nm. The buffer layer 7 in this manufacturing method has been described in detail in the above array substrate, and will not be repeated here.
  • the display device includes an array substrate, and the array substrate includes:
  • the gate 2 is formed on the substrate 1;
  • An active layer 4 is formed on the gate insulating layer 3;
  • Source and drain 5 are formed on the active layer 4;
  • a buffer layer 7 is provided between the source and drain electrodes 5 and the passivation layer 6 to improve adhesion between the source and drain electrodes 5 and the passivation layer 6, and the buffer layer 7 is coated on the surface of the source and drain 5;
  • the buffer layer 7 is composed of an insulating material, and the insulating material is an organic insulating material or an inorganic insulating material; the organic insulating material is a resin, and the inorganic insulating material includes silicon nitride, silicon oxynitride, and aluminum oxide At least one of.
  • the display device provided in the embodiment of the present application is provided with an array substrate unique to the present application, and the array substrate has good flatness and uniformity, which can improve the presence of air bubbles during the display process of the display panel and the occurrence of bright or dark spots.
  • the display is uneven, so the display device having the array substrate has a good display effect.
  • the display device is a liquid crystal display device, which may be an active liquid crystal display device; or an organic light emitting diode display device, which may be an active organic light emitting diode display device. That is, an active liquid crystal display device composed of an array substrate according to the embodiment of the present application, a color filter substrate and a liquid crystal layer located between the two substrates, and an active type composed of an array substrate and an organic light emitting diode layer according to the embodiment of the present application Organic light emitting diode display device.
  • FIG. 2 is a schematic structural diagram of an array substrate composed of a plurality of thin film transistors according to this embodiment.
  • the array substrate includes: a substrate 1 made of glass material; a gate 2 formed on the substrate 1; and a gate insulating layer 3 formed on The substrate 1 covers the gate 2; an active layer 4 is formed on the gate insulating layer 3; a source and drain 5 composed of a copper material is formed on the active layer 4; silicon oxide A passivation layer 6 made of a material, the passivation layer covering the source and drain electrodes 5; wherein a gap between the source and drain electrodes 5 and the passivation layer 6 is provided for improving the source and drain electrodes 5 and
  • the adhesive layer 7 made of ITO material is adhered between the passivation layers 6, and the buffer layer 7 covers the surface of the source and drain electrodes 5.
  • the manufacturing process of the array substrate is as follows:
  • S11 a substrate 1 (Glass) provided with a glass material;
  • S16 preparing a buffer layer 7 (ITO layer) on the source and drain electrodes 5, and preparing a passivation layer 6 (PV, silicon oxide material) on the buffer layer 7;
  • the buffer layer 7 covers the surface of the source and drain electrodes 5, and the buffer layer 7 is used to improve the adhesion between the source and drain electrodes 5 and the passivation layer 6 and solve the problem of poor adhesion between Cu and silicon oxide. .
  • FIG. 2 is a schematic structural diagram of an array substrate composed of a plurality of thin film transistors according to this embodiment.
  • the array substrate includes: a substrate 1 made of glass material; a gate 2 formed on the substrate 1; and a gate insulating layer 3 formed on The substrate 1 covers the gate 2; an active layer 4 is formed on the gate insulating layer 3; a source and drain 5 composed of a copper material is formed on the active layer 4; silicon oxide A passivation layer 6 made of a material, the passivation layer covering the source and drain electrodes 5; wherein a gap between the source and drain electrodes 5 and the passivation layer 6 is provided for improving the source and drain electrodes 5 and
  • the adhesive layer 7 composed of an organic insulating material or an inorganic insulating material between the passivation layers 6 is covered, and the buffer layer 7 covers the surface of the source and drain electrodes 5.
  • S21 substrate 1 (Glass) provided with glass material
  • S26 preparing a buffer layer 7 (organic insulating layer or inorganic insulating layer) on the source and drain electrodes 5, and preparing a passivation layer 6 (PV, silicon oxide material) on the buffer layer 7;
  • a buffer layer 7 organic insulating layer or inorganic insulating layer
  • PV silicon oxide material
  • the buffer layer 7 covers the surface of the source and drain electrodes 5, and the buffer layer 7 is used to improve the adhesion between the source and drain electrodes 5 and the passivation layer 6 and solve the problem of poor adhesion between Cu and silicon oxide. .

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  • Thin Film Transistor (AREA)

Abstract

阵列基板包括：基板；栅极；栅极绝缘层；有源层；源漏极；钝化层；其中，源漏极与钝化层之间设置有用于提高源漏极与钝化层之间粘附性的缓冲层，且缓冲层包覆在源漏极表面。

Description

阵列基板及其制备方法和显示器件 技术领域
本申请属于显示技术领域，具体涉及一种阵列基板及其制备方法和显示器件。
背景技术
随着显示科技的日渐进步，平板显示成为人们不可缺少的必备品之一。目前主流显示包括主动式液晶显示器(Active Matrix Liquid Crystal Display，AMLCD)和主动式有机发光二极管显示器(Active Matrix Organic Light Emitting Diode，AMOLED)，两种显示方式以各自优势相互并存。
主动式液晶显示器包括主动阵列基板，彩色滤光片基板以及与位于两基板之间的液晶层所构成。主动式有机发光二极管显示器包括主动阵列基板和有机发光二极管层。两种显示方式均需要有稳定可靠的阵列基板。阵列基板包含一个或多个薄膜晶体管(Thin-film Transistor，TFT)，随着人们对显示面板的分辨率以及显示品质的需求不断提升，所构成薄膜晶体管的导电层、绝缘层材料和制程方式相较于传统开始发生转变。如，从传统的Al/Mo开始转向Cu/Mo，Cu/Mo-Ti，ITO等，或氮化硅到氧化硅以及其它有机或无机绝缘材料。然而，随着材料的变化，导电层源漏极(Source/Drain)与钝化层(Passivation，PV)往往会产生粘附很差的情况，如此不仅降低成品良率，还会影响显示品质。如当Source/Drain为Cu导线，PV为氧化硅时，Source/Drain与氧化硅粘附力比较差，会出现气隆起，极大地降低了面板良率。
申请内容
本申请的目的在于克服现有技术的上述不足，提供一种阵列基板及其制备方法和显示器件，旨在包括但不限于解决现有薄膜晶体管组成的阵列基板中，源漏极与钝化层之间粘附性差的技术问题。
为实现上述目的，本申请实施例采用的技术方案如下：
一种阵列基板，包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成于所述基板上并覆盖所述栅极；
有源层，形成于所述栅极绝缘层上；
源漏极，形成于所述有源层上；
钝化层，所述钝化层覆盖所述源漏极；
其中，所述源漏极与所述钝化层之间设置有用于提高所述源漏极与所述钝化层之间的粘附性的缓冲层，且所述缓冲层包覆在所述源漏极表面。
在一个实施例中，所述缓冲层由导电材料组成，且所述导电材料为氧化铟锡、含钼合金或含钛合金含。
在一个实施例中，所述缓冲层由半导体材料组成，且所述半导体材料为金属氧化物半导体材料。
在一个实施例中，所述缓冲层由绝缘材料组成，且所述绝缘材料为有机绝缘材料或无机绝缘材料。
在一个实施例中，所述有机绝缘材料为树脂。
在一个实施例中，所述无机绝缘材料包括氮化硅、氮氧化硅和三氧化二铝中的至少一种。
一种阵列基板的制备方法，包括如下步骤：
提供基板；
在所述基板上制备栅极；
在所述栅极上制备栅极绝缘层；
在所述栅极绝缘层上制备有源层；
在所述有源层上制备源漏极；
在所述源漏极上制备缓冲层，在所述缓冲层上制备钝化层；
其中，所述缓冲层包覆在所述源漏极表面，且所述缓冲层用于提高所述源漏极与所述钝化层之间的粘附性。
在一个实施例中，所述缓冲层由导电材料、半导体材料或绝缘材料组成。
在一个实施例中，所述缓冲层的厚度为10-200nm。
最后，本申请提供一种显示器件，所述显示器件包括阵列基板，所述阵列基板包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成于所述基板上并覆盖所述栅极；
有源层，形成于所述栅极绝缘层上；
源漏极，形成于所述有源层上；
钝化层，所述钝化层覆盖所述源漏极；
其中，所述源漏极与所述钝化层之间设置有用于提高所述源漏极与所述钝化层之间的粘附性的缓冲层，且所述缓冲层包覆在所述源漏极表面；
所述缓冲层由绝缘材料组成，且所述绝缘材料为有机绝缘材料或无机绝缘材料；所述有机绝缘材料为树脂，所述无机绝缘材料包括氮化硅、氮氧化硅和 三氧化二铝中的至少一种。
在一个实施例中，所述显示器件为液晶显示器件或有机发光二极管显示器件。
本申请实施例提供的阵列基板中，在源漏极与钝化层之间增设一层缓冲层，该缓冲层包覆在源漏极表面，且对源漏极和钝化层同时具有很好的粘附性，这样可以提高源漏极与钝化层之间的粘附性，与现有技术相比，本申请增设有缓冲层的阵列基板具有很好的平整度和均一性，能改善显示面板的显示过程中存在气泡，以及出现亮点或暗点的显示不均等现象。
本申请实施例提供的阵列基板的制备方法，直接在源漏极与钝化层之间增设一层用于提高源漏极与钝化层之间的粘附性的缓冲层，该缓冲层包覆在源漏极表面将源漏极完全包裹，该制备过程不需要增加额外的光罩费用支出，因此，工艺简单，且成本低，而且最终制得的阵列基板，具有很好的平整度和均一性，能够显著改善显示面板的显示过程中存在气泡，以及出现亮点或暗点的显示不均等现象。
本申请实施例提供的显示器件中设置有本申请特有的阵列基板，而该阵列基板具有很好的平整度和均一性，能改善显示面板的显示过程中存在气泡，以及出现亮点或暗点的显示不均等现象，因此具有该阵列基板的显示器件具有很好的显示效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳 动的前提下，还可以根据这些附图获得其它的附图。
图1为现有阵列基板的源漏极和钝化层之间粘附性差引起的异常效果图：
图2为本申请的一实施例提供的阵列基板的源漏极和钝化层之间增加有缓冲层的结构图；
其中，图中各附图标记为：
1-基板；2-栅极；3-栅极绝缘层；4-有源层；5-源漏极；6-钝化层；7-缓冲层。
具体实施方式
为了使本申请要解决的技术问题、技术方案和优点更加清楚明白，以下结合附图和实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
需要说明的是，当元件被称为“固定于”或“设置于”另一个元件，它可以直接在另一个元件上或者间接在该另一个元件上。当一个元件被称为是“连接于”另一个元件，它可以是直接连接到另一个元件或间接连接至该另一个元件上。
需要理解的是，术语“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、 “第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
一方面，本申请实施例提供了一种阵列基板，其结构如图2所示，包括：
基板1；
栅极2，形成于所述基板1上；
栅极绝缘层3，形成于所述基板1上并覆盖所述栅极2；
有源层4，形成于所述栅极绝缘层3上；
源漏极5，形成于所述有源层4上；
钝化层6，所述钝化层覆盖所述源漏极5；
其中，所述源漏极5与所述钝化层6之间设置有用于提高所述源漏极5与所述钝化层6之间的粘附性的缓冲层7，且所述缓冲层7包覆在所述源漏极5表面。
图1为现有阵列基板的结构示意图，其中，源漏极5(如Cu)与钝化层6(如氧化硅)之间粘附性差，出现气隆起：而本申请实施例提供的阵列基板中(如图2所示)，在源漏极5与钝化层6之间增设一层缓冲层7，该缓冲层7包覆在源漏极5表面，且对源漏极5和钝化层6同时具有很好的粘附性，这样可以提高源漏极5与钝化层6之间的粘附性；因此，本申请实施例提供的增设有缓冲层7的阵列基板，具有很好的平整度和均一性，能改善显示面板的显示过程中存在气泡，以及出现亮点或暗点的显示不均等现象。
进一步地，本申请实施例提供的阵列基板中，所述缓冲层7由导电材料、半导体材料或绝缘材料中的任意一种组成，即该缓冲层7可以为导电材料组成的导电层，或可以为半导体材料组成的半导体层，也可以为绝缘材料组成的绝缘层。
可选地，所述缓冲层由导电材料组成，且所述导电材料为氧化铟锡(ITO)、含钼(Mo)合金或含钛(Ti)的合金。或者，所述缓冲层由半导体材料组成，且所述半导体材料为金属氧化物半导体材料，比如氧化锌，氧化锡，氧化铟，氧化钼等或者它们的混合物。或者，所述缓冲层由绝缘材料组成，且所述绝缘材料为有机绝缘材料或无机绝缘材料；其中，所述无机绝缘材料包括氮化硅、氮氧化硅和三氧化二铝中的至少一种(因要解决氧化硅材料组成的钝化层与铜材料组成的源漏极之间的粘附性不好的问题，此处缓冲层材料不包括氧化硅)；所述有机绝缘材料为树脂，树脂包括各种天然树脂和人工树脂，如酚醛树脂、脲醛树脂、苯胺甲醛树脂、三聚氰胺甲醛树脂、甘油树脂、有机硅树脂、聚酯薄膜、不饱和聚酯树脂、环氧树脂等。
氧化硅材料组成的钝化层与铜材料组成的源漏极之间的粘附性不佳的原因为：氧化硅(SiO x)表面缺陷较少，悬空的Si-相对较小，因此较少的悬空Si-键与面心立方结构的Cu表面结合较小，容易出现粘附性不佳的状况。导体材料和半导体材料其连接方式为离子键，能与Cu表面接触良好；而有机材料如树脂由于特殊的热膨胀系数以及可能存在的范德华力，也能与Cu表面接触良好。因此，上述材料组成的缓冲层能增加钝化层与源漏极之间的粘附性。
在一具体的实施例中，该源漏极5为铜材料，源漏极5在有源层4的上方设有沟道，将源漏极5分为源极和漏极，分布在有源层4两侧。该钝化层6为氧化硅，而该缓冲层7则可选为ITO层，在铜表面增加氧化物导体ITO层，可以解决铜与氧化硅粘附性较差的问题；同时，源漏极5的金属导线(如Cu)的湿刻蚀线宽Loss较氧化物导电材料ITO大，因此，源漏极5的金属导线与ITO层(缓冲层7)可以采用同一道光罩的同时，ITO还可以覆盖在源漏极5的金属表面，形成为源漏极5的保护层。
进一步地，本申请实施例提供的阵列基板中，所述缓冲层7的厚度为10-200nm。在该厚度范围内，既可以增加源漏极5与钝化层6之间的粘附性，又不影响显示面板的显示性能，综合效果最佳。
另一方面，本申请实施例还提供了一种阵列基板的制备方法，包括如下步骤：
S01：提供基板1；
S02：在所述基板1上制备栅极2；
S03：在所述栅极2上制备栅极绝缘层3；
S04：在所述栅极绝缘层3上制备有源层4；
S05：在所述有源层4上制备源漏极5；
S06：在所述源漏极5上制备缓冲层7，在所述缓冲层7上制备钝化层6；
其中，所述缓冲层7包覆在所述源漏极5表面，且所述缓冲层7用于提高所述源漏极5与所述钝化层6之间的粘附性。
本申请实施例提供的阵列基板的制备方法，直接在源漏极5与钝化层6之间增设一层用于提高源漏极5与钝化层6之间的粘附性的缓冲层7，该缓冲层7包覆在源漏极5表面将源漏极完全包裹，该制备过程不需要增加额外的光罩费用支出，因此，工艺简单，且成本低，而且最终制得的阵列基板，具有很好的平整度和均一性，能够显著改善显示面板的显示过程中存在气泡，以及出现亮点或暗点的显示不均等现象。
进一步地，上述基板1为玻璃(Glass)基板，制备的栅极绝缘层3(GI)可以为氮化硅或氧化硅。制备的有源层4(Active Layer)为刻蚀阻挡型结构(ESL)，具体可以为a-Si层。制备的缓冲层7则由导电材料、半导体材料或绝缘材料组成，而缓冲层的厚度为10-200nm。该制备方法中的缓冲层7在上 文的阵列基板中已经详细阐述，在此不再重复说明。
最后，本申请实施例提供一种显示器件，所述显示器件包括阵列基板，所述阵列基板包括：
基板1；
栅极2，形成于所述基板1上；
栅极绝缘层3，形成于所述基板1上并覆盖所述栅极2；
有源层4，形成于所述栅极绝缘层3上；
源漏极5，形成于所述有源层4上；
钝化层6，所述钝化层覆盖所述源漏极5；
其中，所述源漏极5与所述钝化层6之间设置有用于提高所述源漏极5与所述钝化层6之间的粘附性的缓冲层7，且所述缓冲层7包覆在所述源漏极5表面；
所述缓冲层7由绝缘材料组成，且所述绝缘材料为有机绝缘材料或无机绝缘材料；所述有机绝缘材料为树脂，所述无机绝缘材料包括氮化硅、氮氧化硅和三氧化二铝中的至少一种。
本申请实施例提供的显示器件中设置有本申请特有的阵列基板，而该阵列基板具有很好的平整度和均一性，能改善显示面板的显示过程中存在气泡，以及出现亮点或暗点的显示不均等现象，因此具有该阵列基板的显示器件具有很好的显示效果。
进一步地，所述显示器件为液晶显示器件，可选为主动式液晶显示器件；或为有机发光二极管显示器件，可选为主动式有机发光二极管显示器件。即由本申请实施例的阵列基板，以及彩色滤光片基板和位于两基板之间的液晶层构成的主动式液晶显示器件，以及，由本申请实施例的阵列基板和有机发光二极 管层组成的主动式有机发光二极管显示器件。
本申请先后进行过多次试验，现举一部分试验结果作为参考对申请进行进一步详细描述，下面结合具体实施例进行详细说明。
其中一个实施例
图2为本实施例的多个薄膜晶体管组成的阵列基板的结构示意图，该阵列基板包括：玻璃材料的基板1；栅极2，形成于所述基板1上；栅极绝缘层3，形成于所述基板1上并覆盖所述栅极2；有源层4，形成于所述栅极绝缘层3上；铜材料组成的源漏极5，形成于所述有源层4上；氧化硅材料组成的钝化层6，所述钝化层覆盖所述源漏极5；其中，所述源漏极5与所述钝化层6之间设置有用于提高所述源漏极5与所述钝化层6之间的粘附性的、ITO材料组成的缓冲层7，且所述缓冲层7包覆在所述源漏极5表面。
该阵列基板的制程过程如下：
S11：提供玻璃材料的基板1(Glass)；
S12：在所述基板1上制备栅极2(Gate)；
S13：在所述栅极2上制备栅极绝缘层3(GI)；
S14：在所述栅极绝缘层3上制备有源层4(Active Layer)；
S15：在所述有源层4上制备源漏极5(Source/Drain，铜材料)；
S16：在所述源漏极5上制备缓冲层7(ITO层)，在所述缓冲层7上制备钝化层6(PV，氧化硅材料)；
其中，该缓冲层7包覆在源漏极5表面，且缓冲层7用于提高源漏极5与钝化层6之间的粘附性，解决Cu与氧化硅粘附性较差的问题。
其中另一个实施例
图2为本实施例的多个薄膜晶体管组成的阵列基板的结构示意图，该阵列 基板包括：玻璃材料的基板1；栅极2，形成于所述基板1上；栅极绝缘层3，形成于所述基板1上并覆盖所述栅极2；有源层4，形成于所述栅极绝缘层3上；铜材料组成的源漏极5，形成于所述有源层4上；氧化硅材料组成的钝化层6，所述钝化层覆盖所述源漏极5；其中，所述源漏极5与所述钝化层6之间设置有用于提高所述源漏极5与所述钝化层6之间的粘附性的、有机绝缘材料或无机绝缘材料组成的缓冲层7，且所述缓冲层7包覆在所述源漏极5表面。
其制程过程如下：
S21：提供玻璃材料的基板1(Glass)；
S22：在所述基板1上制备栅极2(Gate)；
S23：在所述栅极2上制备栅极绝缘层3(GI)；
S24：在所述栅极绝缘层3上制备有源层4(Active Layer)；
S25：在所述有源层4上制备源漏极5(Source/Drain，铜材料)；
S26：在所述源漏极5上制备缓冲层7(有机绝缘层或无机绝缘层)，在所述缓冲层7上制备钝化层6(PV，氧化硅材料)；
其中，该缓冲层7包覆在源漏极5表面，且缓冲层7用于提高源漏极5与钝化层6之间的粘附性，解决Cu与氧化硅粘附性较差的问题。
以上所述仅为本申请的可选实施例而已，并不用以限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (12)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成于所述基板上并覆盖所述栅极；
    有源层，形成于所述栅极绝缘层上；
    源漏极，形成于所述有源层上；
    钝化层，所述钝化层覆盖所述源漏极；
    其中，所述源漏极与所述钝化层之间设置有用于提高所述源漏极与所述钝化层之间的粘附性的缓冲层，且所述缓冲层包覆在所述源漏极表面。
  2. 如权利要求1所述的阵列基板，其中，所述缓冲层由导电材料组成，且所述导电材料为氧化铟锡、含钼合金或含钛合金含。
  3. 如权利要求1所述的阵列基板，其中，所述缓冲层由半导体材料组成，且所述半导体材料为金属氧化物半导体材料。
  4. 如权利要求1所述的阵列基板，其中，所述缓冲层由绝缘材料组成，且所述绝缘材料为有机绝缘材料或无机绝缘材料。
  5. 如权利要求4所述的阵列基板，其中，所述有机绝缘材料为树脂。
  6. 如权利要求4所述的阵列基板，其中，所述无机绝缘材料包括氮化硅、氮氧化硅和三氧化二铝中的至少一种。
  7. 如权利要求1-6任一项所述阵列基板，其中，所述缓冲层的厚度为10-200nm。
  8. 一种阵列基板的制备方法，其中，包括如下步骤：
    提供基板；
    在所述基板上制备栅极；
    在所述栅极上制备栅极绝缘层；
    在所述栅极绝缘层上制备有源层；
    在所述有源层上制备源漏极；
    在所述源漏极上制备缓冲层，在所述缓冲层上制备钝化层；
    其中，所述缓冲层包覆在所述源漏极表面，且所述缓冲层用于提高所述源漏极与所述钝化层之间的粘附性。
  9. 如权利要求8所述的制备方法，其中，所述缓冲层由导电材料、半导体材料或绝缘材料组成。
  10. 如权利要求8所述的制备方法，其中，所述缓冲层的厚度为10-200nm。
  11. 一种显示器件，其中，所述显示器件包括阵列基板，所述阵列基板包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成于所述基板上并覆盖所述栅极；
    有源层，形成于所述栅极绝缘层上；
    源漏极，形成于所述有源层上；
    钝化层，所述钝化层覆盖所述源漏极；
    其中，所述源漏极与所述钝化层之间设置有用于提高所述源漏极与所述钝化层之间的粘附性的缓冲层，且所述缓冲层包覆在所述源漏极表面；
    所述缓冲层由绝缘材料组成，且所述绝缘材料为有机绝缘材料或无机绝缘材料；所述有机绝缘材料为树脂，所述无机绝缘材料包括氮化硅、氮氧化硅和 三氧化二铝中的至少一种。
  12. 如权利要求11所述的显示器件，其中，所述显示器件为液晶显示器件或有机发光二极管显示器件。
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