WO2019188321A1

WO2019188321A1 - Solid-state imaging device, imaging device, and electronic device

Info

Publication number: WO2019188321A1
Application number: PCT/JP2019/010458
Authority: WO
Inventors: 正彦中溝
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2018-03-28
Filing date: 2019-03-14
Publication date: 2019-10-03

Abstract

The present invention relates to an imaging device, an electronic device, and a solid-state imaging device which can enhance the charge transmitting capacity and the charge holding capacity of the solid-state imaging device. According to the present invention, when a switch which brings into a floating state a control signal line that supplies a control signal for controlling the opening and closing of a transmission gate that transmits a charge of a photodiode to an FD unit, and an additional wiring line for capacitive-coupling of the control signal line are disposed in parallel and the switch brings the control signal line into the floating state by switching off the switch, the voltage of the control signal is increased or decreased in response to the coupling capacity of the control signal line. The present invention can be adapted to an imaging device by applying a signal to the additional wiring line.

Description

Solid-state imaging device, imaging device, and electronic apparatus

The present disclosure relates to a solid-state imaging device, an imaging device, and an electronic device, and more particularly, to a solid-state imaging device, an imaging device, and an electronic device that improve charge transfer performance and charge retention performance in each pixel of the solid-state imaging device. .

A technique for improving the charge transfer capability and the charge retention capability of an image sensor has been proposed.

For example, by using the coupled gate voltage coupling phenomenon, the gate bias voltage of the transmission transistor and the initial voltage of the floating diffusion node are increased to a level higher than the power supply voltage, thereby increasing the capacitance of the photodiode and reducing the image lag phenomenon. Has been proposed (see Patent Document 1).

In addition, the gate voltage of the transfer transistor is controlled to the first gate voltage to transfer electrons as a signal charge from the phototransistor to the charge detection unit, and in the second period after the first period The gate voltage of the transfer transistor is set to a second gate voltage that increases the capability of transferring the signal charge to the charge detection unit, compared to the first gate voltage, in the second period, while making the gate of the transistor high impedance. A control technique has been proposed (see Patent Document 2).

JP 2006-186355 A JP 2006-042120 A

However, in the technique of Patent Document 1, it is necessary to create a double gate, and it is impossible to fabricate with a normal CMOS (Complementary Metal Metal Oxide Semiconductor) process. Increase. In addition, two types of gate control lines are required for each pixel, which increases the area and power consumption of the drive circuit.

In the technique of Patent Document 2, since the control signal line and the transfer gate control line are capacitively coupled via an FD (Floating Diffusion) node, the coupling is indirect. The effect of displacing the potential of the control line is small, and since the capacity connected to the FD increases, the conversion efficiency may be lowered.

The present disclosure has been made in view of such a situation, and in particular, improves charge transfer performance and charge retention performance in each pixel of the solid-state imaging device.

A solid-state imaging device, an imaging device, and an electronic device according to one aspect of the present disclosure include a transfer gate that transfers a pixel signal from a pixel that generates a pixel signal corresponding to the amount of incident light by photoelectric conversion, and opens and closes the transfer gate. It is a solid-state imaging device including a floating mechanism unit that brings a control signal line that supplies a control signal to be controlled into a floating state, and an additional wiring that is capacitively coupled to the control signal line.

In one aspect of the present disclosure, a control signal for supplying a control signal for transferring a pixel signal from a pixel that generates a pixel signal corresponding to the amount of incident light by photoelectric conversion by a transfer gate and that controls the opening and closing of the transfer gate. The line is in a floating state, and includes an additional wiring that is capacitively coupled to the control signal line.

According to one aspect of the present disclosure, it is possible to improve the charge transfer performance and the charge retention performance in each pixel of the solid-state imaging device.

It is a figure explaining the structural example of the imaging device of this indication. It is a figure explaining the structural example of 1st Embodiment of the imaging device of FIG. 3 is a timing chart for explaining the operation of the imaging apparatus having the circuit configuration of FIG. 2. FIG. 3 is a diagram illustrating a configuration example of a physical layout in the circuit configuration of FIG. 2. It is a figure explaining AB cross section of FIG. It is a figure explaining the 1st modification of 1st Embodiment of the imaging device of this indication. It is a figure explaining the 2nd modification of 1st Embodiment of the imaging device of this indication. It is a figure explaining the structural example of the physical layout in the circuit structure of FIG. It is a figure explaining the 3rd modification of 1st Embodiment of the imaging device of this indication. It is a figure explaining the structural example of 2nd Embodiment of the imaging device of this indication. It is a timing chart explaining operation | movement of the imaging device which consists of a circuit structure of FIG. It is a figure explaining the structural example of the physical layout in the circuit structure of FIG. It is a figure explaining the 1st modification of 2nd Embodiment of the imaging device of this indication. It is a timing chart explaining operation | movement of the imaging device which consists of a circuit structure of FIG. It is a figure explaining the 2nd modification of 2nd Embodiment of the imaging device of this indication. 16 is a timing chart for explaining the operation of the imaging apparatus having the circuit configuration of FIG. It is a block diagram which shows the structural example of the imaging device as an electronic device to which the camera module of this indication is applied. It is a figure explaining the usage example of the camera module to which the technique of this indication is applied. It is a figure which shows an example of a schematic structure of an endoscopic surgery system. It is a block diagram which shows an example of a function structure of a camera head and CCU. It is a block diagram which shows an example of a schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1. First embodiment 2. First modification of the first embodiment 2. Second modification of first embodiment 4. Third modification of the first embodiment Second Embodiment 6. 6. First modification of the second embodiment Second modification of second embodiment 8. 8. Application example to electronic equipment Example of use of solid-state imaging device 10. 10. Application example to endoscopic surgery system Application examples for moving objects

<< 1. First embodiment >>
<Configuration example of solid-state imaging device>
A configuration example of a solid-state imaging device that improves charge transfer performance and charge retention performance in each pixel will be described with reference to the block diagram of FIG.

1 includes a control circuit 31, a driver 32, a pixel array 33, a column processing unit 34, and a signal processing unit 35.

The control circuit 31 includes a processor and a memory, and controls the entire operation of the solid-state imaging device 11. The control circuit 31 controls the pixel array 33 and instructs the driver 32 to capture an image.

The driver 32 is controlled by the control circuit 31 and accumulates charges corresponding to incident light for each pixel arranged in the pixel array 33 via the control signal line 43 and the additional wiring 44 for each row. A control signal for controlling an operation related to reading and transfer of charges or resetting is output.

The pixel array 33 is composed of, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like, and pixels 41 that generate pixel signals corresponding to the amount of incident light are arranged in an array. Based on a control signal supplied via the line 43 and the additional wiring 44, operations such as accumulation of pixel signals (charges) of each pixel 41, readout and transfer of pixel signals (charges), or reset are performed in units of rows. Be controlled. Then, the pixel signal read from each pixel 41 of the pixel array 33 in units of rows is output to the column processing unit 34 through the vertical transfer line 45.

The column processing unit 34 sequentially AD (Analog / Digital) converts the pixel signals supplied in units of rows from the pixel array 33 via the vertical transfer lines 45, and transfers the pixel signals in units of rows. To the unit 35.

The signal processing unit 35 is composed of, for example, an LSI (Large Scale Integration) and sequentially accumulates pixel signals supplied from the column processing unit 34, and when an image for one frame is formed, it is demosaiced and synthesized. The general development process is performed and output.

<Configuration Example of Pixel Circuit in First Embodiment>
Next, the configuration of the pixel circuit in the first embodiment in the pixel 41 of the pixel array 33 in FIG. 1 will be described with reference to FIG. In the pixel array 33, an example in which pixels 41 of N rows × M columns are provided is shown, and pixels 41-1-1 to 41-MN are arranged. In the following description, the pixels 41-1-1 to 41 -MN are simply referred to as the pixel 41 when it is not necessary to distinguish between the pixels 41-1-1 to 41 -MN. “The following symbols are omitted.

The pixel circuit constituting the pixel 41 includes, for example, a photodiode (PD) 51 as a photoelectric conversion element. The pixel circuit constituting the pixel 41 includes, for example, a transfer transistor (TG: transfer gate) 52, a reset transistor (RST) 54, in addition to the photodiode 51 and the floating diffusion (FD) 53 that accumulates electric charges. There are four transistors: an amplification transistor (AMP) 55 and a selection transistor (SEL) 56.

In FIG. 2, only the pixel 41-1-1 includes a photodiode 51, a transfer transistor (TG: transfer gate) 52, a floating diffusion (FD) 53, a reset transistor (RST) 54, and an amplification transistor (AMP) 55. And the selection transistor (SEL) 56 are denoted by reference numerals, but the same applies to the other pixels 41, and the reference numerals are omitted.

A transfer signal TG, a reset signal RST, and a selection signal SEL, which are drive signals (control signals) for driving the pixel circuit, are appropriately supplied from the driver 32 to the pixel circuit constituting the pixel 41. That is, the transfer signal TG is applied to the gate electrode of the transfer transistor 52, the reset signal RST is applied to the gate electrode of the reset transistor 54, and the selection signal SEL is applied to the gate electrode of the selection transistor 106. Among these, the transfer signal TG is applied to the gate electrode of the transfer transistor 52 via the switch 42 and the control signal line 43.

The photodiode 51 has an anode electrode connected to a low-potential-side power source (for example, ground), and photoelectrically converts received light (incident light) into photocharge (here, photoelectrons) having a charge amount corresponding to the amount of light. Then, the photocharge is accumulated. The cathode electrode of the photodiode 51 is electrically connected to the gate electrode of the amplification transistor 55 through the transfer transistor 52. A node electrically connected to the gate electrode of the amplification transistor 55 is a floating diffusion / floating diffusion region (FD) portion 53.

The transfer transistor 52 is connected between the cathode electrode of the photodiode 51 and the FD portion 53. A transfer signal TG is supplied from the driver 32 to the gate electrode of the transfer transistor 52 via the switch 42 and the control signal line 43. In response to the transfer signal TG, the transfer transistor 52 becomes conductive, and the photoelectric charge photoelectrically converted by the photodiode 51 is transferred to the FD unit 53.

The reset transistor 54 has a drain electrode connected to a power source (not shown) and a source electrode connected to the FD portion 53. A reset signal RST is supplied from the driver 32 to the gate electrode of the reset transistor 54. In response to the reset signal RST, the reset transistor 54 becomes conductive, and the FD unit 53 is reset by throwing away the charge of the FD unit 53 to the pixel power supply.

The amplification transistor 55 has a gate electrode connected to the FD portion 53 and a drain electrode connected to a power source (not shown). Then, the amplification transistor 55 outputs the potential of the FD unit 53 after being reset by the reset transistor 54 as a reset signal (reset level) Vreset. Further, the amplification transistor 55 outputs the potential of the FD unit 53 after the signal charge is transferred by the transfer transistor 52 as a light accumulation signal (signal level). The pixel value of each pixel 41 is the difference between the light accumulation signal (signal level) and the reset signal (reset level).

The selection transistor 56 has, for example, a drain electrode connected to the source electrode of the amplification transistor 55 and a source electrode connected to the vertical signal line VSL45. A selection signal SEL is supplied from the driver 32 to the gate electrode of the selection transistor 56. In response to the selection signal SEL, the selection transistor 56 becomes conductive, and the signal output from the amplification transistor 55 is read out to the vertical signal line (VSL) 45 with the pixel 41 selected. In FIG. 2, vertical signal lines (VSL) 45-1 to VSL45-M from the first column to the Mth column are shown.

The additional wirings 44 are arranged in the pixel array 33 in the horizontal direction in the same manner as the control signal lines 43 and are capacitively coupled with the control signal lines 43 in each pixel 41 by a capacitor C. Here, the capacitance C is a MOS capacitance, a MIM (Metal-Insulator-Metal) / MOM (Metal-Oxide-Metal) capacitance, a Poly-Poly capacitance (capacitance in which both counter electrodes are made of polysilicon), or a parasitic formed by wiring. An additional capacitor including a capacitor may be used, and it is not necessary that a capacitor circuit such as a capacitor is actually provided. Further, it is desirable that the values of the capacitors C1-1, C1-2,. The switch 42 is, for example, a MOS (Metal （Oxide Semiconductor) transistor switch. In FIG. 2, switches 42-1 to 42-N are provided for the control signal lines 43-1 to 43-N, respectively, and each of the control signal lines 43-1 to 43-N has a capacitance. Combined additional wirings 44-1 to 44-N are provided.

From the pixel circuit that constitutes the pixel 41 of FIG. 2, the potential of the FD portion 53 after reset is the reset level Vreset, and then the potential of the FD portion 53 after transfer of the signal charge is the signal level Vsig in order. VSL) 45.

Here, the selection transistor 56 has a circuit configuration connected between the source electrode of the amplification transistor 55 and the vertical signal line (VSL) 45. However, a pixel power supply (not shown) and a drain electrode of the amplification transistor 55 are not connected. It is also possible to adopt a circuit configuration connected between them.

Further, the pixel circuit constituting the pixel 41 is not limited to the pixel configuration including the above four transistors. For example, a pixel configuration including three transistors in which the amplification transistor 55 has the function of the selection transistor 56, or a pixel configuration in which a transistor after the FD portion 53 is shared between a plurality of photoelectric conversion elements (between pixels). There may be any pixel circuit configuration.

<Operation of Pixel Circuit in FIG. 2>
Next, the operation of the pixel circuit in FIG. 2 will be described with reference to the timing chart in FIG.

In FIG. 3, from the top, the control signal line 43-1 and the additional wiring 44-1, respectively, of the control signal High or Low, the switch 42-1 on (High) or off (Low), and The waveforms of the control signal High or Low in each of the control signal line 43-N and the additional wiring 44-N and the ON (High) or OFF (Low) waveform of the switch 42-N are shown. Also, there are various timings in the pixel signal reading process of the first row from the left, the pixel signal reading process of the N row, the discharge reset process of the pixel signal of the first row, and the discharge reset process of the pixel signal of the N row. It is shown.

First, the reading process of the pixel signal in the first row will be described.

At time t21, the driver 32 controls the switch 42-1 to be on.

Further, at time t1, which is the timing immediately after time t21, the driver 32 sets the control signal of the control signal line 43-1 to high. By this process, the transfer transistor 52 is turned on, and the charge accumulated in the photodiode 51 of the pixel 41-1 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is closed.

At time t22, the driver 32 turns off the switch 42-1 while maintaining the control signal of the control signal line 43-1 in the high state. As a result, the control signal line 43-1 enters a floating state.

At time t11 (= t2), which is the timing immediately after time t22, the control signal for the additional wiring 44-1 is set to high. At this time, since the control signal line 43-1 is in a floating state, the potential of the control signal on the control signal line 43-1 is indicated by the solid circle Za by capacitive coupling with the additional wiring 44-1. Increases by the rising potential ΔV _TGC1r . This rising potential ΔV _TGC1r is expressed by the following equation (1). In the figure, only “Δ” is shown as the rising potential.

ΔV _TGC1r = (C _cuptotal / C _TGCtotal ) ・ V _swing
... (1)

Here, ΔV _TGC1r is the rising potential, C _TGCtotal is the total capacity of the control signal line 43-1, and C _cuptotal is the total capacity between the control signal line 43-1 and the additional wiring 44-1. , V _swing is the amplitude of the control signal of the additional wiring 44-1.

By increasing the potential of the control signal on the control signal line 43-1 by the rising potential ΔV _TGC1r , the charge transfer performance from the photodiode 51 of the pixel 41-1 is improved, and the readout time can be shortened. If the high level of the potential of the control signal on the control signal line 43-1 is lowered, the voltage can be lowered with the same transfer capability.

At time t3 (= t12 = t23), the driver 32 controls the switch 42-1 to be on, and lowers the potentials of the control signals of the control signal line 43-1 and the additional wiring 44-1, thereby reducing the pixel The signal reading process is completed.

Thereafter, the same processing is repeated for the second to Nth lines.

That is, for the Nth row, at time t51, the driver 32 controls the switch 42-N to be turned on.

At time t31, which is the timing immediately after time t51, the driver 32 sets the control signal of the control signal line 43-N to high. By this process, the transfer transistor 52 is turned on, and the charge accumulated in the photodiode 51 is transferred to the FD unit 53.

At time t52, the driver 32 turns off the switch 42-N while maintaining the control signal of the control signal line 43-N in the high state. As a result, the control signal line 43-1 enters a floating state.

At time t41 (= t22), which is the timing immediately after time t52, the driver 32 sets the control signal for the additional wiring 44-N to high. At this time, since the control signal line 43-N is in a floating state, as indicated by a solid circle Zb due to capacitive coupling with the additional wiring 44-N, the control signal line 43-N The potential rises by the rising potential ΔV _TGC1r .

At time t33 (= t42 = t53), the driver 32 controls the switch 42-N to be on. As a result, the control signal potentials of the control signal line 43-N and the additional wiring 44-N become low, and the pixel signal readout process is completed.

Next, the discharge reset process of the pixel signal in the first row will be described.

A reset (shutter) operation is performed by discharging charges from the photodiode 51 so that a signal with a desired accumulation time can be obtained in accordance with the read timing.

At time t4 (= t13), the driver 32 sets the control signal potential of the control signal line 43-1 and the additional wiring 44-1 to high, sets the reset signal RST to the gate electrode of the reset transistor 54, and transfers the transfer transistor. 52 and the reset transistor 54 are turned on to discharge the charge in the photodiode 51.

At time t5, the potential of the control signal on the control signal line 43-1 is set low, the reset signal RST is set low on the gate electrode of the reset transistor 54, and the reset transistor 54 is turned off.

At time t24, the driver 32 controls the switch 42-1 to be turned off. As a result, the control signal line 43-1 enters a floating state.

At time t6 (= t14) immediately after time t24, the driver 32 sets the control signal potentials of the control signal line 43-1 and the additional wiring 44-1 to low.

At this time, since the control signal line 43-1 is in a floating state, the potential drops by a drop potential ΔV _TGC1f due to capacitive coupling as indicated by a solid circle Zc. The drop potential ΔV _TGC1f is expressed by the following equation (2).

ΔV _TGC1f = (C _cuptotal / C _TGCtotal ) ・ V _swing
... (2)

Here, ΔV _TGC1f is the drop potential, C _TGCtotal is the total capacity of the control signal line 43-1, and C _cuptotal is the total capacity between the control signal line 43-1 and the additional wiring 44-1. V _swing is the amplitude of the control signal of the additional wiring 44-1.

The potential of the control signal on the control signal line 43-1 is held until the switch 42-1 is turned on next time.

Thereafter, the same processing is repeated for the second to Nth lines.

That is, in the discharge process of the pixel signal of the Nth row, at time t34 (= t43), the driver 32 sets the control signal potentials of the control signal line 43-N and the additional wiring 44-N to high, and the reset transistor 54 The reset signal RST is set to high at the gate electrode of the first electrode, and the transfer transistor 52 and the reset transistor 54 are turned on to discharge the charge in the photodiode 51.

At time t35, the potential of the control signal on the control signal line 43-1 is set low, the reset signal RST is set low on the gate electrode of the reset transistor 54, and the reset transistor 54 is turned off.

At time t54, the driver 32 controls the switch 42-N to be turned off. As a result, the control signal line 43-N enters a floating state.

At time t36 (= t44) immediately after time t54, the driver 32 sets the control signal potentials of the control signal line 43-N and the additional wiring 44-N to low.

At this time, since the control signal line 43-N is in a floating state, the potential drops by a drop potential ΔV _TGC1f due to capacitive coupling as indicated by a solid circle Zd.

The potential of the control signal on the control signal line 43-N is held until the next time the switch 42-N is turned on.

As a result of the above processing, the potential of the control signal on the control signal line 43-N drops, whereby the amount of charge that can be held in the photodiode 51 is improved, and the saturation characteristics can be improved. In addition, pinning of the surface of the photodiode 51 can be enhanced.

For example, the power supply voltage supplied to the circuit is used as the high voltage of the control signal of the control signal line 43 and the additional wiring 44, and low generally increases the saturation signal amount of the photodiode 51 and dark current. A voltage lower than 0 V (or more) is used for the purpose of suppressing the above.

It should be noted that the pixel signal discharge process is started after the completion of the pixel signal read process for the Nth row, and the pixel signal read process is not necessarily started after the pixel signal discharge process is completed. Depending on the accumulation time, the pixel signal discharge process for the first row is performed during the pixel signal read process for the second and subsequent rows, and the pixel signal read process for the first row during the pixel signal discharge process for the second and subsequent rows. May be performed. Further, the processing order does not necessarily have to be performed in the order of the first row, the second row, the third row,...

<Physical Layout of Pixel Circuit in FIG. 2>
Next, the physical layout of the pixel 41 will be described with reference to FIG. FIG. 4 shows a layout example showing a planar arrangement for two pixels arranged in the horizontal direction of the pixels 41 arranged in an array. Note that the area surrounded by the dotted line is the arrangement of one pixel of the pixel 41. In the figure, only the pixel 41 in the middle left part is given a reference, but the reference is omitted for the other pixels 41. However, each configuration is the same.

In the pixel 41, a photodiode 51 is disposed on the upper right portion, and a selection transistor 56, an amplification transistor 55, and a reset transistor 54 are disposed on the left side from above.

Further, between the photodiode 51 and the reset transistor 54, a transfer transistor 52 and an FD unit 53 are arranged from the photodiode 51 side.

Further, a control signal line 43 connected via the through electrode 71 is arranged on the transfer transistor 52, and an additional wiring 44 is arranged so that a wiring capacitance C is formed.

The left part of FIG. 5 is an AB cross-sectional view of FIG.

As shown in the left part of FIG. 5, each of the control signal line 43 and the additional wiring 44 has a thickness, and the additional capacitance generated between the wirings facing each other forms an inter-wiring capacitance C _cuptotal .

By increasing the inter-wiring capacitance C _cuptotal of the control signal line 43 and the additional wiring 44, it is possible to increase the rising voltage during the pixel signal reading process and the dropping voltage during the pixel signal discharge process.

Further, as shown in the central portion of FIG. 5, the control signal line 43 includes a plurality of control signal lines 43 such as the control signal lines 43-A and 43-B. 71-B may be connected to the transfer transistor 52.

Further, as shown in the right part of FIG. 5, the control signal line 43 and the additional wiring 44 may be laid out so as to be stacked in the vertical direction.

<< 2. First Modification of First Embodiment >>
In the above, an example in which the control signal line 43 and the additional wiring 44 are formed in a straight line has been described. However, the control signal line 43 and the additional wiring 44 are increased by increasing the area where the control signal line 43 and the additional wiring 44 are opposed to each other. The inter-wiring capacitance C _cuptotal of the wiring 44 may be increased.

For example, as shown in FIG. 6, the layout may be such that the area where the control signal line 43 and the additional wiring 44 face each other increases. In other words, in FIG. 6,

convex wirings

43 a and 44 a are formed alternately in the opposing portions of the control signal line 43 and the additional wiring 44, and the control signal line 43 and the additional wiring 44 are opposed to each other. The area to be increased is formed. As a result, the inter-wiring capacitance C _cuptotal of the control signal line 43 and the additional wiring 44 can be increased.

<< 3. Second Modification of First Embodiment >>
In the above description, an example in which the control signal line 43 and the additional wiring 44 are formed one by one has been described, but a plurality of control signal lines 43 and additional wirings 44 may be formed.

That is, for example, as shown in FIG. 7, two additional wirings 44 -A and 44 -B may be formed for one control signal line 43. In FIG. 7, two additional wirings 44-A-1 and 44-B-1 are provided for the control signal line 43-1. Similarly, for the control signal line 43-N, A configuration in the case where two additional wirings 44-AN and 44-BN are provided is shown. By doing so, the inter-wiring capacitance C _cuptotal of the control signal line 43 and the additional wiring 44 can be increased.

Further, as shown in FIG. 7, the driver 32 may be the same for the two additional wirings 44-A and 44-B, or may be operated by different drivers 32 individually. . By providing different drivers 32 for the additional wirings 44-A and 44-B individually, it is possible to increase the operation speed.

Further, in this case, for example, as shown in FIG. 8, the two additional wirings 44-A and 44-B may be laid out in the horizontal direction with the control signal line 43 sandwiched in the horizontal direction. . Further, the two additional wirings 44 -A and 44 -B may be formed on the upper or lower metal wiring layer of the control signal line 43 with the control signal line 43 interposed therebetween. In any case, the inter-wiring capacitance C _cuptotal of the control signal line 43 and the additional wiring 44 can be increased.

<< 4. Third Modification of First Embodiment >>
In the above description, the control signal output via the control signal line 43 and the additional wiring 44 has been described as being controlled by the driver 32 and the switch 42. However, the output stage of the driver 32 is controlled by a PMOS or NMOS. The switch may be controlled by opening / closing a switch made of PMOS or NMOS.

FIG. 9 shows a configuration example of a pixel circuit in which the output stage of the driver 32 is formed by a switch made of PMOS or NMOS.

In FIG. 9, at the end of the control signal line 43 in the driver 32, a switch 91-A made of PMOS or NMOS and connected to a power supply (high potential) and 91 connected to a low potential. -B is formed. Further, at the end of the additional wiring 44, a switch 92-A made of PMOS or NMOS and connected to a power source (high potential) and a switch 92- connected to a low potential in the upper and lower stages in the figure. Each B is formed.

In FIG. 2, the control signal line 43 is brought into a floating state by turning off the switch 42. However, in FIG. 9, instead of the switch 42, the switches 91-A and 91-B are simultaneously turned off. As a result, a floating state is obtained.

In FIG. 9, switches 91-A-1 to 91-AN and 91-B-1 to 91-BN and switches 92-A-1 to An example in which 92-A-N and 92-B-1 to 92-BN are provided is shown.

<< 5. Second embodiment >>
<Configuration Example of Pixel Circuit in Second Embodiment>
In the above description, the configuration in which one FD portion 53 is provided for each pixel has been described. However, a shared pixel configuration in which one FD portion 53 is shared for a plurality of pixels may be employed. .

FIG. 10 shows a configuration example of a pixel circuit having a shared pixel configuration.

In the pixel circuit of FIG. 10, a pixel sharing block 111 in which one FD portion is shared for four pixels is configured. In the drawing, pixel sharing blocks 111-1-1 to 111-M-1 are included. An example of horizontal arrangement is shown. However, in the pixel array 33, the pixel sharing blocks 111 are also arranged in an array.

The pixel sharing block 111 is provided with photodiodes 51-1 to 51-4 and transfer transistors 52-1 to 52-4 for 4 pixels (2 pixels × 2 pixels). In the pixel sharing block 111, one FD section 53 is shared and connected to the configurations of the photodiodes 51-1 to 51-4 and the transfer transistors 52-1 to 52-4 for the four pixels. Has been.

Further, control signal lines 43-1 to 43-4 are connected to the respective gate electrodes of the transfer transistors 52-1 to 52-4, and the control signal lines 43-1 to 43-4 are sandwiched therebetween. In addition, additional wirings 44-1 and 44-2 are arranged.

Here, in FIG. 10, the additional wiring 44-1, the control signal lines 43-1 to 43-4, and the additional wiring 44-2 are arranged in this order from the top in the drawing. Also, the capacitors C1-1-a to C1-1-e,..., And the capacitors C1-Ma to CN-Me between the control signal lines 43 and the additional wirings 44 are all equal. It is desirable to be arranged in.

10 shows an example in which a total of 4 pixels of 2 pixels × 2 pixels share one FD portion 53, the FD portion 53 has a number of pixels 41 other than 4 pixels. You may make it share with.

Further, the FD 53 may be provided for each pixel 41 individually. However, even when the FD 53 is provided individually for each pixel 41, the additional wiring 44-1, the control signal lines 43-1 to 43-4, and the additional wiring 44-2 for four pixels in the vertical direction are provided. In order, they are arranged so that the capacitances between the wirings are all equal.

<Operation of Pixel Circuit in FIG. 10>
Next, the operation of the pixel circuit in FIG. 10 will be described with reference to the timing chart in FIG.

In FIG. 11, the control signal High or Low in each of the additional wiring 44-1 and the control signal line 43-1 from the top, the switch 42-1 on (High) or off (Low), the control signal The control signal High or Low on the line 43-2 and the switch 42-2 on (High) or Off (Low), the control signal High or Low on the control signal line 43-3, and the switch 42-3 on ( High) or off (Low), control signal line 43-4 high or low, and switch 42-4 on (High) or off (Low), and additional wiring 44-2 control signal high Or a low waveform is shown. However, in FIG. 11, only the reference numerals are given on the left side in the figure.

In starting the pixel signal reading process of the photodiode 51-1, the driver 32 controls the switch 42-1 to be on at time t121.

At time t111, which is the timing immediately after time t121, the driver 32 sets the control signal of the control signal line 43-1 to high. By this processing, the transfer transistor 52-1 is turned on, and the electric charge accumulated in the photodiode 51-1 is transferred to the FD unit 53. At this time, the reset signal RST is low, and the reset transistor 54 is off.

At time t122, the driver 32 turns off the switch 42-1 while maintaining the control signal of the control signal line 43-1 in the high state. As a result, the control signal line 43-1 enters a floating state.

At time t101 (= t112), which is the timing immediately after time t122, the driver 32 sets the control signal for the additional wiring 44-1 to high. At this time, since the control signal line 43-1 is in a floating state, the potential of the control signal of the additional wiring 44-1 due to capacitive coupling with the additional wiring 44-1 as indicated by the solid circle Z1. Increases by the rising potential ΔV _TGC1r .

At time t102 (= t113 = t123), the driver 32 sets the control signal of the additional wiring 44-1 to Low, sets the control signal of the control signal line 43-1 to Low, and controls the switch 42-1 to turn on.

The processing so far completes the pixel signal readout processing of the photodiode 51-1.

Next, when starting the pixel signal reading process of the photodiode 51-2, at time t141, the driver 32 controls the switch 42-2 to be turned on.

At time t131, which is the timing immediately after time t141, the driver 32 sets the control signal of the control signal line 43-2 to high. By this processing, the transfer transistor 52-2 is turned on, and the charge accumulated in the photodiode 51-2 is transferred to the FD unit 53. At this time, the reset signal RST is low, and the reset transistor 54 is off.

At time t142, the driver 32 turns off the switch 42-2 while maintaining the control signal of the control signal line 43-2 in the high state. As a result, the control signal line 43-2 enters a floating state.

Then, at time t114 (= t132), which is the timing immediately after time t142, the driver 32 sets the control signal of the control signal line 43-1 to high. At this time, since the control signal line 43-2 is in a floating state, the control signal of the control signal line 43-2 is coupled by capacitive coupling with the control signal line 43-1 as indicated by a solid circle Z2. Increases by the rising potential ΔV _TGC1r .

At time t115 (= t133 = t143), the driver 32 sets the control signal of the control signal line 43-1 to Low, sets the control signal of the control signal line 43-2 to Low, and controls the switch 42-2 to turn on.

The processing so far completes the pixel signal readout processing of the photodiode 51-2.

Further, when starting the reading process of the pixel signal of the photodiode 51-3, at time t161, the driver 32 controls the switch 42-3 to be on.

At time t151, which is the timing immediately after time t161, the driver 32 sets the control signal of the control signal line 43-3 to high. By this processing, the transfer transistor 52-3 is turned on, and the charge accumulated in the photodiode 51-3 is transferred to the FD unit 53. At this time, the reset signal RST is low, and the reset transistor 54 is off.

At time t162, the driver 32 turns off the switch 42-3 while maintaining the control signal of the control signal line 43-3 at the high level. As a result, the control signal line 43-3 enters a floating state.

Then, at time t134 (= t152), which is the timing immediately after time t162, the driver 32 sets the control signal of the control signal line 43-3 to high. At this time, since the control signal line 43-3 is in a floating state, the control signal of the control signal line 43-3 is coupled by capacitive coupling with the control signal line 43-2 as indicated by a solid circle Z3. Increases by the rising potential ΔV _TGC1r .

At time t135 (= t153 = t163), the driver 32 sets the control signal of the control signal line 43-2 to Low, sets the control signal of the control signal line 43-3 to Low, and controls the switch 42-3 to be on.

The processing so far completes the pixel signal readout processing of the photodiode 51-3.

Next, pixel signal readout processing of the photodiode 51-4 will be described.

In starting the pixel signal readout processing of the photodiode 51-4, at time t181, the driver 32 controls the switch 42-4 to be turned on.

Thus, at time t171, which is the timing immediately after time t181, the driver 32 sets the control signal of the control signal line 43-4 to high. By this processing, the transfer transistor 52-4 is turned on, and the charge accumulated in the photodiode 51-4 is transferred to the FD unit 53. At this time, the reset signal RST is low, and the reset transistor 54 is off.

At time t182, the driver 32 turns off the switch 42-4 while maintaining the control signal of the control signal line 43-4 in a high state. As a result, the control signal line 43-4 becomes floating.

At time t154 (= t172), which is the timing immediately after time t182, the driver 32 sets the control signal of the control signal line 43-3 to high. At this time, since the control signal line 43-4 is in a floating state, the control signal of the control signal line 43-4 is coupled by capacitive coupling with the control signal line 43-3 as indicated by a solid circle Z4. Increases by the rising potential ΔV _TGC1r .

At time t155 (= t173 = t183), the driver 32 sets the control signal of the control signal line 43-3 to Low, sets the control signal of the control signal line 43-4 to Low, and controls the switch 42-4 to be on.

The processing so far completes the pixel signal readout processing of the photodiode 51-4.

Next, the pixel signal discharge reset processing of the photodiode 51-1 will be described.

That is, at time t116, the driver 32 controls the control signal of the control signal line 43-1 to high, sets the reset signal RST to high, turns on the transfer transistor 52-1, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-1 is discharged.

At time t117, which is the timing when the discharge of the charge of the photodiode 51-1 is completed, the driver 32 controls the control signal of the control signal line 43-1 to low and sets the reset signal RST to low to transfer the signal. The transistor 52-1 and the reset transistor 54 are turned off.

The processing up to this point ends the pixel signal discharge reset processing of the photodiode 51-1.

Next, the pixel signal discharge reset processing of the photodiode 51-2 will be described.

At time t136, the driver 32 sets the potential of the control signal on the control signal line 43-2 to high, sets the reset signal RST to high, turns on the transfer transistor 52-2, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-2 is discharged.

At time t124, the driver 32 controls the switch 42-1 to be turned off. As a result, the control signal line 43-1 enters a floating state.

At time t137 (= t118), which is the timing when the discharge of the charge of the photodiode 51-2 is completed, the driver 32 controls the control signal of the control signal line 43-2 to low and sets the reset signal RST to low. The transfer transistor 52-2 and the reset transistor 54 are turned off.

At this time, since the control signal line 43-1 is in a floating state, the potential drops by the drop potential ΔV _TGC1f due to capacitive coupling with the control signal line 43-2 as indicated by a solid circle Z11.

The processing up to this point ends the pixel signal discharge reset processing of the photodiode 51-2.

Next, the pixel signal discharge reset processing of the photodiode 51-3 will be described.

At time t156, the driver 32 sets the potential of the control signal on the control signal line 43-3 to high, sets the reset signal RST to high, turns on the transfer transistor 52-3, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-3 is discharged.

At time t144, the driver 32 controls the switch 42-2 to be turned off. Along with this, the control signal line 43-2 enters a floating state.

At time t157 (= t138), which is the timing when the charge discharge of the photodiode 51-3 is completed, the driver 32 controls the control signal of the control signal line 43-3 to be low and sets the reset signal RST to be low. The transfer transistor 52-3 and the reset transistor 54 are turned off.

At this time, since the control signal line 43-2 is in a floating state, the potential drops by a drop potential ΔV _TGC1f due to capacitive coupling with the control signal line 43-3 as indicated by a solid circle Z12.

The potential of the control signal on the control signal line 43-2 is held until the switch 42-2 is turned on next time.

The processing up to this point ends the pixel signal discharge reset processing of the photodiode 51-3.

Next, the pixel signal discharge reset process of the photodiode 51-4 will be described.

At time t174, the driver 32 sets the potential of the control signal on the control signal line 43-4 to high, sets the reset signal RST to high, turns on the transfer transistor 52-4, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-4 is discharged.

At time t164, the driver 32 controls the switch 42-3 to be off. Along with this, the control signal line 43-3 enters a floating state.

At time t175 (= t158), which is the timing when the discharge of the charge of the photodiode 51-4 is completed, the driver 32 controls the control signal of the control signal line 43-4 to low and sets the reset signal RST to low. The transfer transistor 52-4 and the reset transistor 54 are turned off.

At this time, since the control signal line 43-3 is in a floating state, the potential drops by the drop potential ΔV _TGC1f due to capacitive coupling with the control signal line 43-4 as indicated by a solid circle Z13.

The potential of the control signal on the control signal line 43-3 is held until the switch 42-3 is turned on next time.

This completes the pixel signal discharge reset processing of the photodiode 51-4.

Next, processing for lowering the potential of the control signal line 43-4 will be described.

At time t191, the driver 32 sets the potential of the control signal of the additional wiring 44-2 to high.

At time t184, the driver 32 controls the switch 42-4 to be off. As a result, the control signal line 43-4 enters a floating state.

Immediately thereafter, at time t192 (= t176), the driver 32 controls the control signal of the additional wiring 44-2 to be low.

At this time, since the control signal line 43-4 is in a floating state, the potential drops by the drop potential ΔV _TGC1f due to capacitive coupling with the additional wiring 44-2.

The potential of the control signal on the control signal line 43-4 is held until the next time the switch 42-4 is turned on.

Through the processing so far, the potential of the control signal line 43-4 drops by the drop potential ΔV _TGC1f due to capacitive coupling.

By performing capacitive coupling between a plurality of adjacent control signal lines 43 by the above processing, charge transfer performance and performance can be improved in the same manner as when the additional wirings 44 are added with only a few additional wirings 44 added. The charge retention performance can be improved. Further, the manufacturing cost can be reduced by reducing the additional wiring 44. Further, by reducing the number of additional wirings 44, the number of wirings to be controlled is reduced, so that the control load of the control signal can be reduced.

In the above operation, as shown in FIG. 10, the reading process and the discharge reset process are performed in the order of the additional wiring 44-1, the control signal lines 43-1 to 43-4, and the additional wiring 44-2. Although an example in which the additional wiring 44-2 is performed has been described, the additional wiring 44-2, the control signal lines 43-4 to 43-1 and the additional wiring 44-1 may be operated in this order.

In the above-described operation, in the pixel signal reading process, when the pixel signal of the photodiode 51-1 is read, the potential of the control signal line 43-1 is capacitively coupled to the additional wiring 44-1. Is raised by.

When the pixel signal of the photodiode 51-2 is read, when the control signal line 43-2 is in a floating state, the potential is raised by the potential of the capacitively coupled control signal line 43-1. The

Further, when the pixel signal of the photodiode 51-3 is read, when the control signal line 43-3 is in a floating state, its potential is raised by the potential of the capacitively coupled control signal line 43-2. The

Further, when the pixel signal of the photodiode 51-4 is read, when the control signal line 43-3 is in a floating state, its potential is raised by the potential of the capacitively coupled control signal line 43-3. The

Further, in the pixel signal discharge reset process, when the pixel signal of the photodiode 51-1 is discharged, when the control signal line 43-1 is in a floating state, the potential is capacitively coupled to the control signal. It is lowered by the potential of the line 43-2.

In addition, when the pixel signal of the photodiode 51-2 is discharged, when the control signal line 43-2 is in a floating state, the potential is lowered by the potential of the capacitively coupled control signal line 43-3. The

Further, when the pixel signal of the photodiode 51-3 is discharged, when the control signal line 43-3 is in a floating state, its potential is lowered by the potential of the capacitively coupled control signal line 43-4. The

Further, when the pixel signal of the photodiode 51-4 is read, the potential of the control signal line 43-4 is lowered by the potential of the additional wiring 44-2 that is capacitively coupled.

That is, between any of the adjacent control signal lines 43-1 to 43-4, when one of the control signal lines 43 is in a floating state, the other control signal line 43 has a low or high control signal. 2 to function as the additional wiring 44 in the pixel circuit configuration of FIG. 2, increase or decrease the potential of one control signal line 43, and improve the pixel transfer performance or the pixel holding performance. Can be considered.

Further, the number of control signal lines 43-1 to 43-4 may be other than this, but when a plurality of control signal lines 43 are arranged, a plurality of control signal lines arranged adjacent to each other. In order to unify all the potentials of 43, the additional wiring 44 is arranged at the end of the plurality of control signal lines 43, and is processed first or last in the above-described operation.

As a result, by configuring a plurality of adjacent control signal lines 43, any wiring between the control signal lines 43 functions as the additional wiring 44, thereby reducing the number of additional wirings 44 to be added. Therefore, it becomes possible to reduce the manufacturing cost and the control load.

<Physical Layout of Shared Pixel Block in FIG. 10>
Next, a physical layout of the shared pixel block in FIG. 10 will be described with reference to FIG. FIG. 11 shows a layout example showing a planar arrangement of the pixel sharing block 111 of FIG.

In the pixel sharing block 111, photodiodes 51-1 to 51-4 are arranged for 2 pixels × 2 pixels in the horizontal direction × vertical direction. An FD portion 53 is disposed at the center position of the photodiodes 51-1 to 51-4. Further, transfer transistors 52-1 to 52-4 are arranged between the FD portion 53 and the photodiodes 51-1 to 51-4, respectively. Further, a reset transistor 54, an amplification transistor 55, and a selection transistor 56 are arranged below the photodiodes 51-1 to 51-4 from the left in the drawing.

Further, in the region where the photodiodes 51-1 to 51-4 are arranged, the additional wiring 44-1 and the control signal line 43-1 are arranged from the top in the figure so as to straddle the pixel sharing block 111 adjacent in the horizontal direction. Through 43-4 and additional wiring 44-2 are arranged. Here, the additional wiring 44-1, the control signal lines 43-1 to 43-4, and the additional wiring 44-2 may be arranged such that the capacitances between the respective control signal lines are all equal. desirable.

Further, the control signal lines 43-1 to 43-4 are connected to the transfer transistors 52-1 to 52-4 via the through electrodes 71-1 to 71-4, respectively.

As described above, by capacitively coupling the plurality of control signal lines 43 to each other, it is possible to reduce the additional wiring while improving the charge transfer performance and the charge retention performance, and thus it is possible to reduce the manufacturing cost. It becomes. That is, when one additional wiring 44 is required for one control signal line 43, the cost can be realized without reducing the line / space (ratio of the wiring area to the space) or increasing the total number of wirings. Can be reduced. Further, since the number of additional wirings is reduced, the control signal for controlling the additional wirings 44 can be reduced, so that the load related to the control can be reduced.

For example, if the plurality of control signal lines 43 are not capacitively coupled to each other, additional wiring 44 is required for each of the four control signal lines 43 required for each of the four pixels, and control is performed with four pixels. Four signal lines 43 are required, and at least four additional wirings 44 are required. On the other hand, when the plurality of control signal lines 43 are mutually capacitively coupled, even if the number of control signal lines 43 is four, it is possible to use only two additional wirings 44. As a result, the manufacturing cost can be reduced and the pixel circuit can be controlled with fewer control signals.

<< 6. First Modification of Second Embodiment >>
In the above, since the additional wirings 44-1 and 44-2 are provided, the potential of the control signal line 43 is increased in the pixel signal reading process, thereby improving the charge transfer performance and the pixel signal. In the discharge process, the example in which the charge transfer performance is improved and the saturation performance and the pinning performance are improved by lowering the potential of the control signal line 43 has been described.

However, the additional wirings 44-1 and 44-2 may be configured so that only one of them is provided, and the potential of the control signal line 43 can be increased or decreased.

FIG. 13 shows a configuration example of the pixel circuit of the pixel sharing block 111 when only the additional wiring 44-1 of FIG. 10 is provided for the pixel sharing block 111.

With the configuration of the pixel sharing block 111 in FIG. 13, it is only necessary to provide the additional wiring 44-1 for a plurality of rows, so that it is possible to reduce the manufacturing cost while improving the charge transfer performance as the voltage increases. Is possible. Further, since only the additional wiring 44-1 needs to be controlled, the control load can be reduced.

<Operation of Pixel Circuit in FIG. 13>
Next, the operation of the pixel circuit in FIG. 13 will be described with reference to the timing chart in FIG.

At time t211, the driver 32 sets the control signal of the control signal line 43-1 to high. By this processing, the transfer transistor 52-1 is turned on, and the electric charge accumulated in the photodiode 51-1 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is in an off state.

At time t221, the driver 32 turns off the switch 42-1 while maintaining the control signal of the control signal line 43-1 in the high state. As a result, the control signal line 43-1 enters a floating state.

At time t201 (= t212), which is the timing immediately after time t221, the driver 32 sets the control signal for the additional wiring 44-1 to high. At this time, since the control signal line 43-1 is in a floating state, as indicated by a solid circle Z21, the control signal line 43-1 is controlled by capacitive coupling with the additional wiring 44-1. The potential rises by the rising potential ΔV _TGC1r .

At time t202 (= t213 = t222), the driver 32 sets the control signal of the additional wiring 44-1 to Low, sets the control signal of the control signal line 43-1 to Low, and controls the switch 42-1 to turn on.

Next, when starting the reading process of the pixel signal of the photodiode 51-2, at time t231, the driver 32 sets the control signal of the control signal line 43-2 to high. By this processing, the transfer transistor 52-2 is turned on, and the charge accumulated in the photodiode 51-2 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is in an off state.

At time t241, the driver 32 turns off the switch 42-2 while maintaining the control signal of the control signal line 43-2 in the high state. As a result, the control signal line 43-2 enters a floating state.

Then, at time t214 (= t232), which is the timing immediately after time t241, the driver 32 sets the control signal of the control signal line 43-1 to high. At this time, since the control signal line 43-2 is in a floating state, the control signal of the control signal line 43-2 is coupled by capacitive coupling with the control signal line 43-1 as indicated by a solid circle Z22. Increases by the rising potential ΔV _TGC1r .

At time t215 (= t233 = t242), the driver 32 controls the control signal line 43-1 to be low, the control signal line 43-2 to be low, and the switch 42-2 to be turned on.

Furthermore, when starting the reading process of the pixel signal of the photodiode 51-3, at time t251, the driver 32 sets the control signal of the control signal line 43-3 to high. By this processing, the transfer transistor 52-3 is turned on, and the charge accumulated in the photodiode 51-3 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is in an off state.

At time t261, the driver 32 turns off the switch 42-3 while maintaining the control signal of the control signal line 43-3 in the high state. As a result, the control signal line 43-3 enters a floating state.

At time t234 (= t252), which is the timing immediately after time t261, the driver 32 sets the control signal of the control signal line 43-2 to high. At this time, since the control signal line 43-3 is in a floating state, the potential of the control signal on the control signal line 43-3 rises by the rising potential ΔV _TGC1r due to capacitive coupling with the control signal line 43-2.

At time t235 (= t253 = t262), the driver 32 sets the control signal of the control signal line 43-2 to low, sets the control signal of the control signal line 43-3 to low, and controls the switch 42-3 to be on.

Next, pixel signal readout processing of the photodiode 51-4 will be described.

In starting the pixel signal reading process of the photodiode 51-4, at time t271, the driver 32 sets the control signal of the control signal line 43-4 to high. By this processing, the transfer transistor 52-4 is turned on, and the charge accumulated in the photodiode 51-4 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is in an off state.

At time t281, the driver 32 turns off the switch 42-4 while maintaining the control signal of the control signal line 43-4 in the high state. As a result, the control signal line 43-4 enters a floating state.

At time t254 (= t272), which is the timing immediately after time t281, the driver 32 sets the control signal of the control signal line 43-3 to high. At this time, since the control signal line 43-4 is in a floating state, the potential of the control signal on the control signal line 43-4 rises by the rising potential ΔV _TGC1r due to capacitive coupling with the control signal line 43-3.

At time t255 (= t273 = t282), the driver 32 sets the control signal of the control signal line 43-3 to Low, sets the control signal of the control signal line 43-4 to Low, and controls the switch 42-4 to be on.

At time t216, the driver 32 controls the control signal line 43-1 to high, sets the reset signal RST to high, turns on the transfer transistor 52-1, and turns on the reset transistor 54. Then, the charge of the photodiode 51-1 is discharged.

At time t217, which is the timing when the charge discharge of the photodiode 51-1 is completed, the driver 32 controls the control signal of the control signal line 43-1 to be low and the reset signal RST to be low, thereby transferring the transfer transistor. While turning off 52-1 and turning off the reset transistor 54, the pixel signal discharge reset of the photodiode 51-1 is completed.

At time t236, the driver 32 sets the potential of the control signal on the control signal line 43-2 to high, sets the reset signal RST to high, turns on the transfer transistor 52-2, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-2 is discharged.

At time t237, which is the timing when the discharge of the charge of the photodiode 51-2 is completed, the driver 32 controls the control signal line 43-2 to low and sets the reset signal RST to low, thereby transferring the transfer transistor 52. -2 and reset transistor 54 are turned off.

At time t256, the driver 32 sets the potential of the control signal on the control signal line 43-3 to high, sets the reset signal RST to high, turns on the transfer transistor 52-3, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-3 is discharged.

At time t257, which is the timing when the discharge of the charge of the photodiode 51-3 is completed, the driver 32 controls the control signal of the control signal line 43-3 to be low and sets the reset signal RST to be low, thereby transferring the transfer transistor 52. -3 and reset transistor 54 are turned off.

Next, the pixel signal discharge set processing of the photodiode 51-4 will be described.

At time t274, the driver 32 sets the potential of the control signal on the control signal line 43-4 to high, sets the reset signal RST to high, turns on the transfer transistor 52-4, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-4 is discharged.

At time t275 when the charge discharge of the photodiode 51-4 is completed, the driver 32 controls the control signal of the control signal line 43-4 to low and sets the reset signal RST to low, thereby transferring the transfer transistor 52. -4 and reset transistor 54 are turned off.

That is, in the pixel signal discharge reset processing of the photodiodes 51-1 to 51-4, since the additional wiring 44-2 does not exist, the processing for potential drop in the processing described with reference to FIG. 11 is omitted. It becomes the operation.

Since the above processing results in a configuration in which a plurality of control signal lines are capacitively coupled, in the pixel signal readout processing, by increasing the potential, the charge transfer performance is improved and additional wiring is provided for each row. Since the number of additional wirings to be added can be reduced as compared with the configuration to be added, the manufacturing cost can be reduced. Further, since the load related to the control can be reduced by reducing the number of additional wirings, it is possible to control an imaging circuit of an equivalent scale with a smaller number of control signals.

<< 7. Second Modification of Second Embodiment >>
In the above, the configuration example of the pixel sharing block 111 when only the additional wiring 44-1 is provided for the pixel sharing block 111 has been described. However, only the additional wiring 44-2 is provided, and the control is performed. A configuration in which only a potential drop of the signal line 43 can be realized may be employed.

FIG. 15 shows a configuration example of the pixel circuit of the pixel sharing block 111 when only the additional wiring 44-2 of FIG. 10 is provided for the pixel sharing block 111.

With the configuration of the pixel sharing block 111 in FIG. 15, it is only necessary to realize capacitive coupling between the plurality of control signal lines 43 and to provide only the additional wiring 44-2, so that the manufacturing cost can be reduced. Become. Further, since only the additional wiring 44-2 needs to be controlled, the control load can be reduced.

<Operation of Pixel Circuit in FIG. 16>
Next, the operation of the pixel circuit in FIG. 15 will be described with reference to the timing chart in FIG.

In starting the pixel signal reading process of the photodiode 51-1, at time t311, the driver 32 controls the switch 42-1 to be turned on.

At time t301, which is the timing immediately after time t311, the driver 32 sets the control signal of the control signal line 43-1 to high. By this processing, the transfer transistor 52-1 is turned on, and the electric charge accumulated in the photodiode 51-1 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is in an off state.

At time t312, the driver 32 sets the control signal of the control signal line 43-1 to Low.

Next, when starting the pixel signal reading process of the photodiode 51-2, at time t331, the driver 32 controls the switch 42-2 to be turned on.

At time t321, which is the timing immediately after time t331, the driver 32 sets the control signal of the control signal line 43-2 to high. By this processing, the transfer transistor 52-2 is turned on, and the charge accumulated in the photodiode 51-2 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is in an off state.

At time t322, the driver 32 sets the control signal of the control signal line 43-1 to Low.

Furthermore, when starting the pixel signal reading process of the photodiode 51-3, at time t351, the driver 32 controls the switch 42-3 to be turned on.

At time t341, which is the timing immediately after time t351, the driver 32 sets the control signal of the control signal line 43-3 to high. By this processing, the transfer transistor 52-3 is turned on, and the charge accumulated in the photodiode 51-3 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is in an off state.

At time t342, the driver 32 sets the control signal of the control signal line 43-3 to Low.

Next, pixel signal readout processing of the photodiode 51-4 will be described.

In starting the pixel signal reading process of the photodiode 51-4, at time t371, the driver 32 controls the switch 42-4 to be turned on.

At time t361, which is the timing immediately after time t371, the driver 32 sets the control signal of the control signal line 43-4 to high. By this processing, the transfer transistor 52-4 is turned on, and the charge accumulated in the photodiode 51-4 is transferred to the FD unit 53. Here, the reset signal RST is low, and the reset transistor 54 is in an off state.

At time t362, the driver 32 sets the control signal of the control signal line 43-4 to Low.

That is, the readout process of the photodiodes 51-1 to 51-4 is a process in which the process for increasing the voltage is omitted because the additional wiring 44-1 is not provided in the case of FIG.

That is, at time t303, the driver 32 controls the control signal line 43-1 to high, sets the reset signal RST to high, turns on the transfer transistor 52-1, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-1 is discharged.

At time t304, which is the timing when the discharge of the photodiode 51-1 is completed, the driver 32 controls the control signal of the control signal line 43-1 to be low and sets the reset signal RST to be low, thereby transferring the transfer transistor 52. -1 and reset transistor 54 are turned off.

At time t323, the driver 32 sets the control signal potential of the control signal line 43-2 to high, sets the reset signal RST to high, turns on the transfer transistor 52-2, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-2 is discharged.

At time t312, the driver 32 controls the switch 42-1 to be turned off. As a result, the control signal line 43-1 enters a floating state.

At time t324 (= t305), which is the timing when the charge discharge of the photodiode 51-2 is completed, the driver 32 controls the control signal of the control signal line 43-2 to low and sets the reset signal RST to low. Then, the transfer transistor 52-2 and the reset transistor 54 are turned off.

At this time, since the control signal line 43-1 is in a floating state, the potential drops by the drop potential ΔV _TGC1f due to capacitive coupling with the control signal line 43-2, as indicated by a solid circle Z31.

At time t343, the driver 32 sets the potential of the control signal on the control signal line 43-3 to high, sets the reset signal RST to high, turns on the transfer transistor 52-3, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-3 is discharged.

At time t332, the driver 32 controls the switch 42-2 to be turned off. Along with this, the control signal line 43-2 enters a floating state.

At time t344 (= t325), which is the timing when the charge discharge of the photodiode 51-2 is completed, the driver 32 controls the control signal of the control signal line 43-3 to be low and sets the reset signal RST to be low. Then, the transfer transistor 52-3 and the reset transistor 54 are turned off.

At this time, since the control signal line 43-2 is in a floating state, the potential drops by the drop potential ΔV _TGC1f due to capacitive coupling with the control signal line 43-3 as indicated by a solid circle Z32.

At time t363, the driver 32 sets the potential of the control signal on the control signal line 43-4 to high, sets the reset signal RST to high, turns on the transfer transistor 52-4, and turns on the reset transistor 54. Thus, the charge of the photodiode 51-4 is discharged.

At time t352, the driver 32 controls the switch 42-3 to be turned off. Along with this, the control signal line 43-3 enters a floating state.

At time t364 (= t345), which is the timing when the charge discharge of the photodiode 51-4 is completed, the driver 32 controls the control signal of the control signal line 43-4 to low and sets the reset signal RST to low. Then, the transfer transistor 52-4 and the reset transistor 54 are turned off.

At this time, since the control signal line 43-3 is floating, the potential drops by the drop potential ΔV _TGC1f due to capacitive coupling with the control signal line 43-4 as indicated by a solid circle Z33.

At time t381, the driver 32 sets the potential of the control signal of the additional wiring 44-2 to high.

At time t372, the driver 32 controls the switch 42-4 to be off. As a result, the control signal line 43-4 enters a floating state.

Immediately thereafter, at time t382 (= t365), the driver 32 controls the control signals of the control signal line 43-4 and the additional wiring 44-2 to low.

At this time, since the control signal line 43-4 is in a floating state, the potential drops by the drop potential ΔV _TGC1f due to capacitive coupling with the additional wiring 44-2 as indicated by a solid circle Z34.

By the above processing, the control signal lines 43 are capacitively coupled to each other, and only the additional wiring 44-2 is added. Therefore, the control signal to be added rather than the configuration in which the control signal line is added to each row. The number of lines can be reduced, and the manufacturing cost can be reduced. Further, by reducing the number of control signal lines to be added, it is possible to reduce the load related to the control. Therefore, it is possible to control image pickup circuits of the same scale with a smaller number of control signals.

<< 8. Application example to electronic equipment >>
The above-described solid-state imaging device 11 of FIG. 1 is applied to various electronic devices such as an imaging device such as a digital still camera and a digital video camera, a mobile phone having an imaging function, or other devices having an imaging function. can do.

FIG. 17 is a block diagram illustrating a configuration example of an imaging apparatus as an electronic apparatus to which the present technology is applied.

An imaging device 501 shown in FIG. 17 includes an optical system 502, a shutter device 503, a solid-state imaging device 504, a driving circuit 505, a signal processing circuit 506, a monitor 507, and a memory 508, and displays a still image and a moving image. Imaging is possible.

The optical system 502 includes one or a plurality of lenses, guides light (incident light) from the subject to the solid-state image sensor 504, and forms an image on the light-receiving surface of the solid-state image sensor 504.

The shutter device 503 is disposed between the optical system 502 and the solid-state imaging device 504, and controls the light irradiation period and the light-shielding period to the solid-state imaging device 504 according to the control of the drive circuit 1005.

The solid-state image sensor 504 is configured by a package including the above-described solid-state image sensor. The solid-state imaging device 504 accumulates signal charges for a certain period in accordance with light imaged on the light receiving surface via the optical system 502 and the shutter device 503. The signal charge accumulated in the solid-state image sensor 504 is transferred according to a drive signal (timing signal) supplied from the drive circuit 505.

The drive circuit 505 outputs a drive signal for controlling the transfer operation of the solid-state image sensor 504 and the shutter operation of the shutter device 503 to drive the solid-state image sensor 504 and the shutter device 503.

The signal processing circuit 506 performs various types of signal processing on the signal charges output from the solid-state imaging device 504. An image (image data) obtained by the signal processing by the signal processing circuit 506 is supplied to the monitor 507 and displayed, or supplied to the memory 508 and stored (recorded).

Also in the imaging apparatus 501 configured as described above, the apparatus configuration can be reduced in size and height by applying the solid-state imaging apparatus 11 of FIG. 1 instead of the optical system 502 and the solid-state imaging element 504 described above. It is possible to suppress ghost and flare caused by internal reflection while realizing the above.
<< 9. Example of use of solid-state imaging device >>

FIG. 18 is a diagram illustrating a usage example in which the solid-state imaging device 11 described above is used.

The solid-state imaging device 11 described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.

・ Devices for taking images for viewing, such as digital cameras and mobile devices with camera functions ・ For safe driving such as automatic stop and recognition of the driver's condition, Devices used for traffic, such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc. Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ・ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc. Equipment used for medical and health care ・ Security equipment such as security surveillance cameras and personal authentication cameras ・ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports-Equipment used for sports such as action cameras and wearable cameras for sports applications-Used for agriculture such as cameras for monitoring the condition of fields and crops apparatus

<< 10. Application example to endoscopic surgery system >>
The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

FIG. 19 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology (present technology) according to the present disclosure can be applied.

FIG. 19 shows a state where an operator (doctor) 11131 is performing an operation on a patient 11132 on a patient bed 11133 using an endoscopic operation system 11000. As shown in the figure, an endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, and a support arm device 11120 that supports the endoscope 11100. And a cart 11200 on which various devices for endoscopic surgery are mounted.

The endoscope 11100 includes a lens barrel 11101 in which a region having a predetermined length from the distal end is inserted into the body cavity of the patient 11132, and a camera head 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, an endoscope 11100 configured as a so-called rigid mirror having a rigid lens barrel 11101 is illustrated, but the endoscope 11100 may be configured as a so-called flexible mirror having a flexible lens barrel. Good.

An opening into which the objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101. Irradiation is performed toward the observation target in the body cavity of the patient 11132 through the lens. Note that the endoscope 11100 may be a direct endoscope, a perspective mirror, or a side endoscope.

An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from the observation target is condensed on the image sensor by the optical system. Observation light is photoelectrically converted by the imaging element, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image is generated. The image signal is transmitted to a camera control unit (CCU: Camera Control Unit) 11201 as RAW data.

The CCU 11201 is configured by a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and the like, and comprehensively controls operations of the endoscope 11100 and the display device 11202. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs various kinds of image processing for displaying an image based on the image signal, such as development processing (demosaic processing), for example.

The display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 under the control of the CCU 11201.

The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), for example, and supplies irradiation light to the endoscope 11100 when photographing a surgical site or the like.

The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) by the endoscope 11100.

The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for tissue ablation, incision, blood vessel sealing, or the like. In order to inflate the body cavity of the patient 11132 for the purpose of securing the field of view by the endoscope 11100 and securing the operator's work space, the pneumoperitoneum device 11206 passes gas into the body cavity via the insufflation tube 11111. Send in. The recorder 11207 is an apparatus capable of recording various types of information related to surgery. The printer 11208 is a device that can print various types of information related to surgery in various formats such as text, images, or graphs.

In addition, the light source device 11203 that supplies the irradiation light when the surgical site is imaged to the endoscope 11100 can be configured by, for example, a white light source configured by an LED, a laser light source, or a combination thereof. When a white light source is configured by a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy. Therefore, the light source device 11203 adjusts the white balance of the captured image. It can be carried out. In this case, laser light from each of the RGB laser light sources is irradiated on the observation target in a time-sharing manner, and the drive of the image sensor of the camera head 11102 is controlled in synchronization with the irradiation timing, thereby corresponding to each RGB. It is also possible to take a time-division image. According to this method, a color image can be obtained without providing a color filter in the image sensor.

Further, the driving of the light source device 11203 may be controlled so as to change the intensity of the output light every predetermined time. Synchronously with the timing of changing the intensity of the light, the drive of the image sensor of the camera head 11102 is controlled to acquire an image in a time-sharing manner, and the image is synthesized, so that high dynamic without so-called blackout and overexposure A range image can be generated.

Further, the light source device 11203 may be configured to be able to supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue, the surface of the mucous membrane is irradiated by irradiating light in a narrow band compared to irradiation light (ie, white light) during normal observation. A so-called narrow band imaging is performed in which a predetermined tissue such as a blood vessel is imaged with high contrast. Alternatively, in special light observation, fluorescence observation may be performed in which an image is obtained by fluorescence generated by irradiating excitation light. In fluorescence observation, the body tissue is irradiated with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally administered to the body tissue and applied to the body tissue. It is possible to obtain a fluorescence image by irradiating excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to be able to supply narrowband light and / or excitation light corresponding to such special light observation.

FIG. 20 is a block diagram illustrating an example of functional configurations of the camera head 11102 and the CCU 11201 illustrated in FIG.

The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light taken from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

The imaging unit 11402 includes an imaging element. One (so-called single plate type) image sensor may be included in the imaging unit 11402, or a plurality (so-called multi-plate type) may be used. In the case where the imaging unit 11402 is configured as a multi-plate type, for example, image signals corresponding to RGB may be generated by each imaging element, and a color image may be obtained by combining them. Alternatively, the imaging unit 11402 may be configured to include a pair of imaging elements for acquiring right-eye and left-eye image signals corresponding to 3D (Dimensional) display. By performing the 3D display, the operator 11131 can more accurately grasp the depth of the living tissue in the surgical site. Note that in the case where the imaging unit 11402 is configured as a multi-plate type, a plurality of lens units 11401 can be provided corresponding to each imaging element.

Further, the imaging unit 11402 is not necessarily provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.

The driving unit 11403 is configured by an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. Thereby, the magnification and the focus of the image captured by the imaging unit 11402 can be adjusted as appropriate.

The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

Further, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes, for example, information for designating the frame rate of the captured image, information for designating the exposure value at the time of imaging, and / or information for designating the magnification and focus of the captured image. Contains information about the condition.

Note that the imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. Good. In the latter case, a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function are mounted on the endoscope 11100.

The camera head control unit 11405 controls driving of the camera head 11102 based on a control signal from the CCU 11201 received via the communication unit 11404.

The communication unit 11411 is configured by a communication device for transmitting and receiving various types of information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

The image processing unit 11412 performs various types of image processing on the image signal that is RAW data transmitted from the camera head 11102.

The control unit 11413 performs various types of control related to imaging of the surgical site by the endoscope 11100 and display of a captured image obtained by imaging of the surgical site. For example, the control unit 11413 generates a control signal for controlling driving of the camera head 11102.

Further, the control unit 11413 causes the display device 11202 to display a picked-up image showing the surgical part or the like based on the image signal subjected to the image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 detects surgical tools such as forceps, specific biological parts, bleeding, mist when using the energy treatment tool 11112, and the like by detecting the shape and color of the edge of the object included in the captured image. Can be recognized. When displaying the captured image on the display device 11202, the control unit 11413 may display various types of surgery support information superimposed on the image of the surgical unit using the recognition result. Surgery support information is displayed in a superimposed manner and presented to the operator 11131, thereby reducing the burden on the operator 11131 and allowing the operator 11131 to proceed with surgery reliably.

The transmission cable 11400 for connecting the camera head 11102 and the CCU 11201 is an electric signal cable corresponding to electric signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.

Here, in the illustrated example, communication is performed by wire using the transmission cable 11400. However, communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

In the foregoing, an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described. Among the configurations described above, the technology according to the present disclosure can be applied to, for example, the endoscope 11100, the camera head 11102 (the imaging unit 11402), the CCU 11201 (the image processing unit 11412), and the like. Specifically, for example, the solid-state imaging device 11 of FIG. 1 can be applied to the lens unit 11401 and the imaging unit 10402. By applying the technology according to the present disclosure to the lens unit 11401 and the imaging unit 10402, the charge transfer capability and the charge retention capability can be improved.

Note that although an endoscopic surgery system has been described here as an example, the technology according to the present disclosure may be applied to, for example, a microscope surgery system and the like.

<< 11. Application example to mobile objects >>
The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device that is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. May be.

FIG. 21 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example illustrated in FIG. 21, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. As a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp. In this case, the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.

The vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.

The vehicle interior information detection unit 12040 detects vehicle interior information. For example, a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.

The microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, following traveling based on inter-vehicle distance, vehicle speed maintaining traveling, vehicle collision warning, or vehicle lane departure warning. It is possible to perform cooperative control for the purpose.

Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.

The sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle. In the example of FIG. 21, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

FIG. 22 is a diagram illustrating an example of an installation position of the imaging unit 12031.

In FIG. 22, the vehicle 12100 includes

imaging units

12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

The

imaging units

12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The

imaging units

12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100. The imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100. The forward images acquired by the

imaging units

12101 and 12105 are mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

FIG. 22 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the

imaging units

12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer 12051, based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100). In particular, it is possible to extract, as a preceding vehicle, a three-dimensional object that travels at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100, particularly the closest three-dimensional object on the traveling path of the vehicle 12100 it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.

For example, the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to be superimposed and displayed. Moreover, the audio | voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.

Heretofore, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. Of the configurations described above, the technology according to the present disclosure may be applied to the imaging unit 12031, for example. Specifically, for example, the solid-state imaging device 11 in FIG. 1 can be applied to the imaging unit 12031. By applying the technique according to the present disclosure to the imaging unit 12031, it is possible to improve the charge transfer capability and the charge retention capability.

In addition, this indication can also take the following structures.
<1> a transfer gate that transfers a pixel signal from a pixel that generates a pixel signal corresponding to the amount of incident light by photoelectric conversion;
A floating mechanism for floating a control signal line for supplying a control signal for controlling opening and closing of the transfer gate; and
A solid-state imaging device comprising: an additional wiring that is capacitively coupled to the control signal line.
<2> The floating mechanism unit is a switch provided between the control signal line and a driver that generates the control signal. When the switch is turned off, the control signal line is in a floating state. The solid-state imaging device according to <1>.
<3> When the output stage in the driver that generates the control signal includes a switch on the power supply side and a switch on the ground side with respect to the control signal line, the floating mechanism unit is configured to switch the power supply side. And the ground-side switch is turned off, whereby the control signal line is brought into a floating state. <1>.
<4> The solid-state imaging device according to <1>, wherein a plurality of the additional wirings are capacity-coupled to one control signal line.
<5> The solid-state imaging device according to <1>, wherein one or two additional wirings are capacitively coupled to the plurality of control signal lines.
<6> The additional wiring is arranged in parallel with the control signal line on the same plane as the control signal line, which is orthogonal to the incident direction of the incident light. Solid-state imaging device.
<7> The solid line according to <1>, wherein the additional wiring is arranged in parallel to the control signal line at least one of a front stage and a rear stage of the control signal line with respect to an incident direction of the incident light. Imaging device.
<8> The solid-state imaging device according to <1>, wherein the additional wiring is an independent wiring that is capacitively coupled to the control signal line and is different from the control signal line.
<9> The additional wiring is an independent wiring that is capacitively coupled to the control signal line and is different from the control signal line, and another control signal line that is capacitively coupled to the control signal line. <1> The solid-state imaging device described in 1.
<10> The potential of the control signal line controlled to be in a floating state by the floating mechanism section is increased according to a signal supplied to the additional wiring that is capacitively coupled to the control signal line in the floating state, or The solid-state imaging device according to <9>.
<11> The control signal line that is capacitively coupled to the additional wiring composed of the independent wiring is first controlled to be in a floating state by the floating mechanism unit, and the potential is set according to a signal supplied to the additional wiring. The solid-state imaging device according to <10>.
<12> The control signal line that is capacitively coupled to the additional wiring composed of the independent wiring is finally controlled to be in a floating state by the floating mechanism unit, and the potential is changed according to a signal supplied to the additional wiring. The solid-state imaging device according to <10>.
<13> The solid-state imaging device according to <9>, wherein a capacity for coupling the adjacent additional wiring and the control signal line and a capacity for coupling the control signal lines are substantially equal.
<14> The capacity for coupling the control signal line and the additional wiring is an additional capacity. The solid-state imaging device according to <1>.
<15> The solid-state imaging device according to <14>, wherein the additional capacitor is a parasitic capacitor.
<16> The solid-state imaging device according to <14>, wherein the additional capacitor is a MOS (Metal Oxide Semiconductor) capacitor.
<17> The solid-state imaging device according to <14>, wherein the additional capacitor is a MIM (Metal Insulator Metal) / MOM (Metal Oxide Metal) capacitor.
<18> The solid-state imaging device according to <14>, wherein the additional capacitor is a capacitor in which both counter electrodes are formed of polysilicon.
<19> a transfer gate that transfers a pixel signal from a pixel that generates a pixel signal corresponding to the amount of incident light by photoelectric conversion;
A floating mechanism for floating a control signal line for supplying a control signal for controlling opening and closing of the transfer gate; and
An imaging apparatus comprising: an additional wiring that is capacitively coupled to the control signal line.
<20> a transfer gate that transfers a pixel signal from a pixel that generates a pixel signal corresponding to the amount of incident light by photoelectric conversion;
A floating mechanism for floating a control signal line for supplying a control signal for controlling opening and closing of the transfer gate; and
An electronic device comprising: an additional wiring that is capacitively coupled to the control signal line.

11 imaging device, 31 control circuit, 32 driver, 33 pixel array, 34 column processing unit, 35 signal processing unit, 41 pixel, 42, 42-1-1 to 42-MN switch, 43, 43-1 to 43 -4 Control signal line, 44, 44-1, 44-2 additional wiring, 45, 45-1 to 45-M VSL, 51 photodiode, 52 transfer transistor, 53 FD section, 54 reset transistor, 55 amplification transistor, 56 Select transistor, 71, 71-1 to 71-4 through electrode, 111, 111-1-1 to 111-MN shared pixel block

Claims

A transfer gate that transfers a pixel signal from a pixel that generates a pixel signal corresponding to the amount of incident light by photoelectric conversion;
A floating mechanism for floating a control signal line for supplying a control signal for controlling opening and closing of the transfer gate; and
A solid-state imaging device comprising: an additional wiring that is capacitively coupled to the control signal line.
The floating mechanism unit is a switch provided between the control signal line and a driver that generates the control signal, and the control signal line is brought into a floating state when the switch is turned off. Item 2. The solid-state imaging device according to Item 1.
When the output stage in the driver that generates the control signal is composed of a switch on the power supply side and a switch on the ground side with respect to the control signal line, the floating mechanism unit, the switch on the power supply side, The solid-state imaging device according to claim 1, wherein the control signal line is brought into a floating state by turning off both of the switches on the ground side.
The solid-state imaging device according to claim 1, wherein a plurality of the additional wirings are capacitively coupled to one control signal line.
The solid-state imaging device according to claim 1, wherein one or two additional wirings are capacitively coupled to the plurality of control signal lines.
The solid-state imaging device according to claim 1, wherein the additional wiring is arranged in parallel with the control signal line on the same plane as the control signal line that is orthogonal to the incident direction of the incident light. .
The solid-state imaging device according to claim 1, wherein the additional wiring is arranged in parallel to the control signal line at least one of a front stage and a rear stage of the control signal line with respect to an incident direction of the incident light.
The solid-state imaging device according to claim 1, wherein the additional wiring is an independent wiring that is capacitively coupled to the control signal line and is different from the control signal line.
The additional wiring is an independent wiring different from the control signal line that is capacitively coupled to the control signal line, and another control signal line that is capacitively coupled to the control signal line. Solid-state imaging device.
The potential of the control signal line controlled to be in a floating state by the floating mechanism section rises or falls according to a signal supplied to the additional wiring that is capacitively coupled to the control signal line in the floating state. Item 10. The solid-state imaging device according to Item 9.
The control signal line capacitively coupled to the additional wiring composed of the independent wiring is first controlled to be in a floating state by the floating mechanism unit, and the potential increases according to a signal supplied to the additional wiring. The solid-state imaging device according to claim 10.
The control signal line capacitively coupled to the additional wiring composed of the independent wiring is finally controlled to be in a floating state by the floating mechanism unit, and the potential increases according to a signal supplied to the additional wiring. The solid-state imaging device according to claim 10.
The solid-state imaging device according to claim 9, wherein a capacity for coupling the adjacent additional wiring and the control signal line and a capacity for coupling the control signal lines are substantially equal.
The solid-state imaging device according to claim 1, wherein a capacitor that couples the control signal line and the additional wiring is an additional capacitor.
The solid-state imaging device according to claim 14, wherein the additional capacitance is a parasitic capacitance.
The solid-state imaging device according to claim 14, wherein the additional capacitor is a MOS (Metal Oxide Semiconductor) capacitor.
The solid-state imaging device according to claim 14, wherein the additional capacitor is a MIM (Metal Insulator Metal) / MOM (Metal Oxide Metal) capacitor.
The solid-state imaging device according to claim 14, wherein the additional capacitor is a capacitor in which both counter electrodes are formed of polysilicon.
A transfer gate that transfers a pixel signal from a pixel that generates a pixel signal corresponding to the amount of incident light by photoelectric conversion;
A floating mechanism for floating a control signal line for supplying a control signal for controlling opening and closing of the transfer gate; and
An imaging apparatus comprising: an additional wiring that is capacitively coupled to the control signal line.
A transfer gate that transfers a pixel signal from a pixel that generates a pixel signal corresponding to the amount of incident light by photoelectric conversion;
A floating mechanism for floating a control signal line for supplying a control signal for controlling opening and closing of the transfer gate; and
An electronic device comprising: an additional wiring that is capacitively coupled to the control signal line.