WO2019135265A1 - Semiconductor device - Google Patents

Abstract

This semiconductor device has a semiconductor substrate, first electrode, second electrode, conductive layer, insulating layer, and third electrode. The semiconductor substrate has a first main surface and a second main surface, which are facing directions opposite to each other. The first electrode and the second electrode are disposed on the first main surface. Between the first electrode and the second electrode, the third electrode is disposed on the first main surface via the insulating layer. The third electrode has: a first region that is closest to, in the third electrode, the first electrode; and a second region that is closest to, in the third electrode, the second electrode. The first region and the second region are electrically connected to each other.

Description

Semiconductor device

The present invention relates to a semiconductor device.

It is known that when a substance such as metal is irradiated with X-rays, the substance emits fluorescence of energy (wavelength) specific to the atoms of the substance. The wavelength band of fluorescence is approximately equal to the wavelength band of X-rays. The intensity of the fluorescence is very weak.

This phenomenon can be applied to the estimation of the type and amount of substances such as metals contained in an object. For this estimation, the object is irradiated with X-rays, and fluorescent X-rays emitted from the object are observed. The above estimation is performed on the basis of the energy intensity for each wavelength of light included in fluorescent X-rays, that is, on the basis of the spectrum of fluorescent X-rays.

A silicon drift detector (SDD) is disclosed that efficiently detects weak fluorescent x-rays. FIG. 15 shows the configuration of a detector 1010 that is an SDD. In FIG. 15, a cross section of detector 1010 is shown. As shown in FIG. 15, the detector 1010 includes a semiconductor substrate 1100, an insulating layer 1130, an anode electrode 1140, a cathode electrode 1150, and a plurality of gate electrodes 1160. In FIG. 15, reference numerals of two gate electrodes 1160 are shown as a representative of the plurality of gate electrodes 1160. The semiconductor substrate 1100 and the insulating layer 1130 are stacked in a direction Dr10 perpendicular to the surface 1100a of the semiconductor substrate 1100.

The semiconductor substrate 1100 includes a first semiconductor layer 1110, a second semiconductor layer 1120, a first impurity layer 1111, and a plurality of second impurity layers 1112. In FIG. 15, the symbol of one second impurity layer 1112 is shown as a representative of the plurality of second impurity layers 1112.

The first semiconductor layer 1110 and the second semiconductor layer 1120 are stacked in a direction Dr10 perpendicular to the surface 1100a of the semiconductor substrate 1100. The semiconductor substrate 1100 has a surface 1100 a and a surface 1100 b. The face 1100a and the face 1100b face in opposite directions.

The first semiconductor layer 1110 contains an N-type semiconductor. The second semiconductor layer 1120 contains a P-type semiconductor. The second semiconductor layer 1120 is configured as a layer from the surface 1100 b to a predetermined depth.

The first impurity layer 1111 and the plurality of second impurity layers 1112 are disposed in the first semiconductor layer 1110. The first impurity layer 1111 contains an N-type semiconductor. For example, the first impurity layer 1111 is formed of a semiconductor material having an impurity concentration different from that of the semiconductor material forming the first semiconductor layer 1110. The second impurity layer 1112 contains a P-type semiconductor. The surface of each of the first impurity layer 1111 and the plurality of second impurity layers 1112 constitutes a surface 1100 a. Each of the first impurity layer 1111 and the plurality of second impurity layers 1112 is configured as a layer from the surface 1100 a to a predetermined depth.

The insulating layer 1130 is stacked on the first semiconductor layer 1110. The anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1160 are disposed on the surface of the insulating layer 1130. These electrodes are arranged at mutually different positions. The anode electrode 1140 is disposed at a position corresponding to the first impurity layer 1111. The cathode electrode 1150 and the plurality of gate electrodes 1160 are disposed at positions corresponding to the second impurity layer 1112.

In the insulating layer 1130, an opening is formed at a position corresponding to each of the first impurity layer 1111 and the plurality of second impurity layers 1112. The anode electrode 1140 is connected to the first impurity layer 1111 through an opening formed in the insulating layer 1130. The cathode electrode 1150 is connected to the second impurity layer 1112 through an opening formed in the insulating layer 1130. The gate electrode 1160 is connected to the second impurity layer 1112 through an opening formed in the insulating layer 1130. That is, the anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1160 penetrate the insulating layer 1130. The gate electrode 1160 and the second impurity layer 1112 constitute a field effect transistor (FET).

FIG. 16 is a plan view of the detector 1010. In FIG. 16, each element when the detector 1010 is viewed in a direction perpendicular to the surface 1100 a of the semiconductor substrate 1100 is shown. That is, in FIG. 16, each element when the detector 1010 is viewed from the front of the semiconductor substrate 1100 is shown. In FIG. 16, the symbol of one gate electrode 1160 is shown as a representative of the plurality of gate electrodes 1160. A cross section through line L10 shown in FIG. 16 is shown in FIG.

The anode electrode 1140 is disposed at the center of the surface 1100 a of the semiconductor substrate 1100. The anode electrode 1140 is a circular electrode. The cathode electrode 1150 and the plurality of gate electrodes 1160 are ring-shaped electrodes. The cathode electrode 1150 and the plurality of gate electrodes 1160 are arranged concentrically. The cathode electrode 1150 and the plurality of gate electrodes 1160 are arranged to surround the anode electrode 1140. The cathode electrode 1150 is disposed at the outermost side. The plurality of gate electrodes 1160 are disposed between the anode electrode 1140 and the cathode electrode 1150.

A voltage is applied to the anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1160. The voltage applied to the anode electrode 1140 is higher than the voltage applied to the cathode electrode 1150. The voltage applied to the anode electrode 1140 is higher than any voltage applied to the plurality of gate electrodes 1160. A negative voltage is applied to the cathode electrode 1150 and the plurality of gate electrodes 1160. The voltage applied to the plurality of gate electrodes 1160 is higher than the voltage applied to the cathode electrode 1150. The voltage applied to the more inner gate electrode 1160 is higher than the voltage applied to the more outer gate electrode 1160. A voltage is applied to the anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1160 so that the potential inside the semiconductor substrate 1100 increases from the outer periphery of the semiconductor substrate 1100 toward the center.

The electrodes are disposed on the surface 1100 b of the semiconductor substrate 1100. That is, the electrode is disposed on the second semiconductor layer 1120. A voltage lower than that applied to the anode electrode 1140 is applied to that electrode. Thus, a voltage is applied to the second semiconductor layer 1120. The second semiconductor layer 1120 functions as a cathode electrode. A voltage is applied to the second semiconductor layer 1120 such that the internal potential of the semiconductor substrate 1100 increases from the surface 1100 b toward the surface 1100 a.

A voltage as described above is applied to detector 1010. The potential in the semiconductor substrate 1100 increases from the outer periphery to the center of the semiconductor substrate 1100 and also increases from the surface 1100 b to the surface 1100 a. That is, a potential gradient is generated in the semiconductor substrate 1100. The potential acting on the electrons decreases from the outer periphery of the semiconductor substrate 1100 toward the center, and decreases from the surface 1100 b to the surface 1100 a. That is, a potential gradient is generated in the semiconductor substrate 1100. When X-rays enter the detector 1010, electrons are generated in the semiconductor substrate 1100. The electrons gather at the anode electrode 1140 according to the potential gradient. A signal based on the electrons is output from detector 1010.

FIG. 17 shows the configuration of a detector 1011 configured similarly to the SDD disclosed in Patent Document 1. As shown in FIG. In FIG. 17 a cross section of the detector 1011 is shown. As shown in FIG. 17, the detector 1011 has a semiconductor substrate 1101. The configuration shown in FIG. 17 will be described about differences from the configuration shown in FIG.

As shown in FIG. 17, in the detector 1011, the semiconductor substrate 1100 shown in FIG. 15 is changed to a semiconductor substrate 1101. The semiconductor substrate 1101 has a surface 1101 a and a surface 1101 b. The face 1101a and the face 1101b face in opposite directions to each other. In the semiconductor substrate 1101, the first semiconductor layer 1110 shown in FIG. 15 is changed to a first semiconductor layer 1113. In the first semiconductor layer 1113, the plurality of second impurity layers 1112 shown in FIG. 15 are changed to a plurality of second impurity layers 1114. In FIG. 17, the symbol of one second impurity layer 1114 is shown as a representative of the plurality of second impurity layers 1114. The plurality of second impurity layers 1114 include a P-type semiconductor.

In FIG. 17, five second impurity layers 1114 are shown. The widths of the plurality of second impurity layers 1114 in the direction parallel to the surface 1101a are different from each other. The width of the more outer second impurity layer 1114 is larger than the width of the more inner second impurity layer 1114. The voltage _{V 15} from the voltage _{V 11} is applied respectively to the second impurity layer 1114. The voltage applied to the inner second impurity layer 1114 is higher than the voltage applied to the outer second impurity layer 1114. Since the widths of the plurality of second impurity layers 1114 are different from each other, the potential gradient can be controlled.

The insulating layer 1130, the anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1160 shown in FIG. 15 are omitted. The voltage _{V 10} is applied to the first impurity layer 1111. Voltage _{V 10} is higher than any of the voltage _{V 11} of the voltage _{V 15.}

Except for the points described above, the configuration shown in FIG. 17 is the same as the configuration shown in FIG.

FIG. 18 shows the configuration of a detector 1012 configured similarly to the other SDD disclosed in Patent Document 1. In FIG. 18 a cross section of the detector 1012 is shown. As shown in FIG. 18, the detector 1012 has a semiconductor substrate 1102, an insulating layer 1131, and a plurality of electrodes 1170. In FIG. 18, reference numerals of one electrode 1170 are shown as a representative of the plurality of electrodes 1170. The configuration shown in FIG. 18 will be described about differences from the configuration shown in FIG.

As shown in FIG. 18, in the detector 1012, the semiconductor substrate 1101 shown in FIG. 17 is changed to a semiconductor substrate 1102. The semiconductor substrate 1102 has a surface 1102 a and a surface 1102 b. The face 1102a and the face 1102b face in opposite directions to each other. In the semiconductor substrate 1102, the first semiconductor layer 1113 shown in FIG. 17 is changed to a first semiconductor layer 1115. In the first semiconductor layer 1115, the outermost second impurity layer 1114 among the plurality of second impurity layers 1114 shown in FIG. 17 is disposed. The other second impurity layers 1114 are not disposed.

In the first semiconductor layer 1115, the region between the first impurity layer 1111 and the second impurity layer 1114 is covered with the insulating layer 1131. A plurality of electrodes 1170 are disposed on the insulating layer 1131. In FIG. 18, four electrodes 1170 are shown. The widths of the plurality of electrodes 1170 in directions parallel to the surface 1102a are different from each other. The width of the more outer electrode 1170 is greater than the width of the more inner electrode 1170. The voltage _{V 14} is applied respectively to the electrodes 1170 from the voltage _{V 11.} The voltage applied to the more inner electrode 1170 is higher than the voltage applied to the more outer electrode 1170.

Except for the points described above, the configuration shown in FIG. 18 is the same as the configuration shown in FIG.

U.S. Pat. No. 8,314,468

In the detector 1010 shown in FIG. 15, in addition to the voltages applied to the anode electrode 1140 and the cathode electrode 1150, a plurality of voltages applied to the plurality of gate electrodes 1160 are required. In the detector 1011 illustrated in FIG. 17, in addition to the voltage V ₁₀ and the voltage V ₁₅ applied to the first impurity layer 1111 and the outermost second impurity layer 1114, the voltage is applied to the plurality of second impurity layers 1114. it is required voltage _{V 14} from the voltage _{V 11} to be. In the detector 1012 illustrated in FIG. 18, in addition to the voltage V ₁₀ and the voltage V ₁₅ applied to the first impurity layer 1111 and the second impurity layer 1114, the voltage V ₁₁ applied to the plurality of electrodes 1170 V ₁₄ is required.

As described above, multiple voltages need to be applied to the semiconductor device. Therefore, an element for controlling a plurality of voltages is required inside or outside the semiconductor device.

An object of the present invention is to provide a semiconductor device capable of reducing the number of required voltages.

According to a first aspect of the present invention, a semiconductor device includes a semiconductor substrate, a first electrode, a second electrode, a conductive layer, an insulating layer, and a third electrode. The semiconductor substrate has a first main surface and a second main surface facing in opposite directions. The first electrode and the second electrode are disposed on the first main surface. The conductive layer is disposed on the second main surface or disposed in the semiconductor substrate so as to include the second main surface. The insulating layer is disposed on the first main surface. The third electrode is disposed on the first main surface between the first electrode and the second electrode via the insulating layer. The third electrode has a first region closest to the first electrode in the third electrode, and a second region closest to the second electrode in the third electrode. When the first voltage applied to the first electrode is higher than the second voltage applied to the second electrode, a third voltage applied to the first region is the second voltage. It is higher than the fourth voltage applied to the region. When the first voltage applied to the first electrode is lower than the second voltage applied to the second electrode, a third voltage applied to the first region is the second voltage. Lower than the fourth voltage applied to the region. The first region and the second region are electrically connected to each other.

According to a second aspect of the present invention, in the first aspect, the third electrode may be configured in a continuous structure connecting the first region and the second region.

According to a third aspect of the present invention, in the second aspect, the second electrode may be disposed around the first electrode. At least four strips of the third electrode may be arranged in parallel with the direction from the first electrode to the second electrode.

According to a fourth aspect of the present invention, in the third aspect, the width of the third electrode in the first region is larger than the width of the third electrode in the second region. Good.

According to a fifth aspect of the present invention, in the second aspect, the second electrode and the third electrode may be disposed around the first electrode. The third electrode may be arranged to intersect at a plurality of positions with an imaginary straight line passing through the first electrode and the second electrode.

According to a sixth aspect of the present invention, in the fifth aspect, the third electrode may be arranged in a spiral.

According to a seventh aspect of the present invention, in the sixth aspect, the width of the third electrode in the first region is smaller than the width of the third electrode in the second region. Good.

According to an eighth aspect of the present invention, in the first aspect, the third electrode may have a plurality of partial electrodes. Each partial electrode included in the plurality of partial electrodes may include a first layer and a second layer different in position in a direction perpendicular to the first major surface. In the two partial electrodes adjacent in a direction parallel to the first main surface, the insulating layer between the first layer of one of the partial electrodes and the second layer of the other partial electrode May be arranged. The first layer of the one partial electrode and the second layer of the other partial electrode may constitute a capacitance.

According to a ninth aspect of the present invention, in the eighth aspect, the third region may be larger than the fourth region. The third region may be a region where the first layer and the second layer constituting the capacitor disposed at a position closest to the first electrode overlap with each other through the insulating layer. . The fourth region may be a region where the first layer and the second layer constituting the capacitor disposed at a position closest to the second electrode overlap with each other via the insulating layer. .

According to each of the above aspects, the semiconductor device can reduce the number of required voltages.

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a top view of the semiconductor device of a 1st embodiment of the present invention. It is a top view of the semiconductor device of the modification of a 1st embodiment of the present invention. It is a graph which shows potential distribution in the semiconductor device of a 1st embodiment of the present invention. It is a graph which shows the potential distribution in the semiconductor device of the modification of the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device of the 2nd Embodiment of this invention. It is a top view of the semiconductor device of a 2nd embodiment of the present invention. FIG. 26 is a plan view of a semiconductor device of a first modified example of the second embodiment of the present invention. FIG. 25 is a plan view of a semiconductor device of a second modified example of the second embodiment of the present invention. It is sectional drawing of the semiconductor device of the 3rd Embodiment of this invention. It is an enlarged view of the cross section of the semiconductor device of a 3rd embodiment of the present invention. It is a top view of the semiconductor device of a 3rd embodiment of the present invention. It is an enlarged view of the cross section of the semiconductor device of the modification of the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device of the 4th Embodiment of this invention. FIG. 1 is a cross-sectional view of a prior art detector. FIG. 1 is a plan view of a prior art detector. FIG. 1 is a cross-sectional view of a prior art detector. FIG. 1 is a cross-sectional view of a prior art detector.

Embodiments of the present invention will be described with reference to the drawings.

First Embodiment
FIG. 1 shows the configuration of a semiconductor device 10 according to a first embodiment of the present invention. In FIG. 1, a cross section of a semiconductor device 10 is shown. The semiconductor device 10 is configured as a silicon drift detector (SDD) that detects radiation, that is, fluorescent X-rays.

The dimensions of the parts constituting the semiconductor device 10 do not necessarily follow the dimensions shown in FIG. The dimensions of the parts constituting the semiconductor device 10 may be arbitrary. The same applies to the dimensions in other cross-sectional views.

The schematic configuration of the semiconductor device 10 will be described. The semiconductor device 10 includes a semiconductor substrate 100, a first electrode 140, a second electrode 150, a second semiconductor layer 120 (conductive layer), an insulating layer 130, and a third electrode 160. The semiconductor substrate 100 has a surface 110a (first main surface) and a surface 120b (second main surface) facing in opposite directions. The first electrode 140 and the second electrode 150 are disposed on the surface 110 a. The second semiconductor layer 120 is disposed in the semiconductor substrate 100 so as to include the surface 120 b and has conductivity. The insulating layer 130 is disposed on the surface 110 a. The third electrode 160 is disposed on the surface 110 a via the insulating layer 130 between the first electrode 140 and the second electrode 150. The third electrode 160 has a first region S1 closest to the first electrode 140 in the third electrode 160 and a second region S2 closest to the second electrode 150 in the third electrode 160. . If the first voltage applied to the first electrode 140 is higher than the second voltage applied to the second electrode 150, the third voltage V ₁ applied to the first region S1 is the second fourth higher than the voltage V ₂ of which is applied to the area S2. If the first voltage applied to the first electrode 140 is lower than the second voltage applied to the second electrode 150, the third voltage V ₁ applied to the first region S1 is the second the fourth lower than the voltage V ₂ applied to the area S2. The first region S1 and the second region S2 are electrically connected to each other.

The detailed configuration of the semiconductor device 10 will be described. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor substrate 100, an insulating layer 130, a first electrode 140, a second electrode 150, and a third electrode 160. The semiconductor substrate 100, the insulating layer 130, and the third electrode 160 are stacked in a direction Dr1 perpendicular to the surface 110a of the semiconductor substrate 100.

The semiconductor substrate 100 includes a first semiconductor layer 110, a second semiconductor layer 120, a first impurity layer 111, and a second impurity layer 112. For example, the semiconductor material forming the semiconductor substrate 100 is silicon (Si).

The first semiconductor layer 110 includes an N-type semiconductor. The first semiconductor layer 110 has a surface 110 a and a surface 110 b. The face 110a and the face 110b face in opposite directions to each other. The surface 110 a and the surface 110 b constitute the main surface of the first semiconductor layer 110. The main surface of the first semiconductor layer 110 is a relatively wide surface among a plurality of surfaces forming the surface of the first semiconductor layer 110. The surface 110 a constitutes the main surface of the semiconductor substrate 100. The main surface of the semiconductor substrate 100 is a relatively wide surface among a plurality of surfaces forming the surface of the semiconductor substrate 100.

The first impurity layer 111 and the second impurity layer 112 are disposed in the first semiconductor layer 110. The first impurity layer 111 contains an N-type semiconductor. For example, the first impurity layer 111 is formed of a semiconductor material having an impurity concentration different from that of the semiconductor material forming the first semiconductor layer 110. The second impurity layer 112 contains a P-type semiconductor. The surface of each of the first impurity layer 111 and the second impurity layer 112 constitutes a surface 110 a. Each of the first impurity layer 111 and the second impurity layer 112 is configured as a layer from the surface 110 a to a predetermined depth.

The second semiconductor layer 120 includes an N-type semiconductor. The second semiconductor layer 120 is stacked on the first semiconductor layer 110. The second semiconductor layer 120 is in contact with the surface 110 b of the first semiconductor layer 110. The second semiconductor layer 120 has a surface 120 a and a surface 120 b. The face 120a and the face 120b face in opposite directions to each other. The surface 120 a and the surface 120 b constitute the main surface of the second semiconductor layer 120. The main surface of the second semiconductor layer 120 is a relatively wide surface among a plurality of surfaces forming the surface of the second semiconductor layer 120. The face 120a is in contact with the face 110b. The surface 120 b constitutes the main surface of the semiconductor substrate 100. The second semiconductor layer 120 covers at least a part of the surface 110 b. In the example shown in FIG. 1, the second semiconductor layer 120 covers the entire surface 110 b. An electrode having a structure similar to that of the second electrode 150 is disposed at the outer peripheral portion of the surface 120 b. A predetermined voltage is applied to the electrode. An opening may be formed in part of the second semiconductor layer 120.

The insulating layer 130 is made of an insulating material. For example, the insulating material forming the insulating layer 130 is silicon dioxide (SiO 2). The insulating layer 130 is stacked on the first semiconductor layer 110. The insulating layer 130 is in contact with the surface 110 a of the first semiconductor layer 110. The insulating layer 130 has a surface 130 a and a surface 130 b. The face 130a and the face 130b face in opposite directions to each other. The surface 130 a and the surface 130 b constitute the main surface of the insulating layer 130. The main surface of the insulating layer 130 is a relatively wide surface among a plurality of surfaces forming the surface of the insulating layer 130. The surface 130 b is in contact with the surface 110 a. The insulating layer 130 covers at least a part of the surface 110 a.

The first electrode 140 and the second electrode 150 are made of a conductive material. For example, the conductive material forming the first electrode 140 and the second electrode 150 is a metal such as copper (Cu), aluminum (Al), and gold (Au). The conductive material forming the first electrode 140 and the second electrode 150 may include a semiconductor such as polysilicon having a high impurity concentration. The first electrode 140 and the second electrode 150 may be made of different conductive materials.

The third electrode 160 is made of a conductive high-resistance material. For example, the high-resistance material forming the third electrode 160 is high-resistance polysilicon and high-resistance amorphous silicon. The high-resistance material that constitutes the third electrode 160 may be a material in which current does not easily flow. The third electrode 160 may be made of a narrow metal. The high resistance material that constitutes the third electrode 160 excludes the insulating material. A plurality of third electrodes 160 are arranged.

The first electrode 140, the second electrode 150, and the third electrode 160 are disposed on the surface 130 a of the insulating layer 130. These electrodes are arranged at mutually different positions. The first electrode 140 is disposed at a position corresponding to the first impurity layer 111. The second electrode 150 is disposed at a position corresponding to the second impurity layer 112. In the example shown in FIG. 1, the impurity layer is not disposed at the position corresponding to the third electrode 160.

In the insulating layer 130, an opening is formed at a position corresponding to each of the first impurity layer 111 and the second impurity layer 112. The first electrode 140 is connected to the first impurity layer 111 through an opening formed in the insulating layer 130. The second electrode 150 is connected to the second impurity layer 112 through an opening formed in the insulating layer 130. That is, the first electrode 140 and the second electrode 150 penetrate the insulating layer 130.

The third electrode 160 is disposed on the insulating layer 130. A portion of the third electrode 160 may be disposed inside the insulating layer 130. The third electrode 160 is separated from the surface 110 a by a predetermined distance. The third electrode 160 is disposed out of contact with the first electrode 140 and the second electrode 150. That is, the third electrode 160 is insulated from the first electrode 140 and the second electrode 150.

The first region S 1 includes an end closest to the first electrode 140 in the third electrode 160. The second region S 2 includes the end closest to the second electrode 150 at the third electrode 160. It is a terminal for applying the voltages V ₁ to the third electrode 160 is disposed on the first region S1. It is a terminal for applying a voltage V ₂ to the third electrode 160 is disposed on the second region S2.

The third electrode 160 has a continuous structure connecting the first region S1 and the second region S2. In other words, the third electrode 160 is configured of a single body that does not break between the first region S1 and the second region S2. In one third electrode 160, there is no gap between the first region S1 and the second region S2. In one third electrode 160, there is a current path passing only through the third electrode 160 between the first region S1 and the second region S2.

FIG. 2 is a plan view of the semiconductor device 10. In FIG. 2, each element when the semiconductor device 10 is viewed in the direction perpendicular to the surface 110 a of the first semiconductor layer 110 is shown. That is, in FIG. 2, each element when the semiconductor device 10 is viewed from the front of the semiconductor substrate 100 is shown. In FIG. 2, a symbol of one third electrode 160 is shown as a representative of the plurality of third electrodes 160. A cross section through line A1-A1 shown in FIG. 2 is shown in FIG.

The shape of the semiconductor device 10 is rectangular. In the example shown in FIG. 2, the shape of the semiconductor device 10 is square. The shape of the semiconductor device 10 is not limited to a rectangle. The first electrode 140 is disposed at the center of the surface 110a. The first electrode 140 is a circular electrode. The shape of the first electrode 140 may be rectangular or the like.

The second electrode 150 is a ring-shaped electrode. The shape of the second electrode 150 may be a rectangle with a hole or the like. The second electrode 150 is disposed to surround the first electrode 140 and the plurality of third electrodes 160. That is, the second electrode 150 is disposed around the first electrode 140 and the plurality of third electrodes 160. It is only necessary that at least one second electrode 150 be disposed. A plurality of second electrodes 150 may be disposed around the first electrode 140 and the plurality of third electrodes 160.

The plurality of third electrodes 160 are disposed between the first electrode 140 and the second electrode 150. At least four strip-shaped third electrodes 160 are disposed in parallel with the direction from the first electrode 140 toward the second electrode 150. The direction from the first electrode 140 to the second electrode 150 is the radial direction of a circle centered on the first electrode 140. The third electrode 160 is elongated in a direction from the first electrode 140 to the second electrode 150. In FIG. 2, eight third electrodes 160 are disposed. Eight third electrodes 160 are radially disposed about the first electrode 140.

The width of the third electrode 160 in the first region S1 is the same as the width of the third electrode 160 in the second region S2. The width of the third electrode 160 is the width in the direction perpendicular to the direction from the first electrode 140 toward the second electrode 150. The width of the third electrode 160 is constant regardless of the position on the third electrode 160. The plurality of third electrodes 160 are arranged not to be in contact with each other. At least two third electrodes 160 may be in contact with each other.

The first distance D1 is smaller than the second distance D2. The first distance D1 is the distance between the first electrode 140 and the first region S1. The second distance D2 is a distance from a position between the first electrode 140 and the second electrode 150 to the first region S1. The third distance D3 is smaller than the fourth distance D4. The third distance D3 is the distance between the second electrode 150 and the second region S2. The fourth distance D4 is a distance from a position between the first electrode 140 and the second electrode 150 to the second region S2.

A voltage is applied to the first electrode 140, the second electrode 150, and the plurality of third electrodes 160. The voltage applied to the first electrode 140 is higher than the voltage applied to the second electrode 150. The first electrode 140 functions as an anode electrode, and the second electrode 150 functions as a cathode electrode. The voltage applied to the first electrode 140 is higher than the voltage applied to the first region S1 of the third electrode 160. A negative voltage is applied to the second electrode 150 and the plurality of third electrodes 160.

The voltage applied to the first region S1 is higher than the voltage applied to the second region S2. The voltage applied to the second region S2 is higher than the voltage applied to the second electrode 150. In the third electrode 160, the voltage changes continuously between the first region S1 and the second region S2. The voltage of the portion closer to the first electrode 140 in the third electrode 160 is higher than the voltage on the portion closer to the second electrode 150. A voltage is applied to the first electrode 140, the second electrode 150, and the plurality of third electrodes 160 such that the potential inside the semiconductor substrate 100 becomes higher from the outer periphery of the semiconductor substrate 100 toward the center.

An electrode for applying a voltage to the second semiconductor layer 120 is disposed on the surface 120 b of the semiconductor substrate 100. That is, the electrode is disposed on the second semiconductor layer 120. A voltage lower than that applied to the first electrode 140 is applied to that electrode. Thus, a voltage is applied to the second semiconductor layer 120. The second semiconductor layer 120 functions as a cathode electrode. A voltage is applied to the second semiconductor layer 120 such that the internal potential of the semiconductor substrate 100 increases from the surface 110 b toward the surface 110 a.

The voltage as described above is applied to the semiconductor device 10. The potential acting on the electrons decreases from the periphery to the center of the semiconductor substrate 100 and decreases from the surface 110 b to the surface 110 a. That is, a potential gradient is generated in the semiconductor substrate 100. When X-rays enter the semiconductor device 10, electrons are generated in the semiconductor substrate 100. The electrons collect at the first electrode 140 according to the potential gradient. A signal based on the electrons is output from the semiconductor device 10.

The first semiconductor layer 110 and the first impurity layer 111 may be made of a P-type semiconductor, and the second semiconductor layer 120 and the second impurity layer 112 may be made of an N-type semiconductor. The voltage applied to each electrode in that case will be described. The voltage applied to the first electrode 140 is lower than the voltage applied to the second electrode 150. The first electrode 140 functions as a cathode electrode, and the second electrode 150 functions as an anode electrode. The voltage applied to the first electrode 140 is lower than the voltage applied to the third electrode 160. A positive voltage is applied to the second electrode 150 and the third electrode 160.

The voltage applied to the first region S1 is lower than the voltage applied to the second region S2. The voltage applied to the second region S2 is lower than the voltage applied to the second electrode 150. In the third electrode 160, the voltage changes continuously between the first region S1 and the second region S2. The voltage of the portion closer to the first electrode 140 in the third electrode 160 is lower than the voltage on the portion closer to the second electrode 150. A voltage is applied to the first electrode 140, the second electrode 150, and the plurality of third electrodes 160 such that the potential inside the semiconductor substrate 100 decreases from the outer periphery of the semiconductor substrate 100 toward the center.

A voltage higher than the voltage applied to the first electrode 140 is applied to the electrode on the second semiconductor layer 120. Thus, a voltage is applied to the second semiconductor layer 120. A voltage is applied to the second semiconductor layer 120 such that the internal potential of the semiconductor substrate 100 decreases from the surface 110 b toward the surface 110 a.

The first impurity layer 111 and the second impurity layer 112 are not essential in the semiconductor device of each aspect of the present invention.

As described above, the third electrode 160 has the first region S1 and the second region S2 electrically connected. The number of voltages that need to be applied to the third electrode 160 is two. Therefore, the semiconductor device 10 can reduce the number of required voltages.

(Modification of the first embodiment)
FIG. 3 is a plan view of a semiconductor device 11 according to a modification of the first embodiment of the present invention. In FIG. 3, each element when the semiconductor device 11 is viewed in the direction perpendicular to the surface 110 a of the first semiconductor layer 110 is shown. That is, in FIG. 3, each element when the semiconductor device 11 is viewed from the front of the semiconductor substrate 100 is shown. The configuration shown in FIG. 3 will be described about differences from the configuration shown in FIG.

A plurality of third electrodes 161 are disposed instead of the plurality of third electrodes 160 shown in FIG. In FIG. 3, the symbol of one third electrode 161 is shown as a representative of the plurality of third electrodes 161. The width of the third electrode 161 in the first region S1 is larger than the width of the third electrode 161 in the second region S2. The width of the third electrode 161 is the width in the direction perpendicular to the direction from the first electrode 140 toward the second electrode 150. The third electrode 161 is configured such that the first region S1 is thicker than the second region S2. The width of the third electrode 161 gradually decreases from the first region S1 to the second region S2.

Except for the points described above, the configuration shown in FIG. 3 is the same as the configuration shown in FIG.

In the semiconductor device 10 shown in FIG. 1, the width of the third electrode 160 is constant regardless of the position on the third electrode 160. Therefore, the resistance value of the third electrode 160 per unit length is constant. As a result, a potential with a constant slope is generated on the surface 110 a of the semiconductor device 10.

FIG. 4 shows a potential distribution Pt1 on the surface 110a of the semiconductor device 10 shown in FIG. The horizontal axis indicates the distance r from the first electrode 140, and the vertical axis indicates the magnitude of the potential. As shown in FIG. 4, the potential on the first electrode 140 side is low, and the potential on the second electrode 150 side is high. The gradient of the potential is constant.

In the semiconductor device 10 in which the potential distribution Pt1 shown in FIG. 4 is generated, electrons generated in a region near the second electrode 150 move toward the first electrode 140. Because the moving distance is long, the electrons may recombine with holes before they reach the first electrode 140.

In the semiconductor device 11 shown in FIG. 3, the width of the third electrode 161 gradually decreases from the first region S1 to the second region S2. Therefore, the resistance value of the third electrode 160 per unit length gradually increases from the first region S1 to the second region S2. As a result, in the surface 110 a of the semiconductor device 10, potentials having different gradients are generated depending on the distance from the first electrode 140.

FIG. 5 shows a potential distribution Pt2 on the surface 110a of the semiconductor device 11 shown in FIG. The horizontal axis indicates the distance r from the first electrode 140, and the vertical axis indicates the magnitude of the potential. As shown in FIG. 5, the gradient of the potential near the second electrode 150 is larger than the gradient of the potential near the first electrode 140. At a position close to the second electrode 150, the gradient of the potential shown in FIG. 5 is larger than the gradient of the potential shown in FIG. At a position close to the first electrode 140, the gradient of the potential shown in FIG. 5 is smaller than the gradient of the potential shown in FIG.

In the semiconductor device 11 in which the potential distribution Pt2 shown in FIG. 5 is generated, electrons generated in a region near the second electrode 150 move toward the first electrode 140. Since the gradient of the potential at a position close to the second electrode 150 is large, the acceleration obtained by the electrons is larger. Thereby, the electrons reach the first electrode 140 in a shorter time. Therefore, the possibility of the electron recombining with the hole before the electron reaches the first electrode 140 is reduced.

The gradient of the potential at a position from near the middle of the first electrode 140 and the second electrode 150 to the first electrode 140 is small. Therefore, the acceleration obtained by the electrons generated near the middle of the first electrode 140 and the second electrode 150 is small. Therefore, before the electron reaches the first electrode 140, the electron may recombine with the hole. Depending on the distance between the first electrode 140 and the second electrode 150 and the voltage applied to each electrode, the potential distribution Pt1 shown in FIG. 4 is preferred, or the potential distribution Pt2 shown in FIG. It may be preferable.

The width of the third electrode 161 in the first region S1 may be smaller than the width of the third electrode 161 in the second region S2. That is, the width of the third electrode 161 may gradually increase from the first region S1 to the second region S2. In other words, the third electrode 161 may be configured such that the first region S1 is thinner than the second region S2.

As described above, the widths of the third electrodes 161 in the first region S1 and the second region S2 are different. Thereby, the potential gradient in the semiconductor device 11 can be changed.

Second Embodiment
FIG. 6 shows the configuration of the semiconductor device 12 according to the second embodiment of the present invention. In FIG. 6, a cross section of the semiconductor device 12 is shown. The configuration shown in FIG. 6 will be described about differences from the configuration shown in FIG.

A third electrode 162 is disposed instead of the third electrode 160 shown in FIG. The third electrode 162 is arranged to intersect at a plurality of positions with an imaginary straight line L1 passing through the first electrode 140 and the second electrode 150. The virtual straight line L1 is an arbitrary straight line passing through the first electrode 140, the second electrode 150, and the third electrode 162. The spacing D5 of each position of the third electrode 160 in the imaginary straight line L1 is the same.

Except for the points described above, the configuration shown in FIG. 6 is the same as the configuration shown in FIG.

FIG. 7 is a plan view of the semiconductor device 12. In FIG. 7, each element when the semiconductor device 12 is viewed in the direction perpendicular to the surface 110a of the first semiconductor layer 110 is shown. That is, in FIG. 7, each element when the semiconductor device 12 is viewed from the front of the semiconductor substrate 100 is shown. A cross section through line A2-A2 shown in FIG. 7 is shown in FIG. The configuration shown in FIG. 7 will be described about differences from the configuration shown in FIG.

In place of the plurality of third electrodes 160, one third electrode 162 is disposed. The second electrode 150 and the third electrode 162 are disposed to surround the first electrode 140. That is, the second electrode 150 and the third electrode 162 are disposed around the first electrode 140. The third electrode 162 is arranged in a spiral. The optional path from the first region S1 to the second region S2 of the third electrode 162 rotates around the first electrode 140 one or more times. In the example shown in FIG. 7, the third electrode 162 is arranged in a curved shape.

The width of the third electrode 162 in the first region S1 is smaller than the width of the third electrode 162 in the second region S2. The width of the third electrode 162 is the width in the direction from the first electrode 140 toward the second electrode 150. The third electrode 162 is configured such that the first region S1 is thinner than the second region S2. The width of the third electrode 162 gradually increases from the first region S1 to the second region S2. For example, the width of the third electrode 162 is designed such that the resistance value of the third electrode 162 for each rotation is constant. In other words, the width of the third electrode 162 is designed so that the voltage drop per round is constant.

Except for the points described above, the configuration shown in FIG. 7 is the same as the configuration shown in FIG.

The width of the third electrode 162 in the first region S1 may be the same as the width of the third electrode 162 in the second region S2. Alternatively, the width of the third electrode 162 in the first region S1 may be larger than the width of the third electrode 162 in the second region S2. That is, the width of the third electrode 162 may be gradually reduced from the first region S1 to the second region S2.

It is assumed that the semiconductor device 12 is configured such that the width of the third electrode 162 is constant regardless of the position on the third electrode 162. Since the width of the third electrode 162 is constant, the resistance value of the third electrode 162 per predetermined length is constant. The length of one round of the third electrode 162 at a position close to the first electrode 140 is shorter than the length of one round of the third electrode 162 at a position near the second electrode 150. Therefore, the voltage drop per round at a position close to the first electrode 140 is smaller than the voltage drop per round at a position close to the second electrode 150. As a result, in the potential distribution according to the distance from the first electrode 140, the gradient of the potential at the position near the second electrode 150 is larger than the gradient of the potential at the position near the first electrode 140. That is, the potential distribution on the surface 110a of the semiconductor device 12 is similar to the potential distribution Pt2 shown in FIG.

In the semiconductor device 12 shown in FIG. 7, since the resistance value of the third electrode 162 for each rotation is constant, the voltage drop per rotation is constant. Therefore, the potential distribution on the surface 110a of the semiconductor device 12 is similar to the potential distribution Pt1 shown in FIG. When a potential distribution such as the potential distribution Pt1 shown in FIG. 4 is preferable or depending on the relationship between the distance between the first electrode 140 and the second electrode 150 and the voltage applied to each electrode, or In some cases, a potential distribution such as the potential distribution Pt2 shown is preferable.

The width of the third electrode 162 in the first region S1 may be larger than the width of the third electrode 162 in the second region S2. That is, the width of the third electrode 162 may be gradually reduced from the first region S1 to the second region S2. In other words, the third electrode 162 may be configured such that the first region S1 is thicker than the second region S2.

The width of the third electrode 162 is constant and the distance between the third electrodes 162 is narrow in a region near the first electrode 140 and the distance between the third electrodes 162 is near a region near the second electrode 150. It may be wide. Under this condition, the potential distribution on the surface 110a of the semiconductor device 12 may be similar to the potential distribution Pt1 shown in FIG.

As described above, the third electrodes 162 are arranged in a spiral. Therefore, one third electrode 162 can surround the first electrode 140. As a result, the number of places requiring application of a voltage to the third electrode 162 is reduced to two.

The widths of the spiral third electrodes 162 in the first region S1 and the second region S2 are different. Thereby, the potential gradient in the semiconductor device 12 can be changed.

(First Modified Example of Second Embodiment)
FIG. 8 is a plan view of a semiconductor device 13 according to a first modification of the second embodiment of the present invention. In FIG. 8, each element when the semiconductor device 13 is viewed in the direction perpendicular to the surface 110a of the first semiconductor layer 110 is shown. That is, in FIG. 8, each element when the semiconductor device 13 is viewed from the front of the semiconductor substrate 100 is shown. The configuration shown in FIG. 8 will be described about differences from the configuration shown in FIG.

A third electrode 163 is disposed instead of the third electrode 162 shown in FIG. The third electrode 163 is arranged in a rectangular shape and in a spiral shape. Similar to the third electrode 162 shown in FIG. 7, the width of the third electrode 163 in the first region S1 is smaller than the width of the third electrode 163 in the second region S2. The third electrode 163 may be arranged in a polygonal shape and in a spiral shape. The polygon may be a figure other than a rectangle.

Regarding the points other than the above, the configuration shown in FIG. 8 is the same as the configuration shown in FIG.

Second Modification of Second Embodiment
FIG. 9 is a plan view of a semiconductor device 14 of a second modification of the second embodiment of the present invention. In FIG. 9, each element when the semiconductor device 14 is viewed in the direction perpendicular to the surface 110 a of the first semiconductor layer 110 is shown. That is, in FIG. 9, each element when the semiconductor device 14 is viewed from the front of the semiconductor substrate 100 is shown. The configuration shown in FIG. 9 will be described about differences from the configuration shown in FIG.

In place of the third electrode 162 shown in FIG. 7, a third electrode 164a and a third electrode 164b are disposed. The region between the first electrode 140 and the second electrode 150 is divided into two regions by a straight line L 2 passing through the center of the first electrode 140 and the second electrode 150. The third electrode 164a is disposed in one of the two regions, and the third electrode 164b is disposed in the other of the two regions.

The third electrode 164a and the third electrode 164b have a plurality of first structures and a plurality of second structures. Each of the plurality of first structures is arranged in a semicircular shape. Each of the plurality of second structures is connected to two first structures. The width of the third electrode 164 a near the first electrode 140 is smaller than the width of the third electrode 164 a near the second electrode 150. The width of the third electrode 164 b near the first electrode 140 is smaller than the width of the third electrode 164 b near the second electrode 150.

Except for the points described above, the configuration shown in FIG. 9 is the same as the configuration shown in FIG.

Third Embodiment
FIG. 10 shows the configuration of a semiconductor device 15 according to the third embodiment of the present invention. In FIG. 10, a cross section of the semiconductor device 15 is shown. Regarding the configuration shown in FIG. 10, points different from the configuration shown in FIG. 1 will be described.

A third electrode 165 is disposed instead of the third electrode 160 shown in FIG. The third electrode 165 is made of a conductive material. For example, the conductive material forming the third electrode 165 is a metal such as copper (Cu), aluminum (Al), and gold (Au). The conductive material forming the third electrode 165 may include a semiconductor such as polysilicon having a high impurity concentration.

The third electrode 165 has a plurality of partial electrodes 165a. The partial electrode 165a has a two-layer electrode structure. The partial electrode 165a closest to the first electrode 140 has a first region S1. The partial electrode 165a closest to the second electrode 150 has a second region S2.

Except for the points described above, the configuration shown in FIG. 10 is the same as the configuration shown in FIG.

FIG. 11 is an enlarged view of a cross section of the semiconductor device 15. Each partial electrode 165a included in the plurality of partial electrodes 165a includes a first layer 1650 and a second layer 1651 which are different in position in the direction Dr1 perpendicular to the surface 110a. In the two partial electrodes 165a adjacent to the direction Dr2, the insulating layer 130 is disposed between the first layer 1650 of one partial electrode 165a and the second layer 1651 of the other partial electrode 165a. The first layer 1650 of one partial electrode 165a and the second layer 1651 of the other partial electrode 165a constitute a capacitance C1. The plurality of partial electrodes 165a are electrically connected via a capacitor C1.

The first layer 1650 is disposed inside the insulating layer 130. The second layer 1651 is disposed inside and outside the insulating layer 130. The distance between one first layer 1650 and the other second layer 1651 of two partial electrodes 165a adjacent to the direction Dr2 is constant regardless of the distance from the first electrode 140.

The first layer 1650 is offset with respect to the second layer 1651 in a direction Dr2 parallel to the surface 110a. The second layer 1651 is offset relative to the first layer 1650 in the direction opposite to the direction Dr2. The first layers 1650 of the two partial electrodes 165a adjacent to the direction Dr2 are separated by a predetermined distance. The second layers 1651 of the two partial electrodes 165a adjacent to the direction Dr2 are separated by a predetermined distance. The spacing of the plurality of first layers 1650 in the direction Dr2 is the same. The spacing between the plurality of second layers 1651 in the direction Dr2 is the same. When the semiconductor device 15 is viewed in the direction Dr1, at least a portion of the first layer 1650 and at least a portion of the second layer 1651 overlap each other. The first layer 1650 and the second layer 1651 constituting the capacitor C1 overlap through the insulating layer 130.

The widths of the first layers 1650 of the plurality of partial electrodes 165a in the direction Dr2 are the same. The widths of the second layers 1651 of the plurality of partial electrodes 165a in the direction Dr2 are the same. The widths of the first layer 1650 and the second layer 1651 in the direction Dr2 are the same. The widths of the first layer 1650 and the second layer 1651 in the direction Dr2 may be different. The distance between the first layer 1650 and the second layer 1651 of the plurality of capacitors C1 is the same.

FIG. 12 is a plan view of the semiconductor device 15. In FIG. 12, each element when the semiconductor device 15 is seen in the direction perpendicular to the surface 110a of the first semiconductor layer 110 is shown. That is, in FIG. 12, each element when the semiconductor device 15 is viewed from the front of the semiconductor substrate 100 is shown. A cross section through line A3-A3 shown in FIG. 12 is shown in FIG. The configuration shown in FIG. 12 will be described about differences from the configuration shown in FIG.

The plurality of partial electrodes 165a are ring-shaped electrodes. The plurality of partial electrodes 165a are arranged concentrically. In FIG. 12, the second layer 1651 of the partial electrode 165a is shown. The first layer 1650 is not shown in FIG. 12 because the first layer 1650 is disposed inside the insulating layer 130. The plurality of partial electrodes 165a may be arranged in a polygonal shape.

The configuration shown in FIG. 12 is the same as the configuration shown in FIG.

The plurality of partial electrodes 165a are connected in series via the capacitor C1. The voltage V ₁ is applied to one point of the partial electrode 165 a closest to the first electrode 140. The voltage V ₂ is applied to one point of the partial electrode 165 a closest to the second electrode 150. When a voltage is applied to the first region S1 and the second region S2, the voltage of the partial electrode 165a closer to the first electrode 140 becomes higher than the voltage of the partial electrode 165a closer to the second electrode 150. As a result, a potential that decreases from the outer periphery to the center of the semiconductor substrate 100 is generated.

As described above, the plurality of partial electrodes 165a including the capacitance C1 are disposed. The plurality of partial electrodes 165a are electrically connected via a capacitor C1. Therefore, the number of places where application of a voltage to the third electrode 165 is required can be reduced to two.

When a voltage is applied to the first region S1 and the second region S2, a transient current for charging the capacitor C1 flows in the plurality of partial electrodes 165a. After the capacitor C1 is charged, no steady current flows to the plurality of partial electrodes 165a. Therefore, the power consumption of the semiconductor device 15 is smaller than that of the semiconductor device 10 shown in FIG. 1 and the semiconductor device 12 shown in FIG.

(Modification of the third embodiment)
FIG. 13 shows the configuration of a semiconductor device 16 according to a modification of the third embodiment of the present invention. FIG. 13 is an enlarged view of a cross section of the semiconductor device 16. The configuration shown in FIG. 13 will be described about differences from the configuration shown in FIG.

The third area S3 is larger than the fourth area S4. The third region S3 is a region where the first layer 1650 and the second layer 1651, which constitute the capacitor C1a disposed at a position closest to the first electrode 140, overlap with the insulating layer 130 interposed therebetween. The fourth region S4 is a region where the first layer 1650 and the second layer 1651 constituting the capacitor C1b disposed at a position closest to the second electrode 150 overlap with the insulating layer 130 interposed therebetween.

The width of the third region S3 in the direction Dr2 parallel to the surface 110a is larger than the width of the fourth region S4. In the region where the two layers forming the capacitor C1 at a position closer to the first electrode 140 overlap via the insulating layer 130, the two layers forming a capacitor C1 at a position closer to the second electrode 150 form the insulating layer 130. Larger than the overlapping area. The region where the two layers overlap with the insulating layer 130 interposed therebetween gradually decreases from the capacitance C1 on the first electrode 140 side to the capacitance C1 on the second electrode 150 side.

The spacing of the plurality of first layers 1650 and the spacing of the plurality of second layers 1651 in the direction Dr2 differ depending on the distance from the first electrode 140. The spacing of the plurality of first layers 1650 closer to the first electrode 140 is smaller than the spacing closer to the second electrode 150. The distance between the plurality of first layers 1650 gradually increases from the first electrode 140 to the second electrode 150. The distance between the plurality of second layers 1651 at a position closer to the first electrode 140 is smaller than that at a position near the second electrode 150. The distance between the plurality of second layers 1651 gradually increases from the first electrode 140 to the second electrode 150.

Except for the points described above, the configuration shown in FIG. 13 is the same as the configuration shown in FIG.

The region where the two layers overlap with the insulating layer 130 interposed therebetween gradually decreases from the capacitance C1 on the first electrode 140 side to the capacitance C1 on the second electrode 150 side. From the capacitance C1 on the first electrode 140 side to the capacitance C1 on the second electrode 150 side, the capacitance value of the capacitance C1 gradually decreases. Since the amount of charge stored in each capacitor C1 is the same, the voltage between the two layers of the capacitor C1 is from the capacitor C1 on the first electrode 140 side to the capacitor C1 on the second electrode 150 side. It will grow gradually. As a result, in the surface 110 a of the semiconductor device 16, potentials having different gradients are generated depending on the distance from the first electrode 140. The potential distribution on the surface 110a of the semiconductor device 16 is similar to the potential distribution Pt2 shown in FIG.

In the semiconductor device 15 shown in FIG. 11, the size of the third region S3 is the same as the size of the fourth region S4. That is, the size of the region where the two layers overlap with the insulating layer 130 is constant regardless of the distance from the first electrode 140. The third area S3 may be smaller than the fourth area S4. That is, the region where the two layers overlap with the insulating layer 130 interposed therebetween may gradually increase from the capacitance C1 on the first electrode 140 side to the capacitance C1 on the second electrode 150 side.

As described above, the sizes of the third area S3 and the fourth area S4 are different. Thereby, the potential gradient in the semiconductor device 16 can be changed.

Fourth Embodiment
FIG. 14 shows the configuration of a semiconductor device 17 according to the fourth embodiment of the present invention. In FIG. 14, a cross section of the semiconductor device 17 is shown. The configuration shown in FIG. 14 will be described about differences from the configuration shown in FIG.

The semiconductor substrate 100 shown in FIG. 1 is changed to a semiconductor substrate 101. The semiconductor substrate 101 does not have the second semiconductor layer 120 shown in FIG. A fourth electrode 170 (conductive layer) is disposed instead of the second semiconductor layer 120 shown in FIG.

The fourth electrode 170 is made of a conductive material. For example, the conductive material forming the fourth electrode 170 is a metal such as copper (Cu), aluminum (Al), and gold (Au). The conductive material forming the fourth electrode 170 may include a semiconductor such as polysilicon having a high impurity concentration.

The fourth electrode 170 is stacked on the first semiconductor layer 110. The surface 110 b constitutes the main surface of the semiconductor substrate 101. The fourth electrode 170 is disposed on the surface 110 b of the first semiconductor layer 110 and has conductivity. The fourth electrode 170 is in contact with the surface 110 b. The fourth electrode 170 has a surface 170a and a surface 170b. The face 170a and the face 170b face in opposite directions to each other. The surface 170 a and the surface 170 b constitute the main surface of the fourth electrode 170. The main surface of the fourth electrode 170 is a relatively wide surface among a plurality of surfaces forming the surface of the first semiconductor layer 110. Surface 170a is in contact with surface 110b. The fourth electrode 170 covers at least a part of the surface 110 b. In the example shown in FIG. 14, the fourth electrode 170 covers the entire surface 110 b. An opening may be formed in part of the fourth electrode 170.

A voltage is applied to the fourth electrode 170. The voltage applied to the fourth electrode 170 is the same as the voltage applied to the second semiconductor layer 120 shown in FIG.

In the semiconductor device 11, the semiconductor device 12, the semiconductor device 13, the semiconductor device 14, the semiconductor device 15 and the semiconductor device 16 described above, the semiconductor substrate 100 is changed to the semiconductor substrate 101 and the second semiconductor layer 120 is replaced with Four electrodes 170 may be disposed.

Similar to the semiconductor device 10 shown in FIG. 1, the semiconductor device 17 can reduce the number of required voltages.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments and their modifications. Additions, omissions, substitutions, and other modifications of the configuration are possible without departing from the spirit of the present invention. Also, the present invention is not limited by the above description, and is limited only by the scope of the attached claims.

According to the embodiments of the present invention, the semiconductor device can reduce the number of required voltages.

10, 11, 12, 13, 14, 15, 16, 17 semiconductor devices 100, 101, 1100, 1101, 1102 semiconductor substrates 110, 1110, 1113, 1115 first semiconductor layers 120, 1120 second semiconductor layers 111, 1111 first impurity layer 112, 1112, 1114 second impurity layer 130, 1130, 1131 insulating layer 140 first electrode 150 second electrode 160, 161, 162, 163, 164a, 164b, 165 third electrode 165a partial electrode 170 fourth electrode 1010, 1011, 1012 detector 1140 anode electrode 1150 cathode electrode 1160 gate electrode 1170 electrode 1650 first layer 1651 second layer

Claims (9)

A semiconductor substrate having a first main surface and a second main surface facing in opposite directions;
A first electrode and a second electrode disposed on the first major surface;
A conductive layer disposed on the second main surface or disposed in the semiconductor substrate to include the second main surface;
An insulating layer disposed on the first major surface;
A third electrode disposed on the first major surface between the first electrode and the second electrode via the insulating layer;
Have
The third electrode has a first region closest to the first electrode in the third electrode, and a second region closest to the second electrode in the third electrode,
When the first voltage applied to the first electrode is higher than the second voltage applied to the second electrode, a third voltage applied to the first region is the second voltage. Higher than the fourth voltage applied to the region,
When the first voltage applied to the first electrode is lower than the second voltage applied to the second electrode, a third voltage applied to the first region is the second voltage. Lower than the fourth voltage applied to the
A semiconductor device, wherein the first region and the second region are electrically connected to each other. The semiconductor device according to claim 1, wherein the third electrode is configured in a continuous structure connecting the first region and the second region. The second electrode is disposed around the first electrode,
The semiconductor device according to claim 2, wherein at least four strip-like third electrodes are arranged in parallel with a direction from the first electrode to the second electrode. The semiconductor device according to claim 3, wherein a width of the third electrode in the first region is larger than a width of the third electrode in the second region. The second electrode and the third electrode are disposed around the first electrode,
The semiconductor device according to claim 2, wherein the third electrode is disposed to intersect at a plurality of positions with imaginary straight lines passing through the first electrode and the second electrode. The semiconductor device according to claim 5, wherein the third electrode is arranged in a spiral shape. The semiconductor device according to claim 6, wherein a width of the third electrode in the first region is smaller than a width of the third electrode in the second region. The third electrode has a plurality of partial electrodes,
Each of the partial electrodes included in the plurality of partial electrodes includes a first layer and a second layer different in position in the direction perpendicular to the first major surface,
In the two partial electrodes adjacent in a direction parallel to the first main surface, the insulating layer between the first layer of one of the partial electrodes and the second layer of the other partial electrode Is placed,
The semiconductor device according to claim 1, wherein the first layer of the one partial electrode and the second layer of the other one of the partial electrodes constitute a capacitance. The third area is larger than the fourth area,
The third region is a region where the first layer and the second layer constituting the capacitor disposed at a position closest to the first electrode overlap with each other via the insulating layer.
The fourth region is a region where the first layer and the second layer constituting the capacitor disposed at a position closest to the second electrode overlap with each other via the insulating layer. The semiconductor device according to claim 1.

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