WO2019127007A1

WO2019127007A1 - Time-delay power supply system and electric device

Info

Publication number: WO2019127007A1
Application number: PCT/CN2017/118594
Authority: WO
Inventors: 秦威
Original assignee: 深圳市道通智能航空技术有限公司
Priority date: 2017-12-26
Filing date: 2017-12-26
Publication date: 2019-07-04

Abstract

A time-delay power supply system and an electric device, comprising: a power supply switch (1) and a power supply time-delay circuit (2), wherein one end of the power supply switch is connected to a cathode interface (PACK-) and the other end of the power supply switch is grounded; an input end of the power supply time-delay circuit is connected to an anode interface (PACK+) and an output end of the power supply time-delay circuit is connected to a control end of the power supply switch; the power supply time-delay circuit is used to transmit a power supply signal from the anode interface to the power supply switch at a time delay; and the power supply switch is used to conduct slowly under the control of the power supply signal transmitted by the power supply time-delay circuit at a time delay. The described system may prevent a peak signal generated within a short period of time from being transmitted to the main board of an electric device and causing damages thereto. The circuit is simple, has a small volume and high integration level, and is low cost without occupying a lot of space, thus being highly applicable to miniaturized electric devices.

Description

Delayed power supply system and electrical equipment

Technical field

The present application relates to the field of electronics, and in particular, to a time delay power supply system and a power consumption device.

Background technique

With the continuous development of various types of electrical equipment, such as terminals, drones, automobiles, etc., the electronic modules with built-in integration or configuration are increasing, and correspondingly, the requirements for power supply voltage stability of electric equipment are getting higher and higher.

In the case of drones, for example, most consumer and industrial drones are powered by multiple strings of high-rate batteries. Because of the high voltage of the battery and the high chemical activity of the battery, when the battery is inserted into the drone, At this time, some large peak voltages and currents will be generated. If it is not protected, it is easy to burn the components of the electrical equipment.

At present, the conventional method is to absorb these spike voltages and currents by using a filter capacitor with a large capacitance value on the end of the power device. However, such a large-capacity filter capacitor is usually large in size, for some miniaturized devices, such as no one. The miniaturization of the machine has limited space and it is impossible to configure large-capacity filter capacitors. Therefore, the above solution cannot be applied to miniaturized devices.

Summary of the invention

The present application provides a time delay power supply system and a power consumption device, which can reliably implement peak protection suitable for miniaturized equipment.

A first aspect of the present application is to provide a time delay power supply system, including: a power supply switch and a power supply delay circuit; wherein two ends of the power supply switch are respectively connected to a negative interface and a ground; and an input of the power supply delay circuit The terminal is connected to the positive interface, and the output end of the power supply delay circuit is connected to the control end of the power supply switch; the power supply delay circuit is configured to delay transmission of the power supply signal from the positive interface to the power supply switch; The power supply switch is configured to be turned on under the control of a power supply signal delayed transmission by the power supply delay circuit.

Preferably, the power supply delay circuit is an RC delay circuit.

Preferably, the power supply delay circuit includes: a power supply delay resistor and a power supply delay capacitor; one end of the power supply delay resistor is connected to a control end of the power supply switch and one end of the power supply delay capacitor, The other end of the power supply delay resistor is connected to the positive interface; the other end of the power supply delay capacitor is connected to the negative interface.

Preferably, the delay capacitor includes a first delay capacitor and a second delay capacitor connected in parallel.

Preferably, the time delay power supply system further includes: a first resistor connected between the positive terminal and the power supply delay resistor; and a second resistor connected between the negative terminal and the power supply delay resistor; One end of the first resistor is connected to the positive terminal, the other end of the first resistor is connected to the other end of the power supply delay resistor; one end of the second resistor is connected to the negative interface, and the other of the second resistor One end is connected to the other end of the power supply delay resistor.

Preferably, the time delay power supply system further includes: a Zener diode; a positive pole of the Zener diode is connected to the negative pole interface, and a cathode of the Zener diode is connected to the other end of the power supply delay resistor.

Preferably, the time delay power supply system further includes: a diode connected in parallel with the power supply delay resistor; a positive pole of the diode is connected to one end of the power supply delay resistor and one end of the power supply delay capacitor, A cathode of the diode is coupled to the other end of the supply delay resistor, the other end of the first resistor, and the other end of the second resistor.

Preferably, the power supply switch includes: a first NMOS transistor; a gate of the first NMOS transistor is connected to one end of the power supply delay resistor and one end of the power supply delay capacitor, and the first NMOS transistor The source is connected to the negative electrode interface, and the drain of the first NMOS transistor is grounded.

Preferably, the number of the power switches is two or more, and the two or more power switches are connected in parallel.

Preferably, the time delay power supply system further includes: an electrostatic protection capacitor; the static protection capacitor includes a first protection capacitor and a second protection capacitor connected in series; one end of the static protection capacitor is connected to the negative interface, and the static protection The other end of the capacitor is grounded.

Preferably, the time delay power supply system further includes: a communication switch and a communication delay circuit; the communication switch is connected between the battery communication interface and the device communication port; and the input end of the communication delay circuit is connected to the positive interface. An output end of the communication delay circuit is connected to a control end of the communication switch; the communication delay circuit is configured to delay transmission of a power supply signal from the positive interface to the communication switch, wherein the communication delay The delay time of the circuit is greater than the delay time of the power supply delay circuit; the communication switch is used to be turned on under the control of the power supply signal delayed transmission by the communication delay circuit.

Preferably, the communication switch comprises: a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor is connected to one end of the communication delay resistor, and a source and a battery of the second NMOS transistor a communication interface BAT-RX is connected, a drain of the second NMOS transistor is connected to a device communication port FC-TX; a gate of the third NMOS transistor is connected to one end of the communication delay resistor, the third NMOS The source of the tube is connected to the battery communication interface BAT-TX, and the drain of the third NMOS transistor is connected to the device communication port FC-RX.

Preferably, the communication delay circuit includes: a communication delay resistor, a communication delay capacitor, a PNP transistor, a third resistor, a fourth resistor, and a fifth resistor; and the communication delay resistor and the communication delay capacitor are connected in parallel One end of the communication delay resistor is connected to the positive interface, and the other end of the communication delay resistor is connected to the negative interface; the emitter of the PNP transistor is connected to one end of the communication delay resistor, the PNP transistor a collector connected to one end of the fifth resistor, a base of the PNP transistor being connected to one end of the third resistor; an other end of the third resistor and one end of the fourth resistor and the communication The other end of the time delay resistor is connected, the other end of the fourth resistor is connected to the negative electrode interface, and the other end of the fifth resistor is connected to the gates of the second NMOS transistor and the third NMOS transistor.

Preferably, the communication delay circuit includes: a communication delay resistor, a communication delay capacitor, a PMOS transistor, a third resistor, a fourth resistor, and a fifth resistor; and the communication delay resistor and the communication delay capacitor are connected in parallel One end of the communication delay resistor is connected to the positive interface, the other end of the communication delay resistor is connected to the negative interface; the source of the PMOS transistor is connected to one end of the communication delay resistor, the PMOS tube a drain connected to one end of the fifth resistor, a gate of the PMOS transistor being connected to one end of the third resistor; an other end of the third resistor and one end of the fourth resistor and the communication The other end of the time delay resistor is connected, the other end of the fourth resistor is connected to the negative electrode interface, and the other end of the fifth resistor is connected to the gates of the second NMOS transistor and the third NMOS transistor.

Preferably, the time delay power supply system further includes: a sixth resistor; one end of the sixth resistor is connected to the other end of the fifth resistor and the control end of the communication switch, and the other end of the sixth resistor Connect to the negative interface.

Preferably, the source of the second NMOS transistor is further connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the negative interface; the source of the third NMOS transistor is also connected to one end of the eighth resistor. The other end of the eighth resistor is connected to the negative interface.

A second aspect of the present application is to provide an electrical device including: a time delay power supply system as described above.

Preferably, the powered device is a drone.

The time delay power supply system and the electric equipment provided by the application include a power supply switch and a power supply delay circuit adopting a negative control mode, and the power supply switch is connected between the negative electrode interface and the grounding port of the electric equipment, and the power supply delay circuit is connected Between the positive terminal and the control terminal of the power switch. It can be understood that when the battery is loaded, since the power supply delay circuit delays the transmission of the power supply signal to the positive interface, the power supply switch is not turned on at this time, and the power supply circuit of the power supply device has not been formed, thereby avoiding the short-time generation. The spike signal is transmitted to the main board of the power device, and the circuit provided by the solution is simple and small in size, high in integration and low in cost, and does not need to occupy too much space, and can be well applied to miniaturized electric equipment, and effectively realized. Spike protection.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present application. Other figures may also be obtained from those of ordinary skill in the art in view of these figures.

1 to FIG. 4 are schematic structural diagrams of a time delay power supply system according to Embodiment 1 of the present application;

5A and FIG. 5B are schematic diagrams of the delay power supply system according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a time delay power supply system according to Embodiment 2 of the present application.

Detailed ways

The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present application. It is a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application are within the scope of the present disclosure.

All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. The terminology used herein is for the purpose of describing particular embodiments, and is not intended to be limiting. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The features of the embodiments and examples described below can be combined with each other without conflict.

1 is a schematic structural diagram of a time delay power supply system according to Embodiment 1 of the present application; as can be seen from FIG. 1 , the present embodiment provides a time delay power supply system for implementing miniaturization. The peak protection of the electrical equipment, specifically, the delayed power supply system includes:

a power supply switch 1 and a power supply delay circuit 2; wherein

The two ends of the power supply switch 1 are respectively connected to the negative interface PACK- and the ground; the input end of the power supply delay circuit 2 is connected with the positive interface PACK+, and the output end of the power supply delay circuit 2 is connected with the control end of the power supply switch 1;

The power supply delay circuit 2 is configured to delay the power supply signal from the positive interface PACK+ to the power supply switch 1;

The power supply switch 1 is configured to be slowly turned on under the control of the power supply signal delayed transmission by the power supply delay circuit 2.

In practical applications, electrical equipment includes, but is not limited to, electronic equipment such as drones, computers, and mobile phones. The time delay power supply system provided by the present application can be applied to the peak protection of various types of electrical equipment, and can be especially applied to miniaturized electrical equipment, such as drones. Taking the drone as an example, although the miniaturized device has a small space, it needs to be powered by a high-rate battery, so it is necessary to implement an effective and reliable spike protection for the device motherboard when the battery is inserted, and avoid the spike signal to the device. Cause damage.

Specifically, in order to implement battery power supply, the electrical device is usually configured with an external interface for connecting to the battery, that is, a positive and negative interface (PACK+/PACK-) of the powered device. When the battery is installed in the electrical device, the external positive and negative interfaces of the battery can be connected with the positive and negative interfaces of the powered device, and the power is supplied to the respective modules of the powered device through the positive and negative interfaces of the powered device.

For example, in the actual scenario, when the battery is installed in the electrical device, the power supply signal can reach the positive interface PACK+ of the powered device in a short time. However, due to the existence of the power supply delay circuit, the power supply signal has not yet reached the power supply switch. The control terminal, therefore, the power switch has not been turned on, and the power supply circuit of the power device has not been formed. Therefore, the spike signal generated at this time, such as spike current, spike voltage, etc., is not transmitted to the working circuit of the powered device. To avoid noise damage to the electrical equipment.

The structure of the power supply delay circuit 2 can be various, for example, it can be an RC delay circuit. Optionally, as shown in FIG. 2, on the basis of other embodiments, the power supply delay circuit 2 may include:

Power supply delay resistor R2 and power supply delay capacitor;

One end of the power supply delay resistor R2 is connected to the control end of the power supply switch 1 and one end of the power supply delay capacitor, and the other end of the power supply delay resistor R2 is connected to the positive interface PACK+;

The other end of the power supply delay capacitor is connected to the negative interface PACK-.

The power supply delay capacitor may be composed of at least one delay capacitor. The amount of the delay capacitor may be adjusted to adjust the capacitance of the power supply delay capacitor, thereby adjusting the delay time of the power supply delay. Optionally, when the power supply delay capacitor includes a plurality of delay capacitors, the plurality of delay capacitors are connected in parallel. For example, as shown in FIG. 2, the power supply delay capacitor may include a first delay capacitor C3 and a second delay capacitor C4 connected in parallel.

In the embodiment, the RC delay power supply circuit realizes the power supply of the power device during the plugging and unplugging of the battery, thereby avoiding damage to the power device caused by the spike signal generated in a short time of the battery insertion and removal, and effectively saving space.

Specifically, the power switch is used to implement conduction and disconnection of the power supply circuit of the power device. In practical applications, there are various ways to control the power supply switch, one is positive control and the other is negative control. Preferably, the power supply switch controlled by the negative pole is used in the present application. Specifically, the PMOS is used because the positive electrode is controlled, and the manufacturing cost of the PMOS is higher than that of the NMOS with the same performance, and even the PMOS with low internal resistance is difficult. Since the low internal resistance value of the NMOS is realized, it is preferable to use a low internal resistance NMOS as a power supply switch for a miniaturized high current device, for example, a drone.

Optionally, as shown in FIG. 3, on the basis of other embodiments, the power supply switch 1 includes: a first NMOS transistor Q1;

The gate of the first NMOS transistor Q1 is connected to one end of the power supply delay resistor R2 and one end of the power supply delay capacitor. The source of the first NMOS transistor Q1 is connected to the negative interface PACK-, and the drain of the first NMOS transistor Q1 is grounded.

In practical applications, the number of power switches 1 includes, but is not limited to, at least one. Alternatively, the number of the power supply switches 1 may be two or more. For example, as shown in FIG. 4, two power supply switches 1 (Q1 and Q2) are provided, and the plurality of power supply switches 1 may be connected in parallel. A larger current can be supported by setting multiple power switches in parallel.

In the present embodiment, the power supply switch controlled by the negative electrode can effectively reduce the cost and realize the low internal resistance switch, and is better suited for miniaturization of large current electric equipment.

Preferably, in order to achieve electrostatic protection against the power supply switch, as shown, the time delay power supply system further includes: an electrostatic protection capacitor;

The electrostatic protection capacitor includes a first protection capacitor C1 and a second protection capacitor C2 connected in series;

One end of the ESD protection capacitor is connected to the negative interface PACK-, and the other end of the ESD protection capacitor is grounded.

The number of the protection capacitors can be set as needed. This embodiment is only exemplified by two protection capacitors, and other implementations are not limited.

In this embodiment, the electrostatic protection of the power supply switch can be further realized by connecting the electrostatic protection capacitors at both ends of the power supply switch.

In addition, as shown in FIG. 4, as a preferred implementation manner, the time delay power supply system may further include:

a first resistor R1 connected between the positive terminal PACK+ and the power supply delay resistor R2, and a second resistor R3 connected between the negative terminal PACK- and the power supply delay resistor R2;

One end of the first resistor R1 is connected to the positive terminal PACK+, and the other end of the first resistor R1 is connected to the other end of the power supply delay resistor R2;

One end of the second resistor R3 is connected to the negative terminal PACK-, and the other end of the second resistor R3 is connected to the other end of the power supply delay resistor R2.

In the present embodiment, by providing the first resistor R1 and the second resistor R3 as the voltage dividing resistor, the reliability and stability of the peak protection can be improved.

Further, as shown in the figure, in order to prevent the voltage from being too high to damage the power supply switch, the time delay power supply system further includes: a Zener diode D2;

The anode of the Zener diode D2 is connected to the negative interface PACK-, and the cathode of the Zener diode D2 is connected to the other end of the power supply delay resistor R2.

The other end of the power supply delay resistor R2 refers to one end of the circuit structure away from the power supply switch. In combination with the foregoing embodiment, the Zener diode D2 is connected to the other end of the power supply delay resistor R2, and is also connected to the end of the first resistor R1 that is away from the positive interface PACK+ in the circuit structure, and is further away from the second resistor R3 in the circuit structure. One end of the negative interface PACK- is connected.

In this embodiment, by providing the Zener diode D2, a Zener diode is provided for the power supply switch to prevent the excessive surge voltage from damaging the power supply switch. It can be understood that the Zener diode D2 may not be provided when the power supply voltage is not very high.

In addition, as shown, the time delay power supply system further includes: a diode D1 in parallel with the power supply delay resistor R2;

The anode of the diode D1 is connected to one end of the power supply delay resistor R2 and one end of the power supply delay capacitor, the cathode of the diode D1 and the other end of the power supply delay resistor R2, the other end of the first resistor R1, and the other of the second resistor R3. Connected at one end.

Specifically, the diode D1 is a drain diode. When the battery is unplugged, the voltage of the power supply switch gate can be quickly discharged through the diode, thereby releasing the voltage of the gate, enabling the power switch to be quickly turned off, and avoiding repeated insertion and removal. Causes the failure of the power supply delay circuit.

In order to further illustrate the solution, the signal processing flow is described in conjunction with FIG. 4: as shown in the schematic diagram: two NMOS transistors of the power supply circuit are connected in parallel, the source of the NMOS transistor is connected to the negative interface PACK-, and the drain of the NMOS transistor is connected to the electrical device. Ground port GND; the gates of both NMOS transistors are connected to the RC delay circuit. Specifically, C1 and C2 are protection capacitors; C3 and C4 are delay capacitors; R2 is power supply delay resistor; D2 is a gate voltage regulator diode of NMOS tube to prevent excessive surge voltage from damaging the NMOS transistor; R1, R3 It is the voltage dividing resistor of the battery; D1 is a drain diode. When the battery is unplugged, the voltage of the gate of the NMOS transistor can be quickly discharged through the diode, thereby releasing the voltage of the gate and allowing the power supply circuit to be quickly cut off.

When the battery is installed in the electrical equipment, the power supply signal quickly reaches the positive interface PACK+. At this time, due to the existence of the RC delay circuit, the power supply signal is charged to the delay capacitors C3 and C4 through the power supply delay resistor R2. The gate voltage is still very low, so the NMOS transistors Q1 and Q2 are not yet turned on, and the power supply circuit of the powered device has not been formed yet.

In order to visually represent the technical effect of the present scheme, as shown by the waveform in FIG. 5A, the solid line is the voltage waveform of the positive interface PACK+, and the broken line is the voltage waveform of the NMOS transistor gate. It can be seen that the voltage of the positive interface PACK+ rises instantaneously when the battery is loaded, and under the action of the power supply delay circuit, the gate voltage of the NMOS transistor rises slowly and linearly, and the NMOS transistor is slowly turned on.

Subsequently, under the action of the power supply delay circuit, after Q1 and Q2 are slowly turned on, the negative interface PACK- is connected to the system ground GND of the powered device, and the power supply loop is formed. Correspondingly, as shown by the waveform in FIG. 5B, the solid line is the voltage waveform of the positive interface PACK+, and the broken line is the voltage waveform of the system ground GND of the powered device. It can be seen that the high voltage state duration of the system ground GND is the delay time of the power supply delay circuit.

It should be noted that the model and parameters of each component in the present application, for example, the resistance of the resistor, the capacitance of the capacitor, etc., can be set according to the needs of the actual circuit. For example, as shown in FIG. 4, the resistance of the power supply delay resistor R2 may be 200K ohms (Ω), the first protection capacitor C1 and the second protection capacitor C2, and the first delay capacitor C3 and the second delay. Capacitor C4 can have a capacitance of 0.1μF, the resistance of the first resistor R1 can be 3.3KΩ, the resistance of the second resistor R3 can be 5.1KΩ, and the model of the diode D1 can be 5819W.

Specifically, the length of the delay time can be realized by changing the resistance value of the power supply delay resistor and the capacitance value of the power supply delay capacitor in the power supply delay circuit. In practical applications, the delay time can be obtained by using the delay formula: delay time = -R * C * ln ((E - V) / E). Where: "-" is a negative sign indicating a time delay. The power supply delay resistor and the power supply delay capacitor are connected in series, R is the resistance value of the power supply delay resistor, C is the capacitance value of the power supply delay capacitor, E is the voltage between the power supply delay resistor and the power supply delay capacitor, and V is the power supply. The voltage to be reached between the delay capacitors, ln is the natural logarithm.

Assume that the resistance value R is 200K ohms, the capacitance value C is 0.2uf, assuming that the PACK+ voltage is 12V, correspondingly, E is 7.29V, and V is the general opening voltage of the NMOS transistor is 2V. The delay time can be obtained from the above formula. It is about 12.8ms.

The delay power supply system provided in this embodiment includes a power supply switch and a power supply delay circuit using a negative control mode, and the power supply switch is connected between the negative interface and the ground port of the power device, and the power supply delay circuit is connected to the positive interface and Between the control terminals of the power switch. It can be understood that when the battery is loaded, since the power supply delay circuit delays the transmission of the power supply signal to the positive interface, the power supply switch is not turned on at this time, and the power supply circuit of the power supply device has not been formed, thereby avoiding the short-time generation. The spike signal is transmitted to the main board of the power device, and the circuit provided by the solution is simple and small in size, high in integration and low in cost, and does not need to occupy too much space, and can be well applied to miniaturized electric equipment, and effectively realized. Spike protection.

In practical applications, the battery and the powered device are also provided with a communication interface to achieve communication between the two. Specifically, the device is internally configured with a device communication port (FC-TX/FC-RX) connected to the communication module. For the communication interface of the external battery, the external interface of the powered device is also configured for loading and loading. Battery communication interface (BAT-TX/BAT-RX) connected to the communication interface of the battery. Optionally, the form of the foregoing interface may specifically be a serial interface.

Specifically, in the negative control scenario, if the battery communication interface (BAT-TX/BAT-RX) is directly connected to the device communication port (FC-RX/FC-TX) of the powered device, there will be a moment when the battery is loaded. The voltage is reversed to the battery communication interface. If the voltage of the backfill exceeds the endurance of the internal chip of the battery, the battery chip may be damaged.

As shown in FIG. 6 , FIG. 6 is a schematic structural diagram of a delay power supply system according to Embodiment 2 of the present application. As shown in the embodiment, the time delay power supply system further includes : communication switch 3 and communication delay circuit 4;

The communication switch 3 is connected between the battery communication interface (BAT-TX/BAT-RX) and the device communication port (FC-RX/FC-TX);

The input end of the communication delay circuit 4 is connected to the positive interface PACK+, and the output end of the communication delay circuit 4 is connected to the control end of the communication switch 3;

The communication delay circuit 4 is configured to delay transmission of the power supply signal from the positive interface PACK+ to the communication switch 3, wherein the delay time of the communication delay circuit is greater than the delay time of the power supply delay circuit;

The communication switch 3 is configured to be slowly turned on under the control of the power supply signal delayed transmission by the communication delay circuit 4.

Similar to the principle of the power supply delay, the present embodiment sets a communication delay circuit between the positive terminal and the communication switch, and ensures that the delay time of the communication delay circuit is greater than the delay time of the power supply delay circuit.

It can be understood that since the voltage signal at the device communication port (FC-RX/FC-TX) is not controlled by the power switch, that is, when the battery is loaded, the high voltage signal can reach the device communication port (FC-RX/FC-TX). At this time, under the action of the communication delay circuit, the communication switch has not been turned on, so the high voltage signal will not be backed up to the battery through the battery communication interface (BAT-TX/BAT-RX) to avoid damage to the battery chip.

Specifically, since the delay time of the communication delay circuit in this embodiment is greater than the delay time of the power supply delay circuit, the battery communication interface (BAT-TX/BAT-RX) and the device communication port (FC) are formed after the power supply circuit is formed. -RX/FC-TX) will be slowly turned on, and the voltage signal after the power supply loop is formed is relatively stable, thereby avoiding adverse effects on the internal chip of the battery.

Similarly, the structure of the communication delay circuit can also be various. In combination with the application scenario of the embodiment, preferably, an RC delay circuit is used. As an example, the communication delay circuit 4 may include: a communication delay resistor and a communication delay capacitor;

One end of the communication delay resistor is connected to the positive interface PACK+, and the other end of the communication delay resistor is connected to the control end of the communication switch;

One end of the communication delay capacitor is connected to the other end of the communication delay resistor, and the other end of the communication delay capacitor is connected to the negative interface PACK-.

In this embodiment, the communication delay circuit is implemented by the RC delay, thereby preventing the reverse sink voltage from adversely affecting the battery.

Specifically, the communication switch is used to implement conduction and disconnection between the battery communication interface (BAT-TX/BAT-RX) and the device communication port (FC-RX/FC-TX). Preferably, as shown in FIG. 7, the communication switch 3 includes:

a second NMOS transistor Q5 and a third NMOS transistor Q6;

The gate of the second NMOS transistor Q5 is connected to one end of the communication delay resistor R11, the source of the second NMOS transistor Q5 is connected to the battery communication interface BAT-RX, and the drain of the second NMOS transistor Q5 is connected to the device communication port FC-TX. connection;

The gate of the third NMOS transistor Q6 is connected to one end of the communication delay resistor R11, the source of the third NMOS transistor Q6 is connected to the battery communication interface BAT-TX, and the drain of the third NMOS transistor Q6 is connected to the device communication port FC-RX. connection.

It should be noted that the present embodiment is merely an example performed on the basis of the previous embodiment. It can be understood that the structure of the communication switch in this embodiment can also be implemented in combination with other embodiments without conflict.

Further preferably, as shown in FIG. 7, the communication delay circuit 4 includes: a communication delay resistor R11, a communication delay capacitor C7, a PNP transistor Q7, a third resistor R13, a fourth resistor R14, and a fifth resistor R10;

The communication delay resistor R11 and the communication delay capacitor C7 are connected in parallel; one end of the communication delay resistor R11 is connected to the positive interface PACK+, and the other end of the communication delay resistor R11 is connected to the negative interface PACK-;

The emitter of the PNP transistor Q7 is connected to one end of the communication delay resistor R11, the collector of the PNP transistor Q7 is connected to one end of the fifth resistor R10, and the base of the PNP transistor Q7 is connected to one end of the third resistor R13;

The other end of the third resistor R13 is connected to one end of the fourth resistor R14 and the other end of the communication delay resistor R11, the other end of the fourth resistor R14 is connected to the negative interface, and the other end of the fifth resistor R10 is connected to the second NMOS transistor Q5 and The gate of the third NMOS transistor Q6 is connected.

Specifically, the PNP transistor Q7 is equivalent to isolating the gates of the second NMOS transistor Q5 and the third NMOS transistor Q6 to avoid the moment when the battery is loaded may cause the gates of the second NMOS transistor Q5 and the third NMOS transistor Q6. The voltage instantaneously exceeds the withstand voltage value, thereby damaging the communication switch.

In other embodiments, the PNP transistor can also be replaced with a PMOS transistor. Correspondingly, in one embodiment, the communication delay circuit 4 includes: a communication delay resistor R11, a communication delay capacitor C7, a PMOS transistor, a third resistor R13, a fourth resistor R14, and a fifth resistor R10;

The source of the PMOS transistor is connected to one end of the communication delay resistor R11, the drain of the PMOS transistor is connected to one end of the fifth resistor R10, and the gate of the PMOS transistor is connected to one end of the third resistor R13;

Specifically, reference may be made to FIG. 7 and the PNP transistor Q7 of FIG. 7 is replaced with a PMOS transistor. In this embodiment, the PMOS transistor is also equivalent to isolating the gates of the second NMOS transistor Q5 and the third NMOS transistor Q6 to avoid the moment when the battery is loaded, which may cause the second NMOS transistor Q5 and the third NMOS transistor Q6. The voltage of the gate momentarily exceeds the withstand voltage value, thereby damaging the communication switch.

Preferably, the time delay power supply system further includes: a sixth resistor R12; one end of the sixth resistor R12 is connected to the other end of the fifth resistor R10 and the control end of the communication switch, and the sixth resistor The other end of R12 is connected to the negative interface PACK-.

Further preferably, the source of the second NMOS transistor Q5 is further connected to one end of the seventh resistor R8, the other end of the seventh resistor R8 is connected to the negative interface; the source of the third NMOS transistor Q6 is also One end of the eight resistor R9 is connected, and the other end of the eighth resistor R9 is connected to the negative interface PACK-. Specifically, the seventh resistor R8 and the eighth resistor R9 serve as pull-down resistors of the communication switch, respectively, to stabilize the gate voltage of the communication switch.

In the above embodiment, the control signal of the communication switch can be stabilized to ensure the reliability of the communication delay.

To further illustrate the solution, the signal processing flow is illustrated in conjunction with FIG. 7:

As shown, BAT-RX and BAT-TX are battery communication interfaces, FC-RX and FC-TX are device communication ports, and C7 and R11 constitute delay circuits. Here, R8 and R9 are the pull-down resistors of the gates of Q5 and Q6, respectively. They function to stabilize the gate voltage. Q7 is equivalent to isolate the gates of Q5 and Q6 to avoid Q5 when the battery is powered on. And the voltage of the gate of Q6 instantaneously exceeds the withstand voltage value, thereby damaging Q5 and Q6. When the battery is just inserted, since Q5 and Q6 are not turned on, the high voltage of the device communication port cannot be reversed to the battery communication interface. When the communication delay is over, there will be a high voltage at the gates of Q5 and Q6. Even if the battery communication interface has a communication voltage of 3.3V, Q5 and Q6 can be normally opened, so that normal communication is not affected.

It should be noted that the model and parameters of each component in the present application, for example, the resistance of the resistor, the capacitance of the capacitor, etc., can be set according to the needs of the actual circuit. For example, as shown in FIG. 7, the second NMOS transistor Q5 and the third NMOS transistor Q6 may be 2N7002; the PNP transistor Q7 may be S8550; the communication delay resistor R11 may have a resistance of 10K ohms (Ω). ), the capacitance of the communication delay capacitor C can be 2.2μF, and the third resistor R13 is a reserved resistor (the resistance of the third resistor R13 is set to 0R in the figure), and the resistance of the fourth resistor R14 can be For 100KΩ, the resistance of the fifth resistor R10 can be 30KΩ, the resistance of the sixth resistor R12 can be 100KΩ, the resistance of the seventh resistor R8 can be 10KΩ, and the resistance of the eighth resistor R9 can be 10KΩ.

In addition, according to the aforementioned delay formula, it can be known that E is 12V. Since the turn-on voltage of the base of the PNP transistor is generally 0.7V, V is 11.3V, so the delay time of the communication delay circuit is about 62.5mS. Since the conduction internal resistance exists between the base and the emitter of the PNP transistor Q7, the resistance of the delay resistor of the communication delay circuit is low, and the actual test delay is about 20 ms, and the communication delay time is greater than The power supply delay time, thereby avoiding the backflush voltage to the battery communication interface, thereby damaging the battery components.

The delay power supply system provided in this embodiment includes a communication switch and a communication delay circuit connected between the battery communication interface and the communication port of the device, and is similar to the principle of the power supply delay. This embodiment is between the positive interface and the communication switch. The communication delay circuit is set, and the delay time of the communication delay circuit is ensured to be greater than the delay time of the power supply delay circuit, thereby avoiding the backflow voltage to the battery communication interface and realizing the protection of the battery.

The embodiment of the present application further provides an electrical device, including: the time delay power supply system according to any of the foregoing embodiments. In practical applications, the powered device can be a drone.

In the electrical equipment provided by the present application, the time delay power supply system includes a power supply switch and a power supply delay circuit adopting a negative control mode, and the power supply switch is connected between the negative electrode interface and the grounding port of the power device, and the power supply delay circuit is connected Between the positive terminal and the control terminal of the power switch. It can be understood that when the battery is loaded, since the power supply delay circuit delays the transmission of the power supply signal to the positive interface, the power supply switch is not turned on at this time, and the power supply circuit of the power supply device has not been formed, thereby avoiding the short-time generation. The spike signal is transmitted to the main board of the power device, and the circuit provided by the solution is simple and small in size, high in integration and low in cost, and does not need to occupy too much space, and can be well applied to miniaturized electric equipment, and effectively realized. Spike protection.

Claims

A time delay power supply system, comprising: a power supply switch and a power supply delay circuit;

The two ends of the power supply switch are respectively connected to the negative interface and the ground; the input end of the power supply delay circuit is connected to the positive interface, and the output end of the power supply delay circuit is connected to the control end of the power supply switch;

The power supply delay circuit is configured to delay transmission of a power supply signal from the positive interface to the power supply switch;

The power supply switch is configured to be turned on under the control of a power supply signal delayed transmission by the power supply delay circuit.
The time delay power supply system according to claim 1, wherein said power supply delay circuit is an RC delay circuit.
The delay power supply system according to claim 2, wherein the power supply delay circuit comprises: a power supply delay resistor and a power supply delay capacitor;

One end of the power supply delay resistor is connected to the control end of the power supply switch and one end of the power supply delay capacitor, and the other end of the power supply delay resistor is connected to the positive interface;

The other end of the power supply delay capacitor is connected to the negative interface.
The time delay power supply system according to claim 3, wherein the delay capacitor comprises a first delay capacitor and a second delay capacitor connected in parallel.
The time delay power supply system according to claim 3 or 4, wherein the time delay power supply system further comprises: a first resistor connected between the positive terminal and the power supply delay resistor, and a negative terminal connected a second resistance between the power supply delay resistor;

One end of the first resistor is connected to the positive terminal, and the other end of the first resistor is connected to the other end of the power supply delay resistor;

One end of the second resistor is connected to the negative interface, and the other end of the second resistor is connected to the other end of the power supply delay resistor.
The time delay power supply system according to claim 5, wherein the time delay power supply system further comprises: a Zener diode;

The anode of the Zener diode is connected to the cathode interface, and the cathode of the Zener diode is connected to the other end of the power supply delay resistor.
The time delay power supply system according to claim 5, wherein the time delay power supply system further comprises: a diode connected in parallel with the power supply delay resistor;

The anode of the diode is connected to one end of the power supply delay resistor and one end of the power supply delay capacitor, and the cathode of the diode and the other end of the power supply delay resistor, the other end of the first resistor, And connecting the other end of the second resistor.
The time delay power supply system according to any one of claims 3-7, wherein the power supply switch comprises: a first NMOS transistor;

a gate of the first NMOS transistor is connected to one end of the power supply delay resistor and one end of the power supply delay capacitor, and a source of the first NMOS transistor is connected to a negative interface, and the first NMOS transistor is connected The drain is grounded.
The time delay power supply system according to claim 8, wherein the number of the power supply switches is two or more, and the two or more power supply switches are connected in parallel.
The time delay power supply system according to claim 1, wherein the time delay power supply system further comprises: an electrostatic protection capacitor;

The electrostatic protection capacitor includes a first protection capacitor and a second protection capacitor connected in series;

One end of the static electricity protection capacitor is connected to the negative electrode interface, and the other end of the static electricity protection capacitor is grounded.
The time delay power supply system according to any one of claims 1 to 10, wherein the time delay power supply system further comprises: a communication switch and a communication delay circuit;

The communication switch is connected between the battery communication interface and the device communication port;

The input end of the communication delay circuit is connected to the positive interface, and the output end of the communication delay circuit is connected to the control end of the communication switch;

The communication delay circuit is configured to delay transmission of a power supply signal from the positive interface to the communication switch, wherein a delay time of the communication delay circuit is greater than a delay time of the power supply delay circuit;

The communication switch is configured to be turned on under the control of a power supply signal delayed transmission by the communication delay circuit.
The time delay power supply system according to claim 11, wherein the communication switch comprises: a second NMOS transistor and a third NMOS transistor;

a gate of the second NMOS transistor is connected to one end of the communication delay resistor, a source of the second NMOS transistor is connected to a battery communication interface BAT-RX, and a drain of the second NMOS transistor is in communication with a device. Port FC-TX connection;

a gate of the third NMOS transistor is connected to one end of the communication delay resistor, a source of the third NMOS transistor is connected to a battery communication interface BAT-TX, and a drain of the third NMOS transistor is in communication with a device. Port FC-RX connection.
The delay power supply system according to claim 12, wherein the communication delay circuit comprises: a communication delay resistor, a communication delay capacitor, a PNP transistor, a third resistor, a fourth resistor, and a fifth resistor;

The communication delay resistor and the communication delay capacitor are connected in parallel; one end of the communication delay resistor is connected to the positive interface, and the other end of the communication delay resistor is connected to the negative interface;

The emitter of the PNP transistor is connected to one end of the communication delay resistor, the collector of the PNP transistor is connected to one end of the fifth resistor, and the base of the PNP transistor and one end of the third resistor connection;

The other end of the third resistor is connected to one end of the fourth resistor and the other end of the communication delay resistor, and the other end of the fourth resistor is connected to the negative interface, and the other end of the fifth resistor is The gates of the second NMOS transistor and the third NMOS transistor are connected.
The delay power supply system according to claim 12, wherein the communication delay circuit comprises: a communication delay resistor, a communication delay capacitor, a PMOS transistor, a third resistor, a fourth resistor, and a fifth resistor;

The communication delay resistor and the communication delay capacitor are connected in parallel; one end of the communication delay resistor is connected to the positive interface, and the other end of the communication delay resistor is connected to the negative interface;

a source of the PMOS transistor is connected to one end of the communication delay resistor, a drain of the PMOS transistor is connected to one end of the fifth resistor, and a gate of the PMOS transistor and one end of the third resistor connection;

The other end of the third resistor is connected to one end of the fourth resistor and the other end of the communication delay resistor, and the other end of the fourth resistor is connected to the negative interface, and the other end of the fifth resistor is The gates of the second NMOS transistor and the third NMOS transistor are connected.
The time delay power supply system according to claim 13 or 14, wherein the time delay power supply system further comprises: a sixth resistor;

One end of the sixth resistor is connected to the other end of the fifth resistor and the control end of the communication switch, and the other end of the sixth resistor is connected to the negative interface.
The time delay power supply system according to claim 15, wherein

The source of the second NMOS transistor is further connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the negative interface;

The source of the third NMOS transistor is also connected to one end of the eighth resistor, and the other end of the eighth resistor is connected to the negative interface.
A powered device, comprising: the time delay power supply system according to any one of claims 1-16.
The electrical device according to claim 17, wherein said powered device is a drone.