WO2019024340A1

WO2019024340A1 - Stress sensor structure and preparation method therefor

Info

Publication number: WO2019024340A1
Application number: PCT/CN2017/112857
Authority: WO
Inventors: 尹雯; 杨恒; 豆传国; 张文奇; 林挺宇; 曹立强
Original assignee: 华进半导体封装先导技术研发中心有限公司
Priority date: 2017-08-03
Filing date: 2017-11-24
Publication date: 2019-02-07
Also published as: US20210223122A1; CN107564890A; CN107564890B; US11067459B1

Abstract

Disclosed are a stress sensor structure and a preparation method therefor. The stress sensor structure comprises: a substrate (10); a blind hole provided on a first surface of the substrate; a first piezoresistive layer (30) and a second piezoresistive layer (50) arranged on a side surface of the blind hole, wherein connections are made at the bottom of the first piezoresistive layer and the second piezoresistive layer, and the first piezoresistive layer and the second piezoresistive layer are formed of a material having a piezoresistive effect; a second insulation layer (40) arranged between the first piezoresistive layer and the second piezoresistive layer; a first electrode (70) arranged on the first surface of the substrate and connected to the first piezoresistive layer; and a second electrode (80) arranged on the first surface of the substrate and connected to the second piezoresistive layer. The resistance measured by externally applying voltage to the first electrode and the second electrode can be used for representing the stress of a TSV structure, especially the axial stress, and thus, the stress sensor can be used for measuring the stress of the TSV structure.

Description

Stress sensor structure and manufacturing method thereof

Technical field

The present invention relates to the field of semiconductor technology, and in particular, to a stress sensor structure and a method of fabricating the same.

Background technique

The through silicon via interconnect (English full name: Through Silicon Via, TSV for short) technology is an advanced packaging technology that realizes vertical interconnection of layers of chips. Through vertical interconnection, the distance of information circulation can be shortened, the working frequency of the chip can be improved, the power consumption of the chip can be reduced, and the integration degree of the chip package can be improved. The TSV structure has been widely used in imaging sensors, high-speed logic memory chips, multi-core processors and the like.

A typical TSV structure is to connect the layers of the chip through a conductive metal pillar (such as a copper pillar) through a substrate (such as a silicon wafer). On the one hand, the difference in thermal expansion coefficient between the conductive metal and the substrate is large; on the other hand, the TSV structure has a large thermal stress due to the fabrication process of the TSV structure. Large thermal stress can significantly affect the performance of integrated circuit chips. For example, the carrier mobility of a single crystal silicon crystal orientation is a function of stress; large thermal stress also has a serious impact on the reliability of the TSV structure. Therefore, measuring the stress of the TSV structure and studying the effect of the fabrication process of the TSV structure on thermal stress is an important method to improve the performance and reliability of the integrated current chip.

The Chinese patent document (CN 104724662 A) discloses a polysilicon stress sensor and a method of fabricating the same. The method first forms a silicon hole structure having a first depth on a surface of the silicon substrate; then forming a first barrier layer on the surface of the silicon substrate and the surface of the silicon via structure, and then removing the first barrier layer at the bottom of the silicon via structure and silicon The hole structure is etched to a second depth; a polysilicon layer is formed on the surface of the first barrier layer, the lower sidewalls and the bottom of the silicon via structure. The stress sensor fabricated by the method uses a silicon substrate as an electrode of the force sensitive resistor, and measures the stress of the TSV structure by a change in resistance between the silicon substrate and the polysilicon layer. However, the measurement accuracy of the stress sensor is greatly affected by the silicon substrate, and the substrate must use a heavily doped silicon wafer of the same type as the polysilicon doping to obtain a more accurate Measurement results. It can be seen that the stress sensor fabricated by the method is difficult to achieve the stress measurement of the TSV structure which is generally fabricated by using a common silicon substrate.

The Chinese patent document (CN 106935526 A) discloses a polysilicon stress sensor structure for a silicon via interconnection and a method of fabricating the same. The method first forms an annular deep groove in the silicon substrate; and fills the polysilicon twice in the deep trench to form a polysilicon stress sensor, thereby avoiding the use of the silicon substrate as the stress sensor electrode, improving the measurement accuracy of the stress sensor, and also canceling the The silicon wafer doping type and concentration limit can be used to measure the axial stress of the TSV structure made by ordinary silicon wafers. However, the method requires high filling of the annular deep groove by polysilicon, and it is generally difficult to achieve non-porous filling, so that the polysilicon distribution in the stress sensor formed by the method is uneven, thereby significantly affecting the measurement accuracy of the stress sensor; The polysilicon layer with these holes is adjacent to the conductive metal posts of the TSV structure, making it difficult to detect these holes by non-destructive measurement methods.

This patent proposes a new structure of sidewall double-layer polysilicon sensor and a new processing method thereof. A polysilicon stress sensor insulated from a silicon substrate can be fabricated on the sidewall of the TSV.

Summary of the invention

In view of this, the embodiment of the invention provides a stress sensor structure and a manufacturing method thereof, so as to solve the defect that the existing stress sensor has low measurement accuracy.

A first aspect of the present invention provides a stress sensor structure including: a substrate; a blind via disposed on the first surface of the substrate; a first piezoresistive layer and a second piezoresistive layer disposed in the blind via a side surface, the first piezoresistive layer and the second piezoresistive layer are connected at a bottom of each layer; the first piezoresistive layer and the second piezoresistive layer are formed of a material having a piezoresistive effect; a second insulating layer disposed between the first piezoresistive layer and the second piezoresistive layer; a first electrode disposed on the first surface of the substrate and connected to the first piezoresistive layer; And a second electrode disposed on the first surface of the substrate and connected to the second piezoresistive layer.

Optionally, a first insulating layer is further included between the first piezoresistive layer and the substrate.

Optionally, a third insulating layer is further disposed on a side of the second piezoresistive layer facing the blind hole.

Optionally, the blind hole is filled with a conductive metal.

A second aspect of the present invention provides a method of fabricating a stress sensor structure, including: lining a first surface of the bottom forming a blind hole; a first piezoresistive layer formed on a sidewall of the blind hole; a second insulating layer formed on a surface of the first piezoresistive layer, a bottom of the second insulating layer being higher than a bottom of the first piezoresistive layer; a second piezoresistive layer formed on a sidewall of the blind via, the second piezoresistive layer being connected to a bottom of the first piezoresistive layer; The first surface is provided with a first electrode connected to the first piezoresistive layer, and a second electrode connected to the second piezoresistive layer is disposed on the first surface of the substrate.

Optionally, the first piezoresistive layer is formed on a sidewall of the blind via; a second insulating layer is formed on a surface of the first piezoresistive layer, and a bottom of the second insulating layer is higher than the first a bottom step of the piezoresistive layer, comprising: forming a first piezoresistive layer on the sidewall and the bottom of the blind via; forming a second insulating layer on the sidewall and the bottom of the blind via; removing the bottom of the blind via a predetermined area of the first piezoresistive layer and the second insulating layer, the first predetermined area being less than or equal to an open area of the blind via.

Optionally, the step of forming a second piezoresistive layer on the sidewall of the blind via, the second piezoresistive layer being connected to the bottom of the first piezoresistive layer, comprising: in the blind via Forming a second piezoresistive layer on the sidewall and the bottom; removing the second piezoresistive layer of the second predetermined area of the bottom of the blind hole, the second predetermined area being less than or equal to the opening area of the blind hole, and The second predetermined area is smaller than the first predetermined area.

Optionally, after the step of forming a blind via on the first surface of the substrate, before the step of forming the first piezoresistive layer on the sidewall of the blind via, further comprising: in the blind via The sidewall and the bottom form a first insulating layer.

Optionally, after the step of forming a second piezoresistive layer on the sidewall of the blind via, further comprising: forming a third insulating layer on the surface of the second piezoresistive layer.

Optionally, after the step of forming a third insulating layer on the surface of the second piezoresistive layer, the method further comprises: filling the blind hole with a conductive metal.

According to the stress sensor structure provided by the embodiment of the present invention, the first piezoresistive layer and the second piezoresistive layer are separated by the second insulating layer and are only connected at the bottom, so that when a voltage is applied to the first electrode and the second electrode, the current is Flowing through the first electrode, the first piezoresistive layer, the second piezoresistive layer and the second electrode in sequence, since the first piezoresistive layer and the second piezoresistive layer have a piezoresistive effect, therefore, through the first electrode and the first The resistance measured by the application of the voltage to the two electrodes can be used to characterize the stress of the TSV structure, especially the axial stress, which in turn can be used to measure the stress of the TSV structure.

DRAWINGS

The features and advantages of the present invention are more clearly understood from the following description of the drawings.

Figure 1 shows a schematic view of forming a blind via on the surface of a substrate;

Figure 2 shows a schematic view of forming a first piezoresistive layer on the sidewall of the blind via;

Figure 3 is a schematic view showing the formation of a second insulating layer on the surface of the first piezoresistive layer;

4 is a schematic view showing the use of a photoresist to remove a first piezoresistive layer and a second insulating layer at the bottom of a blind via;

FIG. 5 is a schematic view showing a structure formed by removing a first piezoresistive layer and a second insulating layer at the bottom of a blind via hole by using a photoresist;

Figure 6 is a schematic view showing the formation of a second piezoresistive layer on the sidewalls and the bottom of the blind via;

7 is a schematic view showing a structure formed by removing a second piezoresistive layer at the bottom of a blind via with a photoresist;

8 is a schematic view showing a third insulating layer formed on a surface of a second piezoresistive layer and a first electrode and a second electrode are disposed;

Figure 9 is a schematic view showing a first insulating layer, a second insulating layer and a third insulating layer on the first surface of the substrate;

Figure 10 is a view showing the position of the first electrode and the second electrode on the first surface of the substrate;

Figure 11 shows a schematic view of filling a conductive metal in a blind via;

Figure 12 shows a schematic view of the second surface of the substrate being thinned.

Detailed ways

In order to make the objects, advantages, and preparation methods of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings in which Preferred structural materials are apparent, and the described embodiments are a part of the embodiments of the invention, rather than all of the embodiments. It should be noted that the embodiments described with reference to the drawings are exemplary, and the structural materials indicated in the embodiments are also exemplary, and are only used for solving The present invention is not to be construed as being limited to the details of the invention. All other embodiments obtained by a person skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Embodiment 1

Embodiments of the present invention provide a stress sensor structure. As shown in FIG. 8, the stress sensor includes a substrate 10 and a blind via disposed on the first surface of the substrate.

A first piezoresistive layer 30 and a second piezoresistive layer 50 are disposed on the blind hole side surface, and the first piezoresistive layer 30 and the second piezoresistive layer 50 are connected at the bottom of each layer. A second insulating layer 40 is disposed between the first piezoresistive layer 30 and the second piezoresistive layer 50. The first piezoresistive layer 30 and the second piezoresistive layer 50 are formed of a material having a piezoresistive effect.

Optionally, the first piezoresistive layer 30 and the second piezoresistive layer 50 are polysilicon. The piezoresistive layer formed by polysilicon is relatively uniform, so that the measurement accuracy of the polysilicon stress sensor is greater than that of the stress sensor prepared by other materials. In addition, the polysilicon can withstand higher temperatures, so that the conductive metal can be filled in the blind via to form the conductive pillar without being affected by the temperature of the conductive metal, thereby avoiding the stress sensor measurement error caused thereby.

A first electrode 70 is disposed on the first surface of the substrate and is connected to the first piezoresistive layer 30. A second electrode 80 is further disposed on the first surface of the substrate to be coupled to the second piezoresistive layer 50.

Optionally, a first insulating layer 20 is further included between the first piezoresistive layer 30 and the substrate 10 to prevent the substrate 10 (eg, the substrate 10 from being a silicon substrate) from affecting the measurement accuracy of the stress sensor.

Optionally, a third insulating layer 60 is further disposed on a side of the second piezoresistive layer 50 facing the blind via to isolate the second piezoresistive layer 50 from the conductive metal filled in the blind via.

As an alternative embodiment of this embodiment, the blind via is filled with a conductive metal such as copper.

Further, the second surface of the substrate 10 (opposite the first surface) may also be thinned to expose the filled conductive metal to form a TSV via structure.

When the stress sensor is used to measure a certain structure (for example, filling a conductive metal in a blind hole) or a stress caused by a step (for example, annealing), before the structure is formed or before the step is performed, the first electrode is passed. Measuring the voltage with the second electrode Resisting; then forming the structure or performing this step, and measuring the second resistance in the same manner (ie, applying a voltage between the first electrode and the second electrode). The stress caused by the structure or the step is determined according to the difference between the first resistance and the second resistance.

Alternatively, the method of measuring the electrical resistance between the first electrode and the second electrode may employ the Wheatstone bridge method.

In the above stress sensor structure, the first piezoresistive layer and the second piezoresistive layer are separated by the second insulating layer and connected only at the bottom, so that when a voltage is applied to the first electrode and the second electrode, current flows through the first electrode in sequence. a first piezoresistive layer, a second piezoresistive layer, and a second electrode. Since the first piezoresistive layer and the second piezoresistive layer have a piezoresistive effect, by applying a voltage to the first electrode and the second electrode The measured resistance can be used to characterize the stress of the TSV structure, especially the axial stress. It can be seen that the above stress sensor can be used to measure the stress of the TSV structure.

Embodiment 2

The embodiment of the invention provides a method for fabricating a stress sensor structure for fabricating the stress sensor structure of the first embodiment. The method comprises the following steps:

Step S101: forming a blind hole on the first surface of the substrate.

Step S102: forming a first piezoresistive layer on the sidewall of the blind via.

As shown in FIG. 2, 10 is a substrate, and 30 is a first piezoresistive layer. When the substrate 10 is better insulated from the first piezoresistive layer 30, the first piezoresistive layer 30 may be directly formed on the surface of the substrate; when the substrate 10 is a silicon substrate, the stress sensor is not affected by the substrate. An insulating layer may be disposed on the surface of the first piezoresistive layer 30 and the substrate 10.

Step S103: forming a second insulating layer on the surface of the first piezoresistive layer, the bottom of the second insulating layer being higher than the bottom of the first piezoresistive layer.

As shown in FIG. 3, 40 is a second insulating layer. The portion of the second insulating layer 40 at the bottom of the blind via is higher than the portion of the first piezoresistive layer 30 at the bottom of the blind via, thereby exposing the first piezoresistive layer 30.

Step S104: forming a second piezoresistive layer on the sidewall of the blind via, and the second piezoresistive layer is connected to the bottom of the first piezoresistive layer.

As shown in FIG. 7, 50 is a second piezoresistive layer. The portion of the second piezoresistive layer 50 at the bottom of the blind via is connected to the portion of the first piezoresistive layer 30 at the bottom of the blind via. It should be added that the first piezoresistive layer 30 and the second piezoresistive layer 50 may be connected at the bottom of the blind hole, or may be connected at the middle of the side wall of the blind hole and other positions of the side wall, which is not limited in the present application. The measured stress is the average stress at the upper surface of the blind hole to the joint position (the joint position of the first piezoresistive layer and the second piezoresistive layer).

Step S105: the first surface of the substrate is provided with a first electrode connected to the first piezoresistive layer, and a second electrode connected to the second piezoresistive layer is disposed on the first surface of the substrate.

As shown in FIG. 8, 70 is a first electrode connected to the first

piezoresistive layer

30, and 80 is a second electrode connected to the second piezoresistive layer 50.

In the above method for manufacturing the stress sensor, since the first piezoresistive layer and the second piezoresistive layer are formed on the inner wall surface of the blind hole, and are not formed by filling the annular deep groove, the manufacturing method is simple, and the formed piezoresistive layer is relatively uniform. And there is no hole between the first piezoresistive layer and the second piezoresistive layer; the limitation of the doping type and concentration of the silicon wafer is removed, and the measurement of the axial stress of the TSV structure made by the ordinary silicon wafer can be realized.

Embodiment 3

Another embodiment of the present invention provides a method for fabricating a stress sensor structure for fabricating the stress sensor structure of the first embodiment. The method comprises the following steps:

Step S201: forming a blind hole on the first surface of the substrate.

The substrate may be etched using a dry etch process or a wet etch process to form a blind via.

Step S202: forming a first insulating layer on the sidewall and the bottom of the blind via.

As shown in FIG. 1, 10 is a substrate, 20 is a first insulating layer, and a blind hole is disposed on the first surface of the substrate 10. The first insulating layer 20 covers the sidewall and the bottom of the blind hole. In order to facilitate the performance of the process steps, the first insulating layer 20 may also cover the area around the blind vias on the first surface of the substrate. The first insulating layer 20 may be silicon oxide or silicon nitride, or may be a stacked structure of silicon oxide and silicon nitride. The first insulating layer 20 may be formed by thermal oxidation or LPCVD (English name: Low Pressure Chemical Vapor Deposition, Chinese: low pressure chemical vapor deposition).

Step S203: forming a first piezoresistive layer on the sidewall and the bottom of the blind hole. The first piezoresistive layer is formed of a material having a piezoresistive effect.

As shown in FIG. 2, 30 is a first piezoresistive layer. The first piezoresistive layer 30 covers all of the bottom of the blind hole. In order to facilitate the execution of the process step, the first piezoresistive layer 30 may also cover the first surface of the blind via or the first An area around the blind hole on an insulating layer. The first piezoresistive layer 30 can be formed by LPCVD.

Step S204: forming a second insulating layer on the sidewall and the bottom of the blind hole.

As shown in FIG. 3, 40 is a second insulating layer. The second insulating layer 40 covers all of the bottom of the blind vias. To facilitate performing the process steps, the second insulating layer 40 may also cover the area around the blind vias on the first surface of the substrate. The second insulating layer 40 may be silicon oxide or silicon nitride, or may be a stacked structure of silicon oxide and silicon nitride. The second insulating layer 40 may be formed by thermal oxidation or LPCVD.

Step S205: removing the first piezoresistive layer and the second insulating layer of the first predetermined area at the bottom of the blind hole, the first predetermined area being less than or equal to the opening area of the blind hole.

As shown in FIG. 5, the first piezoresistive layer 30 and the second insulating layer 40 at the bottom of the blind via are removed to obtain a blind via structure as shown in FIG. When the first predetermined area is smaller than the opening area of the blind hole, both the first piezoresistive layer 30 and the second insulating layer 40 protrude toward the center of the blind hole, and the first piezoresistive layer 30 is exposed, as shown in FIG. 5; When the first predetermined area is equal to the opening area of the blind hole, the second insulating layer 40 only retains the sidewall and does not protrude toward the center of the blind hole, and the first piezoresistive layer 30 protrudes toward the center of the blind hole and exposes the first piezoresistive Layer 30.

Since the aspect ratio of the blind via is up to 10:1, the process of conventional photolithography and the like is difficult to implement step S205, and the first piezoresistive layer 30 and the second insulating layer 40 at the bottom of the blind via can be removed by the method shown in FIG.

As shown in FIG. 4, a

photoresist

01, 02 is applied to the first surface of the substrate and the blind via is a photolithographic plate, and 03 is a light transmissive or opaque region on the photolithographic plate, the area of which is the first predetermined The areas are equal, or slightly smaller than the first predetermined area (the difference in size is greater than the difference in lithographic alignment). The photoresist corresponding to the 03 region is removed during exposure. On the basis of this, the bottom of the blind via is etched with the remaining photoresist as a mask layer, for example, deep reactive ion etching or ion bombardment can be used. . The photoresist 01 may be a dry film photoresist or a negative photoresist.

When the photoresist is a negative thin photoresist, the negative photoresist is fixed after exposure, and the photoresist in the opaque region is removed during development, and the photoresist in the blind via is poor in light transmittance of the thin adhesive. The photoresist is deposited so thick that the photoresist in the light-transmissive area at the edge of the blind hole will remain only on the surface, and the rest will also be removed during development. The use of a negative thin photoresist method avoids the problem of scattering causing inaccurate bottom dimensions.

Step S206: forming a second piezoresistive layer on the sidewall and the bottom of the blind hole. The second piezoresistive layer is formed of a material having a piezoresistive effect.

As shown in FIG. 6, 50 is a second piezoresistive layer. The second piezoresistive layer 50 may cover all of the bottom of the blind hole, or may cover only the edge of the bottom of the blind hole, which is not limited in the present application. To facilitate performing the process steps, the second piezoresistive layer 50 can also cover areas around the blind vias on the first surface of the substrate. The second piezoresistive layer 50 can be formed by LPCVD.

Since the first piezoresistive layer 30 at the bottom of the blind via has been exposed after step 205, the second piezoresistive layer 50 formed in step S206 is necessarily connected to the first piezoresistive layer 30.

Step S207: removing the second piezoresistive layer of the second predetermined area at the bottom of the blind hole, the second predetermined area is less than or equal to the opening area of the blind hole, and the second predetermined area is smaller than the first predetermined area.

It should be emphasized that the opening area of the blind hole of this step is smaller than the opening area of the blind hole in step S205, and thus the second predetermined area is smaller than the first predetermined area.

When the second predetermined area is smaller than the opening area of the blind hole, the second piezoresistive layer 50 protrudes toward the center of the blind hole, as shown in FIG. 7; when the second predetermined area is equal to the open area of the blind hole, the second piezoresistive layer 50 Does not protrude to the center of the blind hole.

The second piezoresistive layer 50 at the bottom of the blind via can be removed by the method shown in FIG. 4, that is, the

photoresist

01, 02 is used as a photolithography plate, and the photolithography is performed on the first surface and the blind via of the substrate. The light transmissive or opaque region on the plate has an area equal to the second predetermined area or slightly smaller than the second predetermined area (the difference in size is greater than the difference in lithographic alignment). The photoresist corresponding to the 03 region is removed during exposure. On the basis of this, the bottom of the blind via is etched with the remaining photoresist as a mask layer, for example, deep reactive ion etching or ion bombardment can be used. . The photoresist 01 may be a dry film photoresist or a negative thin photoresist.

When the photoresist is a negative thin photoresist, the negative photoresist is fixed after exposure, and the photoresist in the opaque region is removed during development, and the photoresist in the blind via is poor in light transmittance of the thin adhesive. The photoresist is deposited so thick that the photoresist in the light-transmissive area at the edge of the blind hole will remain only on the surface, and the rest will also be removed during development. The use of a negative thin photoresist method can avoid the problem that ultraviolet light hardly penetrates the photoresist accumulated in the blind via when the positive photoresist is exposed.

Removing the second piezoresistive layer at the bottom of the blind via can reduce the unnecessary area of the piezoresistive layer, thereby reducing parasitic capacitance. It should be noted that the manufacturing method provided by the embodiment of the present invention may also eliminate the need to remove the second piezoresistive layer at the bottom of the blind hole.

Step S208: forming a third insulating layer on the surface of the second piezoresistive layer.

As shown in FIG. 8, 60 is a third insulating layer. Since the second piezoresistive layer 50 remains only on the sidewall of the blind via before step S208, the third insulating layer formed in step S208 is also only on the sidewall of the blind via. Specifically, a third insulating layer may be formed on the sidewalls and the bottom of the blind hole, and then the insulating layer at the bottom of the blind hole is removed. The third insulating layer 60 may be silicon oxide or low stress silicon nitride, or may be a stacked structure of silicon oxide and silicon nitride. The third insulating layer 60 may be formed by thermal oxidation or LPCVD.

Since the bottom of the blind via is the first insulating layer before step S208, the third insulating layer may not cover the bottom of the blind via. Alternatively, as a modification of step S208, in order to facilitate the execution of the process step, a third insulating layer may be formed on both the sidewall and the bottom of the blind via.

Step S209: a first surface of the substrate is provided with a first electrode connected to the first piezoresistive layer, and a second electrode connected to the second piezoresistive layer is disposed on the first surface of the substrate.

As shown in FIG. 8, 70 is a first electrode connected to the first

piezoresistive layer

The method of forming the first electrode and the second electrode may be first forming a contact window on the surface of the substrate by photolithography or etching, and then forming a first electrode and a method by using an aluminum sputtering method and a wet etching method at a position of the contact window. Two electrodes.

9 shows a schematic view of a first insulating layer 20, a second insulating layer 40, and a third insulating layer 60 on a first surface of the substrate, wherein the dashed circle is a blind via opening. It should be noted that each insulating layer may have various shapes; each layer size and coverage relationship may also be other different situations, and only the first insulating layer 20 is required to isolate the substrate 10 and the first piezoresistive layer 30 and the second insulating layer. The isolation of the first piezoresistive layer 30 and the second piezoresistive layer 50 and the third insulating layer 60 can isolate the conductive metal filled in the blind via and the second piezoresistive layer 50. FIG. 9 shows only one shape design and a covering relationship of each insulating layer, that is, the third insulating layer cover 60 covers the second insulating layer 40, and the second insulating layer 40 covers the first insulating layer 20. on. Figure 10 is a schematic view showing the position of the first electrode and the second electrode on the first surface of the substrate.

Step S210: filling the blind holes with a conductive metal.

As shown in FIG. 11, 90 is a conductive metal. The conductive metal can be copper.

Step S211: thinning the second surface of the substrate to expose the first piezoresistive layer or the filled conductive metal. The second surface is disposed opposite the first surface.

As shown in FIG. 12, after the second surface is thinned, the blind via becomes a through hole penetrating the first surface and the second surface, and the bottom of the first insulating layer 20 is removed to expose the first piezoresistive layer 30 or The filled conductive metal forms a TSV via structure.

While the invention has been described with respect to the exemplary embodiments and the embodiments of the present invention, various modifications, alternatives and modifications can be made to the embodiments without departing from the spirit and scope of the invention. Such modifications and variations are intended to be included within the scope of the appended claims. For other examples, those of ordinary skill in the art will readily appreciate that the order of process steps may vary while remaining within the scope of the invention.

Further, the scope of application of the present invention is not limited to the process, mechanism, manufacture, composition of matter, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, it will be readily understood by those skilled in the art that the processes, mechanisms, manufactures, compositions, means, methods, or steps that are presently present or will be developed in the The corresponding embodiments described have substantially the same function or substantially the same results, which can be applied in accordance with the invention. Therefore, the appended claims are intended to cover such modifications, such structures, structures,

Claims

A stress sensor structure, comprising:

Substrate

a blind hole disposed on the first surface of the substrate;

a first piezoresistive layer and a second piezoresistive layer are disposed on the blind hole side surface, and the first piezoresistive layer and the second piezoresistive layer are connected at a bottom of each layer; the first piezoresistive layer And the second piezoresistive layer is formed of a material having a piezoresistive effect;

a second insulating layer disposed between the first piezoresistive layer and the second piezoresistive layer;

a first electrode disposed on the first surface of the substrate and connected to the first piezoresistive layer;

The second electrode is disposed on the first surface of the substrate and connected to the second piezoresistive layer.
The stress sensor structure of claim 1 further comprising a first insulating layer between the first piezoresistive layer and the substrate.
The stress sensor structure according to claim 1, wherein a third insulating layer is further disposed on a side of the second piezoresistive layer facing the blind hole.
The stress sensor structure of claim 3 wherein said blind via is filled with a conductive metal.
A method for fabricating a stress sensor structure, comprising:

Forming a blind hole in the first surface of the substrate;

Forming a first piezoresistive layer on a sidewall of the blind via;

Forming a second insulating layer on a surface of the first piezoresistive layer, a bottom of the second insulating layer being higher than a bottom of the first piezoresistive layer;

Forming a second piezoresistive layer on a sidewall of the blind via, the second piezoresistive layer being connected to a bottom of the first piezoresistive layer;

The first surface of the substrate is provided with a first electrode connected to the first piezoresistive layer, and a second electrode connected to the second piezoresistive layer is disposed on the first surface of the substrate.
The method of fabricating a stress sensor structure according to claim 5, wherein the first piezoresistive layer is formed on a sidewall of the blind via; and a second insulating layer is formed on a surface of the first piezoresistive layer The bottom of the second insulating layer is higher than the bottom portion of the first piezoresistive layer, and includes:

Forming a first piezoresistive layer on a sidewall and a bottom of the blind hole;

Forming a second insulating layer on the sidewall and the bottom of the blind hole;

And removing the first piezoresistive layer and the second insulating layer of the first predetermined area of the bottom of the blind hole, the first predetermined area being less than or equal to an opening area of the blind hole.
The method of fabricating a stress sensor structure according to claim 5, wherein the second piezoresistive layer is formed on a sidewall of the blind via, the second piezoresistive layer and the first piezoresistive layer The steps of connecting the bottom of the layer include:

Forming a second piezoresistive layer on the sidewall and the bottom of the blind hole;

Removing the second piezoresistive layer of the second predetermined area of the bottom of the blind hole, the second predetermined area is less than or equal to the opening area of the blind hole, and the second predetermined area is smaller than the first predetermined area .
The method of fabricating a stress sensor structure according to claim 5, wherein after the step of forming a blind via on the first surface of the substrate, the first piezoresistive is formed on the sidewall of the blind via Before the steps of the layer, it also includes:

A first insulating layer is formed on sidewalls and a bottom of the blind via.
The method of fabricating a stress sensor structure according to claim 5, wherein after the step of forming a second piezoresistive layer on the sidewall of the blind via, the method further comprises:

A third insulating layer is formed on the surface of the second piezoresistive layer.
The method of fabricating a stress sensor structure according to claim 9, wherein after the step of forming a third insulating layer on the surface of the second piezoresistive layer, the method further comprises:

A conductive metal is filled in the blind via.