[go: up one dir, main page]

WO2018218547A1 - 金属氧化物薄膜晶体管及显示面板 - Google Patents

金属氧化物薄膜晶体管及显示面板 Download PDF

Info

Publication number
WO2018218547A1
WO2018218547A1 PCT/CN2017/086724 CN2017086724W WO2018218547A1 WO 2018218547 A1 WO2018218547 A1 WO 2018218547A1 CN 2017086724 W CN2017086724 W CN 2017086724W WO 2018218547 A1 WO2018218547 A1 WO 2018218547A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
metal oxide
oxide thin
drain
Prior art date
Application number
PCT/CN2017/086724
Other languages
English (en)
French (fr)
Inventor
陈小明
赵晓辉
李春林
黄丽莹
马晓丹
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2017/086724 priority Critical patent/WO2018218547A1/zh
Priority to CN201780004627.6A priority patent/CN108496253B/zh
Publication of WO2018218547A1 publication Critical patent/WO2018218547A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a metal oxide thin film transistor applied to a display panel.
  • a semiconductor device such as a Thin Film Transistor (TFT) is usually used in the flexible display panel as a switching element for receiving image data from a pixel unit and other conductive electrodes.
  • TFT Thin Film Transistor
  • the flexible display panel often produces a certain degree of bending under the action of external force during use.
  • the electrodes in the thin film transistor and other conductive electrodes in the display panel are usually made of a metal material. It is well known that the flexibility of the metal material is poor. When the display panel is bent, the electrodes in the thin film transistor and the conductive electrodes in the display panel are relatively thin. It is prone to cracks or even breaks, which in turn causes the image display effect of the display panel to be affected or even causes the display panel to fail, thereby affecting the service life of the display panel.
  • the present invention provides a metal oxide thin film transistor which is more flexible.
  • a display panel having the aforementioned thin film transistor is provided.
  • a metal oxide thin film transistor includes a gate, a source, and a drain, wherein the source and/or the drain includes at least one via to increase flexibility of the metal oxide thin film transistor.
  • a display substrate includes a flexible substrate on which the foregoing metal oxide thin film transistor is disposed.
  • the conductive electrode in the display panel or the electrode in the thin film transistor has a hollow structure, which can effectively increase the flexibility of the electrode in the display panel and prevent the electrode from cracking during the bending process of the display panel. Affects the display effect and life of the display panel.
  • FIG. 1 is a cross-sectional structural view of a display panel in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic plan view showing the source, drain, and conductive channels of FIG.
  • FIG. 3 is a schematic plan view showing a source, a drain, and a conductive channel in a modified embodiment as shown in FIG. 1.
  • FIG. 4 is a schematic plan view showing the structure of a conductive electrode in another modified embodiment shown in FIG. 1.
  • Figure 5 is a side elevational view of a display panel in accordance with a modified embodiment of the present invention.
  • the present invention discloses a thin film transistor (TFT) of a metal oxide, the thin film transistor being disposed on a flexible substrate, including a gate, a source and a drain, wherein the source and/or the drain There are through holes to form a hollow structure.
  • the conductive channel between the source and the drain also has an opening and forms a hollow structure.
  • other conductive electrodes in the display panel including the aforementioned thin film transistor may be provided with through holes to form a hollow structure, thereby effectively increasing the flexibility of the electrodes in the thin film transistor and the display panel.
  • FIG. 1 is a cross-sectional structural view of a display panel according to an embodiment of the invention.
  • the display panel 100 includes a thin film transistor 10 disposed on a substrate 10a.
  • the substrate 10a is a substrate made of a flexible material.
  • the thin film transistor 10 is a metal oxide thin film transistor including a gate electrode 11, a gate insulating layer 12, a semiconductor layer 13, a source electrode 14, and a drain electrode 15.
  • the gate electrode 11 is disposed on the surface of the substrate 10a, the gate insulating layer 12 covers the gate electrode 11, the semiconductor layer 13 is disposed on the surface of the gate insulating layer 12, and the source electrode 14 and the drain electrode 15 are spaced apart from each other. The distance is provided on the surface of the semiconductor layer 13.
  • the source electrode 14 and the drain electrode 15 are disposed above the gate electrode 11 with the gate insulating layer 12 and the semiconductor layer 13 interposed therebetween, thereby forming a bottom gate type thin film transistor.
  • the gate electrode 11 may be spaced apart.
  • the gate insulating layer 12 and the semiconductor layer 13 are disposed above the source 14 and the drain 151 to constitute a top gate thin film transistor.
  • the semiconductor layer 13 between the source 14 and the drain 15 constitutes the conductive channel 16 of the thin film transistor 10.
  • the conductive electrode 20 is disposed on the thin film transistor 10 through the molding layer 21, and the molding layer 21 and the conductive electrode 20 cooperate to form a three-dimensional hollow structure.
  • the molding layer 21 includes a plurality of matrix-arranged protrusions 211 having curved edges, and the adjacent protrusions 211 form a recess portion 212, wherein the recess portion 212 is also a smooth curved structure.
  • the conductive electrode 20 is disposed on the surface of the molding layer 21, and the conductive electrode 20 is a hollow structure having a plurality of through holes 22. Wherein, each of the through holes 22 corresponds to one of the protrusions 211, and the protrusions 211 are at least partially exposed outside the through holes 22.
  • FIG. 2 is a schematic diagram of the planar structure of the source 14 , the drain 15 and the conductive channel as shown in FIG. 1 .
  • the source 14 and the drain 15 have a structure corresponding to each other.
  • the shapes of the source 14 and the drain 15 are axisymmetric with respect to the conductive channel 16.
  • the source 14 and the drain 15 include a hollow structure.
  • the source 14 includes a first base portion 141 and a first connecting portion 143 having a hollow structure formed by a through hole, wherein the first base portion 141 is cross-connected with the first connecting portion 143.
  • the first connecting portion 143 is a curved structure extending along the first direction X as a whole
  • the first base portion 141 is a curved structure extending integrally along the second direction Y
  • the first direction X is perpendicular to the second direction Y, that is, the first base portion
  • the 141 is vertically connected to the first connecting portion 143.
  • the first base portion 141 includes a plurality of first through holes 14a whose edges are smooth curved, and the through holes 14a constitute a hollow structure of the first base portion 141.
  • the edge of the first base 141 is a smooth curved structure.
  • the first connecting portion 143 includes a plurality of first through holes 14a whose edges are smooth curved, and the first through holes 14a constitute a hollow structure of the first connecting portion 143.
  • the edge of the first base 141 has a smooth curved structure.
  • the first through hole 14a is circular, and the first through hole 14a may have other shapes, such as an elliptical shape and a quadrangular shape, and is not limited thereto.
  • the first base portion 141 and the first connecting portion 143 The connection includes a first through hole 14a.
  • the width of the first base portion 141 and the first connection portion 143 in the first direction X or the second direction Y at the position corresponding to the first through hole 14a is greater than the first The width of the through hole 14a.
  • the drain 15 includes a second base portion 151 and a second connecting portion 153 having a hollow structure formed by the through holes, wherein the second base portion 151 is cross-connected with the second connecting portion 153.
  • the second connecting portion 153 is a curved structure extending along the first direction X as a whole
  • the second base portion 151 is a curved structure extending integrally along the second direction Y
  • the first direction X is perpendicular to the second direction Y, that is, the first base portion
  • the 141 is vertically connected to the first connecting portion 143.
  • the first connecting portion 143 and the second connecting portion 153 extend in opposite directions.
  • the second base portion 151 includes a plurality of second through holes 15a whose edges are smooth curved, and the second through holes 15a constitute a hollow structure of the second base portion 151.
  • the edge of the second base 151 has a smooth curved structure.
  • the second connecting portion 153 includes a plurality of second through holes 15a whose edges are smooth curved, and the second through holes 15a constitute a hollow structure of the second connecting portion 153.
  • the edge of the second base 153 has a smooth curved structure.
  • the second through hole 15a has the same shape as the first through hole 14a, and is circular.
  • the second through hole 15a may have other shapes, such as an elliptical shape and a quadrangular shape. This is limited to this.
  • the second base portion 151 and the second connecting portion 153 are connected to each other including a second through hole 15a.
  • the second base portion 151 and the second connecting portion 153 are along the position corresponding to the second through hole 15a.
  • the width of one direction X or the second direction Y is larger than the width of the second through hole 15a.
  • the conductive channel 16 includes a plurality of sub-conducting channels 161 spaced apart by a predetermined distance strip, the sub-conducting channels 161 integrally extending in a first direction X, and respectively connected to the first of the sources 14
  • the base portion 141 and the second base portion 143 of the drain electrode 15 and the plurality of sub-conducting channels 161 are in a rounded curved shape.
  • the conductive channel 16 is connected to the first base portion 141 and the second base portion 151 in a smooth curved shape.
  • a plurality of strip openings 163 are defined between the plurality of sub-conductive channels 161, and the plurality of strip-shaped openings 163 extend in the same direction as the sub-conducting channel 161, and are all in the first direction X. And the overall structure is a curve. Wherein, the plurality of openings 163 constitute a hollow structure of the conductive channel 16.
  • the material of the gate 11, the source 14, the drain 15, and the conductive electrode 16 is aluminum, titanium, molybdenum, copper or Indium Tin Oxide (ITO).
  • ITO Indium Tin Oxide
  • first base portion 141 corresponding to the source electrode 14 and the drain electrode 15 are disposed opposite to the second base portion 151 by a predetermined distance, so as to form the conductive channel 16 with the semiconductor layer 13 (FIG. 1).
  • the first connecting portion 143 and the second connecting portion 153 corresponding to the source 14 and the drain 15 are respectively used for electrically connecting with a conductive line or a conductive element.
  • the gate electrode 11 may be a hollow structure provided with a through hole.
  • the conductive electrode 20 in the display panel 100 or the electrode in the thin film transistor 13 has a hollow structure composed of at least one through hole, which can effectively increase the flexibility of the electrode in the display panel 100 and prevent the display panel 100 from being damaged.
  • the electrode generates cracks during the bending process to affect the display effect and life of the display panel 100.
  • FIG. 3 is a schematic diagram showing the planar structure of the source 14 , the drain 15 , and the conductive channel shown in FIG. 1 according to the second embodiment of the present invention.
  • the source 24 and the source 14 are identical in structure, and the drain 25 and the drain 15 are identical in structure.
  • the main difference is that the structure of the conductive channel 26 is different from that of the conductive channel 16, and the conductive channel 26 does not include a hollow structure.
  • the conductive channels 26 are respectively connected between the first base 241 of the source 24 and the second base 251 of the drain 25, and the whole extends along the second direction Y, that is, The extending direction of the conductive channel 26 is parallel to the first base portion 241 and the second base portion 251, and the connection between the conductive channel 26 and the first base portion 241 and the second base portion 251 is also a smooth curved shape.
  • the conductive channel 26 has a smooth curved shape as a whole.
  • FIG. 4 is a schematic plan view of a conductive electrode in another modified embodiment shown in FIG. 1 .
  • the conductive electrodes 30 extend along the entire first direction X, and the conductive electrodes 30 are all in the plane in which the first direction X lies.
  • the conductive electrode 30 is formed by a plurality of through holes 31, and the edge is a smooth curved structure.
  • the through hole 31 may also have other shapes, such as an elliptical shape and a quadrangular shape, and is not limited thereto.
  • the structure of the conductive electrode 30 in this embodiment can also be applied to the source and/or the drain in the thin film transistor.
  • FIG. 5 is a side view of the display panel 400 according to a modified embodiment of the present invention
  • the conductive electrode 40 and the molding layer 41 are not disposed on the thin film transistor, but are directly disposed on the substrate 40a.
  • the substrate 40a is a flexible substrate.
  • the conductive electrode 40 is disposed on the flexible substrate 40 through the molding layer 41, and the molding layer 41 and the conductive electrode 30 cooperate to form a three-dimensional hollow structure.
  • the molding layer 41 includes a plurality of matrix-arranged protrusions 411 having curved edges, and the adjacent protrusions 411 form a recessed portion 412 and a recessed portion 413, wherein the recessed portion 412 and the recessed portion 313 are also smoothed.
  • the conductive electrode 40 is disposed on the surface of the molding layer 41, and the conductive electrode 40 is a hollow structure having a plurality of through holes 32.
  • the through hole 42 corresponds to one of the protrusions 411, and the protrusion 311 is at least partially exposed outside the through hole 42.
  • the through hole 32 may also correspond to the concave portion 313 having a larger curvature.
  • the conductive electrodes 30, 40 each include a hollow structure composed of at least one through hole, the conductive electrodes 30, 40 have better flexibility and can accommodate a greater degree of bending, thereby enabling the conductive electrodes 30, 40.
  • the display panel also has good bending resistance.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

一种金属氧化物薄膜晶体管(10)以及具有所述金属氧化物薄膜晶体管(10)的显示面板(100)。所述金属氧化物薄膜晶体管(10)，包括栅极(11)、源极(14)以及漏极(15)，其中，所述源极(14)和/或漏极(15)包括至少一个通孔(22)，以增加所述金属氧化物薄膜晶体管(10)的柔韧性。

Description

金属氧化物薄膜晶体管及显示面板
本专利文件披露的内容包含受版权保护的材料。该版权为版权所有人所有。版权所有人不反对任何人复制专利与商标局的官方记录和档案中所存在的该专利文件或该专利披露。
技术领域
本发明涉及显示技术领域，尤其涉及应用于显示面板的金属氧化物薄膜晶体管。
背景技术
柔性显示面板的内通常采用薄膜晶体管(Thin Film Transistor，TFT)等半导体器件来作为像素单元是否接收图像数据的开关元件以及其他导电电极。柔性显示面板在使用过程中经常在外力作用下产生一定程度的弯曲。
然而，薄膜晶体管中的电极以及显示面板内的其他导电电极通常采用金属材料构成，众所周知，金属材料的柔韧性较差，当显示面板弯曲时，薄膜晶体管中的电极以及显示面板内的导电电极较为容易产生裂缝甚至断裂，继而造成显示面板的图像显示效果受到影响甚至导致显示面板失效，进而影响显示面板的使用寿命。
发明内容
为解决前述问题，本发明提供一种柔韧性较好的金属氧化物薄膜晶体管。
进一步，提供一种具有前述薄膜晶体管的显示面板。
一种金属氧化物薄膜晶体管，包括栅极、源极以及漏极，其中，所述源极和/或漏极包括至少一个通孔，以增加所述金属氧化物薄膜晶体管的柔韧性。
一种显示基板，所述显示面板包括一柔性基板，所述柔性基板上设置有前述的金属氧化物薄膜晶体管。
显示面板中的导电电极或者薄膜晶体管中的电极具有镂空结构，能够有效增加显示面板中的电极的柔韧性，防止显示面板在弯曲过程中电极产生裂缝而 影响显示面板的显示效果与寿命。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一实施例中显示面板的剖面结构示意图。
图2为如图1所示源极、漏极以及导电沟道的平面结构示意图。
图3为如1所示一变更实施例中源极、漏极以及导电沟道的平面结构示意图。
图4为图1所示另一变更实施例中一导电电极的平面结构示意图。
图5为本发明一变更实施例中显示面板的侧视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明公开一种金属氧化物的薄膜晶体管(Thin Film Transistor，TFT)，该薄膜晶体管设置于一柔性基底上，包括栅极、源极以及漏极，其中，所述源极和/或漏极具有通孔从而形成镂空结构。较佳地，源极与漏极之间的导电沟道也具有开口并形成镂空结构。另外，对应包括有前述薄膜晶体管的显示面板中的其他导电电极也可以设置有通孔而构成镂空结构，从而有效增加薄膜晶体管与显示面板中电极的柔韧性。
请参阅图1，其为本发明一实施例中显示面板的剖面结构示意图。如图1所示，显示面板100包括设置于基板10a上的薄膜晶体管10。
具体地，所述基板10a为以柔性材质构成的基底。薄膜晶体管10为一金属氧化物薄膜晶体管，包括有栅极11、栅极绝缘层12、半导体层13、源极14、漏极15。
本实施例中，栅极11设置于基板10a的表面，栅极绝缘层12覆盖所述栅极11，半导体层13则设置于栅极绝缘层12的表面，源极14与漏极15间隔预定距离设置于半导体层13的表面。虽然本实施例中，源极14与漏极15间隔所述栅极绝缘层12以及半导体层13设置于栅极11的上方，构成底栅型薄膜晶体管，可变更地，栅极11亦可以间隔所述栅极绝缘层12以及半导体层13设置于源极14与漏极151的上方，构成顶栅型薄膜晶体管。
进一步，源极14与漏极15之间的半导体层13构成薄膜晶体管10的导电沟道16。
较佳地，导电电极20通过成型层21设置于薄膜晶体管10上，成型层21与导电电极20配合构成立体镂空结构。具体地，成型层21包括多个矩阵排列的具有弧形边缘的凸起211，相邻的凸起211之间构成凹陷部212，其中，凹陷部212也为平滑的曲线结构。
导电电极20设置于成型层21的表面，且所述导电电极20为具有多个通孔22的镂空结构。其中，所述每个通孔22对应于其中一个凸起211，并且所述凸起211至少部分显露于通孔22外。
请参阅图2，其为如图1所示源极14、漏极15以及导电沟道的平面结构示意图。如图2所示，源极14、漏极15结构相互对应，本实施方式中，源极14与漏极15的形状相对于导电沟道16轴对称。其中，源极14与漏极15包括有镂空结构。
具体地，源极14包括具有由通孔构成镂空结构的第一基部141与第一连接部143，其中，第一基部141与第一连接部143交叉连接，本实施例中，第一连接部143为整体沿着第一方向X延伸的曲线结构，第一基部141为整体沿第二方向Y延伸的曲线结构，且所述第一方向X垂直于第二方向Y，也即是第一基部141与第一连接部143垂直连接。
第一基部141包括多个边缘为光滑弧形的第一通孔14a，通孔14a构成第一基部141的镂空结构。所述第一基部141边缘为平滑曲线结构。第一连接部143包括多个边缘为光滑弧形的第一通孔14a，第一通孔14a构成第一连接部143的镂空结构。所述第一基部141的边缘为平滑曲线结构。本实施例中，所述第一通孔14a为圆形，可变更地，第一通孔14a还可以为其他形状，例如椭圆形，四边形，并不以此为限。较佳地，所述第一基部141与第一连接部143 连接处包括一个第一通孔14a，另外，第一基部141与第一连接部143在对应第一通孔14a的位置的沿第一方向X或者第二方向Y的宽度大于未设置有第一通孔14a的宽度。
对应地，漏极15包括具有由通孔构成镂空结构的第二基部151与第二连接部153，其中，第二基部151与第二连接部153交叉连接，本实施例中，第二连接部153为整体沿着第一方向X延伸的曲线结构，第二基部151为整体沿第二方向Y延伸的曲线结构，且所述第一方向X垂直于第二方向Y，也即是第一基部141与第一连接部143垂直连接。另外，第一连接部143与第二连接部153的延伸方向相反。
第二基部151包括多个边缘为光滑弧形的第二通孔15a，第二通孔15a构成第二基部151的镂空结构。所述第二基部151的边缘为平滑曲线结构。同时，第二连接部153包括多个边缘为光滑弧形的第二通孔15a，第二通孔15a构成第二连接部153的镂空结构。所述第二基部153的边缘为平滑曲线结构。本实施例中，所述第二通孔15a与第一通孔14a的形状相同，均为圆形，可变更地，第二通孔15a还可以为其他形状，例如椭圆形，四边形，并不以此为限。较佳地，所述第二基部151与第二连接部153连接处包括一个第二通孔15a，另外，第二基部151与第二连接部153在对应第二通孔15a的位置的沿第一方向X或者第二方向Y的宽度大于未设置有第二通孔15a的宽度。
进一步，导电沟道16包括多个间隔预定距离条状结构的子导电沟道161，所述子导电沟道161整体沿第一方向X延伸的曲线结构，并且分别连接于源极14的第一基部141以及漏极15的第二基部143，且所述的多个子导电沟道161沿均为圆滑的曲线形状。其中，所述导电沟道16与所述第一基部141、第二基部151均以平滑曲线形状连接。
所述多个子导电沟道161之间包括多个条形开口163，且所述多个条形开口163的延伸方向与所述子导电沟道161的延伸方向相同，均为第一方向X，且整体为曲线结构。其中，所述多个开口163构成导电沟道16的镂空结构。
较佳地，栅极11、源极14、漏极15以及导电电极16的材质为铝、钛、钼、铜或者氧化铟锡(Indium Tin Oxide,ITO)。
可以理解，所述源极14与漏极15对应的第一基部141与第二基部151间隔预定距离正对设置，以便于配合半导体层13(图1)形成导电沟道16， 源极14与漏极15对应的第一连接部143与第二连接部153则分别用于与导电线路或者导电元件进行电性连接。另外，当薄膜晶体管10对应栅极11的位置设有遮光元件时，栅极11也可以为设置有通孔的镂空结构。
相较于现有技术，显示面板100中的导电电极20或者薄膜晶体管13中的电极具有由至少一个通孔构成的镂空结构，能够有效增加显示面板100中的电极的柔韧性，防止显示面板100在弯曲过程中电极产生裂缝而影响显示面板100的显示效果与寿命。
请参阅图3，其为本发明第二实施例中如图1所示源极14、漏极15以及导电沟道的平面结构示意图。
本实例中，源极24与源极14结构相同，漏极25与漏极15结构相同，主要区别在于导电沟道26的结构与导电沟道16不同，导电沟道26并不包括镂空结构。
具体地，如图3所示，所述导电沟道26分别连接于源极24的第一基部241以及漏极25的第二基部251之间，其整体沿着第二方向Y延伸，也即是导电沟道26的延伸方向平行于所述第一基部241、第二基部251，且所述导电沟道26与第一基部241以及第二基部251的连接处亦为平滑的曲线形状。较佳地，所述导电沟道26整体呈平滑的曲线形状。
请参阅图4，其为如图1所示另一变更实施例中一导电电极的平面结构示意图。如图4所示，导电电极30沿整体沿着第一方向X延伸设置，且导电电极30均处于第一方向X所在的平面内。所述导电电极30为由多个通孔31构成镂空结构，边缘为平滑曲线结构同时。通孔31还可以为其他形状，例如椭圆形，四边形，并不以此为限。当然，本实施例中导电电极30的结构也可以应用至薄膜晶体管中的源极和/或漏极。
当然，可变更地，如图5所示，其为本发明一变更实施例中显示面板400的侧视图，导电电极40与成型层41并未设置于薄膜晶体管上，而是直接设置于基底40a上，其中，基底40a为柔性基底。
导电电极40通过成型层41设置于柔性的基底40上，成型层41与导电电极30配合构成立体镂空结构。具体地，成型层41包括多个矩阵排列的具有弧形边缘的凸起411，相邻的凸起411之间构成凹陷部412与凹陷部413，其中，凹陷部412与凹陷部313也具有平滑的曲线结构，其中，凹陷部413的曲率半 径大于凹陷部412的曲率半径。
导电电极40设置于成型层41的表面，且所述导电电极40为具有多个通孔32的镂空结构。其中，所述通孔42对应于其中一个凸起411，并且所述凸起311至少部分显露于通孔42外，同时，通孔32也可以对应曲率较大的凹陷部313。
由于前述导电电极30、40均包括有由至少一个通孔构成的镂空结构，因此导电电极30、40具有较好的柔韧性，能够适应较大程度的弯曲，从而使得具有导电电极30、40的显示面板也具有较好的抗弯曲性能。
可以理解，以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (15)

  1. 一种金属氧化物薄膜晶体管，其特征在于，包括栅极、源极以及漏极，其中，所述源极和/或漏极包括至少一个通孔，以增加所述金属氧化物薄膜晶体管的柔韧性。
  2. 根据权利要求1所述的金属氧化物薄膜晶体管，其特征在于，所述栅极和/或漏极包括相互连接的基部与连接部，所述基部的延伸方向与连接部的延伸方向交叉，且所述基部与所述连接部其中至少一个具有所述通孔。
  3. 根据权利要求2所述的金属氧化物薄膜晶体管，其特征在于，所述基部与所述连接部的所述通孔具有平滑边缘。
  4. 根据权利要求3所述的金属氧化物薄膜晶体管，其特征在于，所述通孔为圆形、椭圆形或者多边形。
  5. 根据权利要求2所述的金属氧化物薄膜晶体管，其特征在于，所述源极、漏极与栅极之间还包括半导体层，所述半导体层构成源极与漏极之间的导电沟道，所述导电沟道包括多个间隔设置的子导电沟道，所述子导电沟道分别连接于所述基部且为平滑的曲线形状。
  6. 根据权利要求5所述的金属氧化物薄膜晶体管，其特征在于，所述子导电沟道为条形结构且延伸方向垂直于所述基部延伸的方向。
  7. 根据权利要求5所述的金属氧化物薄膜晶体管，其特征在于，所述多个子导电沟道之间包括多个条形开口，且所述多个条形开口的延伸方向与所述子导电沟道的延伸方向相同。
  8. 根据权利要求2所述的金属氧化物薄膜晶体管，其特征在于，所述源、漏极与栅极之间还包括半导体层，所述半导体层构成源极与漏极之间的导电沟道，所述导电沟道分别连接于所述基部且为圆滑的曲线形状，且所述导电沟道的延伸方向平行于所述基部。
  9. 根据权利要求2所述的金属氧化物薄膜晶体管，其特征在于，所述基部呈曲线形状，且所述基部的边缘呈平滑的曲线形状。
  10. 根据权利要求9所述的金属氧化物薄膜晶体管，其特征在于，所述连接部的边缘呈平滑的曲线形状。
  11. 根据权利要求1所述的源极或者漏极材料为铝、钛、钼、铜或者氧化铟锡。
  12. 一种显示基板，所述显示面板包括一柔性基板，其特征在于，所述柔性基板上设置有权利要求1-11任意一项所述的金属氧化物薄膜晶体管。
  13. 根据权利要求12所述的显示基板，所述的金属氧化物薄膜晶体管上还设置有一导电电极，所述导电电极包括镂空结构，所述镂空结构为多个具有光滑圆弧形的通孔。
  14. 根据权利要求13所述的显示基板，其特征在于，所述金属氧化物薄膜晶体管上还设置有感光树脂层与导电电极，所述感光树脂层包括多个具有弧形边缘的凸起，所述导电电极设置于所述感光树脂层的表面，且所述凸起对应所述镂空结构中的通孔且部分显露于所述通孔外。
  15. 根据权利要求14所述的显示基板，其特征在于，相邻的所述凸起之间构成凹陷部，所述凹陷部对应所述镂空结构中的所述通孔。
PCT/CN2017/086724 2017-05-31 2017-05-31 金属氧化物薄膜晶体管及显示面板 WO2018218547A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2017/086724 WO2018218547A1 (zh) 2017-05-31 2017-05-31 金属氧化物薄膜晶体管及显示面板
CN201780004627.6A CN108496253B (zh) 2017-05-31 2017-05-31 金属氧化物薄膜晶体管及显示面板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/086724 WO2018218547A1 (zh) 2017-05-31 2017-05-31 金属氧化物薄膜晶体管及显示面板

Publications (1)

Publication Number Publication Date
WO2018218547A1 true WO2018218547A1 (zh) 2018-12-06

Family

ID=63344785

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/086724 WO2018218547A1 (zh) 2017-05-31 2017-05-31 金属氧化物薄膜晶体管及显示面板

Country Status (2)

Country Link
CN (1) CN108496253B (zh)
WO (1) WO2018218547A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109256429B (zh) * 2018-08-03 2021-01-26 Tcl华星光电技术有限公司 氧化物半导体薄膜晶体管及其制作方法
US10749036B2 (en) 2018-08-03 2020-08-18 Shenzhen China Star Optoelectronics Technology Co., Ltd. Oxide semiconductor thin film transistor having spaced channel and barrier strips and manufacturing method thereof
CN113437156A (zh) * 2021-06-07 2021-09-24 惠州华星光电显示有限公司 半导体器件及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681697A (zh) * 2013-12-27 2014-03-26 京东方科技集团股份有限公司 阵列基板及显示装置
CN204130548U (zh) * 2014-10-28 2015-01-28 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板、显示装置
CN106356408A (zh) * 2016-11-30 2017-01-25 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板、显示面板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498376B1 (en) * 1994-06-03 2002-12-24 Seiko Instruments Inc Semiconductor device and manufacturing method thereof
JP4060125B2 (ja) * 2002-05-30 2008-03-12 シャープ株式会社 液晶表示装置用基板及びそれを備えた液晶表示装置及びその製造方法
WO2011071198A1 (ko) * 2009-12-10 2011-06-16 경기대학교 산학협력단 트랜지스터와, 그를 포함하는 유기 전계 발광 표시 장치 및 평판 표시 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681697A (zh) * 2013-12-27 2014-03-26 京东方科技集团股份有限公司 阵列基板及显示装置
CN204130548U (zh) * 2014-10-28 2015-01-28 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板、显示装置
CN106356408A (zh) * 2016-11-30 2017-01-25 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板、显示面板及显示装置

Also Published As

Publication number Publication date
CN108496253B (zh) 2021-07-20
CN108496253A (zh) 2018-09-04

Similar Documents

Publication Publication Date Title
CN108695369B (zh) 具有微盖层的显示装置及其制造方法
CN106796364B (zh) 包括具有增强部分的配线的柔性显示装置及其制造方法
CN107765488B (zh) 阵列基板、触控显示面板和触控显示装置
US10509500B2 (en) Touch display apparatus
CN102655156B (zh) 一种阵列基板及其制造方法
CN111490053B (zh) 阵列基板
US20160147123A1 (en) Array substrate and display device
US20200242992A1 (en) Display devices
KR102295477B1 (ko) 박막 트랜지스터 표시판
WO2018218547A1 (zh) 金属氧化物薄膜晶体管及显示面板
WO2019085700A1 (zh) 阵列基板及其制造方法和显示装置及其制造方法
KR102001556B1 (ko) Ffs 어레이 기판 및 액정 표시 패널
CN104407463A (zh) 像素结构的制造方法及液晶显示面板的制造方法
US20190101802A1 (en) Array substrate, display panel and display device
JP6336765B2 (ja) 表示装置
TWI597830B (zh) 顯示裝置
KR102011315B1 (ko) 어레이 기판, 제조 방법, 및 대응하는 디스플레이 패널과 전자 디바이스
US20110221992A1 (en) Array substrate for use in displays, and method of manufacturing the same
JP2016133811A (ja) 表示装置
TW201636712A (zh) 顯示裝置
TWI612645B (zh) 顯示面板
CN109103345B (zh) 一种显示面板和显示装置
TWI595298B (zh) 顯示面板
JP2009053477A5 (zh)
CN103913917A (zh) 一种tft阵列基板及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17912144

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17912144

Country of ref document: EP

Kind code of ref document: A1