WO2018063370A1

WO2018063370A1 - Semiconductor chip manufacturing process for integrating logic circuitry, embedded dram and embedded non-volatile resistive random access memory (rram) on a same semiconductor die

Info

Publication number: WO2018063370A1
Application number: PCT/US2016/054906
Authority: WO
Inventors: Elijah Ilya V. KARPOV; Yih Wang; Niloy Mukherjee; Prashant Majhi; Ravi Pillarisetty
Original assignee: Intel Corporation
Priority date: 2016-09-30
Filing date: 2016-09-30
Publication date: 2018-04-05

Abstract

An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded resistive random access memory (RRAM) cells.

Description

SEMICONDUCTOR CHIP MANUFACTURING PROCESS FOR INTEGRATING LOGIC CIRCUITRY, EMBEDDED DRAM AND EMBEDDED NON-VOLATILE RESISTIVE RANDOM ACCESS MEMORY (RRAM) ON A SAME SEMICONDUCTOR

DIE

Field of Invention

The field of invention pertains generally to the computing sciences, and, more specifically, to a semiconductor chip manufacturing process for integrating logic circuitry, embedded DRAM and embedded non- volatile resistive random access memory (RRAM) on a same semiconductor die.

Background

Computing systems typically include a system memory (or main memory) that contains data and program code of the software code that the system' s processor(s) are currently executing. A pertinent issue in many computer systems is the system memory. Here, as is understood in the art, a computing system operates by executing program code stored in system memory. The program code when executed reads and writes data from/to system memory. As such, system memory is heavily utilized with many program codes and data reads as well as many data writes over the course of the computing system' s operation. Finding ways to improve system memory is therefore a motivation of computing system engineers.

Figures

A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

Figs, la and lb pertain to a prior art system on chip;

Figs. 2a and 2b pertain to an improved system on chip;

Figs. 3a through 31 show a manufacturing process for manufacturing the improved system on chip of Figs. 2a and 2b;

Figs. 4a through 4c pertain to accessing details for a system on chip having embedded DRAM and embedded RRAM cells;

Fig. 5 shows a computing system. Detailed Description

Fig. la shows a computing system 100 that includes a plurality of processing cores 101 coupled to a memory controller 102. The memory controller 102 is coupled to a peripheral control hub 103 and a system memory 104. Owing to the cost reductions associated with manufacturing integration, device and system designers prefer to use technologies in which as many system components as possible are monolithically integrated on a same semiconductor die.

Over the past decade or so, "system on chip" devices that integrate the processing cores 101, memory controller 102 and peripheral control 103 hub on a same semiconductor chip have become commonplace. Historically though, monolithic integration of system memory 104, composed of dynamic random access memory (DRAM) cells on the same semiconductor die as the logic used to implement the cores 101 and controllers 102, 103 has been problematic.

Recently, however, new efforts have been made to monolithically integrate DRAM cells onto the same die as the logic circuitry. Fig. lb shows one embedded DRAM approach in which the capacitors used to implement the respective DRAM cells are manufactured as metal- insulator-metal (MIM) capacitors 105 within the interconnect metallurgy 106 of the

semiconductor die. Here, Fig. lb shows the DRAM MIM capacitors 105 extending

approximately between the fourth layer of metallization (M4) and the second layer of metallization (M2).

From an architectural perspective there can also be justifications for implementing a multi-level system memory. In the case of a multi-level system memory, for example, faster DRAM cells act as a faster, higher priority region of system memory and slower, emerging non volatile memory cells (e.g., resistive random access memory (RRAM) cells) act as a slower, lower priority region of system memory. For example, faster DRAM cells may be implemented as a memory side cache for the emerging non volatile memory cells (in which case system memory addresses are assigned primarily to the non volatile memory cells), and/or, the DRAM cells may be allocated their own respective, separate system memory address space so that they behave as a truly higher priority region of system memory.

Fig. 2a shows a possible system on chip in which a multi-level system memory composed of different memory cell technologies, e.g., DRAM 204_1 and RRAM 204_2, are monolithically integrated onto the same semiconductor die 200 as the processing cores 201, memory controller 202 and peripheral controller 203. As depicted, the non volatile RRAM cells 204_2 can be coupled to the main memory controller 202 as, e.g., a (lower) level of system memory that is integrated on the die 200. Alternatively or in combination, the RRAM cells 204_2 may be coupled to the peripheral controller 203, e.g., to effect deeper mass storage (such as an embedded solid state disk) that is monolithically integrated on the die 200. Fig. 2b depicts integration of both MIM capacitor DRAM cells 205_1 and emerging non volatile memory RRAM cells 205_2 in the interconnect metallurgy 206 of the semiconductor die.

Figs. 3a through 3k shows a manufacturing process sequence capable of integrating logic circuitry, DRAM cells and RRAM cells on a same semiconductor die.

Fig. 3 a shows the manufactured structure after the polishing of the second level metal 303 (M2) to the surface of the second metal level dielectric 304. In an embodiment, a damascene process is used to form the M2 (and Ml) metal layers. That is, the M2 level dielectric 304 is first deposited on the M2/M1 interlayer dielectric 303. In various embodiments, both interlayer 302 and metal level 304 dielectrics are formed of a low-k carbon doped oxide (CDO).

After deposition of the M2 level dielectric 304, it is pattered according to a

photolithographic process that forms openings in the dielectric where M2 layer metal structures are to be formed. Then, a barrier layer (e.g., Tantalum (Ta), Titanium (Ti), Titanium Nitride (TiN), Tantalum Nitride (TaNi)), not shown in Fig. 3a for simplicity, is disposed over the M2 dielectric 304 so as to fill the aforementioned openings. Here, the aforementioned barrier layer prevents diffusion of the (yet to formed) copper metal structures from diffusing into any surrounding dielectric.

Then, copper M2 metal structures 303 are formed by electroplating copper on the barrier layer. In an embodiment, a copper seed layer is first deposited on the barrier layer (e.g., by a physical vapor deposition process such as sputter deposition). Then the M2 copper layer is deposited on the seed layer by electroplating. Here, the thickness of the M2 copper should be sufficient to fill the openings in the M2 dielectric 304 and form a copper layer over the upper surface of the M2 dielectric 304. The copper is then polished using a chemical mechanical polishing (CMP) process until the surface of the M2 dielectric 304 is reached.

An Ml metal layer with specific Ml metal features 301 resides beneath the M2 layer. Active transistor devices (such as FINFETs) reside beneath the Ml layer in/on the

semiconductor substrate 300. Certain ones of the Ml features 301 are electrically connected with contacts to the devices through vias that extend from the Ml layer to the contacts which are disposed on or just above the semiconductor surface 300. For ease of drawing, the transistor devices, their contacts and the associated vias have not been drawn. Vias 305 are shown, however, between the M2 and Ml metal layers. After the formation of the M2 layer, as observed in Fig. 3b, the M3 layer is formed, an M3/M4 interlayer dielectric layer is formed on the M3 layer and the M4 dielectric layer 306 is formed on the M3/M4 interlayer dielectric. In an embodiment, like the Ml and M2 layers beneath them, the M3, M4 and higher metal layers are also composed of copper and patterned according to a damascene process. Here, notably, region 307 corresponds to logic interconnect, whereas, as will be explained more thoroughly below, region 308 corresponds to regions where both embedded DRAM and embedded RRAM memory cells will be formed.

Figs. 3c through 3i depict formation of both DRAM and RRAM memory cell structures in the M4 through M2 interconnect. Here, as will be more apparent in the following discussion, referring briefly back to Fig. 3b, pairs of Ml metal features 309, 329 in region 308 reside beneath each storage cell to be formed in region 308. More specifically, as will be explained in more detail further below, each storage cell to be formed in region 308 has an access transistor Ml feature 309 and a bitline Ml feature (for ease of drawing, only the Ml feature pair 309, 339 have been labeled in Fig. 3b with respect to the rightmost storage cell location. As is understood in the art, generally, storage cells have individual supporting circuit structures that include an access transistor and a bitline. Feature 309 corresponds to the connection to the access transistor for the rightmost storage cell of Fig. 3b and feature 339 corresponds to the bitline that the rightmost storage cell of Fig. 3b will be coupled to. Metal features formed at the M4 level in region 308 will correspond to the top electrode of the memory cells.

As observed in Fig. 3c, a layer of photoresist 310 is deposited on the structure of Fig. 3b and patterned by way of the photolithographic techniques so as to expose openings 311 in a region 312 where RRAM cells are to be formed. As observed in Fig. 3d, trenches 312 are etched with an anisotropic dry etch process through the M4 through M2 dielectrics so as to expose the top surfaces of the underlying M2 metal structures 313. Here, the anisotropic etching process etches the dielectrics in a substantially vertical direction but not a substantially lateral direction so that high aspect ratio vias are formed. In various embodiments, a dry plasma etch is used to remove dielectric material from the exposed area of patterned region in 312. Underlying M2 copper 313 is then selectively etched. In an embodiment, the trenches 312 are approximately 300-500nm high and about lOOnm wide.

As observed in Fig. 3e, the photoresist 310 is removed to expose the wafer surface and the openings 312 that were just formed in the interconnect layering. As observed in Fig. 3f, the exposed underlying M2 structures and the M2/M1 vias beneath them are removed by a wet etch that is selective to copper. That is, the ambient of the etch process contains reactants that chemically react with copper but not with dielectric. As such, the copper is gradually eroded. In an embodiment, the top surface of the Ml metal structures 309 have an etch stop metal that does not react with the chemical etch which causes the etch to cease at the top of the Ml metal. In an embodiment, the M2 metal and M2/M1 vias are not removed and the etching of the openings is designed to stop at the top of the M2 metal.

As observed in Fig. 3g, the RRAM material stack 314 is sequentially deposited onto the wafer in a manner that fills the trenches 312 to form respective RRAM cells from respective metal-insulator-metal (MIM) like structures. A resistive random access memory cell generally includes a dielectric layer which, although normally insulating, can also be conductive under certain circumstances (e.g., application of a large voltage potential). A binary 1 or 0 is stored in the storage cell depending on whether the insulating layer is insulating (higher resistance) or conducting (lower resistance).

In an embodiment, the RRAM stack comprises a bottom electrode material 315 (e.g., Titanium Nitride (TiN)), an oxide layer 316 (composed of, e.g., a Hafnium Oxide (Hf02), a Hafnium Tantalum Oxide (HfTaOx), a Hafnium Aluminum Oxide (HfAlOx), a Tantalum Oxide (Ta205) or other combinations of transition metal oxides), an oxygen exchange layer (OEL) 317 (composed of, e.g., Tantalum (Ta), Titanium (Ti), Hafnium (Hf)), and an upper electrode material 318 (composed of, e.g., TiN).

In various embodiments, the stoichiometric oxide layer 316 may be deposited by atomic layer deposition (ALD). The metal layers 315, 318 can be deposited by ALD or DC sputtering. A nitride layer, e.g., a TiN top electrode can be deposited by reactive sputtering or ALD. In various embodiments, the thickness of each active layers is in the range of 2 -30 nm. In various embodiments, after deposition of the RRAM material stack on the wafer, the wafer is polished until the M4 dielectric is reached which leaves only the vias having the material stack within their respective openings.

As is known in the art, each individual storage cell in a memory has associated circuitry that permits the reading/writing of a bit of information from/to the cell. Each cell therefore has an associated access transistor that, with proper control, permits access to its particular cell. A pertinent feature of the RRAM design of Fig. 3g (described in more detail further below with respect to Figs. 4a through 4c) is that the access transistor for an RRAM cell resides directly beneath the cell. That is, for example, the access transistor for RRAM cell 331 resides in/on region 332 of the substrate directly beneath cell 331, and, the access transistor for RRAM cell 333 resides in/on region 334 of the substrate directly beneath cell 333.

Here again, recalling the discussion of Ml features 309 and 339 with respect to Fig. 3b, note that Ml feature 309 is connected to a contact of access transistor 332 and Ml feature 340 is connected to a contact of access transistor 334. Additionally, also as described above with respect to Fig. 3b, the respective bitline that each storage cell is coupled to resides beneath its respective cell. For example, feature 339 corresponds to the bitline for the rightmost storage cell 331 and feature 341 corresponds to the bitline for the second to rightmost storage cell 333. The respective access transistors and bitlines for the other RRAM cells are similarly located.

As observed in Fig. 3h, a process similar to the process of Figs. 3c through 3g is performed over region 319 in order to form MIM capacitor DRAM cells 320. Note that in the case of the DRAM cells 320, the removal of the M2 metal and M2/M1 vias to form the DRAM cell openings effectively increases the surface area of the DRAM capacitance. As is understood in the art, larger surface area capacitors should be able to operate at higher frequencies than smaller surface area capacitors. Hence, DRAM cells formed with the lower M2 and M2/M1 via metallurgy having been removed should be able to operate at higher clock speeds.

In an embodiment the DRAM cell material stack is composed of a lower electrode 321, a high-K dielectric 322 and a top electrode 323. In various embodiments, the lower electrode 321 is composed of Ta or TiN; the high-K dielectric 322 is composed of ZrC>2_, Hf0₂, Ti0₂, or AI2O₃; and the top electrode 323 is composed of Ta or TiN. The high-K dielectric 322 completely covers the lower electrode 321 so that the upper and lower electrodes are not shorted. In an embodiment, deposition of a conformal Cu diffusion layer may precede the deposition of the lower electrode 321. As described above, the capacitor trench is patterned into the Metal-4 and Metal-3 layers. This is followed by a selective removal of Metal-2 by a wet etch. Then a Cu diffusion barrier layer and conformal electrode are deposited, and the bottom electrode 321 is isolated with polish and etch. The thickness of bottom electrode 321 can be in the range of 20- 40nm. A conformal hi-k dielectric is then deposited within the surface of trench by chemical vapor deposition, followed by conformal top-electrode and additional Cu diffusion barrier deposition. Typical thickness of hi-k dielectric is in the range of 5-8nm. Thickness of top electrode is in the range of 20-40nm.

In an embodiment, the DRAM is designed similarly to the RRAM in that the access transistor for a particular DRAM cell and a bitline for the DRAM cell reside beneath the cell. As such, a capacitor-over-bitline (COB) design approach is adopted. As is known in the art, in a COB approach, a DRAM storage cell is directly connected to its access transistor, where, the access transistor resides directly beneath the DRAM cell in/on the semiconductor substrate. The access transistor itself is directly connected to the DRAM cell's bitline and wordline. For example, a gate of the access transistor is connected to the cell's word line, one S/D terminal of the access transistor is connected to the cell's bit line and another S/D terminal of the access transistor is connected to the bottom electrode of the cell. Here, again, the bit line (and even the word line) are formed from Ml metal. As discussed at length above, the RRAM cells may be similarly designed.

In an alternate embodiment, the DRAM MIM stack can be the same as the RRAM MIM stack except the OEL layer 317. That is, the DRAM and RRAM, stacks can be processed simultaneously until the OEL layer 317 deposition at which point the DRAM array area should be masked, and the OEL layer 317 deposited only in the RRAM array area. Then the mask over the DRAM can be removed and both arrays can be processed through top electrode deposition.

Fig. 3i shows topside processing of the storage cells with metal plate structure 325 in the M5/M4 dielectric 324 above the DRAM cells and metal plate structures 326_1, 326_2 in the M5/M4 dielectric above the RRAM cells. Here, the top electrodes of the DRAM cells, are coupled to a same electrical node, such as a reference potential node. As such, metal plate structure 325 effectively shorts the top electrodes of the DRAM cells together. Thus, e.g., in an embodiment, all DRAM cells of a same embedded DRAM memory are connected to a same metal plate structure 325.

By contrast, in an embodiment, the RRAM cells have a different circuit design that does not electrically connect the top electrode of all RRAM cells to a same node. As such, as observed in Fig. 3i, different groups of RRAM cells are coupled to different plate structures 326_1, 326_2. Here, as is understood in the art, words of a specific bit length are written to and read from a memory device. In the case of the RRAM cells, each address that is received and decoded by the memory device activates only one of a plurality of storage cells that are coupled to a same bit-line. That is, each bit line is driven by a selected one of multiple storage cells that are coupled to the bit line.

As such, like the DRAM cells, the bottom electrode of each RRAM cell is connected to that cell's access transistor which resides directly beneath the RRAM cell. Unlike the DRAM cells, however, the top electrodes of the RRAM cells are not coupled to a same reference node. Instead the respective top electrodes of RRAM cells in a same group are coupled to a common source node for that group. That is, each group of RRAM cells in a same group or array share a common source node.

With the RRAM embedded memory design coupling a group of RRAM devices to a particular common source node, Fig. 3j depicts different source nodes 328, 329 within the embedded RRAM device and shows different groups of storage cells being coupled to the different source nodes 328, 329. The different RRAM source nodes 328, 329 are formed in the M5 metal layer. The reference node 327 that is coupled to the DRAM cells is also formed in the M5 metal layer.

Fig. 3k shows formation of vias 330 in the M6/M5 interlayer dielectric 328 that make respective contact to the DRAM reference node 327 and the RRAM source node structures 328, 329. Fig. 31 shows M6 metal structures that are used to couple the DRAM reference node 327 and the RRAM source nodes 328, 329 to their correct respective interconnects. Note also that the logic circuitry portion 335 of the semiconductor chip has also been developed throughout the process described above with respect to Figs. 3a through 31.

After the features of Fig. 31 are formed, the remainder of the semiconductor chip is formed according to standard processes.

Although embodiments above have been directed to the formation of vias according to a traditional damascene process, in yet other embodiments, a self-aligned via approach may be used to form the storage cell trenches. Here, as is known in the art, self-aligned vias use already patterned metal (copper) as a hard mask for the etched into regions of the trenches.

Figs. 4a through 4c pertain to other implementation details concerning an SOC having embedded RRAM and DRAM cells. A characteristic of RRAM cells vs DRAM cells is that RRAM cells typically require higher drive current and voltage when being written to or otherwise accessed as compared to DRAM cells. As such, an RRAM cell's access transistor should be larger (have wider channel width which generally corresponds to a wider gate length in the direction orthogonal to current flow) and be able to sustain higher voltage than a DRAM cell's access transistor (e.g., by being designed with a thicker gate dielectric).

Fig. 4a depicts this characteristic graphically where regions 401 correspond to regions where corresponding access transistors are located for the DRAM cells above them. Likewise, regions 402 correspond to regions where corresponding access transistors are located for the RRAM cells above them. As can be seen from Fig. 4a regions 402 are larger than regions 401 to demonstrate that the RRAM access transistors are larger than the DRAM access transistors.

Figs. 4b and 4c elaborate further on embodiments of accessing details of DRAM cells versus RRAM cells. Fig. 4b shows the accessing dynamics of DRAM cells whereas Fig. 4c shows the accessing dynamics of RRAM cells.

Referring to Fig. 4b, a four bit word is written to or read from depending on which word line is activated. That is, in an embodiment, there is one word line per supported address and each word line is coupled to the respective access transistor of a number of DRAM cells equal to the word size of the overall DRAM memory. In the depiction of Fig. 4b, word line 410 is activated which enables the access transistors and corresponding DRAM cells of region 411. The bit lines of the DRAM cells within region 411 either present the stored data in these cells in the case of a read or present data to be written into these cells in the case of a write. Note that all the cells can share the same reference voltage node .

By contrast, Fig. 4c shows that in the case of an RRAM memory different bits of a same memory word originate from different physical word lines. Here, sector A produces a first bit of a memory word and sector B produces a second bit of the memory word. As such, only one RRAM cell in a sector are activated for any applied memory address. In the example of Fig. 4c, only RRAM cells 420 and 421 are activated. As such, both of these RRAM cells control their respective source nodes which is common to all cells within their respective sector. As discussed at length above, the top electrode of the RRAM cells correspond to the source node and is connected to all RRAM cells in a same sector. RRAM cells in a same sector that are also coupled to a same word line are connected to the same word line through the bottom electrode metallurgy (e.g., at Ml in a direction orthogonal to the bitlines).

In an embodiment, during a read operation, the bitline of a selected RRAM cell in each sector is coupled to a sense amplifer. The source node is coupled to a ground voltage during the read operation. During a write operation, the source node is coupled to a ground voltage during the read operation. During a write operation, the source node is coupled to a ground voltage and a write current flows from the bitline to the access transistor, and, to reset the resistance of an RRAM cell, current flows from the access transistor to the RRAM cell and source node. To set the resistance of the RRAM cell, the source node is biased at a positive supply voltage and the write current flows from the source node to the RRAM cell and from the RRAM cell to the access transistor and bitline. Resetting the resistance of the RRAM cell changes its resistance value from a lower range to a high range. Setting the resistance of the RRAM cell, on the other hand, changes its resistance value from a higher range to a lower range.

Although embodiments discussed above show only one level of DRAM and RRAM cells, in various embodiments, there may be multi-levels of, e.g., at least RRAM cells. For example, an entire additional level of RRAM cells may be formed above the RRAM cells depicted in Figs. 3m and 4a in higher level interconnect so as to form, e.g., a three-dimensional non volatile memory. Further still, although embodiments above have depicted DRAM and RRAM cells of same height, in various embodiments the DRAM and RRAM cells may have different heights. Conceivably a vertical stack of RRAM cells could be formed over the same vertical expanse as a single DRAM cell. For instance, in reference to Figs. 3m and 4a, conceivably, a different RRAM cell could be formed in each of the M2, M3 and M4 levels so that a three-dimensional non volatile embedded memory is formed in the same vertical height dimension as a single embedded DRAM memory.

Fig. 5 shows a depiction of an exemplary computing system 500 such as a personal computing system (e.g., desktop or laptop) or a mobile or handheld computing system such as a tablet device or smartphone, or, a larger computing system such as a server computing system. As observed in Fig. 5, the basic computing system may include a central processing unit 501 (which may include, e.g., a plurality of general purpose processing cores and a main memory controller disposed on an applications processor or multi-core processor), system memory 502, a display 503 (e.g., touchscreen, flat-panel), a local wired point-to-point link (e.g., USB) interface 504, various network I/O functions 505 (such as an Ethernet interface and/or cellular modem subsystem), a wireless local area network (e.g., WiFi) interface 506, a wireless point-to-point link (e.g., Bluetooth) interface 507 and a Global Positioning System interface 508, various sensors 509_1 through 509_N (e.g., one or more of a gyroscope, an accelerometer, a magnetometer, a temperature sensor, a pressure sensor, a humidity sensor, etc.), a camera 510, a battery 511, a power management control unit 512, a speaker and microphone 513 and an audio coder/decoder 514.

An applications processor or multi-core processor 550 may include one or more general purpose processing cores 515 within its CPU 501, one or more graphical processing units 516, a memory management function 517 (e.g., a memory controller) and an I/O control function (peripheral control hub) 518. The general purpose processing cores 515 typically execute the operating system and application software of the computing system. The graphics processing units 516 typically execute graphics intensive functions to, e.g., generate graphics information that is presented on the display 503. The memory control function 517 interfaces with the system memory 502. The system memory 502 may be a multi-level system memory such as the multi-level system memory discussed at length above.

The host side processing cores 515, memory controller 517 and peripheral control hub 518 may be integrated on a system on chip that also includes embedded DRAM storage cells and embedded RRAM storage cells as described at length above. The DRAM and RRAM storage cells may be coupled to the memory controller 517 as parts of a multi-level system memory that is integrated on the system on chip. Alternatively or in combination, the RRAM storage cells may be used for traditional non volatile mass storage (e.g., a solid state disk drive) and may be coupled to the peripheral control hub 518.

Each of the touchscreen display 503, the communication interfaces 504 - 507, the GPS interface 508, the sensors 509, the camera 510, and the speaker/microphone codec 513, 514 all can be viewed as various forms of I/O (input and/or output) relative to the overall computing system including, where appropriate, an integrated peripheral device as well (e.g., the camera 510). Depending on implementation, various ones of these I/O components may be integrated on the applications processor/multi-core processor 550 or may be located off the die or outside the package of the applications processor/multi-core processor 550.

An apparatus has been described. The apparatus includes a semiconductor chip. The semiconductor chip includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded resistive random access memory (RRAM) cells. In various embodiments, the semiconductor chip is a system-on-chip and the logic circuitry is to implement: a plurality of processing cores, a memory controller and a peripheral control hub. In various embodiments at least a portion of the embedded RRAM cells are components within a multi-level system memory.

In various embodiments at least a portion of the embedded RRAM cells are components within a mass storage portion of the semiconductor chip. In various embodiments the semiconductor chip further includes DRAM cell access transistors and RRAM cell access transistors, where, the DRAM cell access transistors are disposed beneath respective ones of the embedded DRAM cells and the RRAM cell access transistors are disposed beneath respective ones of the embedded RRAM cells

In various embodiments, the DRAM cell access transistors are smaller than the RRAM cell access transistors. In various embodiments respective bit lines of the embedded DRAM cells reside beneath a MIM capacitor of the embedded DRAM cells. In various embodiments respective bit lines of the embedded RRAM cells reside beneath the RRAM cells. In various embodiments respective common source nodes of the embedded RRAM cells reside at a same metal level as a reference potential node of the embedded DRAM cells. In various embodiments both the embedded DRAM cells and the embedded RRAM cells are vertically disposed in structures that extend across the M4, M3 and M2 metal levels.

A computing system has been described. The computing system includes a flat panel screen and a semiconductor chip. The semiconductor chip includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded resistive random access memory (RRAM) cells.

In various embodiments of the computing system, the semiconductor chip is a system-on- chip and the logic circuitry is to implement: a plurality of processing cores, a memory controller and a peripheral control hub. In various embodiments of the computing system at least a portion of the embedded RRAM cells are components within a multi-level system memory. In various embodiments of the computing system at least a portion of the embedded RRAM cells are components within a mass storage portion of the semiconductor chip. In various embodiments of the computing system the semiconductor chip further includes DRAM cell access transistors and RRAM cell access transistors, where, the DRAM cell access transistors are disposed beneath respective ones of the embedded DRAM cells and the RRAM cell access transistors are disposed beneath respective ones of the embedded RRAM cells

In various embodiments of the computing system, the DRAM cell access transistors are smaller than the RRAM cell access transistors. In various embodiments of the computing system respective bit lines of the embedded DRAM cells reside beneath a MIM capacitor of the embedded DRAM cells. In various embodiments of the computing system respective bit lines of the embedded RRAM cells reside beneath the RRAM cells. In various embodiments of the computing system respective common source nodes of the embedded RRAM cells reside at a same metal level as a reference potential node of the embedded DRAM cells. In various embodiments of the computing system both the embedded DRAM cells and the embedded RRAM cells are vertically disposed in structures that extend across the M4, M3 and M2 metal levels.

A method has been described. The method includes forming the on-die interconnect structure of a semiconductor chip by depositing and patterning layers of dielectric and metal, the depositing and patterning including forming logic circuitry, embedded DRAM cells and embedded RRAM cells.

In various embodiments the method further includes, prior to the forming of the embedded DRAM cells and the embedded RRAM cells, forming smaller access transistors in the semiconductor substrate of the semiconductor die in locations beneath where respective MIM capacitors of the embedded DRAM cells are to be formed and forming larger access transistors in the semiconductor substrate of the semiconductor die in locations beneath where respective RRAM devices of embedded RRAM cells are to be formed.

In various embodiments of the method respective structures within the on-die interconnect structure include features of the logic circuitry, where, the embedded DRAM cells and the embedded RRAM cells reside along a same metal level. In various embodiments, prior to the forming of the embedded DRAM cells, embedded DRAM bit lines are formed in the on- die interconnect structure in locations beneath where their respective MIM capacitors of the embedded DRAM cells are to be formed. In various embodiments the method includes forming embedded RRAM bit lines beneath respective RRAM devices of the embedded RRAM cells. In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An apparatus, comprising:

a semiconductor chip comprising:

logic circuitry;

embedded dynamic random access memory (DRAM) cells;

embedded resistive random access memory (RRAM) cells.

2. The apparatus of claim 1 wherein the semiconductor chip is a system-on-chip and the logic circuitry is to implement:

a plurality of processing cores;

a memory controller;

a peripheral control hub.

3. The apparatus of claim 1 wherein at least a portion of the embedded RRAM cells are components within a multi-level system memory.

4. The apparatus of claim 1 wherein at least a portion of the embedded RRAM cells are components within a mass storage portion of the semiconductor chip.

5. The apparatus of claim 1 wherein the semiconductor chip further comprises DRAM cell access transistors and RRAM cell access transistors, the DRAM cell access transistors disposed beneath respective ones of the embedded DRAM cells, the RRAM cell access transistors disposed beneath respective ones of the embedded RRAM cells

6. The apparatus of claim 5 wherein the DRAM cell access transistors are smaller than the RRAM cell access transistors.

7. The apparatus of claim 1 wherein respective bit lines of the embedded DRAM cells reside beneath a MIM capacitor of the embedded DRAM cells.

8. The apparatus of claim 1 wherein respective bit lines of the embedded RRAM cells reside beneath the RRAM cells.

9. The apparatus of claim 1 wherein respective common source nodes of the embedded RRAM cells reside at a same metal level as reference potential node of the embedded DRAM cells.

10. The apparatus of claim 1 wherein both the embedded DRAM cells and the embedded RRAM cells are vertically disposed in structures that extend across the M4, M3 and M2 metal levels.

11. A computing system, comprising:

a flat panel screen;

a semiconductor chip comprising:

logic circuitry;

embedded dynamic random access memory (DRAM) cells;

embedded resistive random access memory (RRAM) cells.

The computing system of claim 11 wherein the semiconductor chip is a system-on-chip and logic circuitry is to implement:

a plurality of processing cores;

a memory controller;

a peripheral control hub.

13. The computing system of claim 11 wherein at least a portion of the embedded RRAM cells are components within a multi-level system memory.

14. The computing system of claim 11 wherein at least a portion of the embedded RRAM cells are components within a mass storage portion of the semiconductor chip.

15. The computing system of claim 11 wherein the semiconductor chip further comprises DRAM cell access transistors and RRAM cell access transistors, the DRAM cell access transistors disposed beneath respective ones of the embedded DRAM cells, the RRAM cell access transistors disposed beneath respective ones of the embedded RRAM cells.

16. The computing system of claim 15 wherein the DRAM cell access transistors are smaller than the RRAM cell access transistors.

17. The computing system of claim 11 wherein respective bit lines of the embedded DRAM cells reside beneath the MIM capacitor of embedded DRAM cells.

18. The computing system of claim 11 wherein respective bit lines of the embedded RRAM cells reside beneath the RRAM cells.

19. The computing system of claim 11 wherein respective common source nodes of the embedded RRAM cells reside at a same metal level as reference potential node of the embedded DRAM cells.

20. The computing system of claim 11 wherein both the embedded DRAM cells and the embedded RRAM cells are vertically disposed in structures that extend across the M4, M3 and M2 metal levels.

21. A method comprising:

forming the on-die interconnect structure of a semiconductor chip by depositing and patterning layers of dielectric and metal, the depositing and patterning including forming logic circuitry, embedded DRAM cells and embedded RRAM cells.

22. The method of claim 21 further comprising, prior to the forming of the embedded DRAM cells and the embedded RRAM cells, forming smaller access transistors in the semiconductor substrate of the semiconductor die in locations beneath where respective MIM capacitors of the embedded DRAM cells are to be formed and forming larger access transistors in the semiconductor substrate of the semiconductor die in locations beneath where respective RRAM devices of embedded RRAM cells are to be formed.

23. The method of claim 21 wherein respective structures within the on-die interconnect structure comprise features of the logic circuitry, the embedded DRAM cells and the embedded RRAM cells residing along a same metal level.

24. The method of claim 21 further comprising, prior to the forming of the embedded DRAM cells, forming embedded DRAM bit lines in the on-die interconnect structure in locations beneath where their respective MIM capacitors of the embedded DRAM cells are to be formed.

25. The method of claim 21 further comprising forming embedded RRAM bit lines beneath respective RRAM devices of the embedded RRAM cells.