WO2018058403A1

WO2018058403A1 - Techniques for movement of data between virtual machines

Info

Publication number: WO2018058403A1
Application number: PCT/CN2016/100727
Authority: WO
Inventors: Danny Y. ZHOU; Cunming LIANG
Original assignee: Intel Corporation
Priority date: 2016-09-29
Filing date: 2016-09-29
Publication date: 2018-04-05

Abstract

Examples include techniques for movement of data between virtual machines supported by a computing system. Example techniques include movement of data for a packet payload of a network packet sourced from a first VM. The data being moved from a first memory region of system memory allocated to a first VM to a second memory region of system memory allocated to a second VM.

Description

Techniques for Movement of Data between Virtual Machines

TECHNICAL FIELD

Examples described herein are generally related to movement of packetized data between virtual machines.

BACKGROUND

A relatively new technology referred to as network function virtualization (NFV) is rapidly evolving over recent years. In some examples, NFV infrastructure is becoming increasingly important to large data centers or telecommunication providers to allow for a pooling of at least some computing resources that may disaggregated and/or located in diverse geographic locations. In a traditional virtualized environment for NFV infrastructure, multiple virtual machines (VMs) may be supported by a host computing system. A software-based virtual switch for the host computing system may work with a host computing system hypervisor to allow the VMs to transmit and receive network packets between each other.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example system.

FIG. 2 illustrates example first and second formats.

FIG. 3 illustrates an example third format.

FIG. 4 illustrates an example process.

FIG. 5 illustrates an example first logic flow.

FIG. 6 illustrates an example second logic flow.

FIG. 7 illustrates an example block diagram for a first apparatus.

FIG. 8 illustrates an example of a third logic flow.

FIG. 9 illustrates an example of a first storage medium.

FIG. 10 illustrates an example block diagram for a second apparatus.

FIG. 11 illustrates an example of a fourth logic flow.

FIG. 12 illustrates an example of a second storage medium.

FIG. 13 illustrates an example computing platform.

FIG. 14 illustrates an example network input/output (I/O) device.

DETAILED DESCRIPTION

As contemplated in the present disclosure, a software-based virtual switch for a host computing system may work with a host computing system hypervisor to allow VMs supported by the host computing system to transmit and receive network packets between each other. In some examples, if a network packet transmitted from a first VM at the host computing system has a destination media access control (MAC) or internet protocol (IP) address matching a second VM at the host computing system, the software-based virtual switch may not physically transmit the packet using, for example, an Ethernet network interface card (NIC) . Rather, the software-based virtual switch may transmit or send the network packet to the destination second VM via software rings for a system memory of the host computing system.

Several technologies including, but not limited to, technologies for an input/output memory management unit (IOMMU) or a single root input/output virtualization (SR-IOV) have been designed and used by Ethernet NICs to support VM-to-VM communication within a hosted computing system. In some examples, these VM-to-VM communications may be facilitated via use of isolated virtual functions (VFs) at an Ethernet NIC. Each isolated VF may be directly assigned to a given VM by a hypervisor arranged to manage VMs supported by the host computing system. The VM-to-VM communications facilitated by the isolated VFs may be routed through an Ethernet NIC arranged as an endpoint that may utilize communication protocols and/or interfaces according to the Peripheral Component Interconnect (PCI) Express Base Specification, revision 3.1a, published in December 2015 ( "PCI Express specification" or "PCIe specification" ) or Ethernet communications protocols according to one or more Ethernet standards promulgated by the Institute of Electrical and Electronics Engineers (IEEE) . For example, one such Ethernet standard promulgated by IEEE may include IEEE 802.3-2012, Carrier sense Multiple access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Published in December 2012 (hereinafter “IEEE 802.3 specification” ) . For these examples, the Ethernet NIC arranged as an endpoint for VM-to-VM communications and arranged to operate according to PCIe and IEEE 802.3 specifications may be referred to as a “PCIe Ethernet NIC” or “PCIe Ethernet endpoint” .

According to some examples, the IOMMU and/or SR-IOV may be designed and used by an Ethernet NIC such as a PCIe Ethernet NIC to support VM-to-VM communications facilitated via use of isolated VFs at the Ethernet NIC without involvement of a software-based virtual switch. For these examples, a PCIe Ethernet NIC enabled to work with an SR-IOV or IOMMU may include either a dummy layer-2 (L2) or programmable switch (e.g., with a network processor or field programmable gate array (FPGA) ) . The dummy L2 or programmable switch may be capable of forwarding network packets from a first VM to a second VM in a high throughput and low latency manner that may be substantially in hardware.

In some examples, operators of data centers or telecommunication providers in an NFV environment may request moving network traffic at a line rate of 10 gigabits (Gb) /40Gb/100Gb or higher among multiple, chained virtualized network functions (VNFs) supported by VMs having directly assigned VFs at a given PCIe Ethernet NIC. Moving this kind of high bandwidth traffic from VM to VM may be challenging. The challenge may be due to a PCIe link routed through the directly assigned VFs at the PCIe Ethernet NIC being limited to a maximum of 16 lanes according to the PCIe specification and this limitation may not offer enough bandwidth in a highly scalable fashion even though a PCIe Ethernet NIC may have built-in switching capabilities sufficient for network packet processing needs between VMs.

According to some examples, a 40Gb/second line rate may be desired for an end-to-end NFV scenario with 4 VNFs being supported by a host computing system or server. For these examples, the PCIe Ethernet NIC would need at least 3*40Gb/second PCIe link bandwidth inbound and 3*40Gb/second PCIe link bandwidth outbound, despite also having to receive/transmit 40Gb/second network traffic from/to a network link or wire. This may be due to each network packet needing to traverse a given PCIe link several times if the PCIe Ethernet NIC utilizes direct memory access (DMA) transactions to move network packets between system memory for the host computing system and the PCIe Ethernet NIC. This movement of full network packets (e.g., headers and payloads) may be problematic to maintaining the desired 40Gb/second line rate. Relatively small packet sizes associated with VMs supporting applications for telecommunication providers may increase difficulties in maintaining the desired 40GB/second line rate. It is with respect to these challenges that the examples described herein are needed.

FIG. 1 illustrates an example system 100. In some examples, as shown in FIG. 1, system 100 includes a processor 110 coupled with a system memory 120 and a PCIe Ethernet NIC 150 via

respective links

130 and 140. Also. As shown in FIG. 1, PCIe Ethernet NIC 150 may be coupled with a network 170 via link 180. According to some examples, as shown in FIG. 1, processor 100 may be capable of supporting a plurality of virtual machines (VMs) including VM 160-1 to 160-N, where “N” as used for VMs 160-1 to 160-N and other elements of system hereinafter refers to any whole positive integer greater than 2.

In some examples, system memory 120, processor 110 and PCIe Ethernet NIC 150 may be physical elements arranged as part of NFV infrastructure that supports virtual elements such as VMs 160-1 to 160-N that may execute applications associated with chained VNFs. Also, communications between VMs 160-1 to 160-N may be facilitated by virtualized functions (VFs) that may be directly assigned to physical I/O devices such as PCIe Ethernet NIC 150. For example, VFs 161-1 to 161-N may be directly assigned to PCIe Ethernet NIC 150 to serve as a lightweight PCIe function to support SR-IOV for communications between respective VMs 160-1 to 160-N. VFs 161-1 to 161-N may be directly assigned by a hypervisor (not shown) arranged to manage VMs 160-1 to 160-N. VFs 161-1 to 161-N may be driven/controlled via VF drivers 162-1 to 162-N executed by respective VMs 160-1 to 160-N to allow these VMs to directly interact with respective packet buffers 154-1 to 154-N. In some examples, direct interaction may be through a PCIe root complex 111 included in an integrated I/O 112 for processor 110 that may couple with PCIe Ethernet NIC 150 via link 140. According to some examples, PCIe root complex 111 and PCIe Ethernet NIC 150 may utilize communication protocols and interfaces according to the PCIe specification to enable the VF drivers 162-1 to 162-N to directly interact with VFs 161-1 to 161-N via link 140.

In some examples, as shown in FIG. 1, processor 110 may include processing element (s) 119. Processing element (s) 119 may include one or more processing cores. In one example, VMs 160-1 to 160-N may be supported by separate processing cores or may be supported by combination of processing cores. Processor 110 may also include a ring bus 117 arranged to facilitate communications between processing element (s) 119, memory controller 118 and elements of integrated I/O 112 to further the support of VMs 160-1 to 160-N. In some examples, memory controller 118 may manage read or write requests to system memory 120 via link 130 in support of VMs 160-1 to 160-N. Meanwhile, integrated I/O 112 may facilitate I/O communications with I/O devices such as PCIe Ethernet NIC 150 via link 140 in support of VMs 160-1 to 160-N.

According to some examples, as shown in FIG. 1, in addition to the above-mentioned PCIe root complex 111, integrated I/O 112 may also include a direct memory access (DMA) engine 114 and an input/output memory management unit (IOMMU) 115. These elements of integrated I/O 111 may be coupled via an integrated I/O (IIO) bus 116. As described more below, these elements of integrated I/O 112 may include logic and/or features capable of facilitating efficient movement of data associated with network packets exchanged by VMs supported by processor 110 and having allocated system memory from system memory 120. One such feature is a Lookup DMA remapping table 109 maintained at IOMMU 115 that may be utilized to translate guest physical addresses (GPAs) used by VMs to host physical addresses (HPAs) used by DMA engine 114 for DMA data to system memory 120.

In some examples, as shown in FIG. 1, packet buffers 154-1 to 154-N may include receive (Rx) or transmit (Tx) packet buffers. Packet buffers 154-1 to 154-N may be directly assigned to respective VFs 161-1 to 161-N. Logic and/or features of PCIe Ethernet NIC 150 such as PCIe endpoint logic 156 may work in cooperation with logic and/or features of PCIe root complex 111 such as a data movement agent 113 may facilitate transfers of data included in or referenced in network packets transmitted between VMs. As described more below, the transmission of network packets between VMs may utilize a process that includes moving data for a packet header of a network packet transmitted by a first VM from a first memory region of a system memory such as memory region 124 of system memory 120 to a second memory region of the system memory such as memory region 122 of system memory 120. The process may then include moving data for a packet payload for the network packet from the first memory region to the second memory region.

According to some examples, in order to utilize the process of moving data for a packet header and a packet payload, both a source VM and a target VM may have to turn on a NIC header split feature on both Tx and Rx sides via their respective VF drivers to cause a PCIe Ethernet NIC to automatically split packet headers from packet payloads. The split packet headers may then be caused to be stored in different memory locations of either a first memory region allocated to a source VM (Tx side) that caused transmission of a network data packet or a second memory region allocated to a destination VM (Rx side) to receive the network data packet.

In some examples, as shown in FIG. 1, a Tx descriptor 125 may include information to indicate that data for a packet header has been split from data for a packet payload. The information in Tx descriptor 125 may include a header pointer (HDR_PTR) field and a header length (HDR_LEN) field to provide information about where in memory region 124 the data for the packet header has been stored. The information in Tx descriptor 125 may also include a payload pointer (PAYLOAD_PTR) field and a payload length (PAYLOAD_LEN) field to provide information about where in memory region 124 the data for the packet payload has been stored. Information in Rx description 123 may include the same pointer fields to indicate where the data for the packet header and data for the packet payload may be eventually stored in memory region 122. According to some examples, both Tx descriptor 125 and Rx descriptor 123 may include a descriptor done (DD) flag to indicate whether or not data for a network packet has been either moved to its targeted memory region (e.g., for a cross-VM transfer) or transmitted to a network (e.g., network 170) .

According to some examples, a source VM such as VM 160-1 may cause transmission of a network packet. For these examples, VF driver 162-1 may cause Tx descriptor 125 to be placed in packet buffer 154-1 directly assigned to VF 161-1 at PCIe Ethernet NIC 150 or may provide a pointer for PCIe Ethernet NIC 150 to fetch Tx descriptor 125 from memory region 124. PCIe Ethernet NIC 150 may then fetch the header from memory region 124 based on information included in Tx descriptor 125. If logic and/or features at PCIe Ethernet NIC 150 such as PCIe endpoint logic 156 decides to forward the network packet to another local VM from among VMs 160-2 to 160-N, the PCIe endpoint logic 156 and logic and/or features at PCIe root complex 111 such as data movement agent 113 may initiate additional actions to move or transfer data for the packet payload of the network packet to memory region 122 that is allocated to the targeted VM.

In some examples, as described more below, data movement agent 113 may be able to facilitate movement of cross-VM data on behalf of PCIe Ethernet NIC 150. For example, data movement agent 113 may directly issue lookup requests to IOMMU 115 to utilize Lookup DMA remapping table 109 to translate GPAs to HPAs and then uses the HPAs to drive DMA transactions through DMA engine 114 to system memory 120. These actions may need no software involvement by utilizing both IOMMU 115 and DMA engine 114 to quickly and efficiently move data while also minimizing amounts of data needing to be routed through link 140 for cross-VM data movement from memory regions allocated to a source VM to memory regions allocated to a target VM.

According to some examples, system memory 120, processor 110 and PCIe Ethernet NIC 150 may be hosted by a host computing platform that may include, but is not limited to, a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, or combination thereof.

In some examples, processor 110 may include various commercially available processors, including without limitation an

and

processors；

application, embedded and secure processors；

and

processors； IBM and

Cell processors；

Core (2)

Core i3, Core i5, Core i7,

or Xeon

processors； and similar processors.

According to some examples, system memory 120 may be composed of one or more memory devices or dies which may include various types of volatile and/or non-volatile memory. Also, packet buffers 154-1 to 154-N may also include one or more memory devices or dies which may include various types of volatile and/or non-volatile memory. Volatile memory may include, but is not limited to, random-access memory (RAM) , Dynamic RAM (D-RAM) , double data rate synchronous dynamic RAM (DDR SDRAM) , static random-access memory (SRAM) , thyristor RAM (T-RAM) or zero-capacitor RAM (Z-RAM) . Non-volatile memory may include, but is not limited to, non-volatile types of memory such as 3-D cross-point memory that may be byte or block addressable. These block addressable or byte addressable non-volatile types of memory may include, but are not limited to, memory that uses chalcogenide phase change material (e.g., chalcogenide glass) , multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM) , resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM) , magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, or spin transfer torque MRAM (STT-MRAM) , or a combination of any of the above, or other non-volatile memory types.

FIG. 2 illustrates example formats 210 and 220. In some examples,

formats

210 and 220 may be example PCIe transaction layer packet (TLP) formats to transmit information between transaction layers of components communicating to each other according to the PCIe specification. For example, between PCIe root complex I/O 111 and PCIe Ethernet NIC 150 of system 100. The information, for example, may include information for a memory-to-memory move request to facilitate cross-VM data movement within system memory as mentioned above for system 100. Example format 210 depicts a PCIe TLP format for 32-bit addressing of memory and example format 220 depicts another PCIe TLP format for 64-bit addressing of memory. For simplicity purposes, example formats 210 and 220 shown in FIG. 2 do not label all fields that may be associated with a PCIe TLP format according to the PCIe specification. Fields that are labeled and shown in FIG. 2 include fields 211 to 218 for

example formats

210 and 220. These labeled fields may be applicable to a memory-to-memory move request and are described in more detail below.

According to some examples, the PCIe specification may support basic transaction TLP types such as memory transactions, I/O transactions, configuration transaction and message transactions. A memory transaction type, according to the PCIe specification, may support Memory Read and Memory Write requests. A Memory Read request may be used to DMA data from a system memory such as system memory 120 to a PCI endpoint such as PCIe Ethernet NIC 150. A Memory Write request may be used to DMA data from the PCI endpoint to the system memory. However, no existing PCIe TLP transaction type described in the PCIe specification allows the PCIe endpoint to issue a memory-to-memory move request.

Although no existing PCIe TLP transaction type described in the PCIe specification exists for a PCIe endpoint initiated memory-to-memory move request, Vender_Defined message types per the PCIe specification may be extended. The extension of the Vender_Defined message type may be such that customized vendor definition fields from Byte 12 to Byte 24 of example format 210 and Byte 12 to 32 of example format 220 may be arranged to include information for a memory-to-memory move request to facilitate cross-VM data movement within a system memory.

In some examples, requestor identifier (ID) 218 field of example formats 210 or 220 may be hard-coded to an ID of a requesting PCIe endpoint (e.g., physical function of a PCIe Ethernet NIC) . Also, type 211 field may include a message routing subfield (not shown) . The message routing sub-field may include 3-bits (e.g., bits [2: 0] ) of the type 211 field and may be hard-coded to a binary value of “000” to indicate that a PCIe TLP message in the format of example formats 210 or 220 is to be routed to a PCIe root complex. Further, AT 212 field may need to be set to a binary value of “01” to indicate a translation (e.g., GPAs to HPAs) is requested of an IOMMU such as IOMMU 115 included at integrated I/O 112. As described more below, logic and/or features at the PCIe root complex (e.g., a data movement agent) may initiate a translation by the IOMMU responsive to receiving a memory-to-memory move request via a PCIe TLP message in the format of

example format

210 or 220.

According to some examples, source ID 213 of

formats

210 or 220 may be an identifier (ID) for a VF directly assigned to a source VM that caused transmission of a network packet that may include payload data associated with a memory-to-memory request. For these examples, the 16 bits in source ID 213 may be in a Bus: Number: Function format that may be composed of three sub-fields to identify the VF. The Bus: Number: Function format may include an 8-bit Bus Number, a 5-bit Device Number, and a 3-bit Function Number.

In some examples, destination ID 214 may be an ID of a VF directly assigned to a target VM that may receive the network packet from the source VM identified in source ID 213. For these examples, the 16 bits in destination ID 214 may also be in a similar Bus: Number: Function format as mentioned for source ID 213.

According to some examples, source address 215 field may indicate a GPA to identify where payload data for the network packet may be located for memory allocated to the source VM that transmitted the network packet. As shown in FIG. 2, source address field 215 for example format 210 may accommodate a 32-bit memory address. Meanwhile, source address field 215 for example format 210 may accommodate a 64-bit memory address.

In some examples, destination address 216 field may indicate a GPA to indicate where payload data for the network packet may be moved to memory allocated to the destination VM that is to receive the network packet. As shown in FIG. 2, destination address field 216 for example format 210 may accommodate a 32-bit memory address. Meanwhile, destination address field 216 for example format 210 may accommodate a 64-bit memory address.

According to some examples, transfer size 217 field may indicate a size for data in the payload packet that is to be moved from the memory allocated to the source VM to the memory allocated to the destination VM. The size indicated in transfer size 217 may be, but is not limited to, an indication of size in number of bytes.

FIG. 3 illustrates an example format 300. In some examples, format 300 may be an example format for a PCIe TLP Completion Header as described in the PCIe specification. For these examples, a PCIe root complex (e.g., PCIe root complex 111) may send a message having a header in the example format of format 300 to indicate to a PCIe endpoint (e.g., PCIe Ethernet NIC 150) whether a requested memory-to-memory move transaction has been completed. For simplicity purposes, example format 300 shown in FIG. 3 does not label all fields that may be associated with a PCIe TLP Completion Header according to the PCIe specification. Fields that are labeled include fields 301 to 305. These labeled fields may be applicable to a PCIe TLP Completion Header to indicate whether a requested memory-to-memory move transaction has been completed.

According to some examples, completer ID 303 field may indicate an ID of a PCIe root complex (e.g., PCIe root complex 111) that includes logic and/or features (e.g., data movement agent 112) that facilitated a cross-VM data movement responsive to a PCIe endpoint initiated memory-to-memory move request. Requester ID 305 may indicate an ID of the PCIe endpoint that initiated the memory-to-memory move request. Completion status 304 field may indicate a completion status to include, but not limited to, a successful completion, an unsupported request, a configuration request retry or a completion abort.

FIG. 4 illustrates an example process 400. In some examples, process 400 may be for initiating a memory-to-memory move request to facilitate a cross-VM data movement within system memory allocated to VMs supported by elements of a host computing system. The VMs may be arranged to separately execute one or more applications associated with chained VNFs. The VMs may each have directly assigned VFs at a physical I/O device such as a PCIe Ethernet NIC. The memory-to-memory move request may be responsive to a network packet transmitted by a first VM to a second VM supported by a same host computing system. The transmission of the network packet may cause a VM-to-VM network packet transaction. For these examples, elements of system 100 as shown in FIG. 1 may be related to process 400. These elements of system 100 may include processor 110, system memory 120 or PCIe Ethernet NIC 150 arranged to support VMs 160-1 to 160-N that may have respective directly assigned VFs 161-1 to 161-N at PCIe Ethernet NIC 150. Also, sub-elements of processor 110 such as PCIe root complex 111, data movement agent 113, DMA engine 114, IOMMU 115 or memory controller 118 of processor 110 or built-in L2/L3 switch 152, buffers 154-1 to 154-N or PCIe endpoint logic 156 of PCIe Ethernet NIC 150 may be related to process 400. Further, example formats 210, 220 or 300 as shown in FIGS. 2-3 may also be related to process 400. However, example process 400 is not limited to implementations using elements/sub-elements of system 100 or example formats 210, 220 or 300 shown in FIGS. 1-3.

Beginning at process 4.1 (Mem-to-Mem Move Req. ) , logic and/or features at PCIe Ethernet NIC 150 such as PCIe endpoint logic 156 may generate a PCIe TLP according to example format 210 (if a 32-bit memory address applies) or example format 220 (if a 64-bit memory address applies) . The PCIe TLP in the format of

example format

210 or 220 may be generated in response to a network packet transmitted by a VM from among VMs 160-1 and 160-2 and may include information for a memory-to-memory move request. The memory-to-memory move request may be to move data included in a packet payload for the network packet from memory region 124 assigned to VM 160-1 to memory region 122 assigned to VM 160-2. As mentioned above, formats 210 or 220 may include information to indicate a GPA source address in memory region 124 to read the data and a GPA destination address in memory region 122 to write the data. GPAs apply because VMs operate using these types of virtual memory addresses. PCIe endpoint logic 156 may cause the PCIe TLP to be transmitted to data movement agent 113 at PCIe root complex 111 via link 140.

Moving to process 4.2 (Lookup DMA Remapping Table) , data movement agent 113, responsive to the memory-to-memory move request indicated in a received PCIe TLP in the

example format

210 or 220, may send the GPAs indicated in the received PCIe TLP to IOMMU 115 via IIO bus 116 to utilize lookup DMA remapping table 109.

Moving to process 4.3 (Translation of GPAs to HPAs) , logic and/or features at IOMMU 115 may translate the GPAs indicated in the PCIe TLP received by data movement agent 113 to HPAs using lookup DMA remapping table 109. In some examples, the translation from GPAs to HPAs is needed because the DMA engine 114 may operate using HPAs to perform read or write operations to system memory 120.

Moving to process 4.4 (Mem-to-Mem DMA Request) , data movement agent 113 may generate a memory-to-memory DMA request message to DMA engine 114 that includes replacing the GPAs indicated in the received PCIe TLP with the translated HPAs provided by IOMMU 115 and also indicates a transfer size for the data included in the packet payload (e.g., pulled from transfer size 217 field of the received PCIe TLP) . The memory-to-memory DMA request message may be made via IIO bus 116 to DMA engine 114.

Moving to process 4.5 (Activate DMA Channel) , responsive to the memory-to-memory DMA request, DMA engine 114 may activate a DMA channel via ring bus 117 for a DMA transaction to system memory 120.

Moving to process 4.6 (Read Packet Payload from Source Memory Region) , DMA engine 114 may read data included in the packet payload from memory region 124.

Moving to process 4.7 (Write Packet Payload to Target Memory Region) , DMA engine 114 may then write the data read from memory region 124 to memory region 122.

Moving to process 4.8 (De-Activate DMA Channel) , DMA engine 114 may then de-active the DMA channel.

Moving to process 4.9 (Completion Indication) , DMA engine 114 may send a DMA transaction done message to data movement agent 113 to indicate that the data included in the packet payload has been moved as requested.

Moving to process 4.10 (PCIe TLP Completion Message) , data movement agent 113 may generate a PCIe TLP completion message having a PCIe completion header in the format of example format 300 to indicate that the data included in the packet payload has been completed. In some examples, completion status 304 field in the TLP completion header may indicate a successful completion.

FIG. 5 illustrates an example logic flow 500. In some examples, logic flow 500 may be implemented by logic and/or features at a PCIe Ethernet NIC such as PCIe endpoint logic 156 at PCIe Ethernet node 150 of system 100 shown in FIG. 1. PCIe endpoint logic 156 may be capable of generating a PCIe TLP in the format of example formats 210 or 220 as shown in FIG. 2 to initiate a memory-to-memory move request similar to what was described above for process 400 shown in FIG. 4 for moving data for a packet payload from memory region 124 allocated to VM 160-1 to memory region 122 allocated to VM 160-2. PCIe endpoint logic 156 may also be capable of receiving a TLP completion message in the format of example format 300 shown in FIG. 3. However, logic flow 500 is not limited to being implemented by a PCIe endpoint logic such as PCIe endpoint logic 156 at PCIe Ethernet node 150 shown in FIG. 1 or to use of

packet formats

210, 220 or 300 shown in FIGS. 2-3.

Beginning at block 502, PCIe endpoint logic 156 to determine whether a Tx packet descriptor is available for sending VM may base this determination on receiving an indication from VF driver 162-1 that VM 160-1 having directly assigned VF 161-1 has generated a network packet and has placed Tx packet descriptor 125 in memory region 124.

At block 504, responsive to VF driver 162-1, PCIe endpoint logic 156 may transfer data for a packet header pointed by a Tx packet descriptor in a memory region of system memory to a packet buffer via a TLP memory read transaction. According to some examples, PCIe endpoint logic 156 may cause VF 161-1 to generate a PCIe TLP memory read message and send to PCIe Root complex 111 to fetch Tx descriptor 125 and then send a second PCIe TLP memory read message to receive data for the packet header stored to memory region 124 based on the header pointer information included in Tx descriptor 125.

At decision block 506, PCIe endpoint logic 156 may determine whether the fetched data for the packet header hits a forwarding rule to a local VF. In some examples, a network packet destined for VM 160-2 may be a hit for a forwarding rule to a local VF. The logic flow may then move to block 514. Otherwise, the network packet is not destined for a local VM and logic flow 500 moves to block 508.

At block 508, PCIe endpoint logic 156 may cause VF 160-1 to transfer data for a packet payload pointed by Tx packet descriptor 125 from memory region 124 to packet buffer 154-1 via a PCIe TLP memory read transaction. According to some examples, PCIe endpoint logic 156 may cause VF 160-1 to generate a PCIe TLP memory read message and send to PCIe Root complex 111 to fetch data for the packet payload stored to memory region 124 based on the payload pointer information included in Tx descriptor 125.

At block 510, logic and/or features at PCIe Ethernet NIC 150 such as PCIe endpoint logic 156 may cause the network packet to be transmitted to a wire. For example, the network packet generated by VM 160-1 may be transmitted from packet buffer 154-1 to network 170 via link 180.

At block 512, an update to a descriptor done (DD) flag for Tx descriptor 125 may result when PCIe endpoint logic 156 causes VF 161-1 to generate a TLP memory write message and then send the TLP memory write message to PCIe root complex 111 to cause the DD flag for Tx descriptor 125 to indicate that data for the network packet transmitted by VM 160-1 has been transmitted from PCIe Ethernet NIC 150.

At block 514, logic flow 500 has determined that the data for the header fetched from memory region for the network packet transmitted by VM 160-1 has hit a forwarding rule to a local VM. At block 514, PCIe endpoint logic 156 may cause VF 161-1 to get a packet payload address from a first available Rx packet descriptor of a receiving VM. In some examples, PCIe endpoint logic 156 may cause VF 161-1 to send a PCIe TLP memory read message to PCIe root complex 111 to fetch Rx descriptor 123 from memory region 122. PCIe endpoint logic 156 may also cause VF 161-1 to send a PCIe TLP memory write message to PCIe root complex 111 to write data for the header of the network packet to memory region 122 and then update the HDR_TR and HDR_LEN of Rx descriptor 123 to indicate where the data for the header has been written to in memory region 122.

At block 516, PCIe endpoint logic 156 may initiate a memory-to-memory move request. In some examples, PCIe endpoint logic 156 may cause VF 161-1 to generate a PCIe TLP according to

example format

210 or 220 and may fill source address 215 field with information pulled from Tx descriptor 125 for a GPA location in memory region 124 to read data for the packet payload of the network packet generated by VM 160-1. PCIe endpoint logic 156 may also fill destination address 216 field with information pulled from Rx descriptor 123 for a GPA location in memory region 122 to write data for the packet payload of the network packet.

At block 518, PCIe endpoint logic 156 may cause VF 161-1 to send the PCIe TLP to PCIe root complex 111 through an upstream port routed via link 140. In some examples, the PCIe TLP may be received by data movement agent 113.

At block 520, PCIe endpoint logic 156 may wait for a PCIe TCP completion message from PCIe root complex 111. According to some examples, the TCP completion message may be in the format of example format 300 and may have been sent by logic and/or features of PCIe root complex 111 such as data movement agent 113 via link 140.

At decision block 522, PCIe endpoint logic 156 may determine whether the TLP completion message has been received. If not, logic flow 500 moves to block 520. If the TLP completion message is received, logic flow 500 moves to block 522.

At decision block 524, PCIe endpoint logic 156 may use information include in completion status 304 field of the TLP completion message to determine if the memory-to-memory move request was successful. If successful, logic flow 500 moves to block 532. Otherwise, logic flow 500 moves to decision block 526.

At decision block 526, PCIe endpoint logic 156 may use information include in completion status 304 field of the TLP completion message to determine if the memory-to-memory move request was an unsupported request. In some examples, an unsupported request may occur if DMA engine 114 does not support direct DMA received from logic and/or features of PCIe root complex 111 such as data movement agent 113 or may be unsupported if PCIe root complex 111 doesn’ t include a data movement agent 113 to obtain GPA-to-HPA translations. If unsupported, logic flow 500 moves to block 526. Otherwise, the TLP completion message may indicate that the memory-to-memory request may be in a configuration request retry or was aborted.

At block 528, PCIe endpoint logic 156 may cause VF 161-1 to transfer data for the packet payload for the network packet generated by VM 160-1 from system memory to packet buffer 154-2 for VF 161-2 directly assigned to destination VM 160-2. In some examples, PCIe endpoint logic 156 may cause VF 161-1 to generate and send a TLP memory read message to PCIe root complex 111 to cause data for the packet payload to be fetched from memory region 124 via a PCIe TLP memory read transaction.

At block 530, PCIe endpoint logic 156 may cause a transfer of data for the packet header and packet payload for the network packet generated by VM 160-1 to the receiving VM 160-2’s memory region 122 via a TLP memory write transaction. In some examples, PCIe endpoint logic 156 may cause VF 161-1 to generate and send a PCIe TLP memory write message to PCIe root complex 111 to cause data for the packet header and packet payload to be written to memory region 124 via a TLP memory write transaction.

At block 532, PCIe endpoint logic 156 may cause VF 161-1 to update the DD flag on both the Tx packet descriptor and the Rx packet descriptor. In some examples, since the TLP completion packet has indicated as a successful completion, the DD flag for both Tx packet descriptor 125 and Rx packet descriptor 123 may be updated (e.g., change a bit value from “0” to “1” ) to indicate that these packet descriptors are complete. PCIe endpoint logic 156 may also have VF 161-1 cause the PAYLOAD_PTR and PAYLOAD_LEN information in Rx packet descriptor 123 to be updated to reflect where the data for the packet payload was stored in memory region 122. VF 161-1 may be able to check the DD flag in Tx packet descriptor 125 to confirm the network packet has been transmitted to VF 161-2. Also, VF 162-1 may be able to check the DD flag in Rx packet descriptor 123 to confirm the network packet has been received by VF 161-2.

FIG. 6 illustrates an example logic flow 600. In some examples, logic flow may be implemented by logic and/or features at a PCIe root complex such as data movement agent 113 at PCIe root complex 111 of system 100 shown in FIG. 1. Data movement agent 113 may be capable of interpreting received PCIe TLPs from logic and/or features at a PCIe Ethernet NIC such as PCIe endpoint logic 156 and/or VF 161-1 to 161-N at PCIe Ethernet NIC 150. The received PCIe TLPs may be in the format of example formats 210 or 220 as shown in FIG. 2 for data movement agent 113 to initiate a memory-to-memory move request similar to what was described above for process 400 shown in FIG. 4 and for logic flow 500 shown in FIG. 5 for moving data for a packet payload from memory region 124 allocated to VM 160-1 to memory region 122 allocated to VM 160-2. Data movement agent 113 may also be capable of generating a TLP completion message in the format of example format 300 shown in FIG. 3 and sending the TLP completion message to VF 161-1 and/or PCIe endpoint logic 156. However, logic flow 600 is not limited to being implemented by a logic and/or features at a PCIe root complex such as data movement agent 113 at PCIe root complex 111 shown in FIG. 1 or to use of

packet formats

210, 220 or 300 shown in FIGS. 2-3.

Beginning at decision block 602, data movement agent 113 may determine whether a memory-to-memory move request has been received. In some examples, the memory-to-memory move request may be received from VF 161-1 at PCIe Ethernet NIC 150 in a PCIe TLP having a format according to

example format

210 or 220. If a memory-to-memory move request is received, logic flow 600 moves to block 604. Otherwise, logic flow 600 remains at decision block 602.

At decision block 604, data movement agent 113 may determine whether DMA engine 114 at integrated I/O 112 supports direct DMA to system memory 120. If supported, logic flow 600 moves to block 608. Otherwise, logic flow 600 moves to block 606.

At block 606, data movement agent 113 may send a PCIe TLP completion message back to VF 161-1 at PCIe Ethernet NIC 150 that indicates unsupported request completion status. In some examples, the TCP completion message may be in the format of example format 300 and the completion status indicated in completion status 304 may indicate that the memory-to-memory move request is unsupported.

At block 608, data movement agent 113 may get a source address (GPA) and VF 160-1’s source ID from the PCIe TLP for the memory-to-memory move request received from VF 160-1.

At block 610, data movement agent 113 may get a destination address (GPA) and a destination ID of receiving VM 160-2’s directly assigned VF 161-2 from the PCIe TLP for the memory-to-memory move request received from VF 161-1.

At block 612, data movement agent 113 may utilize DMA remapping table at an IOMMU such as IOMMU 115 to translate GPAs to HPAs. In some examples, data movement agent 113 may send the GPAs for both source and destination addresses indicated in the received PCIe TLP to IOMMU 115 via IIO bus 116 to utilize lookup DMA remapping table 109.

At block 614, data movement agent 113 may generate a memory-to-memory DMA request by including HPAs and transfer size and then send the request via IIO bus 116 to DMA engine 114. In some examples, HPAs include the translated source and destination addresses. The transfer size may indicate a size a data for a packet payload of the network packet generated by VM 160-1 and destined for VM 160-2.

At block 616, data movement agent 113 may receive a DMA done message from DMA engine 114 following DMA engine 114 performing a DMA transfer of the data for the packet payload from source VM memory at memory region 124 to target VM memory at memory region 122.

At block 618, data movement agent 113 may send a PCIe TLP completion message to VF 161-1 at PCIe Ethernet NIC 150 indicating a successful completion status. This PCIe TLP completion message may also be in the format of example format 300 and the completion status indicated in completion status 304 may include the indication of a successful completion of the memory-to-memory move.

FIG. 7 illustrates an example block diagram for apparatus 700. Although apparatus 700 shown in FIG. 7 has a limited number of elements in a certain topology, it may be appreciated that the apparatus 700 may include more or less elements in alternate topologies as desired for a given implementation.

According to some examples, apparatus 700 may be supported by circuitry 720 maintained at a network input/output device such as PCIe Ethernet NIC 150 shown in FIG. 1. The network input/output device may be coupled with a computing system and may have VFs directly assigned to VMs supported by the computing system. Circuitry 720 may be arranged to execute one or more software or firmware implemented modules, components or logic 722-a(module, component or logic may be used interchangeably in this context) . It is worthy to note that “a” and “b” and “c” and similar designators as used herein are intended to be variables representing any positive integer. Thus, for example, if an implementation sets a value for a ＝4, then a complete set of software or firmware for components 722-amay include logic 722-1, 722-2, 722-3 or 722-4. The examples presented are not limited in this context and the different variables used throughout may represent the same or different integer values. Also, “logic” may also include software/firmware stored in computer-readable media, and although logic is shown in FIG. 7 as discrete boxes, this does not limit this logic to storage in distinct computer-readable media components (e.g., a separate memory, etc. ) .

According to some examples, circuitry 720 may include a processor, processor circuit or processor circuitry. Circuitry 720 may be generally arranged to execute one or more software components 722-a. Circuitry 720 may be any of various commercially available processors, including without limitation an

and

processors；

application, embedded and secure processors；

and

processors； IBM and

Cell processors；

Core (2)

Core i3, Core i5, Core i7,

Xeon

and

processors； and similar processors. According to some examples circuitry 720 may also include an application specific integrated circuit (ASIC) and at least some components 722-amay be implemented as hardware elements of the ASIC. According to some examples, circuitry 720 may also include a field programmable gate array (FPGA) and at least some logic 722-amay be implemented as hardware elements of the FPGA.

According to some examples, apparatus 700 may include a packet indication logic 722-1. Packet indication logic 722-1 may be executed by circuitry 720 to receive an indication that a network packet that includes data for a packet header and data for a packet payload has been generated at a first VM supported by a computing system coupled with the network input/output device that includes apparatus 700. The network packet may have a destination at a second VM supported by the computing system. For these examples, network packet indication 705 may include an indication from a first VF driver executed by the first VM. The first VF driver may control a directly assigned first VF at the network input/output device.

In some examples, apparatus 700 may include a descriptor logic 722-2. Descriptor logic 722-2 may be executed by circuitry 720 to determine a size of the data for the packet payload and a first GPA in a first memory region of system memory for the computing system, the first memory region allocated to the first VM, the first GPA to indicate a location in the first memory region where the data for the packet payload is at least temporarily stored. For these examples, apparatus 700 may determine the first GPA and the size of the data for the packet payload based on a Tx packet descriptor 710. Tx packet descriptor 710 may be fetched from the first memory region.

According to some examples, descriptor logic may also determine a second GPA in a second memory region of the system memory, the second memory region allocated to the second VM, the second GPA to indicate a location in the second memory region where the data for the packet payload is to be moved in order to send the network packet to the destination at the second VM. For these examples, apparatus 700 may determine the second GPA based on a Rx packet descriptor 715. Rx packet descriptor 715 may be fetched from the second memory region.

In some examples, apparatus 700 may also include request logic 722-3. Request logic 722-3 may be executed by circuitry 720 to send a memory-to-memory move request message that includes the first and second GPAs and the size of the data for the packet payload to a processor of the computing system, the processor to translate the first and second GPAs to respective first and second HPAs and cause a direct memory access transaction to the system memory to move the data for the packet payload from the first memory region to the second memory region based on the first and second HPAs and the size of the data for the packet payload. For these examples, the memory-to-memory move request message may be included in memory-to-memory move request 730.

In some examples, apparatus 700 may also include a completion logic 722-4. Completion logic 722-4 may be executed by circuitry 720 to receive a completion message that indicates a completion of the memory-to-memory move request. For these examples, the completion message may be included in completion message 740.

According to some examples, descriptor logic 722-2 update the Tx descriptor maintained in the first memory region to set a descriptor done flag to indicate the network packet has been transmitted to the destination VM. Descriptor logic 722-2 may also update the Rx descriptor maintained in the second memory region to set a similar descriptor done flag to indicate the network packet has been received at the destination VM. Tx/Rx packet descriptor update 745 may include the setting of the descriptor done flag.

Various components of apparatus 700 and a device or node implementing apparatus 700 may be communicatively coupled to each other by various types of communications media to coordinate operations. The coordination may involve the uni-directional or bi-directional exchange of information. For instance, the components may communicate information in the form of signals communicated over the communications media. The information can be implemented as signals allocated to various signal lines. In such allocations, each message is a signal. Further embodiments, however, may alternatively employ data messages. Such data messages may be sent across various connections. Example connections include parallel interfaces, serial interfaces, and bus interfaces.

Included herein is a set of logic flows representative of example methodologies for performing novel aspects of the disclosed architecture. While, for purposes of simplicity of explanation, the one or more methodologies shown herein are shown and described as a series of acts, those skilled in the art will understand and appreciate that the methodologies are not limited by the order of acts. Some acts may, in accordance therewith, occur in a different order and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all acts illustrated in a methodology may be required for a novel implementation.

A logic flow may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, a logic flow may be implemented by computer executable instructions stored on at least one non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. The embodiments are not limited in this context.

FIG. 8 illustrates an example logic flow 800. Logic flow 800 may be representative of some or all of the operations executed by one or more logic, features, or devices described herein, such as apparatus 800. More particularly, logic flow 800 may be implemented by at least packet indication logic 722-1, descriptor logic 722-2, request logic 722-3 or completion logic 722-4.

According to some examples, logic flow 800 at block 802 may receive, at a network input/output device coupled with a computing system, an indication that a network packet having data for a packet header and data for a packet payload has been generated at a first VM supported by the computing system, the network packet having a destination at a second VM supported by the computing system. For these examples, packet indication logic 722-1 may receive the indication.

In some examples, logic flow 800 at block 804 may determine a size of the data for the packet payload and a first GPA in a first memory region of system memory for the computing system, the first memory region allocated to the first VM, the first GPA indicating a location in the first memory region where the data for the packet payload is at least temporarily stored. For these examples, descriptor logic 722-2 may determine the size of the data for the packet payload and the first GPA.

According to some examples, logic flow 800 at block 806 may determine a second GPA in a second memory region of the system memory, the second memory region allocated to the second VM, the second GPA indicating a location in the second memory region where the data for the packet payload is to be moved in order to send the network packet to the destination at the second VM. For these examples, descriptor logic 722-2 may determine the second GPA.

In some examples, logic flow 800 at block 808 may send a memory-to-memory move request message that includes the first and second GPAs and the size of the data for the packet payload to a processor of the computing system, the processor to translate the first and second GPAs to respective first and second HPAs and cause a direct memory access transaction to the system memory to move the data for the packet payload from the first memory region to the second memory region based on the first and second HPAs and the size of the data for the packet payload. For these examples, request logic 722-3 may send the memory-to-memory move request message.

According to some examples, logic flow 800 at block 810 may receive a completion message indicating completion of the memory-to-memory move request. For these examples, completion logic 722-4 may receive the completion message.

FIG. 9 illustrates an example storage medium 900. As shown in FIG. 9, the first storage medium includes a storage medium 900. The storage medium 900 may comprise an article of manufacture. In some examples, storage medium 900 may include any non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. Storage medium 900 may store various types of computer executable instructions, such as instructions to implement logic flow 800. Examples of a computer readable or machine readable storage medium may include any tangible media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. The examples are not limited in this context.

FIG. 10 illustrates an example block diagram for apparatus 1000. Although apparatus 1000 shown in FIG. 10 has a limited number of elements in a certain topology, it may be appreciated that the apparatus 1000 may include more or less elements in alternate topologies as desired for a given implementation.

According to some examples, apparatus 1000 may be supported by circuitry 1020 at a processor for a computing system supporting multiple VMs. Circuitry 1020 may be arranged to execute one or more software or firmware implemented modules, components or logic 1022-a(module, component or logic may be used interchangeably in this context) . It is worthy to note that “a” and “b” and “c” and similar designators as used herein are intended to be variables representing any positive integer. Thus, for example, if an implementation sets a value for a ＝ 4, then a complete set of software components 1022-amay include components 1022-1, 1022-2, 1022-3 or 1022-4. The examples are not limited in this context and the different variables used throughout may represent the same or different integer values. Also, “logic” may also include software/firmware stored in computer-readable media, and although logic is shown in FIG. 10 as discrete boxes, this does not limit this logic to storage in distinct computer-readable media components (e.g., a separate memory, etc. ) .

According to some examples, circuitry 1020 may include a processor, processor circuit or processor circuitry. Circuitry 1020 may be generally arranged to execute one or more software components 1022-a. Circuity 1020 can be any of various commercially available processors to include but not limited to the processors mentioned above for apparatus 1000. Also, according to some examples, circuitry 1020 may also be an ASIC and at least some components 1022-amay be implemented as hardware elements of the ASIC.

According to some examples, apparatus 1000 may include a receive logic 1022-1. Receive logic 1022-1 may be executed by circuitry 1020 to receive, at the processor, a memory-to-memory move request message from a network input/output device coupled with the processor, the memory-to-memory move request including information to indicate a source ID, a source GPA, a destination ID, a destination GPA and a length of data for a packet payload of a network packet generated at a first VM from among the multiple VMs, the network packet destined to a second VM from among the multiple VMs, the first VM associated with the source ID, the second VM associated with the destination ID. For these examples, the memory-to-memory move request may be included in mem-to-mem move request 1010.

In some examples, apparatus 1000 may include a translation logic 1022-2. Translation logic 1022-2 may be executed by circuitry 1020 to translate the source and destination GPAs using an IOMMU to determine a source HPA and a destination HPA. For these examples, transaction logic 1022-2 may have access to DMA remapping table 1024-a maintained at the IOMMU. DMA remapping table 1024-a may enable translation logic 1022-2 to complete the translation of the source and destination GPAs to source and destination HPAs.

According to some examples, apparatus 1000 may also include DMA logic 1022-3. DMA logic 1022-3 may be executed by circuitry 1020 to cause a DMA transaction to a system memory coupled with the computing system using the source HPA, the destination HPA and the length of data for the packet payload to result in movement of data for the packet payload from a first memory region of the system memory allocated to the first VM to a second memory region of the system memory allocated to the second VM. For these examples, DMA logic 1022-3 may use a DMA engine at the processor to read the data for the packet payload from the first memory region based on the source HPA and write the data for the packet payload to the second memory region based on the destination HPA.

In some examples, apparatus 1000 may also include a completion logic 1022-4. Completion logic 1022-4 may be executed by circuitry 1020 to send a completion message to the network input/output device indicating a status for completion of the memory-to-memory move request. For these examples, the completion message may be included in completion message 1040.

Various components of apparatus 1000 and a device implementing apparatus 1000 may be communicatively coupled to each other by various types of communications media to coordinate operations. The coordination may involve the uni-directional or bi-directional exchange of information. For instance, the components may communicate information in the form of signals communicated over the communications media. The information can be implemented as signals allocated to various signal lines. In such allocations, each message is a signal. Further embodiments, however, may alternatively employ data messages. Such data messages may be sent across various connections. Example connections include parallel interfaces, serial interfaces, and bus interfaces.

FIG. 11 illustrates an example logic flow 1100. Logic flow 1100 may be representative of some or all of the operations executed by one or more logic, features, or devices described herein, such as apparatus 1100. More particularly, logic flow 1100 may be implemented by at least receive logic 1022-1, translation logic 1022-2, DMA logic 1022-3 or completion logic 1022-4.

According to some examples, logic flow 1100 at block 1102 may receive, at a processor for a computing system supporting multiple VMs, a memory-to-memory move request message from a network input/output device coupled with the processor, the memory-to-memory move request including information to indicate a source ID, a source GPA, a destination ID, a destination GPA and a length of data for a packet payload of a network packet generated at a first VM from among the multiple VMs, the network packet destined to a second VM from among the multiple VMs, the first VM associated with the source ID, the second VM associated with the destination ID. For these examples, receive logic 1022-1 may receive the memory-to-memory move request message.

In some examples, logic flow 1100 at block 1104 may translate the source and destination GPAs using an IOMMU to determine a source HPA and a destination HPA. For these examples, translation logic 1022-2 may translate the source and destination GPAs using the IOMMU.

According to some examples, logic flow 1100 at block 1106 may cause a DMA transaction to a system memory coupled with the computing system using the source HPA, the destination HPA and the length of data for the packet payload to result in movement of data for the packet payload from a first memory region of the system memory allocated to the first VM to a second memory region of the system memory allocated to the second VM. For these examples, DMA logic 1022-3 may cause the DMA transaction.

In some examples, logic flow 1100 at block 1108 may send a completion message to the network input/output device indicating a status for completion of the memory-to-memory move request. For these examples, completion logic 1022-4 may send the completion request message.

FIG. 12 illustrates an example storage medium 1200. As shown in FIG. 12, the first storage medium includes a storage medium 1200. The storage medium 1200 may comprise an article of manufacture. In some examples, storage medium 1200 may include any non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. Storage medium 1200 may store various types of computer executable instructions, such as instructions to implement logic flow 1100. Examples of a computer readable or machine readable storage medium may include any tangible media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. The examples are not limited in this context.

FIG. 13 illustrates an example computing platform 1300. In some examples, as shown in FIG. 13, computing platform 1300 may include a processing component 1340, other platform components 1350 or a communications interface 1360.

According to some examples, processing component 1340 may execute processing operations or logic for apparatus 700 and/or storage medium 900. Processing component 1340 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth) , integrated circuits, application specific integrated circuits (ASIC) , programmable logic devices (PLD) , digital signal processors (DSP) , field programmable gate array (FPGA) , memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API) , instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given example.

In some examples, other platform components 1350 may include common computing elements, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components (e.g., digital displays) , power supplies, and so forth. Examples of memory units or memory devices may include without limitation various types of computer readable and machine readable storage media in the form of one or more higher speed memory units, such as read-only memory (ROM) , random-access memory (RAM) , dynamic RAM (DRAM) , Double-Data-Rate DRAM (DDRAM) , synchronous DRAM (SDRAM) , static RAM (SRAM) , programmable ROM (PROM) , erasable programmable ROM (EPROM) , electrically erasable programmable ROM (EEPROM) , flash memory, polymer memory such as ferroelectric polymer memory, ovonic memory, phase change or ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, an array of devices such as Redundant Array of Independent Disks (RAID) drives, solid state memory devices (e.g., USB memory) , solid state drives (SSD) and any other type of storage media suitable for storing information.

In some examples, communications interface 1360 may include logic and/or features to support a communication interface. For these examples, communications interface 1360 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate over direct or network communication links. Direct communications may occur via use of communication protocols or standards described in one or more industry standards (including progenies and variants) such as those associated with the PCIe specification. Network communications may occur via use of communication protocols or standards such those described in one or more Ethernet standards promulgated by IEEE such as IEEE 802.3. Network communication may also occur according to one or more OpenFlow specifications such as the OpenFlow Hardware Abstraction API Specification. Network communications may also occur according to Infiniband Architecture specification.

As mentioned above computing platform 1300 may be implemented in a server or client computing device. Accordingly, functions and/or specific configurations of computing platform 1300 described herein, may be included or omitted in various embodiments of computing platform 1300, as suitably desired for a server or client computing device.

The components and features of computing platform 1300 may be implemented using any combination of discrete circuitry, application specific integrated circuits (ASICs) , logic gates and/or single chip architectures. Further, the features of computing platform 1300 may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware and/or software elements may be collectively or individually referred to herein as “logic” or “circuit. ”

It should be appreciated that the exemplary computing platform 1300 shown in the block diagram of FIG. 13 may represent one functionally descriptive example of many potential implementations. Accordingly, division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in embodiments.

FIG. 14 illustrates an example network input/output (NW I/O) device 1400. In some examples, as shown in FIG. 14, NW I/O device 1400 may include a processing component 1440, other platform components or a communications interface 1460. According to some examples, network I/O device 1400 may be implemented in a NW I/O device coupled to a computing system similar to PCIe Ethernet NIC 150 shown in FIG. 1 and described above.

According to some examples, processing component 1440 may execute processing operations or logic for apparatus 1000 and/or storage medium 1200. Processing component 1440 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth) , integrated circuits, application specific integrated circuits (ASIC) , programmable logic devices (PLD) , digital signal processors (DSP) , field programmable gate array (FPGA) , memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API) , instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given example.

In some examples, other platform components 1450 may include common computing elements, such as one or more processors, multi-core processors, co-processors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, and so forth. Examples of memory units may include without limitation various types of computer readable and machine readable storage media in the form of one or more higher speed memory units, such as ROM, RAM, DRAM, DDRAM, SDRAM, SRAM, PROM, EPROM, EEPROM, flash memory or any other type of storage media suitable for storing information.

In some examples, communications interface 1460 may include logic and/or features to support a communication interface. For these examples, communications interface 1460 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate over direct or network communication links. Direct communications may occur via use of communication protocols or standards described in one or more industry standards (including progenies and variants) such as those associated with the PCIe specification or the IEEE 802.3 specification.

The components and features of NW I/O device 1400 may be implemented using any combination of discrete circuitry, application specific integrated circuits (ASICs) , logic gates and/or single chip architectures. Further, the features of NW I/O device 1400 may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware and/or software elements may be collectively or individually referred to herein as “logic” or “circuit. ”

It should be appreciated that the exemplary NW I/O device 1400 shown in the block diagram of FIG. 14 may represent one functionally descriptive example of many potential implementations. Accordingly, division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in embodiments.

One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium which represents various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth) , integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.

Some examples may include an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations in accordance with the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

Some examples may be described using the expression “in one example” or “an example” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase “in one example” in various places in the specification are not necessarily all referring to the same example.

Some examples may be described using the expression "coupled" and "connected" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term "coupled” or “coupled with” , however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The follow examples pertain to additional examples of technologies disclosed herein.

Example 1. An example apparatus may include circuitry at a network input/output device coupled with a computing system. The apparatus may also include packet indication logic for execution by the circuitry to receive an indication that a network packet that includes data for a packet header and data for a packet payload has been generated at a first VM supported by the computing system. The network packet may have a destination at a second VM supported by the computing system. The apparatus may also include descriptor logic for execution by the circuitry to determine a size of the data for the packet payload and a first GPA in a first memory region of system memory for the computing system. The first memory region may be allocated to the first VM. The first GPA may indicate a location in the first memory region where the data for the packet payload is at least temporarily stored. The apparatus may also include the descriptor logic to determine a second GPA in a second memory region of the system memory. The second memory region may be allocated to the second VM. The second GPA may indicate a location in the second memory region where the data for the packet payload is to be moved in order to send the network packet to the destination at the second VM. The apparatus may also include request logic for execution by the circuitry to send a memory-to-memory move request message that includes the first and second GPAs and the size of the data for the packet payload to a processor of the computing system. The processor may translate the first and second GPAs to respective first and second HPAs and cause a direct memory access transaction to the system memory to move the data for the packet payload from the first memory region to the second memory region based on the first and second HPAs and the size of the data for the packet payload. The apparatus may also include completion logic for execution by the circuitry to receive a completion message that indicates a completion of the memory-to-memory move request.

Example 2. The apparatus of example 1, the processor may translate the first and second GPAs to respective first and second HPAs via use of an IOMMU at the processor.

Example 3. The apparatus of example 2, the descriptor logic to receive the indication that the network packet has been generated at the first VM may include the descriptor logic to receive the indication from a first VF driver executed by the first VM. The first VF driver may control a directly assigned first VF at the network input/output device.

Example 4. The apparatus of example 1 may also include a plurality of packet buffers. The plurality of packet buffers may include a first packet buffer arranged to at least temporarily store data for packet headers for network packets generated by the first VM. The plurality of packet buffers may also include a second packet buffer arranged to at least temporarily store data for packet headers for network packets having the second VM as a destination.

Example 5. The apparatus of example 4, the plurality of packet buffers may include one or more volatile memory devices or one or more non-volatile memory devices.

Example 6. The apparatus of example 1, the network I/O device may be NIC with a built in layer-2/layer-3 switch. The NIC may operate according to PCIe and IEEE 802.3 802.3 specifications. The NIC may be coupled with the processor via a PCIe link.

Example 7. The apparatus of example 6, the request logic to send the memory-to-memory request message to the processor may include the request logic to send a PCIe TLP to a PCIe root complex at the processor via the PCIe link. Also, in addition to including the first and second GPAs and the size of the data for the packet payload, the PCIe TLP may include an indication to translate the first and second GPAs to respective first and second HPAs.

Example 8. The apparatus of example 7, the completion logic to receive the completion message may include the completion logic to receive the completion message from the PCIe root complex in a PCIe TLP.

Example 9. The apparatus of example 7 may also include the descriptor logic to determine the size of the data for the packet payload and the first GPA via a first PCIe TLP memory read message to the PCIe root complex to read a Tx descriptor from the first memory region that indicates the size of the data for the packet payload and the first GPA. The apparatus may also include the descriptor logic to determine the second GPA via a second PCIe TLP memory read message to the PCIe root complex to read a Rx descriptor from the second memory region that indicates the second GPA.

Example 10. An example method may include receiving, at a network input/output device coupled with a computing system, an indication that a network packet having data for a packet header and data for a packet payload has been generated at a first VM supported by the computing system. The network packet may have a destination at a second VM supported by the computing system. The method may also include determining a size of the data for the packet payload and a first GPA in a first memory region of system memory for the computing system. The first memory region may be allocated to the first VM. The first GPA may indicate a location in the first memory region where the data for the packet payload is at least temporarily stored. The method may also include determining a second GPA in a second memory region of the system memory. The second memory region may be allocated to the second VM. The second GPA may indicate a location in the second memory region where the data for the packet payload is to be moved in order to send the network packet to the destination at the second VM. The method may also include sending a memory-to-memory move request message that includes the first and second GPAs and the size of the data for the packet payload to a processor of the computing system. The processor may translate the first and second GPAs to respective first and second HPAs and cause a direct memory access transaction to the system memory to move the data for the packet payload from the first memory region to the second memory region based on the first and second HPAs and the size of the data for the packet payload. The method may also include receiving a completion message indicating completion of the memory-to-memory move request.

Example 11. The method of example 10, the processor may translate the first and second GPAs to respective first and second HPAs using an IOMMU at the processor.

Example 12. The method of example 10, receiving the indication that the network packet has been generated at the first VM may include receiving the indication from a first VF driver executed by the first VM, the first VF driver to control a directly assigned first VF at the network input/output device.

Example 13. The method of example 10, the network I/O device may be a NIC with a built in layer-2/layer-3 switch. The NIC may operate according to PCIe and IEEE 802.3 802.3 specifications, the NIC coupled with the processor via a PCIe link.

Example 14. The method of example 13, sending the memory-to-memory request message to the processor may include the NIC sending a PCIe TLP to a PCIe root complex at the processor via the PCIe link. In addition to including the first and second GPAs and the size of the data for the packet payload, the PCIe TLP may include an indication to translate the first and second GPAs to respective first and second HPAs.

Example 15. The method of example 14, receiving the completion message may include receiving the completion message from the PCIe root complex in a PCIe TLP.

Example 16. The method of example 14 may also include determining the size of the data for the packet payload and the first GPA via a first PCIe TLP memory read message to the PCIe root complex to read a Tx descriptor from the first memory region that indicates the size of the data for the packet payload and the first GPA. The method may also include determining the second GPA via a second PCIe TLP memory read message to the PCIe root complex to read a Rx descriptor from the second memory region that indicates the second GPA.

Example 17. An example at least one machine readable medium may include a plurality of instructions that in response to being executed by a system may cause the system to carry out a method according to any one of examples 10 to 16.

Example 18. An example apparatus may include means for performing the methods of any one of examples 10 to 16.

Example 19. An example at least one machine readable medium may include a plurality of instructions that in response to being executed by a system at a network input/output device coupled with a computing system may cause the system to receive an indication that a network packet having data for a packet header and data for a packet payload has been generated at a first VM supported by the computing system. The network packet may have a destination at a second VM supported by the computing system. The instructions may also cause the system to determine a size of the data for the packet payload and a first GPA in a first memory region of system memory for the computing system, the first memory region allocated to the first VM. The first GPA may indicate a location in the first memory region where the data for the packet payload is at least temporarily stored. The instructions may also cause the system to determine a second GPA in a second memory region of the system memory. The second memory region may be allocated to the second VM. The second GPA may indicate a location in the second memory region where the data for the packet payload is to be moved in order to send the network packet to the destination at the second VM. The instructions may also cause the system to send a memory-to-memory move request message that includes the first and second GPAs and the size of the data for the packet payload to a processor of the computing system. The processor may translate the first and second GPAs to respective first and second HPAs and cause a direct memory access transaction to the system memory to move the data for the packet payload from the first memory region to the second memory region based on the first and second HPAs and the size of the data for the packet payload. The instructions may also cause the system to receive a completion message that indicates completion of the memory-to-memory move request.

Example 20. The at least one machine readable medium of example 19, the processor may translate the first and second GPAs to respective first and second HPAs using an IOMMU at the processor.

Example 21. The at least one machine readable medium of example 19, the instructions to cause the system to receive the indication that the network packet has been generated at the first VM may include the system to receive the indication from a first VF driver executed by the first VM, the first VF driver to control a directly assigned first VF at the network input/output device.

Example 22. The at least one machine readable medium of example 19, the network I/O device may be a NIC with a built in layer-2/layer-3 switch. The NIC may operate according to PCIe and IEEE 802.3 802.3 specifications, the NIC coupled with the processor via a PCIe link.

Example 23. The at least one machine readable medium of example 19, the instructions to cause the system to send the memory-to-memory request message to the processor may include the system to cause the NIC to send a PCIe TLP to a PCIe root complex at the processor via the PCIe link. In addition to including the first and second GPAs and the size of the data for the packet payload, the PCIe TLP may include an indication to translate the first and second GPAs to respective first and second HPAs.

Example 24. The at least one machine readable medium of example 23, the instructions to cause the system to receive the completion message may include the system to receive the completion message from the PCIe root complex in a PCIe TLP.

Example 25. The at least one machine readable medium of example 23, further including the instructions to cause the system to determine the size of the data for the packet payload and the first GPA via a first PCIe TLP memory read message to the PCIe root complex to read a Tx descriptor from the first memory region that indicates the size of the data for the packet payload and the first GPA. The instructions may also cause the system to determine the second GPA via a second PCIe TLP memory read message to the PCIe root complex to read a Rx descriptor from the second memory region that indicates the second GPA.

Example 26. An example apparatus may include circuitry at a processor for a computing system supporting multiple VMs. The apparatus may also include receive logic for execution by the circuitry to receive a memory-to-memory move request message from a network input/output device coupled with the processor. The memory-to-memory move request may include information to indicate a source ID, a source GPA, a destination ID, a destination GPA and a length of data for a packet payload of a network packet generated at a first VM from among the multiple VMs. The network packet may be destined to a second VM from among the multiple VMs. The first VM may be associated with the source ID, the second VM associated with the destination ID. The apparatus may also include translation logic for execution by the circuitry to translate the source and destination GPAs using an IOMMU to determine a source HPA and a destination HPA. The apparatus may also include DMA logic for execution by the circuitry to cause a DMA transaction to a system memory coupled with the computing system via use of the source HPA. The destination HPA and the length of data for the packet payload may result in movement of data for the packet payload from a first memory region of the system memory allocated to the first VM to a second memory region of the system memory allocated to the second VM. The apparatus may also include completion logic for execution by the circuitry to send a completion message to the network input/output device that indicates a status for completion of the memory-to-memory move request.

Example 27. The apparatus of example 26, the network packet generated at the first VM may include the network packet generated by a first VF driver executed by the first VM. The first VF driver may control a directly assigned first VF at the network input/output device.

Example 28. The apparatus of example 26, the translation logic to translate the source and destination GPAs via use of the IOMMU may include the IOMMU utilizing a DMA remapping table to determine the source and destination HPAs based on the source and destination GPAs.

Example 29. The apparatus of example 26, the DMA logic to cause the DMA transaction may include the DMA logic to use a DMA engine at the processor to read the data for the packet payload from the first memory region based on the source HPA and write the data for the packet payload to the second memory region based on the destination HPA.

Example 30. The apparatus of example 29, the completion logic to send the completion message to the network input/output device to indicate the status for completion of the memory-to-memory move request may include the completion logic to receive an indication from the DMA engine that indicates the DMA transaction has been completed and indicates the status as successfully completed.

Example 31. The apparatus of example 26, the network I/O device may be a NIC with a built in layer-2/layer-3 switch. The NIC may operate according to PCIe and IEEE 802.3 802.3 specifications, the NIC coupled with the processor via a PCIe link.

Example 32. The apparatus of example 31, the request logic may include a PCIe root complex. The request logic to receive the memory-to-memory request message includes the NIC to send a PCIe TLP to the PCIe root complex via the PCIe link. In addition to including the first and second GPAs and the length of the data for the packet payload, the PCIe TLP may include an indication to translate the source and destination GPAs to respective source and destination HPAs.

Example 33. The apparatus of example 31, the completion logic t0 send the completion message may include the completion logic to send the completion message from the PCIe root complex in a PCIe TLP.

Example 34. The apparatus of example 26 may also include a digital display coupled to the circuitry to present a user interface view.

Example 35. An example method may include receiving, at a processor for a computing system supporting multiple VMs, a memory-to-memory move request message from a network input/output device coupled with the processor. The memory-to-memory move request may include information to indicate a source ID, a source GPA, a destination ID, a destination GPA and a length of data for a packet payload of a network packet generated at a first VM from among the multiple VMs. The network packet may be destined to a second VM from among the multiple VMs. The first VM may be associated with the source ID, the second VM associated with the destination ID. The method may also include translating the source and destination GPAs using an IOMMU to determine a source HPA and a destination HPA. The method may also include causing a DMA transaction to a system memory coupled with the computing system using the source HPA. The destination HPA and the length of data for the packet payload may result in movement of data for the packet payload from a first memory region of the system memory allocated to the first VM to a second memory region of the system memory allocated to the second VM. The method may also include sending a completion message to the network input/output device indicating a status for completion of the memory-to-memory move request.

Example 36. The method of example 35, the network packet generated at the first VM may include the network packet generated by a first VF driver executed by the first VM. The first VF driver may control a directly assigned first VF at the network input/output device.

Example 37. The method of example 35, translating the source and destination GPAs using the IOMMU may include the IOMMU utilizing a DMA remapping table to determine the source and destination HPAs based on the source and destination GPAs.

Example 38. The method of example 35, causing the DMA transaction may include using a DMA engine at the processor to read the data for the packet payload from the first memory region based on the source HPA and write the data for the packet payload to the second memory region based on the destination HPA.

Example 39. The method of example 38, sending the completion message to the network input/output device indicating the status for completion of the memory-to-memory move request may include receiving an indication from the DMA engine to indicate the DMA transaction has been completed and indicating the status as successfully completed.

Example 40. The method of example 35, the network I/O device may be a NIC with a built in layer-2/layer-3 switch. The NIC may operate according to PCIe and IEEE 802.3 802.3 specifications, the NIC coupled with the processor via a PCIe link.

Example 41. The method of example 40, receiving the memory-to-memory request message may include the NIC sending a PCIe TLP to a PCIe root complex at the processor via the PCIe link. In addition to including the first and second GPAs and the length of the data for the packet payload, the PCIe TLP may include an indication to translate the source and destination GPAs to respective source and destination HPAs.

Example 42. The method of example 40, sending the completion message may include sending the completion message from the PCIe root complex in a PCIe TLP.

Example 43. An example at least one machine readable medium may include a plurality of instructions that in response to being executed by a system may cause the system to carry out a method according to any one of examples 35 to 42.

Example 44. An example apparatus may include means for performing the methods of any one of examples 35 to 42.

Example 45. An example at least one machine readable medium may include a plurality of instructions that in response to being executed by a system at a processor for a computing system supporting multiple VMs may cause the system to receive a memory-to-memory move request message from a network input/output device coupled with the processor. The memory-to-memory move request may include information to indicate a source ID, a source GPA, a destination ID, a destination GPA and a length of data for a packet payload of a network packet generated at a first VM from among the multiple VMs. The network packet may be destined to a second VM from among the multiple VMs. The first VM may be associated with the source ID, the second VM may be associated with the destination ID. The instructions may also cause the system to translate the source and destination GPAs using an IOMMU to determine a source HPA and a destination HPA. The instructions may also cause the system to cause a DMA transaction to a system memory coupled with the computing system using the source HPA. The destination HPA and the length of data for the packet payload to result in movement of data for the packet payload from a first memory region of the system memory allocated to the first VM to a second memory region of the system memory allocated to the second VM. The instructions may also cause the system to send a completion message to the network input/output device indicating a status for completion of the memory-to-memory move request.

Example 46. The at least one machine readable medium of example 45, the network packet generated at the first VM may include the network packet generated by a first VF driver executed by the first VM. The first VF driver may control a directly assigned first VF at the network input/output device.

Example 47. The at least one machine readable medium of example 45, the system to translate the source and destination GPAs using the IOMMU includes the IOMMU utilizing a DMA remapping table to determine the source and destination HPAs based on the source and destination GPAs.

Example 48. The at least one machine readable medium of example 45, the system to cause the DMA transaction may include the system to use a DMA engine at the processor to read the data for the packet payload from the first memory region based on the source HPA and write the data for the packet payload to the second memory region based on the destination HPA.

Example 49. The at least one machine readable medium of example 48, the system to send the completion message to the network input/output device indicating the status for completion of the memory-to-memory move request may include the system to receive an indication from the DMA engine to indicate the DMA transaction has been completed and indicating the status as successfully completed.

Example 50. The at least one machine readable medium of example 45, the network I/O device may be a NIC with a built in layer-2/layer-3 switch. The NIC may operate according to PCIe and IEEE 802.3 802.3 specifications, the NIC coupled with the processor via a PCIe link.

Example 51. The at least one machine readable medium of example 50, the system to receive the memory-to-memory request message may include the NIC to send a PCIe TLP to a PCIe root complex at the processor via the PCIe link. In addition to including the first and second GPAs and the length of the data for the packet payload, the PCIe TLP may include an indication to translate the source and destination GPAs to respective source and destination HPAs.

Example 52. The at least one machine readable medium of example 50, the system to send the completion message may include the system to send the completion message from the PCIe root complex in a PCIe TLP.

It is emphasized that the Abstract of the Disclosure is provided to comply with 37 C.F.R. Section 1.72 (b) , requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein, " respectively. Moreover, the terms "first, " "second, " "third, " and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

An apparatus comprising:

circuitry at a network input/output device coupled with a computing system；

packet indication logic for execution by the circuitry to receive an indication that a network packet that includes data for a packet header and data for a packet payload has been generated at a first virtual machine (VM) supported by the computing system, the network packet having a destination at a second VM supported by the computing system；

descriptor logic for execution by the circuitry to determine a size of the data for the packet payload and a first guest physical address (GPA) in a first memory region of system memory for the computing system, the first memory region allocated to the first VM, the first GPA to indicate a location in the first memory region where the data for the packet payload is at least temporarily stored；

the descriptor logic to determine a second GPA in a second memory region of the system memory, the second memory region allocated to the second VM, the second GPA to indicate a location in the second memory region where the data for the packet payload is to be moved in order to send the network packet to the destination at the second VM；

request logic for execution by the circuitry to send a memory-to-memory move request message that includes the first and second GPAs and the size of the data for the packet payload to a processor of the computing system, the processor to translate the first and second GPAs to respective first and second host physical addresses (HPAs) and cause a direct memory access transaction to the system memory to move the data for the packet payload from the first memory region to the second memory region based on the first and second HPAs and the size of the data for the packet payload； and

completion logic for execution by the circuitry to receive a completion message that indicates a completion of the memory-to-memory move request.
The apparatus of claim 1, comprising the processor to translate the first and second GPAs to respective first and second HPAs via use of an input/output memory management unit (IOMMU) at the processor.
The apparatus of claim 2, the descriptor logic to receive the indication that the network packet has been generated at the first VM comprises the descriptor logic to receive the indication from a first virtual function (VF) driver executed by the first VM, the first VF driver to control a directly assigned first VF at the network input/output device, the first VM to generate the network packet for transmission to the second.
The apparatus of claim 1, comprising a plurality of packet buffers, the plurality of packet buffers including:

a first packet buffer arranged to at least temporarily store data for packet headers for network packets generated by the first VF； and

a second packet buffer arranged to at least temporarily store data for packet headers for network packets having the second VF as a destination.
The apparatus of claim 4, comprising the plurality of packet buffers including one or more volatile memory devices or one or more non-volatile memory devices.
The apparatus of claim 1, the network I/O device comprising a network interface card (NIC) with a built in layer-2/layer-3 switch, the NIC to operate according to Peripheral Component Interconnect Express (PCIe) and Institute of Electrical and Electronics Engineers (IEEE) 802.3 specifications, the NIC coupled with the processor via a PCIe link.
The apparatus of claim 6, the request logic to send the memory-to-memory request message to the processor comprises the request logic to send a PCIe transaction layer packet (TLP) to a PCIe root complex at the processor via the PCIe link, in addition to including the first and second GPAs and the size of the data for the packet payload, the PCIe TLP includes an indication to translate the first and second GPAs to respective first and second HPAs.
The apparatus of claim 7, the completion logic to receive the completion message comprises the completion logic to receive the completion message from the PCIe root complex in a PCIe TLP.
The apparatus of claim 7, comprising:

the descriptor logic to determine the size of the data for the packet payload and the first GPA via a first PCIe TLP memory read message to the PCIe root complex to read a transmit (Tx) descriptor from the first memory region that indicates the size of the data for the packet payload and the first GPA； and

the descriptor logic to determine the second GPA via a second PCIe TLP memory read message to the PCIe root complex to read a receive (Rx) descriptor from the second memory region that indicates the second GPA.
At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system at a network input/output device coupled with a computing system cause the system to:

receive an indication that a network packet having data for a packet header and data for a packet payload has been generated at a first virtual machine (VM) supported by the computing system, the network packet having a destination at a second VM supported by the computing system；

determine a size of the data for the packet payload and a first guest physical address (GPA) in a first memory region of system memory for the computing system, the first memory region allocated to the first VM, the first GPA indicating a location in the first memory region where the data for the packet payload is at least temporarily stored；

determine a second GPA in a second memory region of the system memory, the second memory region allocated to the second VM, the second GPA to indicate a location in the second memory region where the data for the packet payload is to be moved in order to send the network packet to the destination at the second VM；

send a memory-to-memory move request message that includes the first and second GPAs and the size of the data for the packet payload to a processor of the computing system, the processor to translate the first and second GPAs to respective first and second host physical addresses (HPAs) and cause a direct memory access transaction to the system memory to move the data for the packet payload from the first memory region to the second memory region based on the first and second HPAs and the size of the data for the packet payload； and

receive a completion message that indicates completion of the memory-to-memory move request.
The at least one machine readable medium of claim 10, comprising the processor to translate the first and second GPAs to respective first and second HPAs using an input/output memory management unit (IOMMU) at the processor.
The at least one machine readable medium of claim 10, the instructions to cause the system to receive the indication that the network packet has been generated at the first VM comprises the system to receive the indication from a first virtual function (VF) drive executed by the first VM, the first VF driver to control a directly assigned first FV at the network input/output device, the first VM generating the network packet for transmission to the second VM.
The at least one machine readable medium of claim 10, the network I/O device comprising a network interface card (NIC) with a built in layer-2/layer-3 switch, the NIC to operate according to Peripheral Component Interconnect Express (PCIe) and Institute of Electrical and Electronics Engineers (IEEE) 802.3 specifications, the NIC coupled with the processor via a PCIe link.
The at least one machine readable medium of claim 10, the instructions to cause the system to send the memory-to-memory request message to the processor comprises the system to cause the NIC to send a PCIe transaction layer packet (TLP) to a PCIe root complex at the processor via the PCIe link, in addition to including the first and second GPAs and the size of the data for the packet payload, the PCIe TLP including an indication to translate the first and second GPAs to respective first and second HPAs.
The at least one machine readable medium of claim 14, the instructions to cause the system to receive the completion message comprises the system to receive the completion message from the PCIe root complex in a PCIe TLP.
The at least one machine readable medium of claim 14, further comprising the instructions to cause the system to:

determine the size of the data for the packet payload and the first GPA via a first PCIe TLP memory read message to the PCIe root complex to read a transmit (Tx) descriptor from the first memory region that indicates the size of the data for the packet payload and the first GPA； and

determine the second GPA via a second PCIe TLP memory read message to the PCIe root complex to read a receive (Rx) descriptor from the second memory region that indicates the second GPA.
An apparatus comprising:

circuitry at a processor for a computing system supporting multiple virtual machines (VMs) ；

receive logic for execution by the circuitry to receive a memory-to-memory move request message from a network input/output device coupled with the processor, the memory-to-memory move request to include information to indicate a source identifier (ID) , a source guest physical address (GPA) , a destination ID, a destination GPA and a length of data for a packet payload of a network packet generated at a first VM from among the multiple VMs, the network packet destined to a second VM from among the multiple VMs, the first VM associated with the source ID, the second VM associated with the destination ID；

translation logic for execution by the circuitry to translate the source and destination GPAs using an input/output memory management unit (IOMMU) to determine a source host physical address (HPA) and a destination HPA；

direct memory access (DMA) logic for execution by the circuitry to cause a DMA transaction to a system memory coupled with the computing system via use of the source HPA, the destination HPA and the length of data for the packet payload to result in movement of data for the packet payload from a first memory region of the system memory allocated to the first VM to a second memory region of the system memory allocated to the second VM； and

completion logic for execution by the circuitry to send a completion message to the network input/output device that indicates a status for completion of the memory-to-memory move request.
The apparatus of claim 17, the network packet generated at the first VM comprises the network packet generated by a first virtual function (VF) driver executed by the first VM, the first VF driver to control a directly assigned first VF at the network input/output device, the first VM to generate the network packet for transmission to the second VM.
The apparatus of claim 17, the translation logic to translate the source and destination GPAs via use of the IOMMU comprises the IOMMU utilizing a DMA remapping table to determine the source and destination HPAs based on the source and destination GPAs.
The apparatus of claim 17, the DMA logic to cause the DMA transaction comprises the DMA logic to use a DMA engine at the processor to read the data for the packet payload from the first memory region based on the source HPA and write the data for the packet payload to the second memory region based on the destination HPA.
The apparatus of claim 20, the completion logic to send the completion message to the network input/output device to indicate the status for completion of the memory-to-memory move request comprises the completion logic to receive an indication from the DMA engine that indicates the DMA transaction has been completed and indicates the status as successfully completed.
The apparatus of claim 17, the network I/O device comprising a network interface card (NIC) with a built in layer-2/layer-3 switch, the NIC to operate according to Peripheral Component Interconnect Express (PCIe) and Institute of Electrical and Electronics Engineers (IEEE) 802.3 specifications, the NIC coupled with the processor via a PCIe link.
The apparatus of claim 22, comprises the request logic to include a PCIe root complex, the request logic to receive the memory-to-memory request message includes the NIC to send a PCIe transaction layer packet (TLP) to the PCIe root complex via the PCIe link, in addition to including the first and second GPAs and the length of the data for the packet payload, the PCIe TLP to include an indication to translate the source and destination GPAs to respective source and destination HPAs.
The apparatus of claim 22, the completion logic to send the completion message comprises the completion logic to send the completion message from the PCIe root complex in a PCIe TLP.
The apparatus of claim 17, comprising a digital display coupled to the circuitry to present a user interface view.