WO2018006800A1

WO2018006800A1 - Clock balancing method, apparatus and system for qpsk system

Info

Publication number: WO2018006800A1
Application number: PCT/CN2017/091711
Authority: WO
Inventors: 袁磊; 蔡轶; 周伟勤
Original assignee: 中兴通讯股份有限公司
Priority date: 2016-07-06
Filing date: 2017-07-04
Publication date: 2018-01-11
Also published as: CN107592194B; CN107592194A

Abstract

Provided are a clock balancing method, apparatus and system for a QPSK system. The method comprises: acquiring a QPSK signal or a 9QAM signal of a QPSK system; and according to different spectrum efficiencies of the QPSK system, adjusting a clock recovery algorithm and/or a balancing algorithm of the QPSK system. By means of the present invention, the problem in the related art of the optimal receiving performance under different spectrum efficiencies is solved, thereby improving the receiving performance under different spectrum efficiencies.

Description

Clock equalization method, device and system for QPSK system

Technical field

The present invention relates to the field of optical communications, and in particular to a clock equalization method, apparatus and system for a QPSK system.

Background technique

In recent years, with the development of the Internet and e-commerce, the demand for multimedia services such as video and audio has increased. It is imperative to increase the bandwidth of the transmission network. Optical transmission is the backbone of the communication network, and its capacity and speed are improved. Demand is also becoming more and more urgent. Therefore, the development of optical communication technology is also very important. Improving spectral efficiency is one of the current efforts. It is to narrow-band filter the signal in the digital or analog domain at the transmitting end, and compress the signal spectrum to achieve even more. Efficient use of bandwidth. However, the compression of the spectrum causes a certain degree of damage to the signal. How to recover the signal better becomes the focus of attention. In particular, the matching scheme of the two core algorithms of the clock recovery and equalization algorithm directly affects the performance of the system.

There are a lot of researches on the QPSK system. The basic processing flow is: at the origin, the signal is first pre-equalized in the digital domain, then input to the DAC, converted into an analog signal, and the two are used as one driver to modulate to two polarizations. In the state, the two polarization states are respectively recorded as: V, H; the optical fiber is transmitted through the processing of the optical device such as the optical amplifier and the wavelength selective switch WSS, wherein the spectrum compression can be completed in the digital domain through the digital filter or through the WSS. At the receiving end, the signal is received by photoelectric conversion, ADC sampling, etc., and the digital signal processing is started. The basic processing flow is shown in Figure 1: First, the signal is compensated for delay, and the compensation is caused by the hardware routing. The delay of the 4-way signal is inconsistent, and then the angular imbalance and amplitude imbalance caused by the device are compensated, and the chromatic dispersion in the fiber link is compensated again, and then the inconsistency of the transmission and reception clock is performed. Clock recovery and equalization for the rest of the channel, followed by carrier synchronization and phase synchronization. Among them, clock recovery and equalization algorithms are two core algorithms for signal recovery, which have a great impact on performance. There are many researches on clock recovery algorithms, some in the time domain, some in the frequency domain, but essentially can be classified as The square phase and the fourth power phase, and because the clock component is directly extracted in the frequency domain, the performance is better than the time domain. The following are two phase discrimination formulas.

Assuming the frequency domain signals are Xpd, Ypd, then the phase discrimination formula is as follows:

Equation (1) is that the square phase is mainly used for broadband systems; formula (2) is that the fourth power phase is mainly used for narrowband systems, and the fourth power phase is relatively complex, but it uses low frequency components for phase discrimination, so It is very good to deal with the damage caused by spectrum compression, and it has great advantages in square-band phase detection in narrow-band systems.

In addition, there are two kinds of equalization schemes. One is to directly signal through equalization algorithms (such as CMA, LMS, etc.). The QPSK signal is restored, and the CMA algorithm is used here. The other is to use the equalization algorithm to sample the signal into a 9QAM-like signal, and then obtain the QPSK signal through the MLSE algorithm. The 9QAM constellation diagram (as shown in Figure 2) can be regarded as 2 circles. One point, here is the CMMA algorithm.

We know that the clock equalization scheme with feedback loop is pre-filtered before the clock, so the overall performance is better than the independent scheme of clock recovery and equalization. Therefore, the optimized design should combine the two as a whole. And complexity to design a clock equalization scheme.

The following four clock equalization schemes are given and their comprehensive performance is compared and analyzed:

Scheme 1 (see Figure 3) and scenario 2 (see Figure 4) are schemes for restoring signals to QPSK signals. In this scheme, the signal is first FFT-converted into the frequency domain, and then the equalization filter coefficients fed back by the equalization algorithm are used for pre-equalization, and the residual channel impairment is compensated to obtain a nearly ISI-free QPSK signal, and then square phase detection or 4 times is used. The algorithm of the square phase is used to estimate the clock error, and the accurate estimation result is obtained. The loop filter is used for interpolation to complete the clock recovery. At this time, the equalization filter is used for filtering to obtain the high-performance QPSK signal output. However, if the feedback equalization filter coefficient cannot fully pre-compensate the ISI of the signal before the phase discrimination, it will affect the accuracy of phase discrimination and the quality of the equalized signal. Therefore, it is better to use the 4th phase discrimination performance when the ISI is large, and vice versa. After the filtering is completed, the input data and the output are used to update the equalization coefficients to obtain a new equalization coefficient. This scheme works well when the QPSK signal spectrum is relatively wide.

Scheme 3 (see Figure 5) and Scheme 4 (see Figure 6) are schemes for shaping the signal into a 9-QAM signal. The 9QAM signal or 9QAM signal mentioned in the text refers to the clock recovery adjustment sampling point position to the QPSK signal. The constellation obtained by sampling is similar to the 9QAM signal. This scheme is mainly used when the signal spectrum is narrow and the signal ISI is strong. If we recover the signal here through the equalization algorithm, although the QPSK signal can be recovered, it is bound to be More high-frequency noise is introduced, which affects the subsequent frequency offset estimation and phase-offset estimation, and reduces the performance of the system. Considering the effect of strong filtering, the signal is closer to the signal of part of the response system, and the partial response system is affected. The strong filtering has less influence, and the signal does not have too much distortion. It is regarded as a partial response system processing. At the same time, the characteristics of the 9-QAM signal are combined with the corresponding equalization algorithm to restore it to a 9QAM-like signal. The filter coefficients obtained in this way are used to filter out the channel impairments such as residual dispersion when used for pre-filtering by the clock recovery algorithm, but there is a strong artificially added ISI, so it is suitable to select the 4th power phase discrimination, square It is difficult to work properly, so the combination in Option 3 is not the optimal choice.

In the broadband system, the performance of the first scheme and the second scheme is equivalent, but the scheme one clock recovery module and the equalization module are relatively simple, and the overall performance, complexity, and power consumption are considered, and the first scheme is the optimal design;

In the compatible narrowband and broadband systems, the performance of scheme 2 is better than that of scheme 1 in the case of narrowband. Although the clock recovery module is more complicated than scheme 1, it is acceptable, so scheme 2 is the optimal design.

In compatible narrowband and ultra-narrowband systems, scheme 4 has the best performance and great improvement. Although the complexity is higher than scheme 1 and scheme 2, its performance is irreplaceable. Therefore, scheme 4 is the most in this system. Good design.

However, the three schemes only have the best performance in a certain spectrum efficiency QPSK system, and have certain limitations in practical applications.

Summary of the invention

The embodiment of the invention provides a clock equalization method, device and system for a QPSK system, so as to at least solve the problem of optimal reception performance under different spectral efficiencies in the related art.

According to an aspect of the present invention, a clock equalization method for a QPSK system is provided, comprising: acquiring a QPSK signal or a 9QAM signal of a QPSK system; adjusting a clock recovery algorithm of the QPSK system according to a difference in spectral efficiency of the QPSK system and/or Equalization algorithm.

Preferably, the QPSK signal or the 9QAM signal of the QPSK system is obtained, including: obtaining a clock signal after the clock recovery by using the square phase discrimination algorithm from the clock recovery module of the QPSK system; and obtaining the equalization filtering by using the QPSK algorithm from the equalization module of the QPSK system. The mean square error signal; the clock signal and the MSE signal are respectively filtered to obtain a clock strength indication signal and an equalization convergence error indication signal.

Preferably, the clock recovery algorithm and/or the equalization algorithm of the QPSK system are adjusted according to different spectral efficiencies of the QPSK system, including: determining whether the first condition is met, wherein the first condition is: the clock strength indication signal is greater than the preset first The clock strength threshold and the equalization convergence error indication signal are less than a preset mean square error threshold; if the first condition is met, it is determined that the clock recovery and equalization filtering of the QPSK system is valid.

Preferably, the method further comprises: if the first condition is not satisfied, adjusting the square phase discrimination algorithm used for clock recovery of the QPSK system to a fourth power phase discrimination algorithm; acquiring a new clock strength indication signal and the equalization convergence error indication signal Determining whether the second condition is met, wherein the second condition is: the clock strength indication signal is greater than the preset second clock strength threshold, and the equalization convergence error indication signal is less than the preset mean square error threshold; if the second condition is met, Then it is determined that the clock recovery and equalization filtering of the QPSK system is effective.

Preferably, the method further comprises: if the second condition is not satisfied, adjusting the QPSK algorithm used for equalizing filtering by the QPSK system to the 9QAM algorithm; acquiring a new clock strength indication signal and the equalization convergence error indication signal; re-determining the second condition Whether it is established; if the second condition is established, it is determined that the clock recovery and equalization filtering of the QPSK system is effective.

Preferably, before acquiring the QPSK signal or the 9QAM signal of the QPSK system, the method further comprises: dividing the signal for completing the dispersion compensation into two paths, one entering the buffer for saving, and the other for performing the FFT to the frequency domain and then the H coefficient fed back by the equalization module. Multiply, and then perform clock error estimation; the estimated result is loop filtered and output to the interpolation module, the signal is taken out from the buffer for interpolation, and the interpolated signal is output to the equalization module.

Preferably, the method further comprises: constructing the M group first signal and the M group second signal according to the signal of the input equalization module, wherein each set of the second signal slides to the left with respect to a time window of each set of the first signal The first signal is used for the calculation of the equalization coefficient H1, and the equalization coefficient H1 is outputted by the even sample; the second signal is used for the update of the equalization coefficient H2, and the equalization coefficient H2 is output by the odd-like point, and M is a positive integer.

Preferably, the equalization coefficients H1 and H2 are respectively zero-padded by the following formula:

H1=[H(M+1:2M-1)0 0 0,...0,H(1:M-1)];

H2=[H(M:2M+1)0 0 0,...0,H(1:M-1)];

Wherein, the order of the equalization filter is 2*M+1.

Preferably, the equalization coefficients H1 and H2 are respectively calculated using the following formulas 1 and 2 for the error (errx, erry):

Formula 1:

Formula 2:

Wherein, (Xo, Yo) is the output signal of the equalization filtering, R _cma radius of convergence is QPSK, Ri is the radius of convergence of 9QAM, Wi is a weighting factor error.

According to another aspect of the present invention, there is provided a clock equalization apparatus configured as a QPSK system, comprising: an acquisition module configured to acquire a QPSK signal or a 9QAM of a QPSK system; and an adjustment module set to be different according to a spectral efficiency of the QPSK system Adjust the clock recovery algorithm and/or equalization algorithm of the QPSK system.

Preferably, the obtaining module comprises: a first acquiring unit, configured to obtain a clock signal after clock recovery using the square phase discrimination algorithm from the clock recovery module of the QPSK system, and obtain an equalization filter from the QPSK system after using the QPSK algorithm for equalization filtering. The mean square error signal; the filtering unit is configured to filter the clock signal and the MSE signal respectively to obtain a clock strength indication signal and an equalization convergence error indication signal.

Preferably, the adjustment module includes: a first determining unit, configured to determine whether the first condition is met, wherein the first condition is: the clock strength indication signal is greater than the preset first clock strength threshold, and the equalization convergence error indication signal is less than the pre- The mean square error threshold is set; the first determining unit is configured to determine that the clock recovery and equalization filtering of the QPSK system is valid when the second condition is established.

Preferably, the adjustment module further includes: a first adjusting unit, configured to adjust the square phase discrimination algorithm used for clock recovery of the QPSK system to a fourth power phase discrimination algorithm if the first condition is not satisfied; the second obtaining unit And being configured to obtain a new clock strength indication signal and a balanced convergence error indication signal; the second determining unit is configured to determine whether the second condition is established, wherein the second condition is: the clock strength indication signal is greater than the preset second clock strength The threshold, and the equalization convergence error indication signal is smaller than the preset mean square error threshold; and the second determining unit is configured to determine that the clock recovery and equalization filtering of the QPSK system is valid if the second condition is satisfied.

Preferably, the adjusting module further comprises: a second adjusting unit, configured to adjust the QPSK algorithm used for equalizing filtering of the QPSK system to the 9QAM algorithm if the second condition is not satisfied; and the third obtaining unit is configured to acquire a new one. a clock strength indication signal and an equalization convergence error indication signal; a third determining unit configured to re-determine whether the second condition is true; and a third determining unit configured to determine clock recovery and equalization of the QPSK system if the second condition is established Filtering is effective.

According to still another aspect of the present invention, there is provided a QPSK system comprising the above-described clock equalization apparatus, The clock equalization device is respectively connected to the clock recovery module and the equalization module in the QPSK system.

In the above embodiment of the present invention, the error signal provided by the clock signal and the equalization algorithm is used as the feedback signal, and the optimal phase discrimination mode and the equalization algorithm are adaptively selected, thereby achieving optimal reception performance under different spectral efficiencies.

DRAWINGS

The drawings described herein are intended to provide a further understanding of the invention, and are intended to be a part of the invention. In the drawing:

1 is a block diagram of a receiving signal processing of a QPSK system according to the related art;

2 is a schematic diagram of a QPSK and 9QAM constellation according to the related art;

3 is a schematic diagram of a square phase clock recovery + PQSK equalization process according to the related art;

4 is a schematic diagram of a fourth-order phase-detection clock recovery + PQSK equalization process according to the related art;

FIG. 5 is a schematic diagram of a square phase phase clock recovery +9QAM equalization process according to the related art; FIG.

6 is a schematic diagram of a fourth-order phase-detection clock recovery +9QAM equalization process according to the related art;

7 is a flow chart of a clock equalization method according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a clock equalization apparatus module according to an embodiment of the present invention; FIG.

9 is a schematic structural diagram of a QPSK system according to an embodiment of the present invention;

10 is a schematic diagram of an adaptive control process of a QPSK system according to an embodiment of the present invention;

11 is a schematic diagram of a clock equalization process of different spectral efficiencies according to an embodiment of the present invention;

12 is a block diagram of an array for CMA coefficient update and CMMA coefficient update, in accordance with an embodiment of the present invention.

detailed description

The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.

It is to be understood that the terms "first", "second" and the like in the specification and claims of the present invention are used to distinguish similar objects, and are not necessarily used to describe a particular order or order.

In this embodiment, a clock balancing method for a QPSK system is provided. FIG. 7 is a flowchart of a clock balancing method according to an embodiment of the present invention. As shown in FIG. 7, the process includes the following steps:

Step S102, obtaining, from the clock recovery module, a clock signal after performing clock recovery by using a square phase discrimination algorithm;

Step S104, obtaining, from the equalization module, a mean square error signal after performing equalization filtering by using a QPSK algorithm;

Step S106, filtering the clock signal and the MSE signal respectively to obtain a clock strength indication signal and an equalization convergence error indication signal;

Step S108, determining whether the clock strength indication signal is greater than a preset first clock strength threshold, and whether the equalization convergence error indication signal is less than a preset mean square error threshold;

Step S110, if yes, determining that the clock recovery and equalization filtering of the QPSK quadrature phase shift keying system is valid.

Through the above steps, the error signal provided by the clock signal and the equalization algorithm is used as the feedback signal, and the optimal phase discrimination mode and the equalization algorithm are adaptively selected, thereby achieving optimal reception performance under different spectral efficiency.

Preferably, if the result of the determination in the above step S108 is no, the following steps are further performed:

Step S112, adjusting the square phase discrimination algorithm used for clock recovery of the QPSK quadrature phase shift keying system to a fourth power phase discrimination algorithm;

Step S114, acquiring a new clock strength indication signal and an equalization convergence error indication signal;

Step S116, determining whether the clock strength indication signal is greater than a preset second clock strength threshold, and whether the equalization convergence error indication signal is less than a preset mean square error threshold;

Step S118, if yes, it is determined that the clock recovery and equalization filtering of the QPSK quadrature phase shift keying system is valid.

Preferably, if the result of the determination in the above step S116 is no, the following steps are further performed:

Step S120, adjusting the QPSK algorithm used by the QPSK quadrature phase shift keying system for equalization filtering to the 9QAM algorithm;

Step S122, acquiring a new clock strength indication signal and an equalization convergence error indication signal;

Step S124: Re-determine whether the clock strength indication signal is greater than a preset second clock strength threshold, and whether the equalization convergence error indication signal is less than a preset mean square error threshold;

Step S126, if yes, it is determined that the clock recovery and equalization filtering of the QPSK quadrature phase shift keying system is valid.

Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation. Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk, The optical disc includes a number of instructions for causing a terminal device (which may be a cell phone, a computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.

A clock equalization device for the QPSK system is also provided in the embodiment, and the device is used to implement the above-mentioned embodiments and preferred embodiments, which are not described again. As used below, the term "module" may implement a combination of software and/or hardware of a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.

FIG. 8 is a schematic structural diagram of a clock equalization apparatus module according to an embodiment of the present invention. As shown in FIG. 8, the apparatus includes an acquisition module 10 and an adjustment module 20.

The obtaining module 10 is configured to acquire a QPSK signal or a 9QAM signal of the QPSK system; the adjusting module 20 is configured to adjust a clock recovery algorithm and/or an equalization algorithm of the QPSK system according to different spectral efficiencies of the QPSK system.

Preferably, the obtaining module 10 includes: a first acquiring unit 101, configured to acquire a clock signal after clock recovery using a square phase discrimination algorithm from a clock recovery module of the QPSK system, and obtain an equalization module from the QPSK system to perform equalization using a QPSK algorithm. The filtered mean square error signal; the filtering unit 102 is configured to filter the clock signal and the MSE signal respectively to obtain a clock strength indication signal and an equalization convergence error indication signal.

Preferably, the adjustment module 20 includes: a first determining unit 201, configured to determine whether the first condition is met, wherein the first condition is: the clock strength indication signal is greater than a preset first clock strength threshold, and the equalization convergence error indication signal Less than the preset mean square error threshold; the first determining unit 202 is configured to determine that the clock recovery and equalization filtering of the QPSK system is valid if the second condition is satisfied.

Preferably, the adjustment module 20 further includes: a first adjusting unit 203, configured to adjust a square phase discrimination algorithm used for clock recovery of the QPSK system to a fourth power phase discrimination algorithm if the first condition is not satisfied; The obtaining unit 204 is configured to acquire a new clock strength indication signal and a balanced convergence error indication signal. The second determining unit 205 is configured to determine whether the second condition is met, wherein the second condition is: the clock strength indication signal is greater than the preset The second clock strength threshold, and the equalization convergence error indication signal is less than the preset mean square error threshold; and the second determining unit 206 is configured to determine that the clock recovery and equalization filtering of the QPSK system is valid if the second condition is satisfied.

Preferably, the adjustment module 20 further includes: a second adjustment unit 207, configured to adjust the QPSK algorithm used for equalizing and filtering the QPSK system to the 9QAM algorithm if the second condition is not satisfied; and the third obtaining unit 208 is configured to Obtaining a new clock strength indication signal and a balanced convergence error indication signal; the third determining unit 209 is configured to re-determine whether the second condition is established; and the third determining unit 210 is configured to determine the QPSK system if the second condition is established. The clock recovery and equalization filtering are effective.

It should be noted that each of the above modules and units may be implemented by software or hardware. For the latter, the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; Among multiple processors.

In the present embodiment, a QPSK system is also provided. As shown in FIG. 9, the QPSK system includes the clock equalization device (shown as an adaptive control module in the figure), and the clock equalization device and the clock in the QPSK system, respectively. The recovery module is connected to the equalization module.

In the prior art, after the QPSK signal is filtered by the digital end of the transmitting end or filtered by the WSS, the spectral efficiency is different, and the signal is damaged. Therefore, it is desirable to use one of the three schemes introduced in the background technology as a general scheme. It is impossible to obtain optimal performance in an actual scenario. The present invention provides an adaptive clock equalization scheme. As shown in FIG. 9, an adaptive control module is added between the clock recovery algorithm and the equalization algorithm, and the clock signal is utilized. And the error signal provided by the equalization algorithm is used as the feedback signal, and the adaptive control optical module algorithm selects the optimal phase discrimination mode and the equalization algorithm, thereby realizing The optimal receiving performance under different spectral efficiencies is compatible with the above three schemes.

The adaptive process is shown in Figure 10:

Step 1: The optical module selects the square phase discrimination + QPSK equalization for clock recovery and equalization, and obtains the clock signal C from the clock recovery module, the mean square error MSE from the equalization module, and the MSE_avg, C_avg for the MSE filter. It is a clock strength indication signal. Since the spectral efficiency is achieved by the source filtering, the spectral efficiency is different, and the filtering at the origin is different, so the degree of the clock signal is weakened. As the spectrum efficiency increases, the clock strength is also increased. Small, C_avg gradually decreases, C_Thresh1 represents the minimum intensity of the squared phase-clocked clock signal. When the clock strength is greater than this value, the spectral efficiency is relatively low, and the square phase discrimination can perform phase discrimination well. C_Thresh2 represents the fourth-order phase detection. Minimum strength of the clock signal; MSE_avg equalization convergence error indication signal, the smaller the value, the better the equalization effect, the larger the value, the worse the equalization effect;

Step 2: Determine whether the following two conditions are true: C_avg>C_Thresh1; and MSE_avg<MSE_Thresh. If it is established, it indicates that the clock signal is stronger, the equalization effect is better, the spectrum efficiency is identified as lower spectral efficiency, and the optical module is the default selection; otherwise, the clock signal is weaker, and the square phase phase is not good for clock recovery, spectrum efficiency. It may be higher, it needs to be adjusted to: 4th power phase detection + QPSK equalization for clock recovery and equalization, using low frequency components for phase discrimination, in order to make further judgment on spectrum efficiency, and skip to step 3;

Step 3: Determine whether the following two conditions are true: C_avg>C_Thresh2; and MSE_avg<MSE_Thresh. If it is established, it indicates that the clock signal obtained by the fourth-order phase is stronger, the equalization effect is better, the spectrum efficiency is recognized as relatively higher spectral efficiency, and the optical module maintains the selection; otherwise, the clock signal obtained by the fourth-order phase discrimination is still It is weak, four phase detection can't complete the clock recovery well, and the spectrum efficiency may be higher. It needs to be adjusted to: 4th power phase detection + 9QAM equalization for clock recovery and equalization, reducing the influence of high frequency noise, so as to improve spectrum efficiency. Make further judgments and skip to step four;

Step 4: Determine if the following two conditions are true: C_avg>C_Thresh2; and MSE_avg<MSE_Thresh. If it is established, it indicates that the clock signal obtained by the fourth-order phase is stronger, the equalization effect is better, the spectrum efficiency is recognized as ultra-high spectral efficiency, and the optical module maintains the selection; otherwise, the clock signal obtained by the fourth-order phase discrimination is still better. Weak, four phase discrimination can not complete the clock recovery well, the spectrum efficiency may be higher, and we need to find a new solution.

In the above embodiment, the adaptive control method is adopted, and the stepwise identification of the spectrum efficiency is completed by determining the size of the clock signal and the mean square error signal, thereby achieving the purpose of self-identification of the spectrum efficiency, and then selecting by the corresponding algorithm module. Compared with the prior art, the optimal clock balancing effect is not only wider in application range, but also better in performance, and power consumption and complexity are not increased, and the effect of adapting different spectral efficiency QPSK systems is achieved.

11 is a schematic diagram of a clock equalization flow of different spectral efficiencies according to an embodiment of the present invention, including a low spectral efficiency QPSK system, a relatively high spectral efficiency QPSK system, and a high spectral efficiency QPSK system, respectively.

Embodiment 1: Low spectral efficiency QPSK system. In this system, the spectrum does not need to be excessively compressed, and the ISI is small, so the scheme is applicable, and the implementation steps are as follows:

Step 1: As shown in FIG. 11, the signal for completing the dispersion compensation is divided into two paths, one directly enters the buffer BUF, and is saved, one for the estimation of the clock error, and the signal for the clock estimation is first converted into the frequency domain by the FFT. Then multiply the H coefficient of the feedback of the equalization algorithm to filter out the damage such as PMD and residual dispersion, and then perform clock error estimation. The estimation result is loop filtered and then input to the interpolation module. At this time, the signal is taken out from the buffer, and interpolation is performed. After interpolation, the interpolation is performed. The signal is output to the equalization algorithm, and the clock signal C is filtered to obtain a stable clock signal Ck, and the size of the Ck is monitored to assist in the selection of the phase discrimination mode. It is expected that the system will monitor Ck>Ck_Thresh1 and MSE<MSE_Thresh, so the system maintains The default selection.

Step 2: The signal is divided into two paths, one signal is filtered by using the previously calculated coefficient H1, the filtering is completed by frequency domain multiplication, and one way is directly used for updating the H coefficient.

Step 3: As shown in FIG. 11, the equalization algorithm constructs M (for example, 32) groups of signals A and B according to the input signal, and the number of samples per group and the equalization filter order are the same, as shown in FIG. 12, if the sample sequence is 1 , 2,3,...,N,N+1,...,N+M,...., then each group B is equivalent to each group A's time window sliding to the left by one sample, each group of data For the output of the group data equalization filter, if the equalization coefficient is selected as the even point output coefficient H1, the CMA is used for equalization, and the coefficient calculation uses the A group signal; if the equalization coefficient is selected as the odd sample output coefficient H2, the coefficient update calculation is used. Group B signal, since the CMMA convergence phase equalization filter adjusts the output forward by a sample point, B as the filter input is also shifted forward by a sample point relative to A. The system startup phase is based on the clock signals Ck and MSE. The size is selected for H1 and H2, and the signals of group A and group B are also selected accordingly. It is expected that the system will monitor Ck>Ck_Thresh1 and MSE<MSE_Thresh as shown in Figure 9, so the system maintains the default selection.

Step 4: As shown in Figure 11, the output data is used for the calculation of the error in addition to the output. In order to achieve the selection of the parity samples, we use different zero-padding modes for the equalization coefficients used for equalization filtering: hypothesis filter The order of H is 2*M+1, then the filter zero-filling method is as follows:

H1=[H(M+1:2M-1)0 0 0,...0,H(1:M-1)]; (5)

H2=[H(M:2M+1)0 0 0,...0,H(1:M-1)]; (6)

When H1 is used for filtering, the output is an even sample. When H2 is used for filtering, the odd-like point is output, that is, the 9QAM-like signal is selected. In the system startup phase, H1 and H2 are selected according to the size of the clock signal Ck and MSE. The system in Figure 9 will monitor Ck>Ck_Thresh1 and MSE<MSE_Thresh, so the system maintains the default selection.

Step 5: Perform FFT transformation on the signal and filter coefficients H1/H2, then multiply the two by frequency domain to complete the filtering, then convert into a time domain signal by performing IFFT, and finally downsample the output.

Step Six: After obtaining the output data, fetch 32 data error calculation, corresponding to 32 groups of output result input, denoted output Xo, Yo, QPSK convergence radius R _cma, 9QAM radius of convergence of R1, R2, R3, the error For errx, erry, if the equalization coefficient is selected as the even point output coefficient H1, the error calculation is performed using Equation 1. If the equalization coefficient is selected as the odd-point output coefficient H2, Equation 2 is used for error calculation:

Calculation formula 1:

Calculation formula 2:

When the equalization coefficient is selected as the even point output coefficient H2, the equalization filter output is adjusted from the even point to the odd point, and the equalization algorithm is also adjusted from the CMA to the CMMA. It is expected that the system startup phase is based on the size of the clock signals Ck and MSE. The selection of H1 and H2 also selects the error formula. It is expected that the system will monitor Ck>Ck_Thresh1 and MSE<MSE_Thresh, so the system maintains the selection formula 1 for error calculation.

Through the above steps, the selection of the algorithm module is completed to achieve the effect of adapting to low spectral efficiency.

Embodiment 2: Relatively high spectral efficiency QPSK system

Step 1: As shown in FIG. 11, the signal for completing the dispersion compensation is divided into two paths, one directly enters the buffer BUF, and is saved, one for the estimation of the clock error, and the signal for the clock estimation is first converted into the frequency domain by the FFT. Then multiply the H coefficient of the feedback of the equalization algorithm to filter out the damage such as PMD and residual dispersion, and then perform clock error estimation. The estimation result is loop filtered and then input to the interpolation module. At this time, the signal is taken out from the buffer, and interpolation is performed. After interpolation, the interpolation is performed. The signal is output to the equalization algorithm, and the clock signal C is filtered to obtain a stable clock signal Ck, and the size of the Ck is monitored to assist in the selection of the phase discrimination mode. It is expected that the system will monitor Ck<Ck_Thresh1 and MSE>MSE_Thresh, and the system reselects. 4th phase discrimination, finally monitoring Ck>Ck_Thresh2 and MSE<MSE_Thresh, the system keeps the selection.

Step 3: As shown in FIG. 11, the equalization algorithm constructs M (for example, 32) groups of signals A and B according to the input signal, and the number of samples per group and the equalization filter order are the same, as shown in FIG. 12, if the sample sequence is 1 , 2,3,...,N,N+1,...,N+M,...., then each group B is equivalent to each group A's time window sliding to the left by one sample, each group of data For the output of the group data equalization filter, if the equalization coefficient is selected as the even point output coefficient H1, the CMA is used for equalization, and the coefficient calculation uses the A group signal; if the equalization coefficient is selected as the odd sample output coefficient H2, the coefficient update calculation is used. Group B signal, since the CMMA convergence phase equalization filter adjusts the output forward by a sample point, B as the filter input is also shifted forward by a sample point relative to A. The system startup phase is based on the clock signals Ck and MSE. The size is selected for H1 and H2, and the signals of group A and group B are also selected accordingly. Expected: The system will monitor Ck<Ck_Thresh1 and MSE>MSE_Thresh, the system will reselect the 4th power phase detection, and the coefficient is still H1, so the system still selects group A, and finally monitors Ck>Ck_Thresh2 and MSE<MSE_Thresh, the system still selects Group A.

H1=[H(M+1:2M-1)0 0 0,...0,H(1:M-1)];

H2=[H(M:2M+1)0 0 0,...0,H(1:M-1)];

When H1 is used for filtering, the output is an even sample. When H2 is used for filtering, the odd-like points are output, that is, the 9QAM-like signal. In the system startup phase, H1 and H2 are selected according to the size of the clock signals Ck and MSE. Expected: The system will monitor Ck<Ck_Thresh1 and MSE>MSE_Thresh, the system will reselect the 4th power phase, and the coefficient will still be H1. Finally, Ck>Ck_Thresh2 and MSE<MSE_Thresh will be monitored, so the system will still use the coefficient H1.

Calculation formula 1:

Calculation formula 2:

When the equalization coefficient is selected as the even point output coefficient H2, the equalization filter output is adjusted from the even point to the odd point, and the equalization algorithm is also adjusted from CMA to CMMA. Expected: The system will monitor Ck<Ck_Thresh1 and MSE>MSE_Thresh, the system will reselect the 4th phase and the coefficient will still be H1, so the system will continue to apply CMA for equalization, use error calculation formula 1 for error calculation, and finally monitor Ck. >Ck_Thresh2 is simultaneously MSE<MSE_Thresh, so the system uses error calculation formula 1 for error calculation.

Through the above steps, the selection of the algorithm module is completed, and the effect of adapting to relatively high spectral efficiency is achieved.

Implementation three: high spectral efficiency QPSK system

In this system, the spectrum is compressed to a large extent, and the ISI is very large. This scheme is applicable. The implementation steps are as follows:

Step 1: As shown in FIG. 11, the signal for completing the dispersion compensation is divided into two paths, one directly enters the buffer BUF, and is saved, one for the estimation of the clock error, and the signal for the clock estimation is first converted into the frequency domain by the FFT. Then multiply the H coefficient of the feedback of the equalization algorithm to filter out the damage such as PMD and residual dispersion, and then perform clock error estimation. The estimation result is loop filtered and then input to the interpolation module. At this time, the signal is taken out from the buffer, and interpolation is performed. After interpolation, the interpolation is performed. The signal is output to the equalization algorithm, and the clock signal C is filtered to obtain a stable clock signal Ck, and the size of the Ck is monitored to assist in the selection of the phase discrimination mode. It is expected that the system will monitor Ck<Ck_Thresh1 and MSE>MSE_Thresh, and the system reselects. 4th phase discrimination, but still monitor Ck<Ck_Thresh2 and MSE>MSE_Thresh, the system reselects coefficient H2 for equalization filtering, and finally monitors Ck>Ck_Thresh2 and MSE<MSE_Thresh, the system keeps the selection.

Step 3: As shown in FIG. 11, the equalization algorithm constructs M (for example, 32) groups of signals A and B according to the input signal, and the number of samples per group and the equalization filter order are the same, as shown in FIG. 12, if the sample sequence is 1 , 2,3,...,N,N+1,...,N+M,...., then each group B is equivalent to each group A's time window sliding to the left by one sample, each group of data For the output of the group data equalization filter, if the equalization coefficient is selected as the even point output coefficient H1, the CMA is used for equalization, and the coefficient calculation uses the A group signal; if the equalization coefficient is selected as the odd sample output coefficient H2, the coefficient update calculation is used. Group B signal, since the CMMA convergence phase equalization filter adjusts the output forward by a sample point, B as the filter input is also shifted forward by a sample point relative to A. The system startup phase is based on the clock signals Ck and MSE. The size is selected for H1 and H2, and the signals of group A and group B are also selected accordingly. Expected: The system will monitor Ck<Ck_Thresh1 and MSE>MSE_Thresh, the system will reselect the 4th phase and the coefficient is still H1, so the system still selects the A group, but still monitors Ck<Ck_Thresh2 and MSE>MSE_Thresh, the system is re- Select the coefficient H2 for equalization filtering, and finally monitor Ck>Ck_Thresh2 and MSE<MSE_Thresh, the system still selects group A.

H1=[H(M+1:2M-1)0 0 0,...0,H(1:M-1)];

H2=[H(M:2M+1)0 0 0,...0,H(1:M-1)];

When H1 is used for filtering, the output is an even sample. When H2 is used for filtering, the odd-like points are output, that is, the 9QAM-like signal. In the system startup phase, H1 and H2 are selected according to the size of the clock signals Ck and MSE. Expected: The system will monitor Ck<Ck_Thresh1 and MSE>MSE_Thresh, the system will reselect the 4th power phase detection, and the coefficient is still H1, but still monitor Ck<Ck_Thresh2 and MSE>MSE_Thresh, the system reselects the coefficient H2 for equalization filtering. Finally, it is monitored that Ck>Ck_Thresh2 and MSE<MSE_Thresh, so the system still uses the coefficient H1.

Calculation formula 1:

Calculation formula 2:

When the equalization coefficient is selected as the even point output coefficient H2, the equalization filter output is adjusted from the even point to the odd point, and the equalization algorithm is also adjusted from CMA to CMMA. Expected: As shown in Figure 9, the system will monitor Ck<Ck_Thresh1 and MSE>MSE_Thresh. The system reselects the 4th phase and the coefficient is still H1. Therefore, the system keeps the CMA balanced, and uses the error calculation formula 1 to calculate the error, but Still monitoring Ck<Ck_Thresh2 and MSE>MSE_Thresh, the system reselects the coefficient H2 for equalization filtering, and finally monitors Ck>Ck_Thresh2 and MSE<MSE_Thresh, so the system uses error calculation formula 1 for error calculation.

Through the above steps, the selection of the algorithm module is completed to achieve the effect of adapting to high spectral efficiency.

Another embodiment of the present invention also provides a storage medium. The storage medium may be configured to store program code for performing the above steps: in this embodiment, the storage medium may include, but is not limited to, a U disk, a read-only memory (ROM), and a random access. A variety of media that can store program code, such as RAM (Random Access Memory), removable hard disk, disk, or optical disk.

It will be apparent to those skilled in the art that the various modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Industrial applicability

The technical solution provided by the embodiment of the present invention can be applied to a QPSK system, and the error signal provided by the clock signal and the equalization algorithm is used as a feedback signal to adaptively select an optimal phase discrimination mode and an equalization algorithm, thereby achieving different spectral efficiency. Optimal reception performance.

Claims

A clock equalization method for a QPSK quadrature phase shift keying system, comprising:

Obtaining a QPSK signal or a 9QAM signal of the QPSK system;

The clock recovery algorithm and/or the equalization algorithm of the QPSK system is adjusted according to the spectral efficiency of the QPSK system.
The clock equalization method according to claim 1, wherein acquiring the QPSK signal or the 9QAM signal of the QPSK system comprises:

Obtaining a clock signal after the clock recovery by using the square phase discrimination algorithm from the clock recovery module of the QPSK system;

Obtaining, from the equalization module of the QPSK system, a mean square error signal after equalization filtering by using a QPSK algorithm;

The clock signal and the mean square error signal are separately filtered to obtain a clock strength indication signal and an equalization convergence error indication signal.
The clock equalization method according to claim 2, wherein the clock recovery algorithm and/or the equalization algorithm of the QPSK system are adjusted according to different spectral efficiencies of the QPSK system, including:

Determining whether the first condition is met, wherein the first condition is: the clock strength indication signal is greater than a preset first clock strength threshold, and the equalization convergence error indication signal is less than a preset mean square error threshold;

If the first condition is true, it is determined that the clock recovery and equalization filtering of the QPSK system is valid.
The clock equalization method according to claim 3, wherein the method further comprises:

If the first condition is not satisfied, the square phase discrimination algorithm used for clock recovery of the QPSK system is adjusted to a fourth power phase discrimination algorithm;

Obtaining a new clock strength indication signal and an equalization convergence error indication signal;

Determining whether the second condition is met, wherein the second condition is: the clock strength indication signal is greater than a preset second clock strength threshold, and the equalization convergence error indication signal is smaller than a preset mean square error threshold;

If the second condition is true, it is determined that the clock recovery and equalization filtering of the QPSK system is valid.
The clock equalization method according to claim 4, wherein the method further comprises:

If the second condition is not satisfied, adjusting the QPSK algorithm used by the QPSK system for equalization filtering to a 9QAM algorithm;

Obtaining a new clock strength indication signal and an equalization convergence error indication signal;

Re-determine whether the second condition is true;

If the second condition is true, it is determined that the clock recovery and equalization filtering of the QPSK system is valid.
The clock equalization method according to claim 1, wherein before acquiring the QPSK signal or the 9QAM signal of the QPSK system, the method further includes:

The signal for completing the dispersion compensation is divided into two paths, one is entered into the buffer for storage, and the other is converted to the frequency domain by the FFT, and multiplied by the H coefficient fed back by the equalization module, and then the clock error is estimated;

The estimation result is loop-filtered and output to the interpolation module, the signal is taken out from the buffer for interpolation, and the interpolated signal is output to the equalization module.
The clock equalization method according to claim 6, wherein the method further comprises:

Constructing a group M first signal and a group M second signal according to a signal input to the equalization module, wherein each group of the second signals slides to the left side with respect to a time window of each group of the first signals, The first signal is used for the calculation of the equalization coefficient H1, and the equalization coefficient H1 is output by the even sample; the second signal is used for the update of the equalization coefficient H2, and the equalization coefficient H2 is output by the odd sample, and M is positive. Integer.
The clock equalization method according to claim 7, wherein the equalization coefficients H1 and H2 are respectively zero-filled by the following formula:

H1=[H(M+1:2M-1)0 0 0,...0,H(1:M-1)];

H2=[H(M:2M+1)0 0 0,...0,H(1:M-1)];

Wherein, the order of the equalization filter is 2*M+1.
The clock equalization method according to claim 8, wherein said equalization coefficients H1 and H2 perform calculation of an error (errx, erry) using Equations 1 and 2, respectively, as follows:

Wherein, (Xo, Yo) is the output signal of the equalization filtering, R cma radius of convergence is QPSK, Ri is the radius of convergence of 9QAM, Wi is a weighting factor error.
A clock equalization device for a QPSK quadrature phase shift keying system, comprising:

Obtaining a module, configured to acquire a QPSK signal or a 9QAM signal of the QPSK system;

The adjustment module is configured to adjust a clock recovery algorithm and/or an equalization algorithm of the QPSK system according to different spectral efficiencies of the QPSK system.
The apparatus of claim 10, wherein the obtaining module comprises:

a first obtaining unit, configured to obtain a clock signal after clock recovery using a square phase discrimination algorithm from a clock recovery module of the QPSK system, and obtain a mean square after equalization filtering by using a QPSK algorithm from an equalization module of the QPSK system Error signal

And a filtering unit configured to separately filter the clock signal and the MSE signal to obtain a clock strength indication signal and an equalization convergence error indication signal.
The apparatus of claim 11 wherein said adjustment module comprises:

The first determining unit is configured to determine whether the first condition is met, wherein the first condition is: the clock strength indication signal is greater than a preset first clock strength threshold, and the equalization convergence error indication signal is less than a preset Mean square error threshold;

The first determining unit is configured to determine that the clock recovery and equalization filtering of the QPSK system is valid if the second condition is established.
The apparatus of claim 12, wherein the adjustment module further comprises:

a first adjusting unit, configured to adjust a square phase discrimination algorithm used for clock recovery of the QPSK system to a fourth power phase discrimination algorithm if the first condition is not satisfied;

a second acquiring unit, configured to acquire a new clock strength indication signal and an equalization convergence error indication signal;

The second determining unit is configured to determine whether the second condition is met, wherein the second condition is: the clock strength indication signal is greater than a preset second clock strength threshold, and the equalization convergence error indication signal is less than a preset Mean square error threshold;

The second determining unit is configured to determine that the clock recovery and equalization filtering of the QPSK system is valid if the second condition is established.
The apparatus of claim 13, wherein the adjustment module further comprises:

a second adjusting unit, configured to adjust a QPSK algorithm used for equalizing filtering by the QPSK system to a 9QAM algorithm if the second condition is not satisfied;

a third acquiring unit, configured to acquire a new clock strength indication signal and an equalization convergence error indication signal;

a third determining unit, configured to re-determine whether the second condition is established;

The third determining unit is configured to determine that the clock recovery and equalization filtering of the QPSK system is valid if the second condition is established.
A QPSK quadrature phase shift keying system, comprising: the clock equalization apparatus according to any one of claims 10 to 14, wherein the clock equalization apparatus is respectively connected to a clock recovery module and the equalization module in the QPSK system .
A computer readable storage medium storing a computer program that, when executed, performs the method of any one of claims 1 to 9.