WO2017213648A1

WO2017213648A1 - Quantum dot devices with doped conductive pathways

Info

Publication number: WO2017213648A1
Application number: PCT/US2016/036573
Authority: WO
Inventors: Ravi Pillarisetty; Jeanette M. Roberts; David J. Michalak; Zachary R. YOSCOVITS; James S. Clarke
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2016-06-09
Filing date: 2016-06-09
Publication date: 2017-12-14
Anticipated expiration: 2018-12-09

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate; a quantum well stack, including a quantum well layer, disposed on the substrate; and a conductive pathway to the quantum well layer through the substrate, wherein the conductive pathway includes a doped region of the substrate.

Description

QUANTUM DOT DEVICES WITH DOPED CONDUCTIVE PATHWAYS

Background

[0001] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0003] FIGS. 1-3 are cross-sectional views of a quantum dot device, in accordance with various embodiments.

[0004] FIGS. 4-38 illustrate various example stages in the manufacture of a quantum dot device, in accordance with various embodiments.

[0005] FIGS. 39-40 are cross-sectional views of various examples of quantum well stacks that may be used in a quantum dot device, in accordance with various embodiments.

[0006] FIG. 41 illustrates an embodiment of a quantum dot device having multiple groups of gates on a single fin, in accordance with various embodiments.

[0007] FIGS. 42-43 illustrate detail views of various embodiments of a doped region in a quantum dot device.

[0008] FIG. 44 is a flow diagram of an illustrative method of manufacturing a quantum dot device, in accordance with various embodiments.

[0009] FIGS. 45-46 are flow diagrams of illustrative methods of operating a quantum dot device, in accordance with various embodiments.

[0010] FIG. 47 is a block diagram of an example quantum computing device that may include any of the quantum dot devices disclosed herein, in accordance with various embodiments.

Detailed Description

[0011] Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate; a quantum well stack, including a quantum well layer, disposed on the substrate; and a conductive pathway to the quantum well layer through the substrate, wherein the conductive pathway includes a doped region of the substrate.

[0012] The quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits ("qubits") in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

[0013] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0014] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0015] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0016] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. As used herein, a "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide.

[0017] FIGS. 1-3 are cross-sectional views of a quantum dot device 100, in accordance with various embodiments. In particular, FIG. 2 illustrates the quantum dot device 100 taken along the section A- A of FIG. 1 (while FIG. 1 illustrates the quantum dot device 100 taken along the section C-C of FIG. 2), and FIG. 3 illustrates the quantum dot device 100 taken along the section B-B of FIG. 1 with a number of components not shown to more readily illustrate how the gates 106/108 may be patterned (while FIG. 1 illustrates a quantum dot device 100 taken along the section D-D of FIG. 3). Although FIG. 1 indicates that the cross-section illustrated in FIG. 2 is taken through the fin 104-1, an analogous cross section taken through the fin 104-2 may be identical, and thus the discussion of FIG. 2 refers generally to the "fin 104."

[0018] The quantum dot device 100 may include a substrate material 131 and multiple fins 104 extending away from the substrate material 131. The fins 104 may include a quantum well stack 146, which may include a quantum well layer 152-1 and a quantum well layer 152-2 spaced apart by a barrier layer 154.

[0019] Although only two fins, 104-1 and 104-2, are shown in FIGS. 1-3, this is simply for ease of illustration, and more than two fins 104 may be included in the quantum dot device 100. In some embodiments, the total number of fins 104 included in the quantum dot device 100 is an even number, with the fins 104 organized into pairs including one active fin 104 and one read fin 104, as discussed in detail below. When the quantum dot device 100 includes more than two fins 104, the fins 104 may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.). The discussion herein will largely focus on a single pair of fins 104 for ease of illustration, but all the teachings of the present disclosure apply to quantum dot devices 100 with more fins 104.

[0020] As noted above, each of the fins 104 may include two quantum well layers 152. The quantum well layers 152 included in the fins 104 may be arranged normal to the z-direction, and may provide layers in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device 100, as discussed in further detail below. The quantum well layers 152 themselves may provide a geometric constraint on the z-location of quantum dots in the fins 104, and the limited extent of the fins 104 (and therefore the quantum well layers 152) in the y-direction may provide a geometric constraint on the y-location of quantum dots in the fins 104. To control the x-location of quantum dots in the fins 104, voltages may be applied to gates disposed on the fins 104 to adjust the energy profile along the fins 104 in the x-direction and thereby constrain the x-location of quantum dots within quantum wells (discussed in detail below with reference to the gates 106/108). The dimensions of the fins 104 may take any suitable values. For example, in some embodiments, the fins 104 may each have a width 162 between 10 and 30 nanometers. In some embodiments, the fins 104 may each have a height 164 between 200 and 400 nanometers (e.g., between 250 and 350 nanometers, or equal to 300 nanometers).

[0021] The fins 104 may be arranged in parallel, as illustrated in FIGS. 1 and 3, and may be spaced apart by an insulating material 128, which may be disposed on opposite faces of the fins 104. The insulating material 128 may be a dielectric material, such as silicon oxide. For example, in some embodiments, the fins 104 may be spaced apart by a distance 160 between 100 and 250 microns.

[0022] Multiple gates may be disposed on each of the fins 104. In particular, a first set of gates 105- 1 may be disposed proximate to the "bottom" of each fin 104, and a second set of gates 105-2 may be disposed proximate to the "top" of each fin 104. In the embodiment illustrated in FIG. 2, the first set of gates 105-1 includes three gates 106-1 and two gates 108-1, and the second set of gates 105-2 includes three gates 106-2 and two gates 108-2. This particular number of gates is simply illustrative, and any suitable number of gates may be used. Additionally, as discussed below with reference to FIG. 41, multiple sets of the gates 105-1 and 105-2 may be disposed on the fin 104.

[0023] As shown in FIG. 2, the gate 108-11 may be disposed between the gates 106-11 and 106-12, and the gate 108-12 may be disposed between the gates 106-12 and 106-13. The gates 106-21, 108- 21, 106-22, 108-22, and 106-23 (of the set of gates 105-2) are distributed along the fin 104 analogously to the distribution of the gates 106-11, 108-11, 106-12, 108-12, and 106-13 (of the set of gates 105-1). References to a "gate 106" herein may refer to any of the gates 106, while reference to a "gate 108" herein may refer to any of the gates 108. Reference to the "gates 106-1" herein may refer to any of the gates 106 of the first set of gates 105-1 (and analogously for the "gates 106-2") and reference to the "gates 108-1" herein may refer to any of the gates 108 of the first set of gates 105-1 (and analogously for the "gates 108-2").

[0024] Each of the gates 106/108 may include a gate dielectric 114 (e.g., the gate dielectric 114-1 for the gates 106-1/108-1, and the gate dielectric 114-2 for the gates 106-2/108-2). In the embodiment illustrated in FIG. 2, the gate dielectric 114 for all of the gates 106/108 in a particular set of gates 105 is provided by a common layer of gate dielectric material. In other embodiments, the gate dielectric 114 for each of the gates 106/108 in a particular set of gates 105 may be provided by separate portions of gate dielectric 114. In some embodiments, the gate dielectric 114 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin 104 and the corresponding gate metal). The gate dielectric 114 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 114 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 114 to improve the quality of the gate dielectric 114. The gate dielectric 114-1 may be a same material as the gate dielectric 114-2, or a different material.

[0025] Each of the gates 106-1 may include a gate metal 110-1. The gate metal 110-1 may be disposed between the gate dielectric 114-1 and some of the substrate material 131 (e.g., between the gate dielectric 114-1 and a filled via 120-1 extending through the substrate material 131), and the gate dielectric 114-1 may be disposed between the gate metal 110-1 and the fin 104. In some embodiments, the gate metal 110-1 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. The sides of the gate metal 110-1 may be substantially parallel, as shown in FIG. 2, and insulating spacers 134-1 may be disposed on the sides of the gate metal 110-1. As illustrated in FIG. 2, the spacers 134-1 may be thinner closer to the fin 104 and thicker farther away from the fin 104. In some embodiments, the spacers 134-1 may have a convex shape. The spacers 134-1 may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride).

[0026] Each of the gates 108-1 may include a gate metal 112-1. The gate metal 112-1 may be disposed between the gate dielectric 114-1 and some of the substrate material 131 (e.g., between the gate dielectric 114-1 and a filled via 122-1 extending through the substrate material 131), and the gate dielectric 114-1 may be disposed between the gate metal 112-1 and the fin 104. In some embodiments, the gate metal 112-1 may be a different metal from the gate metal 110-1; in other embodiments, the gate metal 112-1 and the gate metal 110-1 may have the same material composition. In some embodiments, the gate metal 112-1 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride.

[0027] Each of the gates 106-2 may include a gate metal 110-2 and a hardmask 116-2. The hardmask 116-2 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 110-2 may be disposed between the hardmask 116-2 and the gate dielectric 114-2, and the gate dielectric 114-2 may be disposed between the gate metal 110-2 and the fin 104. Only one portion of the hardmask 116-2 is labeled in FIG. 2 for ease of illustration. In some embodiments, the gate metal 110-2 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 116-2 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 116-2 may be removed during processing, as discussed below). The sides of the gate metal 110-2 may be substantially parallel, as shown in FIG. 2, and insulating spacers 134-2 may be disposed on the sides of the gate metal 110-2 and the hardmask 116-2. As illustrated in FIG. 2, the spacers 134-2 may be thicker closer to the fin 104 and thinner farther away from the fin 104. In some embodiments, the spacers 134-2 may have a convex shape. The spacers 134-2 may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride). In some embodiments, the gate metal 110-2 may be a different metal from the gate metal 110-1; in other embodiments, the gate metal 110-2 and the gate metal 110-1 may have the same material composition.

[0028] Each of the gates 108-2 may include a gate metal 112-2 and a hardmask 118-2. The hardmask 118-2 may be formed of any of the materials discussed above with reference to the hardmask 116-2. The gate metal 112-2 may be disposed between the hardmask 118-2 and the gate dielectric 114-2, and the gate dielectric 114-2 may be disposed between the gate metal 112-2 and the fin 104. In the embodiment illustrated in FIG. 2, the hardmask 118-2 may extend over the hardmask 116-2 (and over the gate metal 110-2 of the gates 106-2), while in other embodiments, the hardmask 118-2 may not extend over the gate metal 110-2. In some embodiments, the gate metal 112-2 may be a different metal from the gate metal 110-2; in other embodiments, the gate metal 112-2 and the gate metal 110-2 may have the same material composition. In some embodiments, the gate metal 112-2 may be a different metal from the gate metal 112-1; in other embodiments, the gate metal 112-2 and the gate metal 112-1 may have the same material composition. In some embodiments, the gate metal 112-2 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 118-2 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 118-2 may be removed during processing, as discussed below).

[0029] The gate 108-11 may extend between the proximate spacers 134-1 on the sides of the gate 106-11 and the gate 106-12, as shown in FIG. 2. In some embodiments, the gate metal 112-1 of the gate 108-11 may extend between the spacers 134-1 on the sides of the gate 106-11 and the gate 106-12. Thus, the gate metal 112-1 of the gate 108-11 may have a shape that is substantially complementary to the shape of the spacers 134-1, as shown. Similarly, the gate 108-12 may extend between the proximate spacers 134-1 on the sides of the gate 106-12 and the gate 106-13. The gates 106-2/108-2 and the dielectric material 114-2 of the second set of gates 105-2 may take the form of any of these embodiments of the gates 106-1/108-1 and the dielectric material 114-1. In some embodiments in which the gate dielectric 114-2 is not a layer shared commonly between the gates 108-2 and 106-2, but instead is separately deposited on the fin 104 between the spacers 134- 2, the gate dielectric 114-2 may extend at least partially up the sides of the spacers 134-2, and the gate metal 112-2 may extend between the portions of gate dielectric 114-2 on the spacers 134-2.

[0030] The dimensions of the gates 106/108 may take any suitable values. For example, in some embodiments, the z-height 166 of the gate metal 110 may be between 40 and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal 112 may be in the same range. In embodiments like the one illustrated in FIG. 2, the z-height of the gate metal 112 may be greater than the z-height of the gate metal 110. In some embodiments, the length 168 of the gate metal 110 (i.e., in the x-direction) may be between 20 and 40 nanometers (e.g., 30 nanometers). In some embodiments, the distance 170 between adjacent ones of the gates 106 (e.g., as measured from the gate metal 110 of one gate 106 to the gate metal 110 of an adjacent gate 106 in the x-direction, as illustrated in FIG. 2) may be between 40 and 60 nanometers (e.g., 50 nanometers). In some embodiments, the thickness 172 of the spacers 134 may be between 1 and 10 nanometers (e.g., between 3 and 5 nanometers, between 4 and 6 nanometers, or between 4 and 7 nanometers). The length of the gate metal 112 (i.e., in the x-direction) may depend on the dimensions of the gates 106 and the spacers 134, as illustrated in FIG. 2. As indicated in FIG. 1, the gates 106/108 on one fin 104 may extend over the insulating material 128 beyond their respective fins 104 and towards the other fin 104, but may be isolated from their counterpart gates by the intervening insulating material 130 and spacers 134.

[0031] As shown in FIG. 2, the gates 106 and 108 of each set 105 may be alternatingly arranged along the fin 104 in the x-direction. During operation of the quantum dot device 100, voltages may be applied to the gates 106-1/108-1 to adjust the potential energy in the quantum well layer 152-1 in the fin 104 to create quantum wells of varying depths in which quantum dots 142-1 may form. Similarly, voltages may be applied to the gates 106-2/108-2 to adjust the potential energy in the quantum well layer 152-2 in the fin 104 to create quantum wells of varying depths in which quantum dots 142-2 may form. Only one quantum dot 142-1 and one quantum dot 142-2 is labeled with a reference numeral in FIGS. 2 and 3 for ease of illustration, but five are indicated as dotted circles in each fin 104. The spacers 134 may themselves provide "passive" barriers between quantum wells under the gates 106/108 in the quantum well layers 152, and the voltages applied to different ones of the gates 106/108 may adjust the potential energy under the gates 106/108 in the associated quantum well layer 152; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers. The discussion below may generally refer to gates 106/108, quantum dots 142, and quantum well layers 152 (e.g., the gates 106-1/108-1, quantum dots 142-1, and quantum well layer 152-1, respectively; the gates 106-2/108-2, quantum dots 142-2, and quantum well layer 152-2, respectively; or to both).

[0032] The fins 104 may include doped regions 140 that may serve as a reservoir of charge carriers for the quantum dot device 100. In particular, the doped regions 140-1 may be in conductive contact with the quantum well layer 152-1, and the doped regions 140-2 may be in conductive contact with the quantum well layer 152-2. For example, an n-type doped region 140 may supply electrons for electron-type quantum dots 142, and a p-type doped region 140 may supply holes for hole-type quantum dots 142. In some embodiments, an interface material 141 may be disposed at a surface of a doped region 140, as shown by the interface material 141-1 at the surface of the doped regions 140-1 and the interface material 141-2 at the surface of the doped regions 140-2. The interface material 141 may facilitate electrical coupling between a conductive contact (e.g., a filled via 136, as discussed below) and the doped region 140. The interface material 141 may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the doped region 140 includes silicon, the interface material 141 may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide (e.g., as discussed below with reference to FIGS. 34-35). In some embodiments, the interface material 141 may be a non-silicide compound, such as titanium nitride. In some embodiments, the interface material 141 may be a metal (e.g., aluminum, tungsten, or indium).

[0033] The quantum dot devices 100 disclosed herein may be used to form electron-type or hole- type quantum dots 142. Note that the polarity of the voltages applied to the gates 106/108 to form quantum wells/barriers depend on the charge carriers used in the quantum dot device 100. In embodiments in which the charge carriers are electrons (and thus the quantum dots 142 are electron-type quantum dots), amply negative voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply positive voltages applied to a gate 106/108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in the associated quantum well layer 152 in which an electron-type quantum dot 142 may form). In embodiments in which the charge carriers are holes (and thus the quantum dots 142 are hole-type quantum dots), amply positive voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply negative voltages applied to a gate 106 and 108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in the associated quantum well layer 152 in which a hole-type quantum dot 142 may form). The quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots. [0034] Voltages may be applied to each of the gates 106 and 108 separately to adjust the potential energy in the associated quantum well layer 152 under the gates 106 and 108, and thereby control the formation of quantum dots 142 under each of the gates 106 and 108. Additionally, the relative potential energy profiles under different ones of the gates 106 and 108 allow the quantum dot device 100 to tune the potential interaction between quantum dots 142 under adjacent gates. For example, if two adjacent quantum dots 142 (e.g., one quantum dot 142-1 under a gate 106-1 and another quantum dot 142-1 under a gate 108-1) are separated by only a short potential barrier, the two quantum dots 142 may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 106/108 may be adjusted by adjusting the voltages on the respective gates 106/108, the differences in potential between adjacent gates 106/108 may be adjusted, and thus the interaction tuned.

[0035] In some applications, the gates 108 may be used as plunger gates to enable the formation of quantum dots 142 under the gates 108, while the gates 106 may be used as barrier gates to adjust the potential barrier between quantum dots 142 formed under adjacent gates 108. In other applications, the gates 108 may be used as barrier gates, while the gates 106 are used as plunger gates. In other applications, quantum dots 142 may be formed under all of the gates 106 and 108, or under any desired subset of the gates 106 and 108.

[0036] Filled vias and lines may make contact with the gates 106/108, and to the doped regions 140, to enable electrical connection to the gates 106/108 and the doped regions 140 to be made in desired locations. As shown in FIGS. 1-3, the gates 106-1 may extend away from the fins 104, and filled vias 120-1 may contact the gate metal 110-1 of the gates 106-1. The filled vias 120-1 may extend through the substrate material 131 and may be part of conductive pathways 133 that also include doped regions of the substrate material 131, as discussed below. The gates 108-1 may extend away from the fins 104, and filled vias 122-1 may contact the gate metal 112-1 of the gates 108-1. Like the filled vias 120-1, the filled vias 122-1 may extend through the substrate material 131 and may be part of conductive pathways 135 that also include doped regions of the substrate material 131, as discussed below. The gates 106-2 may extend away from the fins 104, and filled vias 120-2 may contact the gates 106-2 (and are drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing). In particular, the filled vias 120-2 may extend through the hardmask 116-2 and the hardmask 118-2 to contact the gate metal 110-2 of the gates 106-2. The gates 108-2 may extend away from the fins 104, and filled vias 122-2 may contact the gates 108-2 (also drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing). The filled vias 122-2 may extend through the hardmask 118-2 to contact the gate metal 112-2 of the gates 108-2. [0037] Filled vias 136 may contact the interface material 141 and may thereby make electrical contact with the doped regions 140. In particular, the filled vias 136-1 may extend through the substrate material 131 and make contact with the doped regions 140-1, and the filled vias 136-2 may extend through the insulating material 130 and make contact with the doped regions 140-2. As illustrated in FIG. 2, the filled vias 136-1 may extend through the fin 104 into the doped regions 140- 2 themselves. The quantum dot device 100 may include further filled vias and/or lines (not shown) through the insulating material 130 and/or through the substrate material 131 to make electrical contact to the gates 106-1/108-1 and/or the doped regions 140-1, as desired. The filled vias and lines included in a quantum dot device 100 may include any suitable materials, such as copper, tungsten (deposited, e.g., by CVD), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium). In particular, the filled vias 120/122/136 may be formed of any of these materials. In some embodiments, the filled vias 136-1 may not extend through the substrate material 131, but may instead extend through the insulating material 130 to contact the doped regions 140-1, analogously to the manner in which the filled vias 136-2 extend through the insulating material to contact the doped regions 140-2.

[0038] As illustrated in FIG. 2, in some embodiments, the fins 104 may include recesses 107 that extend at least as far as the barrier layer 154, and may extend into the quantum well layer 152-1. The recesses 107 may be filled with the insulating material 130, and the bottoms of the recesses 107 may be doped to provide the doped regions 140-1. The filled vias 136-1 may extend from the bottoms of the recesses 107 (and in particular, the doped regions 140-1) into the substrate 131 to make conductive contact with the doped lines 137.

[0039] During operation, a bias voltage may be applied to the doped regions 140 (e.g., via the filled vias 136 and the interface material 141) to cause current to flow through the doped regions 140. When the doped regions 140 are doped with an n-type material, this voltage may be positive; when the doped regions 140 are doped with a p-type material, this voltage may be negative. The magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).

[0040] The filled vias 120-1, 122-1, and 136-1 may be electrically isolated from each other by a substrate material 131. The substrate material 131 may be any insulating material that can be doped to form conducting regions, as discussed in further detail below. For example, in some embodiments, the substrate material 131 may be silicon, germanium, or silicon germanium. The filled vias 120-2, 122-2, and 136-2 may be electrically isolated from each other by an insulating material 130. The insulating material 130 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 130 may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. As known in the art of integrated circuit manufacturing, filled vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other. In some embodiments, the filled vias 120/122/136 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some embodiments, filled lines (not shown) included in the quantum dot device 100 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater. The particular arrangement of filled vias shown in FIGS. 1- 3 is simply illustrative, and any electrical routing arrangement may be implemented.

[0041] As noted above, conductive pathways 133, 135, and 139 may extend through the substrate material 131 to route electrical signals to/from the gates 106-1, the gates 108-1, and the doped regions 140-1, respectively. In some embodiments, these conductive pathways 133, 135, and 139 may include filled vias 120-1, 122-1, and 136-1, respectively, and may also include portions of the substrate material 131 that have been doped so as to be conductive. The substrate material 131 may be doped with an n-type or a p-type dopant, depending on the desired carrier, and the doping density may depend on the substrate material 131, the dopant, and the desired conductivity. The conductive pathways 133 may include one or more doped lines 121 and/or one or more doped vias 143. As used herein, a "doped line" may be a conductive region analogous to a filled line (e.g., one that runs parallel to the quantum well layer 152-1), and a "doped via" may be a conductive region analogous to a filled via (e.g., one that runs perpendicular to the quantum well layer 152-1). The conductive pathways 135 may include one or more doped lines 123 and/or one or more doped vias (not shown in FIG. 2). The conductive pathways 139 may include one or more doped lines 137 and/or one or more doped vias (not shown in FIG. 2). In some embodiments, the doped lines included in a quantum dot device 100 may be dimensioned to have similar dimensions (e.g., pitch, cross-sectional areas) as filled lines in the quantum dot device 100, and the doped vias included in a quantum dot device 100 may be dimensioned to have similar dimension (e.g., pitch, diameters) as filled vias in the quantum dot device 100.

[0042] In the embodiment of FIG. 2, the doped lines 121, 123, and 137 are in conductive contact with the filled vias 120-1, 122-1, and 136-1, respectively, and along with other conductive structures (including filled vias, filled lines, doped vias, and/or doped lines) may route electrical pathways from the gates 106-1, gates 108-1, and doped regions 140-1, respectively, to any other desired location in the quantum dot device 100. In some embodiments, one or more of the conductive pathways 133, 135, and 139 may run through the substrate material 131, and then extend into the insulating material 130. For example, FIG. 3 depicts an embodiment in which a filled via 125 is in conductive contact with the doped line 137 to route the conductive pathway 139 into the insulating material 130, a filled via 127 is in conductive contact with the doped line 121 to route the conductive pathway 135 into the insulating material 130, and a filled via 129 is in conductive contact with the doped line 123 to route the conductive pathway 133 into the insulating material 130. The particular elements and arrangements of the conductive pathways 133/135/139 shown in FIGS. 1-3 (and other accompanying drawings) are simply illustrative, and any desired elements and arrangements may be used.

[0043] As discussed above, the structure of the fin 104-1 may be the same as the structure of the fin 104-2; similarly, the construction of gates 106/108 on the fin 104-1 may be the same as the construction of gates 106/108 on the fin 104-2. The gates 106/108 on the fin 104-1 may be mirrored by corresponding gates 106/108 on the parallel fin 104-2. The insulating material 128 may separate the sets of gates 105-1 on the different fins 104-1 and 104-2, and the insulating material 130 may separate the sets of gates 105-2 on the different fins 104-1 and 104-2.

[0044] In some embodiments, the quantum dots 142-2 in a fin 104 may be used as "active" quantum dots in the sense that these quantum dots 142-2 act as qubits and are controlled (e.g., by voltages applied to the gates 106-2/108-2 of the fin 104-1) to perform quantum computations. The quantum dots 142-1 in a fin 104 may be used as "read" quantum dots in the sense that these quantum dots 142-2 may sense the quantum state of the quantum dots 142-2 in the same fin 104 by detecting the electric field generated by the charge in the quantum dots 142-1, and may convert the quantum state of the quantum dots 142-2 into electrical signals that may be detected by the gates 106-1/108-1. Each quantum dot 142-2 in a fin 104 may be read by its corresponding quantum dot 142-1 in the fin 104. Thus, the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation within a single fin, if desired.

[0045] [0036][0045] In some embodiments, the quantum dots 142 in the fin 104-1 may be used as "active" quantum dots in the sense that these quantum dots 142 act as qubits and are controlled (e.g., by voltages applied to the gates 106/108 of the fin 104-1) to perform quantum computations. The quantum dots 142 in the fin 104-2 may be used as "read" quantum dots in the sense that these quantum dots 142 may sense the quantum state of the quantum dots 142 in the fin 104-1 by detecting the electric field generated by the charge in the quantum dots 142 in the fin 104-1, and may convert the quantum state of the quantum dots 142 in the fin 104-1 into electrical signals that may be detected by the gates 106/108 on the fin 104-2. Each quantum dot 142 in the fin 104-1 may be read by its corresponding quantum dot 142 in the fin 104-2. Thus, the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation across two fins 104. [0046] Using doped regions of a substrate to provide conductive pathways for electrical signaling, as disclosed herein, is an approach that may provide advantages in quantum computing devices, but that runs counter to conventional computing wisdom. In particular, in conventional computing devices that operate at room temperature, the conductivity achievable by the doped substrate regions may be lower than that achievable by copper (the conventional conductor). Additionally, materials that may be used for the substrate material 131, such as silicon germanium, may not provide particularly strong electrical isolation at room temperature. However, at the low temperatures in which the quantum dot device 100 may operate, silicon germanium or other suitable substrate materials 131 may be amply resistive. Additionally, since the doped regions may be part of conductive pathways through which only a small number of carriers flow (as appropriate for the quantum dot device 100), the higher conductivity of these pathways relative to copper may result in operationally acceptable losses. Thus, a number of the embodiments disclosed herein represent a strong departure from conventional approaches to computing device design.

[0047] The quantum dot devices 100 disclosed herein may be manufactured using any suitable techniques. FIGS. 4-38 illustrate various example stages in the manufacture of the quantum dot device 100 of FIGS. 1-3, in accordance with various embodiments. Although the particular manufacturing operations discussed below with reference to FIGS. 4-38 are illustrated as manufacturing a particular embodiment of the quantum dot device 100, these operations may be applied to manufacture many different embodiments of the quantum dot device 100, as discussed herein. Any of the elements discussed below with reference to FIGS. 4-38 may take the form of any of the embodiments of those elements discussed above (or otherwise disclosed herein). For ease of illustration, not all elements in each of FIGS. 4-38 are expressly labeled with reference numerals, but reference numerals for each element are included among the drawings of FIGS. 4-38.

[0048] FIG. 4 is a cross-sectional view of an assembly 202 including a portion of substrate material 131. The substrate material 131 may take any of the forms discussed above. In some embodiments, the substrate material 131 may include a semiconductor material (e.g., a semiconductor compound) that has been grown on an underlying material (not shown). For example, the portion of substrate material 131 of the assembly 202 may be silicon germanium grown on a silicon wafer. Examples of the substrate material 131 are discussed in further detail below with reference to FIGS. 39-40. In some embodiments, the substrate material 131 of the assembly 202 may be planarized (e.g., using a chemical mechanical polishing (CMP) technique) after growth to provide a flat surface for further processing.

[0049] FIG. 5 is a cross-sectional view of an assembly 204 subsequent to providing a patterned layer of resist material 201 on the substrate material 131 of the assembly 202 (FIG. 4). The resist material 201 may be any suitable resist for masking off areas of the substrate material 131 for doping, as discussed below with reference to FIG. 6 (e.g., a photoresist). The patterned resist material 201 may include openings 207 that extend down to and expose portions of the substrate material 131. The resist material 201 may be initially provided on the assembly 202 by any suitable technique (e.g., spin-coating or lamination), and may be patterned to form the openings 207 in accordance with any suitable technique (e.g., a photolithography technique).

[0050] FIG. 6 is a cross-sectional view of an assembly 206 subsequent to doping the assembly 204 (FIG. 5) in accordance with the pattern provided by the patterned resist material 201 so that the areas of the substrate material 131 exposed by the openings 207 are doped to a desired depth to form doped lines 121. The dopant used and the doping concentration may take any of the forms discussed above with reference to FIGS. 1-3. In particular, the doping concentration may be great enough that the doped lines 121 achieve a desired conductivity for the carrier of interest.

[0051] FIG. 7 is a cross-sectional view of an assembly 208 subsequent to removing the patterned resist material 201 from the assembly 206 (FIG. 6). The patterned resist material 201 may be removed using any suitable technique (e.g., chemical stripping).

[0052] FIG. 8 is a cross-sectional view of an assembly 210 subsequent to providing additional substrate material 131 on the assembly 208 (FIG. 7). In some embodiments, the additional substrate material 131 may be grown on the assembly 208 (e.g., by epitaxy). The thickness 215 of the additional substrate material 131 may correspond to the desired depth of the doped via 143 that will be subsequently formed (e.g., as discussed below with reference to FIG. 10). In some embodiments, the additional substrate material 131 of the assembly 210 may be planarized after growth to provide a flat surface for further processing.

[0053] FIG. 9 is a cross-sectional view of an assembly 212 subsequent to providing a patterned layer of resist material 203 on the substrate material 131 of the assembly 210 (FIG. 8). The patterned resist material 203 may include openings 209 that extend down to and expose portions of the substrate material 131. The resist material 203, and its patterning, may take any of the forms discussed above with reference to the patterned resist material 201 (FIG. 5).

[0054] FIG. 10 is a cross-sectional view of an assembly 214 subsequent to doping the assembly 212 (FIG. 9) in accordance with the pattern provided by the patterned resist material 203 so that the areas of the substrate material 131 exposed by the openings 209 are doped to a desired depth to form doped vias 143. In some embodiments, the doped vias 143 may extend down to make conductive contact with the doped lines 121, as shown. The dopant used to form the doped vias 143, and the doping concentration, may take any of the forms discussed above with reference to FIGS. 1-3. In particular, the doping concentration may be great enough that the doped vias 143 achieve a desired conductivity for the carrier of interest.

[0055] FIG. 11 is a cross-sectional view of an assembly 216 subsequent to removing the patterned resist material 203 from the assembly 214 (FIG. 10). The patterned resist material 203 may be removed using any suitable technique (e.g., chemical stripping).

[0056] FIG. 12 is a cross-sectional view of an assembly 218 subsequent to providing a patterned layer of resist material 205 disposed on the substrate material 131 of the assembly 216 (FIG. 11). The patterned resist material 205 may include openings 211 that extend down to and expose portions of the substrate material 131. The resist material 205, and its patterning, may take any of the forms discussed above with reference to the patterned resist material 201 (FIG. 5).

[0057] FIG. 13 is a cross-sectional view of an assembly 220 subsequent to doping the assembly 218 (FIG. 12) in accordance with the pattern provided by the patterned resist material 205 so that the areas of the substrate material 131 exposed by the openings 211 are doped to a desired depth to form doped lines 123 and additional doped lines 121. In some embodiments, the additional doped lines 121 may overlap with the doped vias 143 by forming the additional doped lines 121 over substrate material 131 that has already been doped to form the doped vias 143. In other embodiments, additional substrate material 131 (not shown) may be provided on the assembly 218 (FIG. 12), and this additional substrate material 131 may be doped to form the doped lines 123 and the additional doped lines 121 so that the additional doped lines 121 are in conductive contact with the doped vias 143. The doped lines 123 and the additional doped lines 121 of the assembly 220 may be formed in accordance with any of the embodiments discussed above with reference to the doped lines 121 of FIG. 6. As noted above, the particular number and arrangement of doped lines 121/123 and doped vias 143 in the assembly 220 are simply illustrative, and any number of doped lines 121/123 and/or doped vias 143 may be formed using the operations discussed above with reference to some or all of FIGS. 4-13.

[0058] FIG. 14 is a cross-sectional view of an assembly 222 subsequent to removing the patterned resist material 205 and providing additional substrate material 131 on the assembly 220 (FIG. 13). The patterned resist material 205 may be removed using any suitable technique (e.g., chemical stripping). In some embodiments, the additional substrate material 131 may be grown on the assembly 220 (e.g., by epitaxy). The thickness 217 of the additional substrate material 131 may correspond to the desired depth of the filled vias 120-1/122-1 that will be subsequently formed (e.g., as discussed below with reference to FIG. 15). In some embodiments, the additional substrate material 131 of the assembly 222 may be planarized after growth to provide a flat surface for further processing. [0059] FIG. 15 is a cross-sectional view of an assembly 224 subsequent to forming, in the assembly 222 (FIG. 14), filled vias 120-1/122-1 through the substrate material 131 to make conductive contact with the conductive lines 121 and 123, respectively, as shown. The filled vias 120-1/122-1 may be formed using any conventional interconnect technique. For example, the filled vias 120-1/122-1 may be formed by providing and patterning a resist material, etching cavities for the filled vias in accordance with the patterned resist material, filling these cavities with any suitable conductive material (e.g., a superconducting material, as discussed above), then polishing away any excess conductive material, as appropriate. In other embodiments, the filled vias 120-1/122-1 may be formed by laser-drilling cavities, then filling these cavities, as discussed above. Any suitable technique may be used to provide conductive material to form the filled vias 120-1/122-1, such as electroplating, electroless deposition, atomic layer deposition (ALD), or sputtering, for example. In some embodiments, the filled vias 120-1/122-1 may have a tapered shape, as shown. The filled vias 120-1, the doped lines 121, and the doped vias 143 may be part of conductive pathways 133 in conductive contact with the gates 106-1, as discussed below. The filled vias 122-1 and the doped lines 123 may be part of conductive pathways 135 in conductive contact with the gates 108-1, as discussed below.

[0060] FIG. 16 is a cross-sectional view of an assembly 226 subsequent to forming a gate stack 174 on the fins 104 of the assembly 224 (FIG. 15). The gate stack 174 may include the gate metal 110-1 and a hardmask 116-1. The hardmask 116-1 may be formed of an electrically insulating material, such as silicon nitride or carbon-doped nitride.

[0061] FIG. 17 is a cross-sectional view of an assembly 228 subsequent to patterning the hardmask 116-1 of the assembly 226 (FIG. 16). The pattern applied to the hardmask 116-1 may correspond to the locations for the gates 106-1, as discussed below. The hardmask 116-1 may be patterned by applying a resist, patterning the resist using lithography, and then etching the hardmask (using dry etching or any appropriate technique).

[0062] FIG. 18 is a cross-sectional view of an assembly 230 subsequent to etching the assembly 228 (FIG. 17) to remove the gate metal 110-1 that is not protected by the patterned hardmask 116-1 to form the gates 106-1.

[0063] FIG. 19 is a cross-sectional view of an assembly 232 subsequent to providing spacer material 132 on the assembly 230 (FIG. 18). The spacer material 132 may include any of the materials discussed above with reference to the spacers 134-1, for example, and may be deposited using any suitable technique. For example, the spacer material 132 may be a nitride material (e.g., silicon nitride) deposited by sputtering. [0064] FIG. 20 is a cross-sectional view of an assembly 234 subsequent to etching the spacer material 132 of the assembly 232 (FIG. 19), leaving spacers 134-1 formed of the spacer material 132 on the sides of the gates 106-1 (e.g., on the sides of the hardmask 116-1 and the gate metal 110-1). The etching of the spacer material 132 may be an anisotropic etch, etching the spacer material 132 "downward" to remove the spacer material 132 on top of the gates 106-1 and in some of the area between the gates 106, while leaving the spacers 134-1 on the sides of the gates 106-1. In some embodiments, the anisotropic etch may be a dry etch.

[0065] FIG. 21 is a cross-sectional view of an assembly 236 subsequent to providing the gate metal 112-1 on the assembly 234 (FIG. 20). The gate metal 112-1 may fill the areas between adjacent ones of the gates 106-1, and may extend over the tops of the gates 106-1.

[0066] FIG. 22 is a cross-sectional view of an assembly 238 subsequent to planarizing the assembly 236 (FIG. 21) to remove the gate metal 112-1 above the gates 106-1. In some embodiments, the assembly 236 may be planarized using a CMP technique. Some of the remaining gate metal 112-1 may fill the areas between adjacent ones of the gates 106-1, while other portions 150 of the remaining gate metal 112-1 may be located "outside" of the gates 106-1.

[0067] FIG. 23 is a cross-sectional view of an assembly 240 subsequent to providing a hardmask 118-1 on the planarized surface of the assembly 238 (FIG. 22). The hardmask 118-1 may be formed of any of the materials discussed above with reference to the hardmask 116-1, for example.

[0068] FIG. 24 is a cross-sectional view of an assembly 242 subsequent to patterning the hardmask 118-1 of the assembly 240 (FIG. 23). The pattern applied to the hardmask 118-1 may extend over the hardmask 116-1 (and over the gate metal 110-1 of the gates 106-1), as well as over the locations for the gates 108-1 (as illustrated in FIG. 2). The hardmask 118-1 may be non-coplanar with the hardmask 116-1, as illustrated in FIG. 24. The hardmask 118-1 illustrated in FIG. 24 may thus be a common, continuous portion of hardmask 118-1 that extends over all of the hardmask 116-1. The hardmask 118-1 may be patterned using any of the techniques discussed above with reference to the patterning of the hardmask 116-1, for example.

[0069] FIG. 25 is a cross-sectional view of an assembly 244 subsequent to etching the assembly 242 (FIG. 24) to remove the portions 150 of the gate metal 112-1 that are not protected by the patterned hardmask 118-1 to form the gates 108-1, replacing the portions 150 with additional substrate material 131 (e.g., by epitaxial growth on the existing exposed substrate material 131) and polishing back the additional substrate material 131 and the hardmasks 116-1/118-1 to remove the hardmasks 116-1/118-1 (e.g., using a CMP technique).

[0070] FIG. 26 is a cross-sectional view of an assembly 246 subsequent to providing a patterned gate dielectric 114-1 on the assembly 244 (FIG. 25). The patterned gate dielectric 114-1 may be provided by depositing a layer of gate dielectric 114-1 (e.g, by spin coating or lamination), then patterning the gate dielectric 114-1 using any suitable technique (e.g., a photolithography technique using a resist material, or without a resist material if the gate dielectric 114-1 is photoimageable). The patterned gate dielectric 114-1 may extend over the gates 106-1/108-1, and additional substrate material 131 may be grown along the sides of the gate dielectric 114-1 (e.g., as part of the provision of the quantum well stack 146, discussed below).

[0071] FIG. 27 is a cross-sectional view of an assembly 248 subsequent to providing a quantum well stack 146 on the assembly 246 (FIG. 26). The quantum well stack 146 may include a quantum well layer 152-1 and a quantum well layer 152-2 spaced apart by a barrier layer 154. As discussed above, during operation of the quantum dot device 100, a 2DEG may form in each of the quantum well layers 152-1 and 152-2. Various embodiments of the quantum well stack 146 are discussed below with reference to FIGS. 39-40. FIG. 28 is another cross-sectional view of the assembly 248, taken along the section C-C indicated in FIG. 27.

[0072] FIG. 29 is a cross-sectional view of an assembly 250 (taken along the same cross-section as represented in FIG. 28) subsequent to forming fins 104 in the quantum well stack 146 of the assembly 248 (FIGS. 27 and 28). The fins 104 may be formed in the assembly 248 by patterning and then etching the assembly 248, as known in the art. For example, a combination of dry and wet etch chemistry may be used to form the fins 104, and the appropriate chemistry may depend on the materials included in the assembly 248, as known in the art. At least some of the quantum well stack 146 may be included in the fins 104; in particular, the quantum well layers 152-1 and 152-2, and the barrier layer 154, may be included in the fins 104.

[0073] FIG. 30 illustrates a cross-sectional view of an assembly 252 (taken along the same cross- section as represented in FIGS. 28 and 29) subsequent to providing an insulating material 128 to the assembly 250 (FIG. 29) and planarizing the result to remove any insulating material 128 above the fins 104. Any suitable material may be used as the insulating material 128 to electrically insulate the fins 104 from each other. As noted above, in some embodiments, the insulating material 128 may be a dielectric material, such as silicon oxide. The assembly 252 may be planarized using a CMP technique, for example.

[0074] FIG. 31 is a cross-sectional view of an assembly 254 (taken along the cross-section A-A indicated in FIG. 30) subsequent to forming gates 106-2 and 108-2 on the assembly 252 (FIG. 30). The gates 106-2 and 108-2 may include gate metals 110-2 and 112-2, respectively, and a gate dielectric 114-2 may be disposed between the gate metals 110-2/112-2 and the quantum well stack 146. The gates 106-2/108-2 may be formed in accordance with any of the techniques discussed above with reference to the gates 106-2/108-2. In some embodiments, the gate dielectric 114-2 may be deposited on the quantum well stack 146 prior to formation of the rest of the gates 106- 2/108-2, and then the gate dielectric 114-2 "outside" of the gates 106-2/108-2 may be removed using any suitable technique, such as chemical etching or silicon bombardment. In some embodiments, the gate metal 110-2/112-2 and the spacers 134-2 may take the same form as the gate metal 110-1/112-1 and the spacers 134-1, respectively. For example, hardmasks 116-2 and 118-2 may be used to pattern the gates 106-2 and 108-2, as discussed above with reference to the hardmasks 116-1 and 118-1 for the gates 106-1 and 108-1. In some embodiments, the hardmasks 116-2 and 118-2 may remain in the quantum dot device 100, while in other embodiments, the quantum dot device 100 may not include the hardmasks 116-2 and 118-2.

[0075] FIG. 32 is a cross-sectional view of an assembly 256 subsequent to forming recesses 107 in the quantum well stack 146 of the assembly 254 (FIG. 31). The recesses 107 may be formed using any of the fin patterning techniques discussed above with reference to FIG. 29, and as discussed above, may extend down to the barrier layer 154 and may extend down into the quantum well layer 152-1.

[0076] FIG. 33 is a cross-sectional view of an assembly 258 subsequent to doping the quantum well stack 146 of the assembly 256 (FIG. 32) to form doped regions 140-1 at the bottoms of the recesses 107 in the quantum well stack 146, and doped regions 140-2 adjacent to the gates 106-2/108-2. The doped regions 140-1 may be in conductive contact with the quantum well layer 152-1, and the doped regions 140-2 may be in conductive contact with the quantum well layer 152-2. The type of dopant used to form the doped regions 140 may depend on the type of quantum dot desired, as discussed above. In some embodiments, the doping may be performed by ion implantation. For example, when a quantum dot 142 is to be an electron-type quantum dot 142, the doped regions 140 may be formed by ion implantation of phosphorous, arsenic, or another n-type material. When a quantum dot 142 is to be a hole-type quantum dot 142, the doped regions 140 may be formed by ion implantation of boron or another p-type material. An annealing process that activates the dopants and causes them to diffuse farther into the fins 104 may follow the ion implantation process. The depth of the doped regions 140 may take any suitable value; for example, in some embodiments, the doped regions 140 may each have a depth 115 between 500 and 1000

Angstroms.

[0077] The outer spacers 134-2 on the outer gates 106-2 may provide a doping boundary, limiting diffusion of the dopant from the doped regions 140-2 into the area under the gates 106-2/108-2. As shown, the doped regions 140-2 may extend under the adjacent outer spacers 134-2. In some embodiments, the doped regions 140-2 may extend past the outer spacers 134-2 and under the gate metal 110-2 of the outer gates 106-2, may extend only to the boundary between the outer spacers 134-2 and the adjacent gate metal 110-2, or may terminate under the outer spacers 134-2 and not reach the boundary between the outer spacers 134-2 and the adjacent gate metal 110-2. Examples of such embodiments are discussed below with reference to FIGS. 42 and 43. The doping concentration of the doped regions 140 may, in some embodiments, be between 10¹⁷/cm³ and 10²⁰/cm³.

[0078] FIG. 34 is a cross-sectional side view of an assembly 260 subsequent to providing a layer of nickel or other material 147 over the assembly 258 (FIG. 33). The nickel or other material 147 may be deposited on the assembly 258 using any suitable technique (e.g., a plating technique, chemical vapor deposition, or atomic layer deposition).

[0079] FIG. 35 is a cross-sectional side view of an assembly 262 subsequent to annealing the assembly 260 (FIG. 34) to cause the material 147 to interact with the doped regions 140 to form the interface material 141, then removing the unreacted material 147. When the doped regions 140 include silicon and the material 147 includes nickel, for example, the interface material 141 may be nickel silicide. Materials other than nickel may be deposited in the operations discussed above with reference to FIG. 34 in order to form other interface materials 141, including titanium, aluminum, molybdenum, cobalt, tungsten, or platinum, for example. More generally, the interface material 141 of the assembly 262 may include any of the materials discussed herein with reference to the interface material 141.

[0080] FIG. 36 is a cross-sectional view of an assembly 264 subsequent to forming filled vias 136-1 in the assembly 262 (FIG. 35). The filled vias 136-1 may extend from the bottoms of the recesses 107 into the substrate material 131, and may make conductive contact with the doped lines 137. The filled vias 136-1 may be formed using any suitable technique (such as those discussed above with reference to the filled vias 120-1/122-1), and the filled vias 136-1 and the doped lines 137 may be part of a conductive pathway 139 in conductive contact with the quantum well layer 154-1 and the doped region 140-1. As noted above, in some embodiments, the filled vias 136-1 of FIG. 36 may not be included in the quantum dot device 100, and instead, conductive contact to the quantum well layer 152-1 and the doped regions 140-1 may be made by a filled via extending through the insulating material 130 (as discussed below with reference to FIG. 38).

[0081] FIG. 37 is a cross-sectional view of an assembly 266 subsequent to providing an insulating material 130 on the assembly 264 (FIG. 36). The insulating material 130 may take any of the forms discussed above. For example, the insulating material 130 may be a dielectric material, such as silicon oxide. The insulating material 130 may be provided on the assembly 264 using any suitable technique, such as spin coating, chemical vapor deposition (CVD), or plasma-enhanced CVD (PECVD). In some embodiments, the insulating material 130 may be polished back after deposition, and before further processing.

[0082] FIG. 38 is a cross-sectional view of an assembly 268 subsequent to forming, in the assembly 266 (FIG. 37), filled vias 120-2 through the insulating material 130 (and the hardmasks 116-2 and 118-2) to contact the gate metal 110-2 of the gates 106-2, filled vias 122-2 through the insulating material 130 (and the hardmask 118-2) to contact the gate metal 112-2 of the gates 108-2, and filled vias 136-2 through the insulating material 130 to contact the interface material 141-2 of the doped regions 140-2. Further filled vias and/or lines may be formed on the assembly 268 using

conventional interconnect techniques, if desired. The resulting assembly 268 may take the form of the quantum dot device 100 discussed above with reference to FIGS. 1-3. In some embodiments, the assembly 266 may be planarized to remove the hardmasks 116-2 and 118-2, then additional insulating material 130 may be provided on the planarized surface before forming the filled vias 120- 2, 122-2, and 136-2; in such an embodiment, the hardmasks 116-2 and 118-2 would not be present in the quantum dot device 100.

[0083] As noted above, a quantum well stack 146 included in a quantum dot device 100 may take any of a number of forms, several of which are illustrated in FIGS. 39-40.

[0084] FIG. 39 is a cross-sectional view of a quantum well stack 146 including only a quantum well layer 152-1, a barrier layer 154, and a quantum well layer 152-2. In some embodiments, the quantum well layers 152 of FIG. 39 may be formed of intrinsic silicon, and the gate dielectrics 114 may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the silicon oxide. Embodiments in which the quantum well layers 152 of FIG. 39 are formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices 100. In some

embodiments, the quantum well layers 152 of FIG. 39 may be formed of intrinsic germanium, and the gate dielectrics 114 may be formed of germanium oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the germanium oxide. Such embodiments may be particularly advantageous for hole-type quantum dot devices 100. In some embodiments, the quantum well layers 152 may be strained, while in other embodiments, the quantum well layers 152 may not be strained.

[0085] The barrier layer 154 of FIG. 39 may provide a potential barrier between the quantum well layer 152-1 and the quantum well layer 152-2. In some embodiments in which the quantum well layers 152 of FIG. 39 are formed of silicon, the barrier layer 154 may be formed of silicon germanium. The germanium content of this silicon germanium may be 20-80% (e.g., 30%). In some embodiments in which the quantum well layers 152 are formed of germanium, the barrier layer 154 may be formed of silicon germanium (with a germanium content of 20-80% (e.g., 70%)).

[0086] The thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 39 may take any suitable values. For example, in some embodiments, the thickness of the barrier layer 154

(e.g., silicon germanium) may be between 0 and 400 nanometers. In some embodiments, the thickness of the quantum well layers 152 (e.g., silicon or germanium) may be between 5 and 30 nanometers.

[0087] The quantum well stack 146 of FIG. 39 may be disposed on the substrate material 131, as discussed above. In some embodiments, the layers of the quantum well stack 146 of FIG. 39 may be grown on the substrate material 131 (and on each other) by epitaxy. For example, the substrate material 131 may be formed of silicon germanium, the quantum well layer 152-1 may be grown on the substrate material 131, etc.

[0088] FIG. 40 is a cross-sectional view of a quantum well stack 146 including quantum well layers 152-1 and 152-2, a barrier layer 154-2 disposed between the quantum well layers 152-1 and 152-2, and additional barrier layers 154-1 and 154-3. The quantum well stack 146 may be disposed on the substrate material 131 such that the barrier layer 154-1 is disposed between the quantum well layer 152-1 and the substrate material 131. In some embodiments, the substrate material 131 and the barrier layer 154-1 may be formed of the same material (e.g., silicon germanium). For example, the substrate material 131 may be grown as a "buffer" that traps defects that form in this material as it is grown on an underlying material (e.g., a silicon wafer). In some embodiments, the substrate material 131 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 154-1. In particular, the barrier layer 154-1 may be grown under conditions that achieve fewer defects than the substrate material 131. In some embodiments in which the substrate material 131 includes silicon germanium, the silicon germanium of the substrate material 131 may have a germanium content that varies from the underlying material (not shown) to the barrier layer 154-1; for example, the silicon germanium of the substrate material 131 may have a germanium content that varies from zero percent at the underlying material to a nonzero percent (e.g., 30%) at the barrier layer 154-1. The barrier layers 154-1 and 154-3 may provide potential energy barriers around the quantum well layers 152-1 and 152-2, respectively, and the barrier layer 154-3 may take the form of any of the embodiments of the barrier layer 154-1 discussed herein. The barrier layer 154-2 may take the form of any of the embodiments of the barrier layer 154 discussed above with reference to FIG. 39.

[0089] The thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 40 may take any suitable values. For example, in some embodiments, the thickness of the barrier layers 154-1 and 154-3 (e.g., silicon germanium) may be between 0 and 400 nanometers. In some embodiments, the thickness of the quantum well layers 152 (e.g., silicon or germanium) may be between 5 and 30 nanometers (e.g., 10 nanometers). The barrier layer 154-2, like the barrier layer 154-1, may provide a potential energy barrier around the quantum well layer 152, and may take the form of any of the embodiments of the barrier layer 154-1. In some embodiments, the thickness of the barrier layer 154-2 (e.g., silicon germanium) may be between 25 and 75 nanometers (e.g., 32 nanometers).

[0090] As discussed above with reference to FIG. 39, the quantum well layers 152 of FIG. 40 may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in each of the quantum well layers 152. For example, the quantum well layers 152 of FIG. 40 may be formed of silicon, and the barrier layer 154-1 and the substrate material 131 may be formed of silicon germanium. In some such embodiments, the silicon germanium of the substrate material 131 may have a germanium content that varies from the underlying material (not shown) to the barrier layer 154-1; for example, the silicon germanium of the substrate material 131 may have a germanium content that varies from zero percent at the underlying material to a nonzero percent (e.g., 30%) at the barrier layer 154-1. The barrier layer 154-1 may in turn have a germanium content equal to the nonzero percent. In other embodiments, the substrate material 131 may have a germanium content equal to the germanium content of the barrier layer 154-1 but may be thicker than the barrier layer 154-1 so as to absorb the defects that arise during growth.

[0091] In some embodiments, the quantum well layer 152 of FIG. 40 may be formed of germanium, and the substrate material 131 and the barrier layer 154-1 may be formed of silicon germanium. In some such embodiments, the silicon germanium of the substrate material 131 may have a germanium content that varies from the underlying material (not shown) to the barrier layer 154-1; for example, the silicon germanium of the substrate material 131 may have a germanium content that varies from zero percent at the underlying material to a nonzero percent (e.g., 70%) at the barrier layer 154-1. The barrier layer 154-1 may in turn have a germanium content equal to the nonzero percent. In other embodiments, the substrate material 131 may have a germanium content equal to the germanium content of the barrier layer 154-1 but may be thicker than the barrier layer 154-1 so as to absorb the defects that arise during growth.

[0092] Although the fins 104 have been illustrated in many of the preceding figures as substantially rectangular with parallel sidewalls, this is simply for ease of illustration, and the fins 104 may have any suitable shape (e.g., a shape appropriate to the manufacturing processes used to form the fins 104). For example, in some embodiments, the fins 104 may be tapered, narrowing as they extend away from the base 102 (FIG. 29). In some embodiments, the fins 104 may taper by 3-10 nanometers in x-width for every 100 nanometers in z-height (e.g., 5 nanometers in x-width for every 100 nanometers in z-height).

[0093] As noted above, a single fin 104 may include multiple groups of the sets of gates 105-1 and 105-2, spaced apart along the fin 104. FIG. 41 is a cross-sectional view of an example of such a quantum dot device 100 having multiple groups of sets of gates 180 on a single fin 104, in accordance with various embodiments. Each of the groups 180 may include a set of gates 105-1 and a set of gates 105-2 (not labeled in FIG. 41 for ease of illustration) that may take the form of any of the embodiments of the sets of gates 105-1 and 105-2 discussed herein. A doped region 140-1 (and its interface material 141-1) may be disposed between the sets of gates 105-1 of two adjacent groups 180 (labeled in FIG. 41 as groups 180-1 and 180-2), and may provide a common reservoir for the sets of gates 105-1 of both groups 180. In some embodiments, this "common" doped region 140-1 may be electrically contacted by a single filled via 136-1. The particular number of gates 106/108 illustrated in FIG. 41, and the particular number of groups 180, is simply illustrative, and a fin 104 may include any suitable number of gates 106/108 arranged in any suitable number of groups 180.

[0094] As discussed above with reference to FIGS. 2 and 33, the outer spacers 134-2 on the outer gates 106-2 may provide a doping boundary, limiting diffusion of the dopant from the doped regions 140-2 into the area under the gates 106-2/108-2. In some embodiments, the doped regions 140-2 may extend past the outer spacers 134-2 and under the outer gates 106-2. For example, as illustrated in FIG. 42, the doped region 140-2 may extend past the outer spacers 134-2 and under the outer gates 106-2 by a distance 182 between 0 and 10 nanometers. In some embodiments, the doped regions 140-2 may not extend past the outer spacers 134-2 toward the outer gates 106-2, but may instead "terminate" under the outer spacers 134-2. For example, as illustrated in FIG. 43, the doped regions 140-2 may be spaced away from the interface between the outer spacers 134-2 and the outer gates 106-2 by a distance 184 between 0 and 10 nanometers. The interface material 141-2 is omitted from FIGS. 42 and 43 for ease of illustration.

[0095] As noted above, any suitable techniques may be used to manufacture the quantum dot devices 100 disclosed herein. FIG. 44 is a flow diagram of an illustrative method 1000 of manufacturing a quantum dot device, in accordance with various embodiments. Although the operations discussed below with reference to the method 1000 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 1000 may be illustrated with reference to one or more of the embodiments discussed above, but the method 1000 may be used to manufacture any suitable quantum dot device (including any suitable ones of the embodiments disclosed herein).

[0096] At 1002, a substrate material may be provided. For example, the substrate material 131 may be formed on an underlying material (e.g., as discussed above with reference to FIG. 4).

[0097] At 1004, a region of the substrate material may be doped to form a conductive region in the substrate material. For example, the substrate material 131 may be doped to form doped lines 121 and 123, and doped vias 143 (e.g., as discussed above with reference to FIGS. 5-13).

[0098] At 1006, a gate may be formed on a substrate material. The gate may be in conductive contact with the conductive region. For example, gates 106-1 and 108-2 may be formed on the substrate material 131, and may be in conductive contact with one or more of the doped lines 121, doped lines 123, or doped vias 143 (e.g., as discussed above with reference to FIGS. 14-25).

[0099] At 1008, a quantum well stack may be formed on the gate. For example, a quantum well stack 146 may be formed on the gates 106-1 and 108-2 (e.g., as discussed above with reference to FIGS. 27 and 28).

[0100] A number of techniques are disclosed herein for operating a quantum dot device 100. FIGS. 45-46 are flow diagrams of particular illustrative methods 1020 and 1040, respectively, of operating a quantum dot device, in accordance with various embodiments. Although the operations discussed below with reference to the methods 1020 and 1040 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the methods 1020 and 1040 may be illustrated with reference to one or more of the embodiments discussed above, but the methods 1020 and 1040 may be used to operate any suitable quantum dot device (including any suitable ones of the embodiments disclosed herein).

[0101] Turning to the method 1020 of FIG. 45, at 1022, electrical signals may be applied to a first set of gates disposed proximate to a first face of a quantum well stack to cause a first quantum dot to form in the first quantum well layer in the quantum well stack under the first set of gates. The electrical signals to the first set of gates may be applied through conductive pathways that extend through a substrate on which the quantum well stack is disposed, and the conductive pathways may include doped regions of the substrate. For example, electrical signals may be provided to the gates 106-1 and 108-1 of the set of gates 105-1 via the conductive pathways 133 and 135, respectively, to cause one or more quantum dots 142-1 to form in the quantum well layer 152-1. The conductive pathways 133 and 135 may include one or more conductive doped regions (e.g., the doped lines 121, the doped lines 123, and/or the doped vias 143). [0102] At 1024, electrical signals may be applied to a second set of gates disposed proximate to a second face of the quantum well stack to cause a second quantum dot to form in a second quantum well layer in the quantum well stack under the second set of gates. The first and second quantum well layers may be spaced apart by a barrier layer, and the first and second faces of the quantum well stack may be opposing faces of the quantum well stack. For example, electrical signals may be provided to the gates 106-2 and 108-2 of the set of gates 105-2 to cause one or more quantum dots 142-2 to form in the quantum well layer 152-2.

[0103] At 1026, the second quantum dot may sense the quantum state of the first quantum dot. For example, a quantum dot 142-1 in the quantum well layer 152-1 may sense the quantum state of a quantum dot 142-2 in the quantum well layer 152-2.

[0104] Turning to the method 1040 of FIG. 46, at 1042, an electrical signal may be provided to a first gate disposed on a quantum well stack to cause a first quantum dot to form in a quantum well layer in the quantum well stack under the first gate. The electrical signal may be provided to the first gate through a conductive pathway that extends through a substrate on which the quantum well stack is disposed, and the conductive pathway may include a doped region of the substrate. For example, a voltage may be applied to the gate 108-11 disposed on a quantum well stack 146 to cause a first quantum dot 142-1 to form in the quantum well layer 152-1 in the quantum well stack 146 under the gate 108-11. A conductive pathway 135 may be in conductive contact with the gate 108-11, and may include a doped line 123.

[0105] At 1044, an electrical signal may be provided to a second gate disposed on the quantum well stack to cause a second quantum dot to form in the quantum well layer in the quantum well stack under the second gate. For example, a voltage may be applied to the gate 108-12 disposed on the quantum well stack 146 to cause a second quantum dot 142-1 to form in the quantum well layer 152-1 under the gate 108-12.

[0106] At 1046, electrical signal may be provided to a third gate disposed on the quantum well stack to (1) cause a third quantum dot to form in the quantum well layer in the quantum well stack under the third gate or (2) provide a potential barrier between the first quantum dot and the second quantum dot. For example, a voltage may be applied to the gate 106-12 to (1) cause a third quantum dot 142-1 to form in the quantum well layer 152-1 in the quantum well stack 146 (e.g., when the gate 106-12 acts as a "plunger" gate) or (2) provide a potential barrier between the first quantum dot 142-1 (under the gate 108-11) and the second quantum dot 142-1 (under the gate 108- 12) (e.g., when the gate 106-12 acts as a "barrier" gate).

[0107] FIG. 47 is a block diagram of an example quantum computing device 2000 that may include any of the quantum dot devices disclosed herein. A number of components are illustrated in FIG. 47 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the

components illustrated in FIG. 47, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.

[0108] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum dot devices 100 disclosed herein, and may perform data processing by performing operations on the quantum dots that may be generated in the quantum dot devices 100, and monitoring the result of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., by another quantum dot). The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters. [0109] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0110] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0111] The quantum computing device 2000 may include a cooling apparatus 2030. The cooling apparatus 2030 may maintain the quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non- quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0112] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0113] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UM B) project (also referred to as "3GPP2"), etc.). IEEE 1402.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 1402.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless

communications (such as AM or FM radio transmissions).

[0114] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0115] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0116] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0117] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0118] The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M IDI) output).

[0119] The quantum computing device 2000 may include a global positioning system (GPS) device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0120] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0121] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFI D) reader.

[0122] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0123] Although various ones of the embodiments illustrated in the accompanying drawings may include exactly two quantum well layers 152, this is simply for illustrative purposes, and any of the quantum dot devices 100 (or associated methods or devices) discussed herein may include three or more quantum well layers 152, in accordance with the teachings of the present disclosure. Thus, various ones of the quantum dot devices 100 disclosed herein may be regarded as stacked quantum well structures including two or more quantum well layers 152. For example, a double quantum well structure in a quantum dot device 100 may include two or more quantum well layers 152.

[0124] The following paragraphs provide examples of various ones of the embodiments disclosed herein.

[0125] Example 1 is a quantum dot device, including: a substrate; a quantum well stack, including a quantum well layer, disposed on the substrate; and a conductive pathway to the quantum well layer through the substrate, wherein the conductive pathway includes a doped region of the substrate.

[0126] Example 2 may include the subject matter of Example 1, and may further specify that the doped region includes a doped line that is oriented parallel to a plane of the quantum well layer.

[0127] Example 3 may include the subject matter of any of Examples 1-2, and may further specify that the doped region includes a doped via that is oriented perpendicular to a plane of the quantum well layer.

[0128] Example 4 may include the subject matter of any of Examples 1-3, and may further include gates disposed on the quantum well stack such that the quantum well stack is disposed between the substrate and the gates.

[0129] Example 5 may include the subject matter of Example 4, and may further include: an insulating material disposed on the gates; and metal vias extending through the insulating material and in conductive contact with the gates.

[0130] Example 6 may include the subject matter of Example 5, and may further specify that the gates are first gates, and the quantum dot device further includes second gates disposed on the quantum well stack such that the second gates are disposed between the quantum well stack and the substrate.

[0131] Example 7 may include the subject matter of Example 6, and may further include conductive pathways to the second gates through the substrate, wherein the conductive pathways include doped regions of the substrate. [0132] Example 8 may include the subject matter of Example 7, and may further specify that the conductive pathways further include metal portions.

[0133] Example 9 may include the subject matter of any of Examples 1-8, and may further include: gates disposed on the quantum well stack such that the gates are disposed between the quantum well stack and the substrate; and conductive pathways to the gates through the substrate, wherein the conductive pathways include doped regions of the substrate.

[0134] Example 10 may include the subject matter of any of Examples 1-9, and may further specify that the quantum well layer is a first quantum well layer, the quantum well stack further includes a second quantum well layer spaced apart from the first quantum well layer by a barrier layer, and the first quantum well layer is disposed between the substrate and the second quantum well layer.

[0135] Example 11 may include the subject matter of Example 10, and may further specify that the conductive pathway includes a metal via disposed in the substrate.

[0136] Example 12 may include the subject matter of any of Examples 10-11, and may further include gates disposed on the quantum well stack such that the second quantum well layer is disposed between the gates and the first quantum well layer.

[0137] Example 13 may include the subject matter of Example 12, and may further include: an insulating material disposed on the gates; and metal vias extending through the insulating material and in conductive contact with the gates.

[0138] Example 14 may include the subject matter of any of Examples 12-13, and may further specify that the gates are first gates, and the quantum dot device further includes second gates disposed on the quantum well stack such that the second gates are disposed between the first quantum well layer and the substrate.

[0139] Example 15 may include the subject matter of Example 14, and may further include conductive pathways to the second gates through the substrate, wherein the conductive pathways include doped regions of the substrate.

[0140] Example 16 may include the subject matter of any of Examples 14-15, and may further specify that the quantum well stack is a first quantum well stack, and the quantum dot device further includes: a second quantum well stack including first and second quantum well layers, wherein a barrier layer of the second quantum well stack is disposed between the first and second quantum well layers of the second quantum well stack; third gates disposed on the second quantum well stack such that the first quantum well layer of the second quantum well stack is disposed between the barrier layer and the third gates of the second quantum well stack; and fourth gates disposed on the second quantum well stack such that the second quantum well layer of the second quantum well stack is disposed between the barrier layer and the fourth gates of the second quantum well stack.

[0141] Example 17 may include the subject matter of Example 16, and may further specify that the first and third gates are spaced apart by a first insulating material, and the second and fourth gates are spaced apart by a second insulating material.

[0142] Example 18 may include the subject matter of any of Examples 16-17, and may further specify that the first and second quantum well stacks are arranged parallel to one another.

[0143] Example 19 may include the subject matter of any of Examples 10-18, and may further specify that the first and second quantum well layers are formed of silicon, and the barrier layer is formed of silicon germanium.

[0144] Example 20 may include the subject matter of any of Examples 1-19, and may further specify that the substrate is formed of silicon germanium.

[0145] Example 21 is a method of operating a quantum dot device, including: applying electrical signals to a first set of gates disposed proximate to a first face of a quantum well stack to cause a first quantum dot to form in a first quantum well layer in the quantum well stack under the first set of gates, wherein the electrical signals to the first set of gates are applied through conductive pathways that extend through a substrate on which the quantum well stack is disposed, and the conductive pathways include doped regions of the substrate; applying electrical signals to a second set of gates disposed proximate to a second face of the quantum well stack to cause a second quantum dot to form in a second quantum well layer in the quantum well stack under the second set of gates, wherein the first and second quantum well layers are spaced apart by a barrier layer, and the first and second faces of the quantum well stack are opposing faces of the quantum well stack; and sensing a quantum state of the first quantum dot with the second quantum dot.

[0146] Example 22 may include the subject matter of Example 21, and may further specify that sensing the quantum state of the first quantum dot with the second quantum dot comprises sensing a spin state of the first quantum dot with the second quantum dot.

[0147] Example 23 may include the subject matter of any of Examples 21-22, and may further include: applying the electrical signals to the first set of gates to cause a third quantum dot to form in the first quantum well layer; and prior to sensing the quantum state of the first quantum dot with the second quantum dot, allowing the first and third quantum dots to interact.

[0148] Example 24 may include the subject matter of Example 23, and may further specify that allowing the first and third quantum dots to interact comprises applying the electrical signals to the first set of gates to control interaction between the first and third quantum dots. [0149] Example 25 may include the subject matter of any of Examples 21-24, and may further include applying the electrical signals to the first set of gates to cause a third quantum dot to form in the first quantum well layer.

[0150] Example 26 may include the subject matter of Example 25, and may further include applying the electrical signals to the first set of gates to provide a potential barrier between the first quantum dot and the third quantum dot.

[0151] Example 27 is a method of manufacturing a quantum dot device, including: providing a substrate material; doping a region of the substrate material to form a conductive region in the substrate material; forming a gate on the substrate material, wherein the gate is in conductive contact with the conductive region; and forming a quantum well stack on the gate.

[0152] Example 28 may include the subject matter of Example 27, and may further specify that the quantum well stack includes first and second quantum well layers spaced apart by a barrier layer, and the first quantum well layer is disposed between the gate and the second quantum well layer.

[0153] Example 29 may include the subject matter of Example 28, and may further include forming an additional gate above the quantum well stack such that the second quantum well layer is disposed between the additional gate and the first quantum well layer.

[0154] Example 30 may include the subject matter of Example 29, and may further include:

providing an insulating material on the additional gate; and forming a filled via through the insulating material to make conductive contact with the additional gate.

[0155] Example 31 may include the subject matter of any of Examples 27-30, and may further include, after forming the quantum well stack, removing at least some of the quantum well stack to form fins.

[0156] Example 32 may include the subject matter of any of Examples 27-31, and may further include, after doping the region of the substrate material and before forming the gate, providing a metal via in the substrate material, wherein the metal via is in conductive contact with the conductive region, wherein forming the gate includes forming the gate in conductive contact with the metal via.

[0157] Example 33 may include the subject matter of any of Examples 27-32, and may further specify that providing the quantum well stack on the gate comprises forming the quantum well stack by epitaxy.

[0158] Example 34 is a quantum computing device, including: a quantum processing device, wherein the quantum processing device includes a quantum well stack including an active quantum well layer and a read quantum well layer spaced apart by a barrier layer, first gates to control formation of quantum dots in the active quantum well layer, second gates to control formation of quantum dots in the read quantum well layer, and conductive pathways to the first gates that include doped regions of a substrate material; a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first gates and the second gates; and memory device to store data generated by the read quantum well layer during operation of the quantum processing device.

[0159] Example 35 may include the subject matter of Example 34, and may further include a coolin apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

[0160] Example 36 may include the subject matter of Example 35, and may further specify that the cooling apparatus includes a dilution refrigerator.

[0161] Example 37 may include the subject matter of Example 35, and may further specify that the cooling apparatus includes a liquid helium refrigerator.

[0162] Example 38 may include the subject matter of any of Examples 34-37, and may further specify that the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[0163] Example 39 may include the subject matter of any of Examples 34-38, and may further specify that the substrate material includes silicon germanium.

Claims

Claims:

1. A quantum dot device, comprising:

a substrate;

a quantum well stack, including a quantum well layer, disposed on the substrate; and

a conductive pathway to the quantum well layer through the substrate, wherein the conductive pathway includes a doped region of the substrate.

2. The quantum dot device of claim 1, wherein the doped region includes a doped line that is oriented parallel to a plane of the quantum well layer.

3. The quantum dot device of claim 1, wherein the doped region includes a doped via that is oriented perpendicular to a plane of the quantum well layer.

4. The quantum dot device of claim 1, further comprising:

gates disposed on the quantum well stack such that the quantum well stack is disposed between the substrate and the gates.

5. The quantum dot device of claim 4, further comprising:

an insulating material disposed on the gates; and

metal vias extending through the insulating material and in conductive contact with the gates.

6. The quantum dot device of claim 5, wherein the gates are first gates, and the quantum dot device further includes:

second gates disposed on the quantum well stack such that the second gates are disposed between the quantum well stack and the substrate.

7. The quantum dot device of claim 6, further comprising:

conductive pathways to the second gates through the substrate, wherein the conductive pathways include doped regions of the substrate.

8. The quantum dot device of claim 7, wherein the conductive pathways further include metal portions.

9. The quantum dot device of any of claims 1-8, wherein the quantum well layer is a first quantum well layer, the quantum well stack further includes a second quantum well layer spaced apart from the first quantum well layer by a barrier layer, and the first quantum well layer is disposed between the substrate and the second quantum well layer.

10. The quantum dot device of claim 9, wherein the conductive pathway includes a metal via disposed in the substrate.

11. The quantum dot device of claim 9, further comprising:

gates disposed on the quantum well stack such that the second quantum well layer is disposed between the gates and the first quantum well layer.

12. The quantum dot device of claim 11, further comprising:

an insulating material disposed on the gates; and

13. The quantum dot device of claim 11, wherein the gates are first gates, and the quantum dot device further includes:

second gates disposed on the quantum well stack such that the second gates are disposed between the first quantum well layer and the substrate.

14. The quantum dot device of any of claims 1-8, wherein the substrate is formed of silicon germanium.

15. A method of operating a quantum dot device, comprising:

applying electrical signals to a first set of gates disposed proximate to a first face of a quantum well stack to cause a first quantum dot to form in a first quantum well layer in the quantum well stack under the first set of gates, wherein the electrical signals to the first set of gates are applied through conductive pathways that extend through a substrate on which the quantum well stack is disposed, and the conductive pathways include doped regions of the substrate;

applying electrical signals to a second set of gates disposed proximate to a second face of the quantum well stack to cause a second quantum dot to form in a second quantum well layer in the quantum well stack under the second set of gates, wherein the first and second quantum well layers are spaced apart by a barrier layer, and the first and second faces of the quantum well stack are opposing faces of the quantum well stack; and

sensing a quantum state of the first quantum dot with the second quantum dot.

16. The method of claim 15, wherein sensing the quantum state of the first quantum dot with the second quantum dot comprises sensing a spin state of the first quantum dot with the second quantum dot.

17. The method of any of claims 15-16, further comprising:

applying the electrical signals to the first set of gates to cause a third quantum dot to form in the first quantum well layer; and

prior to sensing the quantum state of the first quantum dot with the second quantum dot, allowing the first and third quantum dots to interact.

18. A method of manufacturing a quantum dot device, comprising:

providing a substrate material;

doping a region of the substrate material to form a conductive region in the substrate material; forming a gate on the substrate material, wherein the gate is in conductive contact with the conductive region; and forming a quantum well stack on the gate.

19. The method of claim 18, wherein the quantum well stack includes first and second quantum well layers spaced apart by a barrier layer, and the first quantum well layer is disposed between the gate and the second quantum well layer.

20. The method of claim 19, further comprising:

forming an additional gate above the quantum well stack such that the second quantum well layer is disposed between the additional gate and the first quantum well layer.

21. The method of any of claims 18-20, further comprising:

after forming the quantum well stack, removing at least some of the quantum well stack to form fins.

22. The method of any of claims 18-20, wherein providing the quantum well stack on the gate comprises forming the quantum well stack by epitaxy.

23. A quantum computing device, comprising:

a quantum processing device, wherein the quantum processing device includes a quantum well stack including an active quantum well layer and a read quantum well layer spaced apart by a barrier layer, first gates to control formation of quantum dots in the active quantum well layer, second gates to control formation of quantum dots in the read quantum well layer, and conductive pathways to the first gates that include doped regions of a substrate material;

a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first gates and the second gates; and

a memory device to store data generated by the read quantum well layer during operation of the quantum processing device.

24. The quantum computing device of claim 23, wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

25. The quantum computing device of any of claims 23-24, wherein the substrate material includes silicon germanium.