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WO2017205015A1 - Wrap around gate field effect transistor (wagfet) - Google Patents

Wrap around gate field effect transistor (wagfet) Download PDF

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Publication number
WO2017205015A1
WO2017205015A1 PCT/US2017/030765 US2017030765W WO2017205015A1 WO 2017205015 A1 WO2017205015 A1 WO 2017205015A1 US 2017030765 W US2017030765 W US 2017030765W WO 2017205015 A1 WO2017205015 A1 WO 2017205015A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
castellation
heavily doped
structures
substrate
Prior art date
Application number
PCT/US2017/030765
Other languages
French (fr)
Inventor
Steven J. SARKOZY
Yaochung Chen
Richard Lai
Original Assignee
Northrop Grumman Systems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northrop Grumman Systems Corporation filed Critical Northrop Grumman Systems Corporation
Priority to JP2018557114A priority Critical patent/JP6949876B2/en
Publication of WO2017205015A1 publication Critical patent/WO2017205015A1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates

Definitions

  • This invention relates generally to a wrap around gate field effect transistor (WAGFET) and, more particularly, to a WAGFET that includes a plurality of three-dimensional castellation structures each having one or more channels layers deposited on a heavily doped layer, where gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer so as to modulate the channel layer from all directions.
  • WAGFET wrap around gate field effect transistor
  • FET Field-effect transistors
  • a typical FET will include various semiconductor layers, such as silicon, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), indium phosphide (InP), etc.
  • the semiconductor layers are doped with various impurities, such as boron, to increase the population of carriers in the layer, where the higher the doping level of the layer the greater the conductivity of the particular semiconductor material.
  • An FET will also include a source terminal, a drain terminal and a gate terminal, where one or more of the semiconductor layers is designated a channel layer and is in a electrical contact with the source and drain terminals.
  • An electrical potential provided to the source terminal allows electrical carriers, either N-type or P-type, to flow through the channel layer to the drain terminal.
  • An electric signal applied to the gate terminal creates an electrical field that modulates the carriers in the channel layer, where a small change in the gate voltage can cause a large variation in the population of carriers in the channel layer to change the current flow from the source terminal to the drain terminal.
  • Figure 1 is an isometric view of a wrap-around field effect transistor (WAGNET);
  • Figure 2 is an isometric view of the WAGFET shown in figure 1 with a gate terminal removed;
  • Figure 3 is a cut-away, cross-sectional profile view of the WAGFET shown in figure 1 through line 3-3.
  • FIG 1 is an isometric view of a WAGFET 10 that provides modulation of one or more channel layers as will be described in detail below.
  • the WAGFET 10 includes a substrate 12 that is made of any suitable material, for example, SiC, Sapphire, GaN, AIN, Si, GaAs, etc.
  • the substrate 12 is a GaAs substrate.
  • a number of semiconductor layers are then grown on the substrate 12 as epitaxial layers to a desired layer thickness for the particular FET design.
  • a buffer layer 14 is grown on the substrate 12 and an InGaAs barrier layer 16 is grown on the buffer layer 14.
  • a heavily doped gate layer 18 is grown on the barrier layer 16, and is a pseudo-conductive layer that provides a modulation signal to a channel layer, as will be described in detail below.
  • the gate layer 18 can be any suitable semiconductor material, such as GaAs in this non-limiting example, having any suitable thickness, and being doped with any suitable impurity or dopant that provides a high number of N-type or P-type carriers. Suitable and well known patterning and metal deposition steps are employed to deposit a source terminal 24, a drain terminal 26 and a gate terminal 28 on the gate layer 18, where the gate terminal 28 includes a top portion 30 and side portions 32 for reasons that will become apparent from the discussion below.
  • FIG 2 is an isometric view of the WAGFET 10 with the gate terminal 28 removed showing a plurality of gate castellation structures 36.
  • Figure 3 is a cut-away cross-sectional view of the WAGFET 10 through line 3-3 of figure 1 .
  • the WAGFET 10 includes two of the castellation structures 36.
  • such a castellated FET of the type described herein would include many of the castellation structures 36 forming a castellated gate.
  • Each castellation structure 36 includes two channel layers, namely, an upper channel layer 38 and a lower channel layer 40, separated by a semiconductor spacer layer 42, where the channel layers 38 and 40 may be quantum well structures, for example, alternating layers of GaAs and AIAs.
  • the castellation structures 36 include the two channel layers 38 and 40, this is by way of a non-limiting example in that the castellated structures 36 may only employ a single channel layer, or more than two channel layers.
  • a second semiconductor spacer layer 44 is provided between the lower channel layer 40 and the gate layer 18.
  • a semiconductor cap layer 46 is grown on the upper channel layer 38 and insulates the upper channel layer 38 from the gate terminal 28.
  • the spacer layers 42 and 44 and the cap layer 46 can be made of any suitable semiconductor material and have any suitable thickness for the purposes described herein.
  • the side portion 32 of the gate terminal 28 encloses sides of the castellation structures 36 and is in electrical contact with the channel layers 38 and 40.
  • the gate terminal 28 is formed on top of each of the castellation structures 36 and around the sides of each of the castellation structures 36 so that a voltage potential from the gate terminal 28 is provided to sides and the top of the channel layers 38 and 40. Further, the gate terminal 28 is in electrical contact with the gate layer 18 so that the gate layer 18 is at the same potential as the terminal 28, which causes a current flow therethrough that generates an electric field applied to a bottom of the channel layers 38 and 40.
  • the field effect from the upper, lateral and lower surfaces of the castellation structures 36 provides a more uniform channel flow in each of the channel layers 36 and 40 in each of the castellation structures 36.
  • applying a modulation signal to all sides of the channel layers 38 and 40 provides a more uniform modulation of the electric field, which allows the WAGFET 10 to operate with higher linearity to amplify signals with different strengths.
  • the modulating signals from the gate terminal 28 and the heavily doped gate layer 18 operate to populate the channel layers 38 and 40 in a uniform manner so that the performance of the channel layers 38 and 40 is improved. In this manner, the gate layer 18 can be grown on the base layers in the same manner as the castellation structures 36, where the gate terminal 28 is then deposited on top of the castellation structures 36, and where the gate layer 18 will ultimately act as a suitable conductor.

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nanotechnology (AREA)

Abstract

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.

Description

WRAP AROUND GATE FIELD EFFECT TRANSISTOR (WAGFET)
BACKGROUND
Field
[0001] This invention relates generally to a wrap around gate field effect transistor (WAGFET) and, more particularly, to a WAGFET that includes a plurality of three-dimensional castellation structures each having one or more channels layers deposited on a heavily doped layer, where gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer so as to modulate the channel layer from all directions.
Discussion
[0002] Field-effect transistors (FET) are well known in the transistor art, and come in a variety of well known types, such a HEMT, MOSFET, MISFET, FinFET, etc., and can be integrated as horizontal devices or vertical devices. A typical FET will include various semiconductor layers, such as silicon, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), indium phosphide (InP), etc. Sometimes the semiconductor layers are doped with various impurities, such as boron, to increase the population of carriers in the layer, where the higher the doping level of the layer the greater the conductivity of the particular semiconductor material. An FET will also include a source terminal, a drain terminal and a gate terminal, where one or more of the semiconductor layers is designated a channel layer and is in a electrical contact with the source and drain terminals. An electrical potential provided to the source terminal allows electrical carriers, either N-type or P-type, to flow through the channel layer to the drain terminal. An electric signal applied to the gate terminal creates an electrical field that modulates the carriers in the channel layer, where a small change in the gate voltage can cause a large variation in the population of carriers in the channel layer to change the current flow from the source terminal to the drain terminal.
[0003] It is known in the art to provide an FET that includes spaced apart castellation structures including one or more channel layers all deposited on a common base structure. In these types of castellated FETs, a common gate metal is deposited on the base structure so that it encloses all of the castellation structures, particularly tops of the castellation structures and sides of the castellation structures. In this type of configuration, the electric field generated by the gate terminal to modulate the channel layer or layers is applied to not only the top of the channel layer, but also to the sides of the channel layer, which improves the amplification of the current flow.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Figure 1 is an isometric view of a wrap-around field effect transistor (WAGNET);
[0005] Figure 2 is an isometric view of the WAGFET shown in figure 1 with a gate terminal removed; and
[0006] Figure 3 is a cut-away, cross-sectional profile view of the WAGFET shown in figure 1 through line 3-3.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0007] The following discussion of the embodiments of the invention is directed to a WAGFET including a plurality of castellation structures and a heavily doped gate layer, where gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer so as to modulate the channel layer from all directions, where the discussion is merely exemplary in nature, and is in no way intended to limit the invention or its applications or uses.
[0008] Figure 1 is an isometric view of a WAGFET 10 that provides modulation of one or more channel layers as will be described in detail below. The WAGFET 10 includes a substrate 12 that is made of any suitable material, for example, SiC, Sapphire, GaN, AIN, Si, GaAs, etc. In this non-limiting example, the substrate 12 is a GaAs substrate. A number of semiconductor layers are then grown on the substrate 12 as epitaxial layers to a desired layer thickness for the particular FET design. For example, in this non-limiting embodiment, a buffer layer 14 is grown on the substrate 12 and an InGaAs barrier layer 16 is grown on the buffer layer 14. A heavily doped gate layer 18 is grown on the barrier layer 16, and is a pseudo-conductive layer that provides a modulation signal to a channel layer, as will be described in detail below. The gate layer 18 can be any suitable semiconductor material, such as GaAs in this non-limiting example, having any suitable thickness, and being doped with any suitable impurity or dopant that provides a high number of N-type or P-type carriers. Suitable and well known patterning and metal deposition steps are employed to deposit a source terminal 24, a drain terminal 26 and a gate terminal 28 on the gate layer 18, where the gate terminal 28 includes a top portion 30 and side portions 32 for reasons that will become apparent from the discussion below.
[0009] Figure 2 is an isometric view of the WAGFET 10 with the gate terminal 28 removed showing a plurality of gate castellation structures 36. Figure 3 is a cut-away cross-sectional view of the WAGFET 10 through line 3-3 of figure 1 . In this embodiment, the WAGFET 10 includes two of the castellation structures 36. However, as would be well understood by those skilled in the art, such a castellated FET of the type described herein would include many of the castellation structures 36 forming a castellated gate. Each castellation structure 36 includes two channel layers, namely, an upper channel layer 38 and a lower channel layer 40, separated by a semiconductor spacer layer 42, where the channel layers 38 and 40 may be quantum well structures, for example, alternating layers of GaAs and AIAs. Although the castellation structures 36 include the two channel layers 38 and 40, this is by way of a non-limiting example in that the castellated structures 36 may only employ a single channel layer, or more than two channel layers. Further, a second semiconductor spacer layer 44 is provided between the lower channel layer 40 and the gate layer 18. A semiconductor cap layer 46 is grown on the upper channel layer 38 and insulates the upper channel layer 38 from the gate terminal 28. The spacer layers 42 and 44 and the cap layer 46 can be made of any suitable semiconductor material and have any suitable thickness for the purposes described herein. The side portion 32 of the gate terminal 28 encloses sides of the castellation structures 36 and is in electrical contact with the channel layers 38 and 40. [0010] As is apparent, in this configuration, the gate terminal 28 is formed on top of each of the castellation structures 36 and around the sides of each of the castellation structures 36 so that a voltage potential from the gate terminal 28 is provided to sides and the top of the channel layers 38 and 40. Further, the gate terminal 28 is in electrical contact with the gate layer 18 so that the gate layer 18 is at the same potential as the terminal 28, which causes a current flow therethrough that generates an electric field applied to a bottom of the channel layers 38 and 40. The field effect from the upper, lateral and lower surfaces of the castellation structures 36 provides a more uniform channel flow in each of the channel layers 36 and 40 in each of the castellation structures 36. In other words, applying a modulation signal to all sides of the channel layers 38 and 40, provides a more uniform modulation of the electric field, which allows the WAGFET 10 to operate with higher linearity to amplify signals with different strengths. The modulating signals from the gate terminal 28 and the heavily doped gate layer 18 operate to populate the channel layers 38 and 40 in a uniform manner so that the performance of the channel layers 38 and 40 is improved. In this manner, the gate layer 18 can be grown on the base layers in the same manner as the castellation structures 36, where the gate terminal 28 is then deposited on top of the castellation structures 36, and where the gate layer 18 will ultimately act as a suitable conductor.
[0011] The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. One skilled in the art will readily recognize from such discussion and from the accompanying drawings and claims that various changes, modifications and variations can be made therein without departing from the spirit and scope of the invention as defined in the following claims.

Claims

CLAIMS What is Claimed is:
1 . A semiconductor device comprising:
a substrate;
a plurality of semiconductor layers deposited on the substrate; a heavily doped gate layer deposited on the semiconductor layers;
a plurality of castellation structures formed on the heavily doped layer and being spaced apart from each other, each castellation structure including at least one channel layer; and
a gate metal structure formed over the plurality of castellation structures so that gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer, wherein a voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.
2. The semiconductor device according to claim 1 wherein each castellation structure includes two channel layers separated by a spacer layer.
3. The semiconductor device according to claim 1 wherein each castellation structure includes a spacer layer between the at least one channel layer and the heavily doped layer.
4. The semiconductor device according to claim 1 wherein each castellation structure includes a cap layer on top of the at least one channel layer.
5. The semiconductor device according to claim 1 wherein the heavily doped layer is a heavily doped N-type GaAs layer.
6. The semiconductor device according to claim 1 wherein the at least one channel layer in each castellation structure is a quantum well structure.
7. The semiconductor device according to claim 1 wherein the substrate is a GaAs substrate.
8. The semiconductor device according to claim 1 wherein the semiconductor device is a field effect transistor.
9. A field effect transistor (FET) comprising:
a substrate;
a plurality of semiconductor layers deposited on the substrate; a heavily doped gate layer deposited on the semiconductor layers;
a plurality of castellation structures formed on the heavily doped layer and being spaced apart from each other, each castellation structure including an upper channel layer, a lower channel layer, a first spacer layer positioned between the upper and lower channel layers, a second spacer layer positioned between the lower channel layer and the heavily doped gate layer, and a cap layer positioned on top of the upper channel layer; and
a gate metal structure formed over the plurality of castellation structures so that gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer, wherein a voltage potential applied to the gate metal structure modulates the channel layers in each castellation structure from an upper, lower and side direction.
10. The FET according to claim 9 wherein the heavily doped layer is a heavily doped N-type GaAs layer.
1 1 . The FET according to claim 9 wherein the at least one channel layer in each castellation structure is a quantum well structure.
12. The FET according to claim 9 wherein the substrate is a GaAs substrate.
13. A method for fabricating a semiconductor device comprising: providing a substrate;
epitaxially growing a plurality of semiconductor layers deposited on the substrate;
epitaxially growing a heavily doped gate layer on the semiconductor layers;
forming a plurality of castellation structures on the heavily doped layer and being spaced apart from each other, where each castellation structure includes at least one channel layer; and
forming a gate metal structure over the plurality of castellation structures so that gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer, wherein a voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.
14. The method according to claim 13 wherein forming a plurality of castellation structures includes forming castellation structures including two channel layers separated by a spacer layer.
15. The method according to claim 13 wherein forming a plurality of castellation structures includes forming castellation structures including a spacer layer between the at least one channel layer and the heavily doped layer.
16. The method according to claim 13 wherein forming a plurality of castellation structures includes forming castellation structures including a cap layer on top of the at least one channel layer.
17. The method according to claim 13 wherein the heavily doped layer is a heavily doped N-type GaAs layer.
18. The method according to claim 13 wherein forming a plurality of castellation structures includes forming castellation structures where the at least one channel layer is a quantum well structure.
19. The method according to claim 13 wherein providing a substrate substrate includes providing a GaAs substrate.
20. The method according to claim 13 wherein the semiconductor device is a field effect transistor.
PCT/US2017/030765 2016-05-24 2017-05-03 Wrap around gate field effect transistor (wagfet) WO2017205015A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2018557114A JP6949876B2 (en) 2016-05-24 2017-05-03 Methods for Manufacturing Semiconductor Devices, Field Effect Transistors (FETs), and Semiconductor Devices

Applications Claiming Priority (2)

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US15/163,375 US9882000B2 (en) 2016-05-24 2016-05-24 Wrap around gate field effect transistor (WAGFET)
US15/163,375 2016-05-24

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JP (1) JP6949876B2 (en)
TW (1) TWI734783B (en)
WO (1) WO2017205015A1 (en)

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US20170345895A1 (en) 2017-11-30
TW201806150A (en) 2018-02-16
TWI734783B (en) 2021-08-01
JP2019517135A (en) 2019-06-20
US9882000B2 (en) 2018-01-30
JP6949876B2 (en) 2021-10-13

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