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WO2017177486A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2017177486A1
WO2017177486A1 PCT/CN2016/081460 CN2016081460W WO2017177486A1 WO 2017177486 A1 WO2017177486 A1 WO 2017177486A1 CN 2016081460 W CN2016081460 W CN 2016081460W WO 2017177486 A1 WO2017177486 A1 WO 2017177486A1
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WIPO (PCT)
Prior art keywords
signal
gate
common
data
line
Prior art date
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PCT/CN2016/081460
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English (en)
French (fr)
Inventor
徐向阳
Original Assignee
深圳市华星光电技术有限公司
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Priority to US15/101,046 priority Critical patent/US10151957B2/en
Publication of WO2017177486A1 publication Critical patent/WO2017177486A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate and a liquid crystal display panel.
  • the liquid crystal display device is widely used due to its small size, light weight, low power consumption and the like.
  • the liquid crystal display device generally includes a liquid crystal display panel and a backlight module, and the backlight module is used to provide a surface light source for the liquid crystal display panel.
  • the In-Plane Switching (IPS) mode display of the liquid crystal display panel is also referred to as a planar conversion mode, and is a mode in which liquid crystal molecules are caused to respond in the in-plane direction of the substrate by an electric field including a component substantially parallel to the substrate surface. Since IPS liquid crystal display panels have excellent viewing angle characteristics, they are widely used in various display applications.
  • the array substrate in the conventional IPS liquid crystal display panel uses a common electrode (COM) line to provide a driving voltage for the common electrode, and the common electrode line and the gate line are made of the same layer of metal. Due to the opaque nature of the metal, the transmittance of the array substrate is lowered, that is, the aperture ratio of the array substrate is lowered.
  • COM common electrode
  • the present invention provides an array substrate including a plurality of gate line units, and a plurality of data and common signal multiplexing lines, the plurality of gate line units extending in a first direction and spaced apart in a second direction Arranging, each of the gate line units includes a first gate line and a second gate line, the data and common signal multiplexing lines extending toward the second direction and spaced apart along the first direction, Two adjacent data and public
  • the signal multiplexing line and the first gate line and the second gate line of the one gate line unit form a pixel area, and the first switching unit, the second switching unit, the common electrode and the pixel electrode are disposed in the pixel area,
  • the first switching unit includes a first gate, a first source, and a first drain
  • the second switching unit includes a second gate, a second source, and a second drain, the first gate Electrically connecting the first gate line to receive a first gate signal
  • the second gate electrically connecting the second gate line to receive a second gate signal
  • the data and the common multiplexed signal and the first gate signal and the second gate signal cooperate to control the first switch unit to be turned on first to charge the common electrode, and then control the first The two switching units are turned on to charge the pixel electrode.
  • the data and the common multiplexed signal and the first gate signal and the second gate signal cooperate to control the second switch unit to be turned on first to charge the pixel electrode, and then control the first A switching unit is turned on to charge the common electrode.
  • the data and the common multiplexed signal are rectangular wave signals, and the high level duration of the rectangular wave is greater than the low level duration of the rectangular wave in one period of the rectangular wave, a gate signal and the second gate signal are both high level signals and the high level durations of the first gate signal and the second gate signal are equal, the first gate signal a high level duration is greater than a high level duration of one cycle of the data and the common multiplexed signal, and for the same gate line unit, the second gate signal is compared to the first The delay time of the gate signal is equal to the high level duration of the first gate signal.
  • the array substrate further includes a signal switching unit, each signal switching unit is electrically connected to a data and a common signal multiplexing line, and the signal switching unit is configured to receive the common signal and the data signal, and according to the common signal and the Generating the data and the common multiplexed signal, wherein the common signal and the first gate signal and the second gate signal cooperate to control the first switching unit to be turned on for the common Electrode charging, the data signal and the first gate signal and the The second gate signal cooperates to control the second switching unit to turn on to charge the pixel electrode.
  • the data signal is a rectangular wave signal, and the high level duration of the rectangular wave is less than the low level duration of the rectangular wave in one period of the rectangular wave.
  • the array substrate includes a common electrode line, a first signal line, and a second signal line
  • the signal switching unit includes a plurality of switch groups
  • the common electrode line is configured to receive the common signal
  • the first signal The line is configured to receive a first signal
  • the first signal is a square wave signal
  • the second signal line is used to receive a second signal, wherein the second signal is an inverted signal of the first signal
  • the switch group includes a third switch unit and a fourth switch unit
  • the third switch unit includes a third gate, a third source, and a third drain
  • the third gate is electrically connected to the first signal line
  • the third source electrically connects the data and the common signal multiplexing line
  • the third drain is configured to receive the data signal
  • the fourth switching unit includes a fourth gate, a fourth source, and a third a fourth drain electrically connected to the second signal line, the fourth source electrically connecting the common electrode line to receive the common signal, and the fourth drain electrically connecting the first Three drains.
  • the signal switching unit, the common electrode line, the first signal line and the second signal line element are all located in a non-display area on the array substrate.
  • the array substrate includes a data signal generating chip and a common signal generating chip, the data signal generating chip is configured to generate the data signal, and the common signal generating chip is configured to generate the common signal, and the data signal is generated.
  • the chip and the common signal generating chip are located in a non-display area on the array substrate.
  • the present invention also provides a liquid crystal display panel comprising the array substrate according to any of the preceding claims.
  • the array substrate of the present invention includes a plurality of data and common signal multiplexing lines, the data and common signal multiplexing lines receive data and a common multiplexed signal, and the data and the common multiplexed signal and
  • the first gate signal and the second gate signal cooperate to control that the first switch and the second switch in the same pixel region (pixel unit) are not turned on at the same time, thereby, it is seen that the array substrate of the present invention does not need image
  • the common electrode line and the gate line are formed in the same layer. Therefore, the array substrate of the present invention reduces the number of metal lines compared with the prior art, thereby improving the transmittance of the array substrate and improving The aperture ratio of the array substrate.
  • FIG. 1 is a schematic structural view of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a timing diagram of respective signals of the array substrate of FIG. 1.
  • FIG. 3 is a schematic structural view of an array substrate according to another preferred embodiment of the present invention.
  • FIG. 4 is a timing diagram of respective signals of the array substrate of FIG.
  • FIG. 5 is a schematic structural diagram of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an array substrate according to a preferred embodiment of the present invention
  • FIG. 2 is a timing diagram of respective signals of the array substrate of FIG.
  • the array substrate 10 includes a plurality of gate line units 110, and a plurality of data and common signal multiplexing lines 120.
  • the gate line unit 110 extends toward the first direction Dr1 and is spaced apart along the second direction Dr2, and each of the gate line units 110 includes a first gate line 111 and a second gate line 112.
  • the data and common signal multiplexing lines 120 extend toward the second direction Dr2 and are arranged along the first direction Dr1, adjacent two data and common signal multiplexing lines 120 and one gate line unit 110
  • the first gate line 111 and the second gate line 112 form a pixel area.
  • the first switching unit T1, the second switching unit T2, the common electrode 130, and the pixel electrode 140 are disposed in the pixel region.
  • the first switching unit T1 includes a first gate G1, a first source S1, and a first drain D1
  • the second switching unit T2 includes a second gate G2, a second source S2, and a second drain. D2.
  • the first gate G1 is electrically connected to the first gate line 111 to receive a first gate signal
  • the second gate G2 is electrically connected to the second gate line 112 to receive a second gate signal.
  • the first source S1 and the second source S2 are electrically connected to form the same piece of data of the pixel area and
  • the common signal multiplexing line 120 is electrically connected to the common electrode 130, and the second drain D2 is electrically connected to the pixel electrode 140.
  • the pixel electrode 130 is insulated from the common electrode 140.
  • the data and common signal multiplexing line 120 is configured to receive data and a common multiplexed signal, and the data and the common multiplexed signal cooperate with the first gate signal and the second gate signal for controlling A switching unit T1 is not turned on at the same time as the second switching unit T2.
  • the first direction Dr1 is the X-axis direction
  • the second direction Dr2 is the Y-axis direction. It can be understood that, in another embodiment, the first direction Dr1 is a Y-axis direction, and the second direction Dr2 is an X-axis direction.
  • the data and the common multiplexed signal and the first gate signal and the second gate signal cooperate to control the first switch unit T1 to be turned on first to be the public The electrode 130 is charged, and the second switching unit T2 is controlled to be turned on to charge the pixel electrode 140, and the first switching unit T1 is not turned on simultaneously with the second switching unit T2.
  • the data and the common multiplexed signal and the first gate signal and the second gate signal cooperate to control the second switch unit T2 to be turned on first
  • the pixel electrode 140 is charged, and then the first switching unit T1 is turned on to charge the common electrode 130, and the first switching unit T1 and the second switching unit T2 are not turned on at the same time.
  • the timing of each signal of the array substrate 10 will be described below.
  • the adjacent two gate line units 110 are the Nth gate line unit and the N+1th gate line unit, respectively.
  • the first gate signal received by the first gate line 111 of the Nth gate line unit 110 is denoted by G-1, and the second gate received by the second gate line 112 of the Nth gate line unit 110
  • the pole signal is represented by G-2.
  • the first gate signal received by the first gate line 111 of the N+1th gate line unit 110 is represented by G-3, and the second gate line 112 of the (N+1)th gate line unit 110 is received.
  • the second gate signal is indicated by G-4.
  • the first gate signal G-1 of the Nth gate line unit 110 may be generated by one shift register.
  • the trigger signal of the shift register is represented by STV in FIG.
  • the trigger signal is used to trigger the shift register to be turned on.
  • the shift register is a high level trigger device, the trigger signal STV is a high level signal, and the trigger signal is continued.
  • Time is equal to one cycle a duration of a high level of the clock signal, and a rising edge of the trigger signal is a rising edge of the clock signal, and a falling edge of the trigger signal corresponds to a falling edge of the clock signal.
  • signals G-1, G-2, G-3, and G-4 are output.
  • the first gate signal and the second gate signal are both high level signals, and the high level durations of the first gate signal and the second gate signal are equal, and the a high level duration of a gate signal, the second gate signal is equal to a duration of a high level of the trigger signal, and a high level duration of the first gate signal is greater than the data and the common The high level duration in one cycle of the multiplexed signal.
  • the delay time of the second gate signal compared to the first gate signal is equal to the high level duration of the first gate signal.
  • a falling edge of a high level of the first gate signal corresponds to a rising edge of a high level of the second gate signal.
  • the first gate signal phase of the first gate line 111 of the (N+1)th gate line unit 110 The time delayed by the second gate signal of the second gate line 112 in the Nth gate line unit 110 is equal to the high level duration of the first gate signal, where N is a natural number.
  • a falling edge of a high level of the first gate signal of the first gate line 111 of the (N+1)th gate line unit 110 corresponds to the Nth gate line unit 110 A rising edge of a high level of the second gate signal of the second gate line 112.
  • the clock signal of the shift register is represented by CLK in FIG. 2, and the clock signal is a square wave signal.
  • the data and the common multiplexed signal are represented by Com/Data in FIG. 2, and the data and the common multiplexed signal are rectangular wave signals, and the data and the common multiplexed signal are in one cycle of the rectangular wave
  • the high level duration of the rectangular wave is greater than the low level duration of the rectangular wave.
  • a rising edge of the high level of the data and the common multiplexed signal is delayed by a first preset time than a falling edge of the clock signal
  • the data sum The falling edge of the low level of the common multiplexed signal is advanced by a second predetermined time than the rising edge of the low level signal in the same period of the clock signal.
  • the sum of the first preset time and the second preset time is equal to the duration of the low level in one cycle of the data and the common multiplexed signal.
  • the duration of one cycle of the data and the common multiplexed signal is equal to the duration of the low level of the clock signal.
  • the array substrate 10 of the present invention includes a plurality of data and common signal multiplexing lines 120, and the data and common signal multiplexing lines 120 receive data and common multiplexing signals, the data And the common multiplexed signal and the first gate signal and the second gate signal cooperate to control that the first switch T1 and the second switch T2 in the same pixel area (pixel unit) are not turned on at the same time, thereby being visible
  • the common electrode lines and the gate lines fabricated in the same layer are not required in the prior art. Therefore, the array substrate of the present invention reduces the number of metal lines compared to the prior art, thereby improving The light transmittance of the array substrate 10 increases the aperture ratio of the array substrate 10.
  • FIG. 3 is a schematic structural diagram of an array substrate according to another preferred embodiment of the present invention
  • FIG. 4 is a timing diagram of respective signals of the array substrate of FIG.
  • the array substrate 10 further includes a signal switching unit 150.
  • Each of the signal switching units 150 is electrically connected to one data and common signal multiplexing line 120.
  • the signal switching unit 150 is configured to receive a common signal and a data signal, and generate the data and the common multiplexed signal according to the common signal and the data signal.
  • the common signal and the first gate signal and the second gate signal cooperate to control the first switching unit T1 to be turned on to charge the common electrode 130; the data signal and the The first gate signal and the second gate signal cooperate to control the second switching unit T2 to be turned on to charge the pixel electrode 140.
  • the timing of each signal of the array substrate 10 will be described below. Please refer to FIG. 4.
  • the adjacent two gate line units 110 are the Nth gate line unit and the N+1th gate line unit, respectively.
  • the first gate signal received by the first gate line 111 of the Nth gate line unit 110 is denoted by G-1, and the second gate received by the second gate line 112 of the Nth gate line unit 110
  • the pole signal is represented by G-2.
  • the first gate signal received by the first gate line 111 of the N+1th gate line unit 110 is represented by G-3, and the second gate line 112 of the (N+1)th gate line unit 110 is received.
  • the second gate signal is indicated by G-4.
  • the first gate signal G-1 of the Nth gate line unit 110 may be generated by one shift register.
  • the trigger signal of the shift register is represented by STV in FIG.
  • the trigger signal is used to trigger the shift register to be turned on.
  • the shift register is a high level trigger device, the trigger signal STV is a high level signal, and the trigger signal is continued.
  • the time is equal to the duration of the high level of the clock signal in one cycle, and the rising edge of the trigger signal is a rising edge of the clock signal, and the falling edge of the trigger signal corresponds to the falling of the clock signal along.
  • signals G-1, G-2, G-3, and G-4 are output.
  • the first gate signal and the second gate signal are both high level signals, and the high level durations of the first gate signal and the second gate signal are equal, and the a high level duration of a gate signal, the second gate signal is equal to a duration of a high level of the trigger signal, and a high level duration of the first gate signal is greater than the data and the common The high level duration in one cycle of the multiplexed signal.
  • the delay time of the second gate signal compared to the first gate signal is equal to the high level duration of the first gate signal.
  • a falling edge of a high level of the first gate signal corresponds to a rising edge of a high level of the second gate signal.
  • the first gate signal phase of the first gate line 111 of the (N+1)th gate line unit 110 The time delayed by the second gate signal of the second gate line 112 in the Nth gate line unit 110 is equal to the high level duration of the first gate signal, where N is a natural number.
  • a falling edge of a high level of the first gate signal of the first gate line 111 of the (N+1)th gate line unit 110 corresponds to the Nth gate line unit 110 A rising edge of a high level of the second gate signal of the second gate line 112.
  • the clock signal of the shift register is represented by CLK in FIG. 4, and the clock signal is a square wave signal.
  • the data signal is represented by Data
  • the first signal is represented by GO
  • the second signal is represented by GE.
  • the first signal is a square wave signal identical to the clock signal
  • the second signal is an inverted signal of the first signal.
  • the data signal is a rectangular wave signal, and the high level duration of the rectangular wave is less than the low level duration of the rectangular wave in one period of the rectangular wave.
  • a rising edge of a high level of the data line is delayed by a first predetermined threshold time compared to a falling edge of a high level of the clock signal, and a high voltage of the data line
  • the flat falling edge is earlier than the rising edge of the next high level of the clock signal by a second predetermined threshold time
  • the array substrate 10 further includes a common electrode line 160, a first signal line 170, and a second signal line 180.
  • the signal switching unit 150 includes a plurality of switch groups 151.
  • the common electrode line 160 is configured to receive the common signal
  • the first signal line 170 is configured to receive a first signal
  • the first signal is a rectangular wave signal
  • the second signal line 180 is used to receive a second signal signal.
  • the two signals are signals in which the first signal is inverted.
  • the switch group 151 includes a third switch unit T3 and a fourth switch unit T4.
  • the third switching unit T3 includes a third gate G3, a third source S3, and a third drain D3.
  • the third gate G3 is electrically connected to the first signal line 170, the third source S3 is electrically connected to the data and common signal multiplexing line 120, and the third drain D3 is used to receive the data. signal.
  • the fourth switching unit T4 includes a fourth gate G4, a fourth source S4, and a fourth drain D4.
  • the fourth gate D4 is electrically connected to the second signal line 180, the fourth source S4 is electrically connected to the common electrode line 160 to receive the common signal, and the fourth drain D4 is electrically connected
  • the third drain D3 is described.
  • the signal switching unit 150, the common electrode line 160, the first signal line 170, and the second signal line 180 are both located in a non-display area corresponding to the array substrate 10.
  • the array substrate 10 further includes a data signal generating chip 191 and a common signal generating chip 192.
  • the data signal generating chip 191 is configured to generate the data signal, and the respective pins of the data signal generating chip 191 are represented by D1 to D6 in FIG. 3, and the common signal line chip 192 is used to generate the common The signal, the data signal generating chip 191 and the common signal generating chip 192 are located in the non-display area of the array substrate 10.
  • FIG. 5 is a schematic structural diagram of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • the liquid crystal display panel 1 includes the array substrate 10 according to any of the foregoing embodiments, and details are not described herein.

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种阵列基板（10）及液晶显示面板（1）。阵列基板（10）包括多个栅极线单元（110），及多个数据和公共信号复用线（120），每个栅极线单元（110）包括第一、第二栅极线（111，112），相邻的两个数据和公共信号复用线（120）及一个栅极线单元（110）形成像素区域，像素区域内设置第一、第二开关单元（T1，T2）、公共电极（130）及像素电极（140），第一开关单元（T1）包括第一栅极（G1）、第一源极（S1）及第一漏极（D1），第二开关单元（T2）包括第二栅极（G2）、第二源极（S2）及第二漏极（D2），第一栅极（G1）电连接第一栅极线（111），第二栅极（G2）电连接第二栅极线（112），第一、第二源极（S1，S2）电连接同一数据和公共信号复用线（120），第一漏极（D1）电连接公共电极（130），第二漏极（D2）电连接像素电极（140），数据和公共信号复用线（120）接收数据和公共复用信号（Com/Data），数据和公共复用信号（Com/Data）和第一、第二栅极信号（G-1，G-2，G-3，G-4）配合控制第一、第二开关单元（T1，T2）不同时开启。

Description

阵列基板及液晶显示面板
本发明要求2016年4月13日递交的发明名称为“阵列基板及液晶显示面板”的申请号201610231670.3的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其涉及一种阵列基板及液晶显示面板。
背景技术
液晶显示装置由于其具有体积小、质量轻、功耗低等优点而被广泛的应用。液晶显示装置通常包括液晶显示面板及背光模组，背光模组用于为液晶显示面板提供面光源。液晶显示面板的面内切换(In-Plane Switching,IPS)模式显示也称为平面转换模式，是利用包含与基板面大致平行的成分的电场使液晶分子沿基板面内方向响应的模式。由于IPS液晶显示面板具有优异的视角特性，所以被广泛应用于各种显示用途当中。在IPS模式的液晶显示面板中，通过像素电极或公共电极边缘所产生的平行电场以及像素电极与公共电极间产生的纵向电场形成多维电场，使液晶盒内像素电极或公共电极之间、像素电极或公共电极正上方所有取向液晶分子都能够产生旋转转换，从而可提高平面取向系液晶工作效率并增大透光效率。然而传统的IPS液晶显示面板中的阵列基板采用公共电极(COM)线为公共电极提供驱动电压，且公共电极线与栅极线采用同层金属制作。由于金属的不透光的特性，从而导致所阵列基板的透光率降低，即导致阵列基板的开口率下降。
发明内容
本发明提供一种阵列基板，所述阵列基板包括多个栅极线单元，及多个数据和公共信号复用线，所述多个栅极线单元向第一方向延伸且沿第二方向间隔排布，每个栅极线单元包括第一栅极线及第二栅极线，所述数据和公共信号复用线向所述第二方向延伸且沿所述第一方向间隔排布，相邻的两个数据和公共 信号复用线及一个栅极线单元中的第一栅极线及第二栅极线形成一个像素区域，所述像素区域内设置第一开关单元、第二开关单元、公共电极及像素电极，所述第一开关单元包括第一栅极、第一源极及第一漏极，所述第二开关单元包括第二栅极、第二源极及第二漏极，所述第一栅极电连接所述第一栅极线以接收第一栅极信号，所述第二栅极电连接所述第二栅极线以接收第二栅极信号，所述第一源极及所述第二源极均电连接形成所述像素区域的同一条数据和公共信号复用线，所述第一漏极电连接所述公共电极，所述第二漏极电连接所述像素电极，其中，所述像素电极与所述公共电极绝缘设置，所述数据和公共信号复用线用于接收数据和公共复用信号，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元与所述第二开关单元不同时开启。
其中，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元先开启以为所述公共电极充电，再控制所述第二开关单元开启以为所述像素电极充电。
其中，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第二开关单元先开启以为所述像素电极充电，再控制所述第一开关单元开启以为所述公共电极充电。
其中，所述数据和公共复用信号为矩形波信号，在所述矩形波的一个周期内，所述矩形波的高电平持续时间大于所述矩形波的低电平持续时间，所述第一栅极信号及所述第二栅极信号均为高电平信号且所述第一栅极信号及所述第二栅极信号的高电平持续时间相等，所述第一栅极信号的高电平持续时间大于所述数据和公共复用信号的一个周期内的高电平持续时间，且对于同一个栅极线单元而言，所述第二栅极信号相较于所述第一栅极信号的延迟时间等于所述第一栅极信号的高电平持续时间。
其中，所述阵列基板还包括信号切换单元，每个信号切换单元电连接一个数据和公共信号复用线，所述信号切换单元用于接收公共信号和数据信号，并根据所述公共信号和所述数据信号产生所述数据和公共复用信号，其中，所述公共信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元开启以为所述公共电极充电，所述数据信号和所述第一栅极信号及所述 第二栅极信号配合用于控制所述第二开关单元开启以为所述像素电极充电。
其中，所述数据信号为矩形波信号，在所述矩形波的一个周期内，所述矩形波的高电平持续时间小于所述矩形波的低电平持续时间。
其中，所述阵列基板包括公共电极线、第一信号线、第二信号线，所述信号切换单元包括多个开关组，所述公共电极线用于接收所述公共信号，所述第一信号线用于接收第一信号，所述第一信号为方波信号，所述第二信号线用于接收第二信号，其中，所述第二信号为所述第一信号经过反相的信号，所述开关组包括第三开关单元及第四开关单元，所述第三开关单元包括第三栅极、第三源极及第三漏极，所述第三栅极电连接第一信号线，所述第三源极电连接所述数据和公共信号复用线，所述第三漏极用于接收所述数据信号，所述第四开关单元包括第四栅极、第四源极及第四漏极，所述第四栅极电连接所述第二信号线，所述第四源极电连接所述公共电极线以接收所述公共信号，所述第四漏极电连接所述第三漏极。
其中，所述信号切换单、所述公共电极线、所述第一信号线及所述第二信号线元均位于所述阵列基板上的非显示区。
其中，所述阵列基板包括数据信号产生芯片及公共信号产生芯片，所述数据信号产生芯片用于产生所述数据信号，所述公共信号产生芯片用于产生所述公共信号，所述数据信号产生芯片及所述公共信号产生芯片位于所述阵列基板上的非显示区。
本发明还提供了一种液晶显示面板，所述液晶显示面板包括前述任意一项所述的阵列基板。
相较于现有技术，本发明的阵列基板中包括多个数据和公共信号复用线，所述数据和公共信号复用线接收数据和公共复用信号，所述数据和公共复用信号和所述第一栅极信号及第二栅极信号配合以控制同一个像素区域(像素单元)中的第一开关和第二开关不同时开启，由此可见，本发明的阵列基板中不需要像现有技术那边采用同层制作的公共电极线和栅极线，因此，本发明的阵列基板相较于现有技术减小了金属线的数量，从而提高了阵列基板的透光率，提升了阵列基板的开口率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的结构示意图。
图2为图1中阵列基板的各个信号的时序示意图。
图3为本发明另一较佳实施方式的阵列基板的结构示意图。
图4为图3中阵列基板的各个信号的时序示意图。
图5为本发明一较佳实施方式的液晶显示面板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1和图2，图1为本发明一较佳实施方式的阵列基板的结构示意图；图2为图1中阵列基板的各个信号的时序示意图。所述阵列基板10包括多个栅极线单元110，及多个数据和公共信号复用线120。所述栅极线单元110向第一方向Dr1延伸且沿第二方向Dr2间隔排布，每个栅极线单元110包括第一栅极线111和第二栅极线112。所述数据和公共信号复用线120向所述第二方向Dr2延伸且沿所述第一方向Dr1间隔排布，相邻的两个数据和公共信号复用线120及一个栅极线单元110中的第一栅极线111及第二栅极线112形成一个像素区域。所述像素区域内设置第一开关单元T1、第二开关单元T2、公共电极130及像素电极140。所述第一开关单元T1包括第一栅极G1、第一源极S1及第一漏极D1，所述第二开关单元T2包括第二栅极G2、第二源极S2及第二漏极D2。所述第一栅极G1电连接所述第一栅极线111以接收第一栅极信号，所述第二栅极G2电连接所述第二栅极线112以接收第二栅极信号，所述第一源极S1及所述第二源极S2均电连接形成所述像素区域的同一条数据和 公共信号复用线120，所述第一漏极D1电连接所述公共电极130，所述第二漏极D2电连接所述像素电极140。其中，所述像素电极130与所述公共电极140绝缘设置。所述数据和公共信号复用线120用于接收数据和公共复用信号，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合，用于控制第一开关单元T1与所述第二开关单元T2不同时开启。
在本实施方式中，所述第一方向Dr1为X轴方向，所述第二方向Dr2为Y轴方向。可以理解地，在另一实施方式中，所述第一方向Dr1为Y轴方向，所述第二方向Dr2为X轴方向。
具体地，在一实施方式中，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元T1先开启以为所述公共电极130充电，再控制所述第二开关单元T2开启以为所述像素电极140充电，且第一开关单元T1与所述第二开关单元T2不同时开启。
具体地，在另一实施方式中，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第二开关单元T2先开启以为所述像素电极140充电，再控制所述第一开关单元T1开启以为所述公共电极130充电，且第一开关单元T1与所述第二开关单元T2不同时开启。
下面对所述阵列基板10的各个信号的时序进行介绍。为了方便描述，以相邻的两个栅极线单元110为例进行描述。其中，相邻的两个栅极线单元110分别为第N个栅极线单元和第N+1个栅极线单元。第N个栅极线单元110中的第一栅极线111接收的第一栅极信号用G-1表示，第N个栅极线单元110中的第二栅极线112接收的第二栅极信号用G-2表示。第N+1个栅极线单元110中的第一栅极线111接收的第一栅极信号用G-3表示，第N+1个栅极线单元110中的第二栅极线112接收的第二栅极信号用G-4表示。所述第N个栅极线单元110中的第一栅极信号G-1、所述第N个栅极线单元110中的第二栅极信号G-2、所述第N+1个栅极线单元110中的第一栅极信号G-3和所述第N+1个栅极线单元110中的第二栅极信号G-4可以由一个移位寄存器产生。所述移位寄存器的触发信号在图2中用STV来表示。所述触发信号用于触发所述移位寄存器开启，在本实施方式中，所述移位寄存器为高电平触发器件，所述触发信号STV为一高电平信号，所述触发信号的持续时间等于一个周期内 所述时钟信号的高电平的持续时间，且所述触发信号的上升沿对于所述时钟信号的上升沿，所述触发信号的下降沿对应所述时钟信号的下降沿。当所述触发信号触发所述移位寄存器开启之后，输出信号G-1、G-2、G-3和G-4。所述第一栅极信号及所述第二栅极信号均为高电平信号，且所述第一栅极信号及所述第二栅极信号的高电平持续时间相等，且所述第一栅极信号、所述第二栅极信号的高电平持续时间等于所述触发信号的高电平的持续时间，所述第一栅极信号的高电平持续时间大于所述数据和公共复用信号的一个周期内的高电平持续时间。且对于同一个栅极线单元110而言，所述第二栅极信号相较于所述第一栅极信号的延迟时间等于所述第一栅极信号的高电平持续时间。在本实施方式中，所述第一栅极信号的高电平的下降沿对应所述第二栅极信号的高电平的上升沿。对于所有栅极线单元110中的第一栅极线111和第二栅极线112而言，第N+1个栅极线单元110中的第一栅极线111的第一栅极信号相较于第N个栅极线单元110中的第二栅极线112的第二栅极信号延迟的时间等于所述第一栅极信号的高电平持续时间，其中，N是自然数。在本实施方式中，所述第N+1个栅极线单元110中的第一栅极线111的第一栅极信号的高电平的下降沿对应所述第N个栅极线单元110中的第二栅极线112的第二栅极信号的高电平的上升沿。
所述移位寄存器的时钟信号在图2中用CLK表示，所述时钟信号为方波信号。所述数据和公共复用信号在图2中用Com/Data表示，所述数据和公共复用信号为矩形波信号，在所述矩形波的一个周期内，所述数据和公共复用信号的矩形波的高电平持续时间大于所述矩形波的低电平持续时间。且，在所述数据和公共复用信号的一个周期内，所述数据和公共复用信号的高电平的上升沿比所述时钟信号的下降沿延迟第一预设时间，所述数据和公共复用信号的低电平的下降沿比所述时钟信号的同个周期内的低电平信号的上升沿提前第二预设时间。其中，所述第一预设时间与所述第二预设时间的和等于所述数据和公共复用信号的一个周期内的低电平的持续时间。且由图2可见，所述数据和公共复用信号的一个周期的持续时间等于所述时钟信号的低电平的持续时间。
相较于现有技术，本发明的阵列基板10中包括多个数据和公共信号复用线120，所述数据和公共信号复用线120接收数据和公共复用信号，所述数据 和公共复用信号和所述第一栅极信号及第二栅极信号配合以控制同一个像素区域(像素单元)中的第一开关T1和第二开关T2不同时开启，由此可见，本发明的阵列基板10中不需要像现有技术那边采用同层制作的公共电极线和栅极线，因此，本发明的阵列基板相较于现有技术减小了金属线的数量，从而提高了阵列基板10的透光率，提升了阵列基板10的开口率。
请一并参阅图3和图4，图3为本发明另一较佳实施方式的阵列基板的结构示意图；图4为图3中阵列基板的各个信号的时序示意图。在本实施方式中，所述阵列基板10还包括信号切换单元150。每个信号切换单元150电连接一个数据和公共信号复用线120。所述信号切换单元150用于接收公共信号和数据信号，并根据所述公共信号和所述数据信号产生所述数据和公共复用信号。其中，所述公共信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元T1开启，以为所述公共电极130充电；所述数据信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第二开关单元T2开启，以为所述像素电极140充电。
下面对所述阵列基板10的各个信号的时序进行介绍，请参阅图4，为了方便描述，以相邻的两个栅极线单元110为例进行描述。其中，相邻的两个栅极线单元110分别为第N个栅极线单元和第N+1个栅极线单元。第N个栅极线单元110中的第一栅极线111接收的第一栅极信号用G-1表示，第N个栅极线单元110中的第二栅极线112接收的第二栅极信号用G-2表示。第N+1个栅极线单元110中的第一栅极线111接收的第一栅极信号用G-3表示，第N+1个栅极线单元110中的第二栅极线112接收的第二栅极信号用G-4表示。所述第N个栅极线单元110中的第一栅极信号G-1、所述第N个栅极线单元110中的第二栅极信号G-2、所述第N+1个栅极线单元110中的第一栅极信号G-3和所述第N+1个栅极线单元110中的第二栅极信号G-4可以由一个移位寄存器产生。所述移位寄存器的触发信号在图4中用STV来表示。所述触发信号用于触发所述移位寄存器开启，在本实施方式中，所述移位寄存器为高电平触发器件，所述触发信号STV为一高电平信号，所述触发信号的持续时间等于一个周期内所述时钟信号的高电平的持续时间，且所述触发信号的上升沿对于所述时钟信号的上升沿，所述触发信号的下降沿对应所述时钟信号的下降 沿。当所述触发信号触发所述移位寄存器开启之后，输出信号G-1、G-2、G-3和G-4。所述第一栅极信号及所述第二栅极信号均为高电平信号，且所述第一栅极信号及所述第二栅极信号的高电平持续时间相等，且所述第一栅极信号、所述第二栅极信号的高电平持续时间等于所述触发信号的高电平的持续时间，所述第一栅极信号的高电平持续时间大于所述数据和公共复用信号的一个周期内的高电平持续时间。且对于同一个栅极线单元110而言，所述第二栅极信号相较于所述第一栅极信号的延迟时间等于所述第一栅极信号的高电平持续时间。在本实施方式中，所述第一栅极信号的高电平的下降沿对应所述第二栅极信号的高电平的上升沿。
对于所有栅极线单元110中的第一栅极线111和第二栅极线112而言，第N+1个栅极线单元110中的第一栅极线111的第一栅极信号相较于第N个栅极线单元110中的第二栅极线112的第二栅极信号延迟的时间等于所述第一栅极信号的高电平持续时间，其中，N是自然数。在本实施方式中，所述第N+1个栅极线单元110中的第一栅极线111的第一栅极信号的高电平的下降沿对应所述第N个栅极线单元110中的第二栅极线112的第二栅极信号的高电平的上升沿。
所述移位寄存器的时钟信号在图4中用CLK表示，所述时钟信号为方波信号。在图4中，所述数据信号用Data表示，所述第一信号用GO表示，所述第二信号用GE表示。所述第一信号为与所述时钟信号相同的方波信号，所述第二信号为所述第一信号经过反相的信号。所述数据信号为矩形波信号，在所述矩形波的一个周期内，所述矩形波的高电平持续时间小于所述矩形波的低电平持续时间。在所述数据信号的一个周期内，所述数据线的高电平的上升沿相较于所述时钟信号高电平的下降沿延迟第一预设阈值时间，且所述数据线的高电平的下降沿相较于所述时钟信号的下一个高电平的上升沿提早第二预设阈值时间，
所述阵列基板10还包括公共电极线160、第一信号线170及第二信号线180。相应地，所述信号切换单元150包括多个开关组151。所述公共电极线160用于接收所述公共信号，所述第一信号线170用于接收第一信号，所述第一信号为矩形波信号，所述第二信号线180用于接收第二信号。其中，所述第 二信号为所述第一信号经过反相的信号。所述开关组151包括第三开关单元T3和第四开关单元T4。所述第三开关单元T3包括第三栅极G3、第三源极S3及第三漏极D3。所述第三栅极G3电连接所述第一信号线170，所述第三源极S3电连接所述数据和公共信号复用线120，所述第三漏极D3用于接收所述数据信号。所述第四开关单元T4包括第四栅极G4、第四源极S4及第四漏极D4。所述第四栅极D4电连接所述第二信号线180，所述第四源极S4电连接所述公共电极线160，以接收所述公共信号，所述第四漏极D4电连接所述第三漏极D3。
所述信号切换单元150、所述公共电极线160、所述第一信号线170及所述第二信号线180及均位于所述阵列基板10对应的非显示区。
在一实施方式中，所述阵列基板10还包括数据信号产生芯片191及公共信号产生芯片192。所述数据信号产生芯片191用于产生所述数据信号，在图3中以D1～D6表示所述数据信号产生芯片191的各个引脚，所述公共信号产线芯片192用于产生所述公共信号，所述数据信号产生芯片191及所述公共信号产生芯片192位于所述阵列基板10的非显示区。
本发明还提供了一种液晶显示面板1，请参阅图5，图5为本发明一较佳实施方式的液晶显示面板的结构示意图。所述液晶显示面板1包括前述任意一实施方式所述的阵列基板10，在此不再赘述。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种阵列基板，其中，所述阵列基板包括多个栅极线单元，及多个数据和公共信号复用线，所述多个栅极线单元向第一方向延伸且沿第二方向间隔排布，每个栅极线单元包括第一栅极线及第二栅极线，所述数据和公共信号复用线向所述第二方向延伸且沿所述第一方向间隔排布，相邻的两个数据和公共信号复用线及一个栅极线单元中的第一栅极线及第二栅极线形成一个像素区域，所述像素区域内设置第一开关单元、第二开关单元、公共电极及像素电极，所述第一开关单元包括第一栅极、第一源极及第一漏极，所述第二开关单元包括第二栅极、第二源极及第二漏极，所述第一栅极电连接所述第一栅极线以接收第一栅极信号，所述第二栅极电连接所述第二栅极线以接收第二栅极信号，所述第一源极及所述第二源极均电连接形成所述像素区域的同一条数据和公共信号复用线，所述第一漏极电连接所述公共电极，所述第二漏极电连接所述像素电极，其中，所述像素电极与所述公共电极绝缘设置，所述数据和公共信号复用线用于接收数据和公共复用信号，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元与所述第二开关单元不同时开启。
  2. 如权利要求1所述的阵列基板，其中，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元先开启以为所述公共电极充电，再控制所述第二开关单元开启以为所述像素电极充电。
  3. 如权利要求1所述的阵列基板，其中，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第二开关单元先开启以为所述像素电极充电，再控制所述第一开关单元开启以为所述公共电极充电。
  4. 如权利要求1所述的阵列基板，其中，所述数据和公共复用信号为矩形波信号，在所述矩形波的一个周期内，所述矩形波的高电平持续时间大于所述矩形波的低电平持续时间，所述第一栅极信号及所述第二栅极信号均为高电平 信号且所述第一栅极信号及所述第二栅极信号的高电平持续时间相等，所述第一栅极信号的高电平持续时间大于所述数据和公共复用信号的一个周期内的高电平持续时间，且对于同一个栅极线单元而言，所述第二栅极信号相较于所述第一栅极信号的延迟时间等于所述第一栅极信号的高电平持续时间。
  5. 如权利要求4所述的阵列基板，其中，所述阵列基板还包括信号切换单元，每个信号切换单元电连接一个数据和公共信号复用线，所述信号切换单元用于接收公共信号和数据信号，并根据所述公共信号和所述数据信号产生所述数据和公共复用信号，其中，所述公共信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元开启以为所述公共电极充电，所述数据信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第二开关单元开启以为所述像素电极充电。
  6. 如权利要求5所述的阵列基板，其中，所述数据信号为矩形波信号，在所述矩形波的一个周期内，所述矩形波的高电平持续时间小于所述矩形波的低电平持续时间。
  7. 如权利要求5所述的阵列基板，其中，所述阵列基板包括公共电极线、第一信号线、第二信号线，所述信号切换单元包括多个开关组，所述公共电极线用于接收所述公共信号，所述第一信号线用于接收第一信号，所述第一信号为方波信号，所述第二信号线用于接收第二信号，其中，所述第二信号为所述第一信号经过反相的信号，所述开关组包括第三开关单元及第四开关单元，所述第三开关单元包括第三栅极、第三源极及第三漏极，所述第三栅极电连接第一信号线，所述第三源极电连接所述数据和公共信号复用线，所述第三漏极用于接收所述数据信号，所述第四开关单元包括第四栅极、第四源极及第四漏极，所述第四栅极电连接所述第二信号线，所述第四源极电连接所述公共电极线以接收所述公共信号，所述第四漏极电连接所述第三漏极。
  8. 如权利要求7所述的阵列基板，其中，所述信号切换单、所述公共电极 线、所述第一信号线及所述第二信号线元均位于所述阵列基板上的非显示区。
  9. 如权利要求7所述的阵列基板，其中，所述阵列基板包括数据信号产生芯片及公共信号产生芯片，所述数据信号产生芯片用于产生所述数据信号，所述公共信号产生芯片用于产生所述公共信号，所述数据信号产生芯片及所述公共信号产生芯片位于所述阵列基板上的非显示区。
  10. 一种液晶显示面板，其中，所述液晶显示面板包括阵列基板，所述阵列基板包括多个栅极线单元，及多个数据和公共信号复用线，所述多个栅极线单元向第一方向延伸且沿第二方向间隔排布，每个栅极线单元包括第一栅极线及第二栅极线，所述数据和公共信号复用线向所述第二方向延伸且沿所述第一方向间隔排布，相邻的两个数据和公共信号复用线及一个栅极线单元中的第一栅极线及第二栅极线形成一个像素区域，所述像素区域内设置第一开关单元、第二开关单元、公共电极及像素电极，所述第一开关单元包括第一栅极、第一源极及第一漏极，所述第二开关单元包括第二栅极、第二源极及第二漏极，所述第一栅极电连接所述第一栅极线以接收第一栅极信号，所述第二栅极电连接所述第二栅极线以接收第二栅极信号，所述第一源极及所述第二源极均电连接形成所述像素区域的同一条数据和公共信号复用线，所述第一漏极电连接所述公共电极，所述第二漏极电连接所述像素电极，其中，所述像素电极与所述公共电极绝缘设置，所述数据和公共信号复用线用于接收数据和公共复用信号，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元与所述第二开关单元不同时开启。
  11. 如权利要求10所述的液晶显示面板，其中，所述数据和公共复用信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元先开启以为所述公共电极充电，再控制所述第二开关单元开启以为所述像素电极充电。
  12. 如权利要求10所述的液晶显示面板，其中，所述数据和公共复用信号 和所述第一栅极信号及所述第二栅极信号配合用于控制所述第二开关单元先开启以为所述像素电极充电，再控制所述第一开关单元开启以为所述公共电极充电。
  13. 如权利要求10所述的液晶显示面板，其中，所述数据和公共复用信号为矩形波信号，在所述矩形波的一个周期内，所述矩形波的高电平持续时间大于所述矩形波的低电平持续时间，所述第一栅极信号及所述第二栅极信号均为高电平信号且所述第一栅极信号及所述第二栅极信号的高电平持续时间相等，所述第一栅极信号的高电平持续时间大于所述数据和公共复用信号的一个周期内的高电平持续时间，且对于同一个栅极线单元而言，所述第二栅极信号相较于所述第一栅极信号的延迟时间等于所述第一栅极信号的高电平持续时间。
  14. 如权利要求13所述的液晶显示面板，其中，所述阵列基板还包括信号切换单元，每个信号切换单元电连接一个数据和公共信号复用线，所述信号切换单元用于接收公共信号和数据信号，并根据所述公共信号和所述数据信号产生所述数据和公共复用信号，其中，所述公共信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第一开关单元开启以为所述公共电极充电，所述数据信号和所述第一栅极信号及所述第二栅极信号配合用于控制所述第二开关单元开启以为所述像素电极充电。
  15. 如权利要求14所述的液晶显示面板，其中，所述数据信号为矩形波信号，在所述矩形波的一个周期内，所述矩形波的高电平持续时间小于所述矩形波的低电平持续时间。
  16. 如权利要求14所述的液晶显示面板，其中，所述阵列基板包括公共电极线、第一信号线、第二信号线，所述信号切换单元包括多个开关组，所述公共电极线用于接收所述公共信号，所述第一信号线用于接收第一信号，所述第一信号为方波信号，所述第二信号线用于接收第二信号，其中，所述第二信号为所述第一信号经过反相的信号，所述开关组包括第三开关单元及第四开关单 元，所述第三开关单元包括第三栅极、第三源极及第三漏极，所述第三栅极电连接第一信号线，所述第三源极电连接所述数据和公共信号复用线，所述第三漏极用于接收所述数据信号，所述第四开关单元包括第四栅极、第四源极及第四漏极，所述第四栅极电连接所述第二信号线，所述第四源极电连接所述公共电极线以接收所述公共信号，所述第四漏极电连接所述第三漏极。
  17. 如权利要求16所述的液晶显示面板，其中，所述信号切换单、所述公共电极线、所述第一信号线及所述第二信号线元均位于所述阵列基板上的非显示区。
  18. 如权利要求16所述的液晶显示面板，其中，所述阵列基板包括数据信号产生芯片及公共信号产生芯片，所述数据信号产生芯片用于产生所述数据信号，所述公共信号产生芯片用于产生所述公共信号，所述数据信号产生芯片及所述公共信号产生芯片位于所述阵列基板上的非显示区。
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CN107463037A (zh) * 2017-08-17 2017-12-12 深圳市华星光电半导体显示技术有限公司 一种液晶显示面板及装置
CN107331342A (zh) * 2017-08-25 2017-11-07 京东方科技集团股份有限公司 像素结构及其驱动方法、显示装置
CN108873415B (zh) * 2018-07-27 2021-03-23 昆山龙腾光电股份有限公司 液晶显示装置及驱动方法
CN109599405B (zh) * 2019-01-02 2021-04-06 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及相关方法

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