[go: up one dir, main page]

WO2017124673A1 - 阵列基板的制作方法及液晶显示面板 - Google Patents

阵列基板的制作方法及液晶显示面板 Download PDF

Info

Publication number
WO2017124673A1
WO2017124673A1 PCT/CN2016/083058 CN2016083058W WO2017124673A1 WO 2017124673 A1 WO2017124673 A1 WO 2017124673A1 CN 2016083058 W CN2016083058 W CN 2016083058W WO 2017124673 A1 WO2017124673 A1 WO 2017124673A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
light shielding
photoresist
drain
gate
Prior art date
Application number
PCT/CN2016/083058
Other languages
English (en)
French (fr)
Inventor
徐向阳
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/112,195 priority Critical patent/US9947754B1/en
Publication of WO2017124673A1 publication Critical patent/WO2017124673A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate and a liquid crystal display panel.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the liquid crystal display panel comprises a CF (Color Filter) substrate, a Thin Film Transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and a sealant.
  • the composition of the frame generally includes: an Array process (film, yellow light, etching and stripping), a middle cell (Cell process) (a TFT substrate and a CF substrate), and a back mode Assembly process (drive IC and printed circuit board is pressed).
  • the front Array process mainly forms a TFT array substrate to control the movement of the liquid crystal molecules; the middle Cell process mainly adds liquid crystal between the TFT array substrate and the CF substrate; the rear module assembly process is mainly the driving IC press and The integration of the printed circuit board drives the liquid crystal molecules to rotate and display images.
  • the TFT array substrate is provided with a plurality of scan lines and a plurality of data lines, wherein the plurality of scan lines and the plurality of data lines define a plurality of pixel units, and each of the pixel units is provided with a thin film transistor and a pixel electrode, and a gate of the thin film transistor Connected to the corresponding gate line, when the voltage on the gate line reaches the turn-on voltage, the source and drain of the thin film transistor are turned on, thereby inputting the data voltage on the data line to the pixel electrode.
  • the structure of the pixel unit on the conventional TFT array substrate is as shown in FIG.
  • the substrate 100 includes a gate electrode 200 , a gate insulating layer 300 , an active layer 400 , a source 610 , and a drain 620 which are stacked in this order from bottom to top.
  • a-Si amorphous silicon
  • BM black matrix
  • An object of the present invention is to provide a method for fabricating an array substrate, wherein a photoresist layer for etching a semiconductor layer is burned to obtain a light-shielding layer on the semiconductor layer, and the manufacturing method is simple.
  • Another object of the present invention is to provide a liquid crystal display panel.
  • the semiconductor layer of the array substrate is provided with a light shielding layer, so that the black matrix layer of the color filter substrate can be omitted, the panel structure is simple, and the aperture ratio is high.
  • the present invention provides a method for fabricating an array substrate, comprising the following steps:
  • Step 1 providing a first substrate, depositing a gate metal layer on the first substrate, and patterning the gate metal layer to obtain a gate;
  • Step 2 depositing a gate insulating layer on the gate electrode and the first substrate, and depositing an amorphous silicon layer on the gate insulating layer;
  • Step 3 coating a photoresist film on the amorphous silicon layer, providing a gray-scale mask, exposing and developing the photoresist film to obtain a photoresist layer, wherein the photoresist layer comprises a first photoresist layer in the middle, and a second photoresist layer having a thickness smaller than the first photoresist layer and located on both sides of the first photoresist layer;
  • the material of the photoresist film is a positive photoresist having light absorbing characteristics
  • Step 4 using the photoresist layer as a shielding layer, etching the amorphous silicon layer to obtain a semiconductor layer;
  • Step 5 performing a photo-resistance on the photoresist layer, wherein the second photoresist layer is completely removed, and the thickness of the first photoresist layer is reduced to obtain a light-shielding layer, and the size of the obtained light-shielding layer is smaller than that of the semiconductor layer. size;
  • Step 6 performing phosphorus ion implantation on both ends of the semiconductor layer with the light shielding layer as a shielding layer, thereby obtaining an ohmic contact region located at both ends of the semiconductor layer and a channel region not in the ion implantation in the middle;
  • Step 7 depositing a source/drain metal layer on the light shielding layer, the semiconductor layer, and the gate insulating layer, and patterning the source and drain metal layers to obtain a source and a drain, the source And a drain respectively contacting the ohmic contact regions at both ends of the semiconductor layer;
  • Step 8 deposit an insulating protective layer on the source, the drain, the light shielding layer, and the gate insulating layer. And patterning the insulating protective layer to obtain a via hole penetrating the insulating protective layer above the drain;
  • Step 9 Deposit a transparent conductive layer on the insulating protective layer, and pattern the transparent conductive layer to obtain a pixel electrode.
  • the pixel electrode is in contact with the drain through the via.
  • the film thickness of the photoresist film is 1.8-3.0 ⁇ m; in the step 4, after the photoresist layer is burned, the thickness of the light-shielding layer is 0.7-1.7. Mm.
  • the gate metal layer is deposited by physical vapor deposition, and the deposited gate metal layer has a film thickness of
  • the material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper; in step 7, the source and drain metal layers are deposited by physical vapor deposition, and the source and drain electrodes are deposited.
  • the film thickness of the metal layer is The material of the source and drain metal layers is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the gate insulating layer and the amorphous silicon layer are deposited by chemical vapor deposition, and the film thickness of the deposited gate insulating layer is The film thickness of the deposited amorphous silicon layer is
  • the gate insulating layer is a silicon nitride layer; in the step 8, the insulating protective layer is deposited by a chemical vapor deposition method, and the deposited insulating protective layer has a film thickness of The insulating protective layer is a silicon nitride layer.
  • the transparent conductive layer is deposited by physical vapor deposition, and the film thickness of the deposited transparent conductive layer is
  • the material of the transparent conductive layer is one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide.
  • the present invention also provides a liquid crystal display panel, comprising: an array substrate, a color film substrate disposed opposite to the array substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate;
  • the array substrate includes: a first base substrate, a plurality of gate scan lines disposed on the first base substrate, a plurality of data lines, and a plurality of gate scan lines and a plurality of data lines insulated from each other Arranging a plurality of pixel units arranged in an array;
  • the color filter substrate includes: a second substrate; a color filter layer disposed on a surface of the color filter substrate adjacent to the array substrate; a common electrode layer disposed on the color filter layer; a spacer layer on the common electrode layer;
  • Each of the pixel units on the array substrate includes: a gate formed on the first substrate, a gate insulating layer formed on the gate and the first substrate, and formed on the gate a semiconductor layer on the insulating layer, a light shielding layer on the semiconductor layer, a source and a drain formed on the light shielding layer, the semiconductor layer, and the gate insulating layer, and the source and the drain are formed on the source and the drain a light shielding layer, and an insulating protective layer on the gate insulating layer, and a pixel electrode formed on the insulating protective layer;
  • the light shielding layer has the functions of etching blocking and light shielding at the same time, and the size is smaller than the size of the semiconductor layer, and the material is a positive photoresist having light absorption characteristics.
  • the thickness of the light shielding layer is 0.7 to 1.7 ⁇ m.
  • the semiconductor layer includes a channel region in the middle and an ohmic contact region at both ends, the light shielding layer completely covers the channel region, and the ohmic contact region passes through the light shielding layer as a shielding layer to the semiconductor Phosphorus ion implantation is performed at both ends of the layer, and the source and the drain are respectively in contact with the ohmic contact regions at both ends of the semiconductor layer.
  • the insulating protective layer is provided with a through hole penetrating through the insulating protective layer above the drain, and the pixel electrode is in contact with the drain through the through hole.
  • the semiconductor layer is obtained by etching an amorphous silicon layer by using a photoresist layer provided on the amorphous silicon layer as a shielding layer, and the light shielding layer is obtained by burning the photoresist from the photoresist layer.
  • the present invention also provides a liquid crystal display panel, comprising: an array substrate, a color film substrate disposed opposite to the array substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate;
  • the array substrate includes: a first base substrate, a plurality of gate scan lines disposed on the first base substrate, a plurality of data lines, and a plurality of gate scan lines and a plurality of data lines insulated from each other Arranging a plurality of pixel units arranged in an array;
  • the color filter substrate includes: a second substrate; a color filter layer disposed on a surface of the color filter substrate adjacent to the array substrate; a common electrode layer disposed on the color filter layer; a spacer layer on the common electrode layer;
  • Each of the pixel units on the array substrate includes: a gate formed on the first substrate, a gate insulating layer formed on the gate and the first substrate, and formed on the gate a semiconductor layer on the insulating layer, a light shielding layer on the semiconductor layer, a source and a drain formed on the light shielding layer, the semiconductor layer, and the gate insulating layer, and the source and the drain are formed on the source and the drain a light shielding layer, and an insulating protective layer on the gate insulating layer, and a pixel electrode formed on the insulating protective layer;
  • the light shielding layer has the functions of etching blocking and light shielding at the same time, the size is smaller than the size of the semiconductor layer, and the material is a positive photoresist having light absorption characteristics;
  • the thickness of the light shielding layer is 0.7 to 1.7 ⁇ m
  • the semiconductor layer includes a channel region in the middle and an ohmic contact region at both ends, the light shielding layer completely covers the channel region, and the ohmic contact region passes through the light shielding layer as a shielding layer.
  • the two ends of the semiconductor layer are obtained by phosphorus ion implantation, and the source and the drain are respectively in contact with the ohmic contact regions at both ends of the semiconductor layer.
  • the present invention provides a method for fabricating an array substrate and a liquid crystal display panel.
  • the method for fabricating the array substrate of the present invention is characterized in that a light shielding layer is provided on the semiconductor layer, and the light shielding layer is positive in light absorption characteristics.
  • a photoresist the light shielding layer is designed in the same layer as the photoresist layer used for etching the semiconductor layer, and after the semiconductor layer is etched, the light shielding layer is burned to obtain a light shielding layer smaller than the semiconductor layer to block the photoresist layer.
  • the fabrication method is simple and easy, and the effect is good; in the liquid crystal display panel of the present invention, the semiconductor layer is provided with a light shielding layer, and the light shielding layer simultaneously has an etching barrier And the function of shading can replace the black matrix on the color film substrate in the prior art, block the illumination of the semiconductor layer by the light, reduce the leakage current, simplify the panel structure, and increase the aperture ratio.
  • 1 is a schematic structural view of a conventional TFT array substrate
  • FIG. 2 is a schematic flow chart of a method of fabricating an array substrate of the present invention
  • FIG. 3 is a schematic view showing the first step of the method for fabricating the array substrate of the present invention.
  • step 2 is a schematic diagram of step 2 of a method for fabricating an array substrate of the present invention
  • FIG. 5 is a schematic view showing exposure of a photoresist film in step 3 of the method for fabricating an array substrate of the present invention
  • FIG. 6 is a schematic view showing development of a photoresist film after exposure in step 3 of the method for fabricating an array substrate of the present invention
  • step 4 is a schematic diagram of step 4 of the method for fabricating an array substrate of the present invention.
  • step 6 is a schematic diagram of step 6 of the method for fabricating an array substrate of the present invention.
  • step 7 of the method for fabricating an array substrate of the present invention is a schematic diagram of step 7 of the method for fabricating an array substrate of the present invention.
  • step 8 is a schematic diagram of step 8 of the method for fabricating an array substrate of the present invention.
  • step 9 is a schematic diagram of step 9 of the method for fabricating an array substrate of the present invention.
  • Figure 13 is a schematic view showing the structure of a liquid crystal display panel of the present invention.
  • the present invention provides a method for fabricating an array substrate, including the following steps:
  • Step 1 as shown in FIG. 3, providing a first substrate 10 on the first substrate A gate metal layer is deposited on 10, and the gate metal layer is patterned to obtain a gate electrode 20.
  • the gate metal layer is deposited by physical vapor deposition, and the film thickness of the deposited gate metal layer is
  • the material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper; specifically, exposure, development, and wet etching and stripping through the mask plate complete the gate metal Patterning of the layers.
  • Step 2 As shown in FIG. 4, a gate insulating layer 30 is deposited on the gate electrode 20 and the first substrate substrate 10, and an amorphous silicon layer 40' is deposited on the gate insulating layer 30.
  • the gate insulating layer 30 and the amorphous silicon layer 40' are deposited by chemical vapor deposition, and the deposited gate insulating layer 30 has a film thickness of The film thickness of the deposited amorphous silicon layer 40' is
  • the gate insulating layer 31 is a silicon nitride layer.
  • Step 3 As shown in FIG. 5-6, a photoresist film is coated on the amorphous silicon layer 40' to provide a gray-scale mask 90, and the photoresist film is exposed and developed to obtain a position.
  • the photoresist layer 50 on the amorphous silicon layer 40 ′ corresponding to the gate electrode 20 , the photoresist layer 50 includes a first photoresist layer 50 in the middle and a thickness smaller than the first photoresist layer 51 .
  • a second photoresist layer 52 located on both sides of the first photoresist layer 51;
  • the material of the photoresist film is a positive photoresist having light absorbing properties.
  • the film thickness of the photoresist film is 1.8-3.0 ⁇ m
  • the first portion 91 of the gray-scale mask 90 corresponding to the first photoresist layer is opaque
  • the second portion 92 corresponding to the second photoresist layer is semi-transmissive, and the remaining portion is completely transparent.
  • Step 4 as shown in Fig. 7, the amorphous silicon layer 40' is etched by using the photoresist layer 50 as a shielding layer to obtain a semiconductor layer 40.
  • the thickness of the light shielding layer 501 obtained is 0.7 to 1.7 ⁇ m.
  • Step 5 as shown in FIG. 8, the photoresist layer 50 is burned, wherein the second photoresist layer 52 is completely removed, and the thickness of the first photoresist layer 51 is reduced to obtain a light shielding layer 501.
  • the size of the light shielding layer 501 is smaller than the size of the semiconductor layer 40.
  • Step 6 as shown in FIG. 9, phosphorus ion implantation is performed on both ends of the semiconductor layer 40 with the light shielding layer 501 as a shielding layer, thereby obtaining an ohmic contact region 41 located at both ends of the semiconductor layer 40, and a middle portion Ion implanted channel region 42;
  • Step 7 As shown in FIG. 10, a source/drain metal layer is deposited on the light shielding layer 501, the semiconductor layer 40, and the gate insulating layer 30, and the source and drain metal layers are patterned to obtain a source. a pole 61 and a drain 62, wherein the source 61 and the drain 62 are in contact with an ohmic contact region 41 at both ends of the semiconductor layer 40;
  • the source and drain metal layers are deposited by physical vapor deposition, and the film thickness of the deposited source and drain metal layers is
  • the material of the source and drain metal layers is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the patterning process of the source/drain metal layer is completed by exposure, development, and wet etching and stripping through a mask.
  • Step 8 As shown in FIG. 11, an insulating protective layer 70 is deposited on the source 61, the drain 62, the light shielding layer 501, and the gate insulating layer 30, and the insulating protective layer 70 is patterned to obtain a location. A via 71 penetrating the insulating protective layer 70 above the drain 62.
  • the insulating protective layer is deposited by chemical vapor deposition, and the deposited insulating protective layer 70 has a film thickness of
  • the insulating protection layer 70 is a silicon nitride layer.
  • the patterning process of the insulating protective layer 70 is completed by exposure, development, and dry etching and peeling through a mask.
  • Step 9 As shown in FIG. 12, a transparent conductive layer is deposited on the insulating protective layer 70, and the transparent conductive layer is patterned to obtain a pixel electrode 80.
  • the pixel electrode 80 passes through the via 71. Contact with the drain 62.
  • the transparent conductive layer is deposited by physical vapor deposition, and the film thickness of the deposited transparent conductive layer is
  • the material of the transparent conductive layer is one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide.
  • the transparent conductive layer is patterned by exposure, development, and wet etching and peeling.
  • the present invention further provides a liquid crystal display panel comprising: an array substrate 1, a color filter substrate 2, and a liquid crystal layer 3 between the array substrate 1 and the color filter substrate 2;
  • the display substrate 1 includes a first base substrate 10, a plurality of gate scan lines disposed on the first base substrate 10, a plurality of data lines, and a plurality of gate scan lines and a plurality of data lines. a plurality of pixel units arranged in an array of mutually interleaved lines;
  • the color filter substrate 2 includes a second substrate 25, a color filter layer 21 disposed on a surface of the color filter substrate 2 adjacent to the array substrate 1, and a common electrode disposed on the color filter layer 21. a layer 22, and a spacer layer 23 disposed on the common electrode layer 22;
  • Each of the pixel units on the array substrate 1 includes: a gate electrode 20 formed on the first substrate substrate 10, a gate insulating layer 30 formed on the gate electrode 20 and the first substrate substrate 10, a semiconductor layer 40 corresponding to the gate electrode 20 and formed on the gate insulating layer 30, a light shielding layer 501 located on the semiconductor layer 40, and the light shielding layer 501, the semiconductor layer 40, and the gate electrode
  • a source 61 and a drain 62 on the insulating layer 30, an insulating protective layer 70 formed on the source 61, the drain 62, the light shielding layer 501, and the gate insulating layer 30, and the insulating protective layer 70 are formed on the insulating layer 70.
  • the light shielding layer 501 has both an etching stopper and a light shielding function, and has a size smaller than that of the semiconductor layer 40, and the material is a positive photoresist having light absorption characteristics.
  • the semiconductor layer 40 is obtained by etching an amorphous silicon layer by using a photoresist layer as a shielding layer, and the light shielding layer 501 is obtained by burning the photoresist from the photoresist layer.
  • the thickness of the light shielding layer 501 is 0.7 to 1.7 ⁇ m.
  • the semiconductor layer 40 includes a channel region 42 in the middle and an ohmic contact region 41 at both ends, the light shielding layer 501 completely covering the channel region 42, and the ohmic contact region 41 passes through the light shielding layer
  • the layer 501 is a shielding layer obtained by phosphorus ion implantation on both ends of the semiconductor layer 40, and the source 61 and the drain 62 are in contact with the ohmic contact regions 41 at both ends of the semiconductor layer 40, respectively.
  • the insulating protection layer 70 is provided with a through hole 71 corresponding to the drain electrode 62, and the pixel electrode 80 is in contact with the drain electrode 62 through the through hole 71.
  • the present invention provides a method for fabricating an array substrate.
  • the semiconductor layer is provided with a light shielding layer.
  • the light shielding layer is a positive photoresist having light absorption characteristics, and the light shielding layer is formed by etching and forming a semiconductor layer.
  • the photoresist layer used is of the same layer design. After the semiconductor layer is etched, the light-shielding layer of the photoresist layer is obtained by burning the photoresist layer to block the light of the semiconductor layer and reduce the leakage current.
  • the ohmic contact layer at both ends of the semiconductor layer is formed by phosphorus ion implantation, and the manufacturing method is simple and easy, and the effect is good.
  • the semiconductor layer is provided with a light shielding layer, and the light shielding layer has the functions of etching blocking and shielding. It can replace the black matrix on the color film substrate in the prior art, block the illumination of the semiconductor layer by the light, reduce the leakage current, simplify the panel structure, and improve the aperture ratio.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板（1）的制作方法及液晶显示面板，阵列基板（1）的制作方法，半导体层（40）上设置有遮光层（501），该遮光层（501）为一种具有吸光特性的正性光刻胶，该遮光层（501）采用与蚀刻形成半导体层（40）所用的光阻层（50）为同层设计，在半导体层（40）完成蚀刻后，通过对光阻层（50）进行烧光阻得到该尺寸小于半导体层（40）的遮光层（501），以遮挡光线对半导体层（40）的照射，降低漏电流，然后通过磷离子注入形成半导体层（40）两端的欧姆接触层（41），该制作方法简单易行，效果良好；该液晶显示面板，半导体层（40）上设有遮光层（501），该遮光层（501）同时具备蚀刻阻挡和遮光的作用，能够取代现有技术中彩膜基板（2）上的黑色矩阵，遮挡光线对半导体层（40）的照射，降低漏电流，简化面板结构，提升开口率。

Description

阵列基板的制作方法及液晶显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法及液晶显示面板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT阵列基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT阵列基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。TFT阵列基板上设置有数条扫描线和数条数据线，该数条扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅线相连，当栅线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极。传统的TFT阵列基板上像素单元的结构如图1所示，包括自下而上依次层叠设置的基板100、栅极200、栅极绝缘层300、有源层400、源极610、漏极620、绝缘保护层700、及像素电极800。由于薄膜晶体管的有源层400对光线的照射比较敏感，尤其是非晶硅(a-Si)半导体材料，环境光照射后会导致薄膜晶体管的漏电流大大增加， 从而产生串扰、电压闪变等现象，进而影响到显示画面的质量。为了避免半导体层受环境光的照射，通常在液晶显示面板的彩膜基板侧会做一层黑色矩阵(Black Matrix，BM)遮光层，这种方法虽然可以有效防止有源层400透光，但遮光层的存在会降低液晶显示面板的开口率。
发明内容
本发明的目的在于提供一种阵列基板的制作方法，将用于蚀刻形成半导体层的光阻层进行烧光阻，得到位于半导体层上的遮光层，制作方法简单。
本发明的目的还在于提供一种液晶显示面板，阵列基板的半导体层上设有遮光层，从而可省去彩膜基板的黑色矩阵层，面板结构简单，开口率高。
为实现上述目的，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、提供一第一衬底基板，在所述第一衬底基板上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极；
步骤2、在所述栅极、及第一衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积一层非晶硅层；
步骤3、在所述非晶硅层上涂布一层光刻胶膜，提供灰阶掩模板，对该层光刻胶膜进行曝光和显影，得到光阻层，所述光阻层包括位于中间的第一光阻层、及厚度小于第一光阻层且位于第一光阻层两侧的第二光阻层；
所述光刻胶膜的材料为具有吸光特性的正性光刻胶；
步骤4、以所述光阻层为遮蔽层，对所述非晶硅层进行蚀刻，得到半导体层；
步骤5、对所述光阻层进行烧光阻，其中第二光阻层被完全去除掉，第一光阻层的厚度减少，得到遮光层，所得到遮光层的尺寸小于所述半导体层的尺寸；
步骤6、以遮光层作为遮蔽层对所述半导体层的两端进行磷离子注入，得到位于所述半导体层两端的欧姆接触区、及位于中间的未经过离子注入的沟道区；
步骤7、在所述遮光层、半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极和漏极，所述源极和漏极分别与所述半导体层两端的欧姆接触区相接触；
步骤8、在所述源极、漏极、遮光层、及栅极绝缘层上沉积绝缘保护层， 并对绝缘保护层进行图案化处理，得到位于所述漏极上方的贯穿绝缘保护层的过孔；
步骤9、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极，所述像素电极通过过孔与漏极相接触。
所述步骤3中，所述光刻胶膜的膜厚为1.8～3.0μm；所述步骤4中，对所述光阻层进行烧光阻后，所得到的遮光层的厚度为0.7～1.7μm。
所述步骤1中，通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
Figure PCTCN2016083058-appb-000001
所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述步骤7中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
Figure PCTCN2016083058-appb-000002
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述步骤2中，通过化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为
Figure PCTCN2016083058-appb-000003
所沉积的非晶硅层的膜厚为
Figure PCTCN2016083058-appb-000004
所述栅极绝缘层为氮化硅层；所述步骤8中，通过化学气相沉积法沉积绝缘保护层，所沉积的绝缘保护层为膜厚为
Figure PCTCN2016083058-appb-000005
的，所述的绝缘保护层为氮化硅层。
所述步骤9中，通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
Figure PCTCN2016083058-appb-000006
所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
本发明还提供一种液晶显示面板，包括：阵列基板、与所述阵列基板相对设置的彩膜基板、以及夹设于所述阵列基板与彩膜基板之间的液晶层；
所述阵列基板包括：第一衬底基板、设于所述第一衬底基板上的数条栅极扫描线、数条数据线、以及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
所述彩膜基板包括：第二衬底基板、设于所述彩膜基板靠近阵列基板一侧表面的彩色滤光层、设于所述彩色滤光层上的公共电极层、及设于所述公共电极层上的间隔物层；
所述阵列基板上的每一像素单元均包括：形成于所述第一衬底基板上的栅极、形成于所述栅极及第一衬底基板上栅极绝缘层、形成于所述栅极绝缘层上的半导体层、位于所述半导体层上的遮光层、形成于所述遮光层、半导体层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、遮光层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极；
所述遮光层同时具备蚀刻阻挡和遮光的作用，尺寸小于所述半导体层的尺寸，材料为具有吸光特性的正性光刻胶。
所述遮光层的厚度为0.7～1.7μm。
所述半导体层包括位于中间的沟道区及位于两端的欧姆接触区，所述遮光层完全覆盖所述沟道区，所述欧姆接触区通过以所述遮光层为遮蔽层，对所述半导体层的两端进行磷离子注入得到，所述源极和漏极分别与所述半导体层两端的欧姆接触区相接触。
所述绝缘保护层对应所述漏极上方设有贯穿所述绝缘保护层的通孔，所述像素电极通过通孔与所述漏极相接触。
所述半导体层通过以设于非晶硅层上的光阻层为遮蔽层，对非晶硅层进行蚀刻得到，所述遮光层由该光阻层通过烧光阻得到。
本发明还提供一种液晶显示面板，包括：阵列基板、与所述阵列基板相对设置的彩膜基板、以及夹设于所述阵列基板与彩膜基板之间的液晶层；
所述阵列基板包括：第一衬底基板、设于所述第一衬底基板上的数条栅极扫描线、数条数据线、以及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
所述彩膜基板包括：第二衬底基板、设于所述彩膜基板靠近阵列基板一侧表面的彩色滤光层、设于所述彩色滤光层上的公共电极层、及设于所述公共电极层上的间隔物层；
所述阵列基板上的每一像素单元均包括：形成于所述第一衬底基板上的栅极、形成于所述栅极及第一衬底基板上栅极绝缘层、形成于所述栅极绝缘层上的半导体层、位于所述半导体层上的遮光层、形成于所述遮光层、半导体层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、遮光层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极；
所述遮光层同时具备蚀刻阻挡和遮光的作用，尺寸小于所述半导体层的尺寸，材料为具有吸光特性的正性光刻胶；
其中，所述遮光层的厚度为0.7～1.7μm；
其中，所述半导体层包括位于中间的沟道区及位于两端的欧姆接触区，所述遮光层完全覆盖所述沟道区，所述欧姆接触区通过以所述遮光层为遮蔽层，对所述半导体层的两端进行磷离子注入得到，所述源极和漏极分别与所述半导体层两端的欧姆接触区相接触。
本发明的有益效果：本发明提供一种阵列基板的制作方法及液晶显示面板，本发明的阵列基板的制作方法，半导体层上设置有遮光层，该遮光层为一种具有吸光特性的正性光刻胶，该遮光层采用与蚀刻形成半导体层所用的光阻层同层设计，在半导体层完成蚀刻后，通过对光阻层进行烧光阻得到该尺寸小于半导体层的遮光层，以遮挡光线对半导体层的照射，降 低漏电流，然后通过磷离子注入形成半导体层两端的欧姆接触层，该制作方法简单易行，效果良好；本发明的液晶显示面板，半导体层上设有遮光层，该遮光层同时具备蚀刻阻挡和遮光的作用，能够取代现有技术中彩膜基板上的黑色矩阵，遮挡光线对半导体层的照射，降低漏电流，简化面板结构，提升开口率。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的TFT阵列基板的结构示意图；
图2为本发明的阵列基板的制作方法的示意流程图；
图3为本发明的阵列基板的制作方法的步骤1的示意图；
图4为本发明的阵列基板的制作方法的步骤2的示意图；
图5为本发明的阵列基板的制作方法的步骤3中对光刻胶膜进行曝光的示意图；
图6为本发明的阵列基板的制作方法的步骤3中对光刻胶膜曝光后进行显影的示意图；
图7为本发明的阵列基板的制作方法的步骤4的示意图；
图8为本发明的阵列基板的制作方法的步骤5的示意图；
图9为本发明的阵列基板的制作方法的步骤6的示意图；
图10为本发明的阵列基板的制作方法的步骤7的示意图；
图11为本发明的阵列基板的制作方法的步骤8的示意图；
图12为本发明的阵列基板的制作方法的步骤9的示意图；
图13为本发明的液晶显示面板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、如图3所示，提供一第一衬底基板10，在所述第一衬底基板 10上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极20。
具体的，所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
Figure PCTCN2016083058-appb-000007
所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；具体的，通过掩模板进行曝光、显影，并进行湿刻和剥离完成所述栅极金属层的图案化处理。
步骤2、如图4所示，在所述栅极20、及第一衬底基板10上沉积栅极绝缘层30，在所述栅极绝缘层30上沉积一层非晶硅层40’。
具体的，所述步骤2中通过化学气相沉积法沉积栅极绝缘层30和非晶硅层40’，所沉积的栅极绝缘层30的膜厚为
Figure PCTCN2016083058-appb-000008
所沉积的非晶硅层40’的膜厚为
Figure PCTCN2016083058-appb-000009
优选的，所述栅极绝缘层31为氮化硅层。
步骤3、如图5-6所示，在所述非晶硅层40’上涂布一层光刻胶膜，提供灰阶掩模板90，对该层光刻胶膜进行曝光显影，得到位于所述非晶硅层40’上的对应所述栅极20上方的光阻层50，所述光阻层50包括位于中间的第一光阻层50、及厚度小于第一光阻层51且位于第一光阻层51两侧的第二光阻层52；
特别的，所述光刻胶膜的材料为具有吸光特性的正性光刻胶。
具体的，所述步骤3中，所述光刻胶膜的膜厚为1.8～3.0μm，则所述灰阶掩模板90上对应于所述第一光阻层的第一部分91为不透光，对应于第二光阻层的第二部分92为半透光，其余部分为完全透光。
步骤4、如图7所示，以所述光阻层50为遮蔽层，对所述非晶硅层40’进行蚀刻，得到半导体层40。
具体的，所述步骤4中，对所述光阻层50进行烧光阻后，所得到的遮光层501的厚度为0.7～1.7μm。
步骤5、如图8所示，对所述光阻层50进行烧光阻，其中第二光阻层52被完全去除掉，第一光阻层51的厚度减少，得到遮光层501，所得到遮光层501的尺寸小于所述半导体层40的尺寸。
步骤6、如图9所示，以遮光层501作为遮蔽层对所述半导体层40的两端进行磷离子注入，得到位于所述半导体层40两端的欧姆接触区41、及位于中间的未经过离子注入的沟道区42；
步骤7、如图10所示，在所述遮光层501、半导体层40、及栅极绝缘层30上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极61和漏极62，所述源极61和漏极62分别与所述半导体层40两端的欧姆接触区41相接触；
具体的，所述步骤7中，通过物理气相沉积法沉积源漏极金属层，所 沉积的源漏极金属层的膜厚为
Figure PCTCN2016083058-appb-000010
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。具体的，通过掩模板进行曝光、显影，并进行湿刻和剥离完成所述源漏极金属层的图案化处理。
步骤8、如图11所示，在所述源极61、漏极62、遮光层501、及栅极绝缘层30上沉积绝缘保护层70，并对绝缘保护层70进行图案化处理，得到位于所述漏极62上方的贯穿绝缘保护层70的过孔71。
具体的，所述步骤8中通过化学气相沉积法沉积绝缘保护层，所沉积的绝缘保护层70为膜厚为
Figure PCTCN2016083058-appb-000011
的；优选的，所述的绝缘保护层70为氮化硅层。具体的，通过掩模板进行曝光、显影，并进行干刻和剥离完成所述绝缘保护层70的图案化处理。
步骤9、如图12所示，在所述绝缘保护层70上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极80，所述像素电极80通过过孔71与漏极62相接触。
具体的，所述步骤9中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
Figure PCTCN2016083058-appb-000012
所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。具体的，通过掩模板进行曝光、显影，并进行湿刻和剥离完成所述透明导电层的图案化处理。
请参阅图13，基于以上阵列基板的制作方法，本发明还提供一种液晶显示面板，包括：阵列基板1、彩膜基板2以及位于阵列基板1与彩膜基板2之间的液晶层3；
所述陈列基板1包括：第一衬底基板10、设于所述第一衬底基板10上的数条栅极扫描线、数条数据线、以及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
所述彩膜基板2包括：第二衬底基板25、设于所述彩膜基板2靠近阵列基板1一侧表面的彩色滤光层21、设于所述彩色滤光层21上的公共电极层22、及设于所述公共电极层22上的间隔物层23；
所述阵列基板1上的每一像素单元包括：形成于所述第一衬底基板10上的栅极20、形成于所述栅极20及第一衬底基板10上栅极绝缘层30、对应所述栅极20上方且形成于所述栅极绝缘层30上的半导体层40、位于所述半导体层40上的遮光层501、形成于所述遮光层501、半导体层40、及栅极绝缘层30上的源极61和漏极62、形成于所述源极61、漏极62、遮光层501、及栅极绝缘层30上绝缘保护层70、及形成于所述绝缘保护层70上的像素电极80；
所述遮光层501同时具备蚀刻阻挡和遮光的作用，尺寸小于所述半导体层40的尺寸，材料为具有吸光特性的正性光刻胶。
具体的，所述半导体层40通过以光阻层为遮蔽层，对非晶硅层进行蚀刻得到，所述遮光层501由该光阻层通过烧光阻得到。
具体的，所述遮光层501的厚度为0.7～1.7μm。
具体的，所述半导体层40包括位于中间的沟道区42及位于两端的欧姆接触区41，所述遮光层501完全覆盖所述沟道区42，所述欧姆接触区41通过以所述遮光层501为遮蔽层，对所述半导体层40的两端进行磷离子注入得到，所述源极61和漏极62分别与所述半导体层40两端的欧姆接触区41相接触。
具体的，所述绝缘保护层70对应所述漏极62上方设有通孔71，所述像素电极80通过通孔71与所述漏极62相接触。
综上所述，本发明提供的一种阵列基板的制作方法，半导体层上设置有遮光层，该遮光层为一种具有吸光特性的正性光刻胶，该遮光层采用与蚀刻形成半导体层所用的光阻层为同层设计，在半导体层完成蚀刻后，通过对光阻层进行烧光阻得到该尺寸小于半导体层的遮光层，以遮挡光线对半导体层的照射，降低漏电流，然后通过磷离子注入形成半导体层两端的欧姆接触层，该制作方法简单易行，效果良好；本发明的液晶显示面板，半导体层上设有遮光层，该遮光层同时具备蚀刻阻挡和遮光的作用，能够取代现有技术中彩膜基板上的黑色矩阵，遮挡光线对半导体层的照射，降低漏电流，简化面板结构，提升开口率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种阵列基板的制作方法，包括如下步骤：
    步骤1、提供一第一衬底基板，在所述第一衬底基板上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极；
    步骤2、在所述栅极、及第一衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积一层非晶硅层；
    步骤3、在所述非晶硅层上涂布一层光刻胶膜，提供灰阶掩模板，对该层光刻胶膜进行曝光和显影，得到光阻层，所述光阻层包括位于中间的第一光阻层、及厚度小于第一光阻层且位于第一光阻层两侧的第二光阻层；
    所述光刻胶膜的材料为具有吸光特性的正性光刻胶；
    步骤4、以所述光阻层为遮蔽层，对所述非晶硅层进行蚀刻，得到半导体层；
    步骤5、对所述光阻层进行烧光阻，其中第二光阻层被完全去除掉，第一光阻层的厚度减少，得到遮光层，所得到遮光层的尺寸小于所述半导体层的尺寸；
    步骤6、以遮光层作为遮蔽层对所述半导体层的两端进行磷离子注入，得到位于所述半导体层两端的欧姆接触区、及位于中间的未经过离子注入的沟道区；
    步骤7、在所述遮光层、半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极和漏极，所述源极和漏极分别与所述半导体层两端的欧姆接触区相接触；
    步骤8、在所述源极、漏极、遮光层、及栅极绝缘层上沉积绝缘保护层，并对绝缘保护层进行图案化处理，得到位于所述漏极上方的贯穿绝缘保护层的过孔；
    步骤9、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极，所述像素电极通过过孔与漏极相接触。
  2. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤3中，所述光刻胶膜的膜厚为1.8～3.0μm；所述步骤4中，对所述光阻层进行烧光阻后，所得到的遮光层的厚度为0.7～1.7μm。
  3. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
    Figure PCTCN2016083058-appb-100001
    所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的 堆栈组合；所述步骤7中，通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
    Figure PCTCN2016083058-appb-100002
    所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  4. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤2中，通过化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为
    Figure PCTCN2016083058-appb-100003
    所沉积的非晶硅层的膜厚为
    Figure PCTCN2016083058-appb-100004
    所述栅极绝缘层为氮化硅层；所述步骤8中，通过化学气相沉积法沉积绝缘保护层，所沉积的绝缘保护层为膜厚为
    Figure PCTCN2016083058-appb-100005
    的，所述的绝缘保护层为氮化硅层。
  5. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤9中，通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
    Figure PCTCN2016083058-appb-100006
    所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
  6. 一种液晶显示面板，包括：阵列基板、与所述阵列基板相对设置的彩膜基板、以及夹设于所述阵列基板与彩膜基板之间的液晶层；
    所述阵列基板包括：第一衬底基板、设于所述第一衬底基板上的数条栅极扫描线、数条数据线、以及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
    所述彩膜基板包括：第二衬底基板、设于所述彩膜基板靠近阵列基板一侧表面的彩色滤光层、设于所述彩色滤光层上的公共电极层、及设于所述公共电极层上的间隔物层；
    所述阵列基板上的每一像素单元均包括：形成于所述第一衬底基板上的栅极、形成于所述栅极及第一衬底基板上栅极绝缘层、形成于所述栅极绝缘层上的半导体层、位于所述半导体层上的遮光层、形成于所述遮光层、半导体层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、遮光层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极；
    所述遮光层同时具备蚀刻阻挡和遮光的作用，尺寸小于所述半导体层的尺寸，材料为具有吸光特性的正性光刻胶。
  7. 如权利要求6所述的液晶显示面板，其中，所述遮光层的厚度为0.7～1.7μm。
  8. 如权利要求6所述的液晶显示面板，其中，所述半导体层包括位于中间的沟道区及位于两端的欧姆接触区，所述遮光层完全覆盖所述沟道区，所述欧姆接触区通过以所述遮光层为遮蔽层，对所述半导体层的两端进行磷离子注入得到，所述源极和漏极分别与所述半导体层两端的欧姆接触区 相接触。
  9. 如权利要求6所述的液晶显示面板，其中，所述绝缘保护层对应所述漏极上方设有贯穿所述绝缘保护层的通孔，所述像素电极通过通孔与所述漏极相接触。
  10. 如权利要求6所述的液晶显示面板，其中，所述半导体层通过以设于非晶硅层上的光阻层为遮蔽层，对非晶硅层进行蚀刻得到，所述遮光层由该光阻层通过烧光阻得到。
  11. 一种液晶显示面板，包括：阵列基板、与所述阵列基板相对设置的彩膜基板、以及夹设于所述阵列基板与彩膜基板之间的液晶层；
    所述阵列基板包括：第一衬底基板、设于所述第一衬底基板上的数条栅极扫描线、数条数据线、以及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
    所述彩膜基板包括：第二衬底基板、设于所述彩膜基板靠近阵列基板一侧表面的彩色滤光层、设于所述彩色滤光层上的公共电极层、及设于所述公共电极层上的间隔物层；
    所述阵列基板上的每一像素单元均包括：形成于所述第一衬底基板上的栅极、形成于所述栅极及第一衬底基板上栅极绝缘层、形成于所述栅极绝缘层上的半导体层、位于所述半导体层上的遮光层、形成于所述遮光层、半导体层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、遮光层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极；
    所述遮光层同时具备蚀刻阻挡和遮光的作用，尺寸小于所述半导体层的尺寸，材料为具有吸光特性的正性光刻胶；
    其中，所述遮光层的厚度为0.7～1.7μm；
    其中，所述半导体层包括位于中间的沟道区及位于两端的欧姆接触区，所述遮光层完全覆盖所述沟道区，所述欧姆接触区通过以所述遮光层为遮蔽层，对所述半导体层的两端进行磷离子注入得到，所述源极和漏极分别与所述半导体层两端的欧姆接触区相接触。
  12. 如权利要求11所述的液晶显示面板，其中，所述绝缘保护层对应所述漏极上方设有贯穿所述绝缘保护层的通孔，所述像素电极通过通孔与所述漏极相接触。
  13. 如权利要求11所述的液晶显示面板，其中，所述半导体层通过以设于非晶硅层上的光阻层为遮蔽层，对非晶硅层进行蚀刻得到，所述遮光层由该光阻层通过烧光阻得到。
PCT/CN2016/083058 2016-01-20 2016-05-23 阵列基板的制作方法及液晶显示面板 WO2017124673A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/112,195 US9947754B1 (en) 2016-01-20 2016-05-23 Manufacturing method of array substrate and LCD panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610041412.9 2016-01-20
CN201610041412.9A CN105652541B (zh) 2016-01-20 2016-01-20 阵列基板的制作方法及液晶显示面板

Publications (1)

Publication Number Publication Date
WO2017124673A1 true WO2017124673A1 (zh) 2017-07-27

Family

ID=56487073

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/083058 WO2017124673A1 (zh) 2016-01-20 2016-05-23 阵列基板的制作方法及液晶显示面板

Country Status (3)

Country Link
US (1) US9947754B1 (zh)
CN (1) CN105652541B (zh)
WO (1) WO2017124673A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449656A (zh) * 2016-10-26 2017-02-22 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板和显示装置
CN107996002A (zh) * 2016-12-30 2018-05-04 深圳市柔宇科技有限公司 阵列基板及阵列基板制造方法
WO2018182738A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Thin film transistors with spacer controlled gate length
CN107086181B (zh) * 2017-04-18 2021-08-13 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示器
CN107093582A (zh) * 2017-04-28 2017-08-25 京东方科技集团股份有限公司 显示面板的制造方法和显示面板
CN108198824B (zh) * 2018-01-17 2020-06-16 京东方科技集团股份有限公司 一种阵列基板的制备方法
CN109190563B (zh) * 2018-09-05 2022-02-25 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置
CN109638080A (zh) * 2018-12-03 2019-04-16 惠科股份有限公司 主动开关及其制作方法、显示装置
CN112366178B (zh) * 2020-11-09 2023-03-28 Tcl华星光电技术有限公司 阵列基板的制备方法及阵列基板
CN112542470A (zh) * 2020-12-04 2021-03-23 Tcl华星光电技术有限公司 一种阵列基板及其制备方法
CN114784114A (zh) * 2022-04-29 2022-07-22 汕头超声显示器技术有限公司 一种氧化物薄膜晶体管

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060001710A (ko) * 2004-06-30 2006-01-06 삼성에스디아이 주식회사 유기 전계 발광 표시 소자 및 그 제조방법
CN103309108A (zh) * 2013-05-30 2013-09-18 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103681693A (zh) * 2013-12-05 2014-03-26 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104485338A (zh) * 2014-12-15 2015-04-01 京东方科技集团股份有限公司 阵列基板及制作方法、液晶显示面板和反射式液晶显示器
CN104752489A (zh) * 2015-04-10 2015-07-01 深圳市华星光电技术有限公司 阵列基板、显示装置及用于制备阵列基板的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661025B2 (en) * 2000-09-22 2003-12-09 Seiko Epson Corporation Method of manufacturing electro-optical apparatus substrate, electro-optical apparatus substrate, electro-optical apparatus and electronic apparatus
JP2002296618A (ja) * 2001-03-29 2002-10-09 Nec Corp 液晶表示装置およびその製造方法
CN100529866C (zh) * 2006-04-19 2009-08-19 群康科技(深圳)有限公司 液晶显示器制造方法
TWI317559B (en) * 2006-11-15 2009-11-21 Au Optronics Corp Method for manufacturing substrate of a liquid crystal display device
CN104377247B (zh) * 2014-11-24 2017-12-08 深圳市华星光电技术有限公司 薄膜晶体管、显示装置及薄膜晶体管的制造方法
CN105093760A (zh) * 2015-09-18 2015-11-25 京东方科技集团股份有限公司 Coa基板及其制备方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060001710A (ko) * 2004-06-30 2006-01-06 삼성에스디아이 주식회사 유기 전계 발광 표시 소자 및 그 제조방법
CN103309108A (zh) * 2013-05-30 2013-09-18 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103681693A (zh) * 2013-12-05 2014-03-26 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104485338A (zh) * 2014-12-15 2015-04-01 京东方科技集团股份有限公司 阵列基板及制作方法、液晶显示面板和反射式液晶显示器
CN104752489A (zh) * 2015-04-10 2015-07-01 深圳市华星光电技术有限公司 阵列基板、显示装置及用于制备阵列基板的方法

Also Published As

Publication number Publication date
US9947754B1 (en) 2018-04-17
US20180097075A1 (en) 2018-04-05
CN105652541A (zh) 2016-06-08
CN105652541B (zh) 2018-11-23

Similar Documents

Publication Publication Date Title
WO2017124673A1 (zh) 阵列基板的制作方法及液晶显示面板
JP3719939B2 (ja) アクティブマトリクス基板およびその製造方法ならびに表示装置および撮像装置
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
CN106876386B (zh) 薄膜晶体管及其制备方法、阵列基板、显示面板
US8018566B2 (en) Method for fabricating an in-plane switching mode liquid crystal display wherein the upper and lower pixel electrodes are formed on opposite sides of the respective upper and lower pixel regions
US8305528B2 (en) Liquid crystal display and manufacturing method thereof
CN105895581A (zh) Tft基板的制作方法
CN113394166B (zh) 阵列基板的制作方法、阵列基板及显示面板
US9070599B2 (en) Array substrate, manufacturing method thereof and display device
US8045077B2 (en) Liquid crystal display device and fabrication method thereof
WO2017012164A1 (zh) Boa型液晶显示面板及其制作方法
WO2017147974A1 (zh) 阵列基板的制作方法及制得的阵列基板
CN106992149B (zh) Tft基板的制作方法
CN106298646B (zh) Tft基板的制作方法
WO2018036027A1 (zh) Ips型阵列基板的制作方法及ips型阵列基板
WO2020093442A1 (zh) 阵列基板的制作方法及阵列基板
US10503034B2 (en) Manufacturing method of a TFT substrate and structure
WO2017147973A1 (zh) 阵列基板的制作方法及制得的阵列基板
KR20120072817A (ko) 액정 표시 장치 및 이의 제조 방법
CN101207092B (zh) 液晶显示器件及其制造方法
CN111427205A (zh) 阵列基板及其制备方法、液晶显示面板
CN104299972B (zh) 薄膜晶体管阵列基板及其制造方法、液晶显示器
US7576808B2 (en) Multi model glass type substrate for liquid crystal display device and method of fabricating the same
KR20110077254A (ko) 횡전계방식 액정표시장치의 제조방법
KR101856209B1 (ko) 액정표시장치의 박막트랜지스터 및 그 제조방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15112195

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16885935

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16885935

Country of ref document: EP

Kind code of ref document: A1