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WO2017076071A1 - 阵列基板及包括该阵列基板的tft显示装置 - Google Patents

阵列基板及包括该阵列基板的tft显示装置 Download PDF

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Publication number
WO2017076071A1
WO2017076071A1 PCT/CN2016/090992 CN2016090992W WO2017076071A1 WO 2017076071 A1 WO2017076071 A1 WO 2017076071A1 CN 2016090992 W CN2016090992 W CN 2016090992W WO 2017076071 A1 WO2017076071 A1 WO 2017076071A1
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Prior art keywords
display area
array substrate
electrostatic guiding
electrostatic
flexible printed
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PCT/CN2016/090992
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English (en)
French (fr)
Inventor
董职福
李红敏
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/502,805 priority Critical patent/US10204921B2/en
Publication of WO2017076071A1 publication Critical patent/WO2017076071A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures

Definitions

  • Embodiments of the present invention relate to an array substrate and a TFT display device including the array substrate.
  • a conventional array substrate 1 for a TFT display screen is shown in Figures 1-2.
  • the array substrate 1 includes a display area 11 and a non-display area 12.
  • the non-display area 12 is provided with a gate drive circuit (GOA) 121, an electrostatic boot ring (GND) 122, a data drive circuit 123, a flexible printed circuit (FPC) 124, a base substrate 126, and an insulating layer 125.
  • the conventional array substrate 1 mainly resists static electricity by the electrostatic guiding ring 122 to protect the display screen.
  • the conventional array substrate 1 having the above structure has a problem that the TFT display screen has a weak resistance to electrostatic charges.
  • an array substrate includes a display area and a non-display area surrounding the display area, wherein an electrostatic guiding layer, the static guiding layer and the display area are disposed on the non-display area Electrical insulation.
  • the non-display area is a planar area corresponding to the exposed base substrate around the display area, and an insulating layer is disposed on the base substrate, wherein the insulating layer is located between the base substrate and the electrostatic guiding layer .
  • an electrostatic guiding ring surrounding the display area is disposed on the non-display area, and a gate driving circuit and a data driving circuit are disposed between the electrostatic guiding ring and the display area;
  • the non-display area further includes a flexible printed circuit electrically connected to the flexible printed circuit, the electrostatic guiding ring being located between the base substrate and the insulating layer.
  • an electrostatic guiding ring surrounding the display area is disposed on the non-display area, the non-display area further comprising a flexible printed circuit, the electrostatic guiding ring and the The flexible printed circuit is electrically connected, and the electrostatic guiding ring is located between the base substrate and the insulating layer.
  • the electrostatic guiding layer is electrically connected to a ground signal terminal of the flexible printed circuit.
  • the electrostatic guiding layer is directly electrically connected to the ground signal terminal of the flexible printed circuit through a via provided in a portion of the insulating layer above the flexible printed circuit.
  • the electrostatic guiding layer is formed of a transparent conductive material.
  • the electrostatic guiding layer is formed of indium tin oxide.
  • the electrostatic guiding layer is formed by a sputtering process.
  • a TFT display device including the above array substrate.
  • the array substrate and the display device have a large-area electrostatic guiding layer for collecting electric charges, enhance the ability to store electric charges, and can discharge static electricity in time, and based on the electric charge guiding ring to guide the electric charge,
  • the antistatic capability is further enhanced to effectively protect the display.
  • the materials and processes used are common to the materials and processes used in the conventional fabrication of array substrates, with little additional cost, but can significantly improve the electrostatically conductive capability.
  • 1 is a schematic structural view of a conventional array substrate.
  • Figure 2 is a cross-sectional view of the array substrate of Figure 1 taken along line A-A'.
  • FIG. 3 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • Figure 4 is a cross-sectional view of the array substrate of Figure 3 taken along line A-A'.
  • FIG. 3 is a schematic structural view of an array substrate 1 (also referred to as a TFT substrate) for a TFT display device according to an embodiment of the present invention.
  • Figure 4 is a cross-sectional view of the array substrate 1 of Figure 3 taken along line A-A'.
  • the array substrate 1 shown in FIG. 3 includes a display area 11 and a non-display area 12 surrounding the display area 11.
  • the non-display area 12 corresponds to the exposure around the display area 11.
  • the area of the base substrate 126 (as shown in Figure 4).
  • An electrostatic guiding ring 122 surrounding the display area 11 is disposed on the non-display area 12, and a gate driving circuit 121 and a data driving circuit 123 are disposed between the electrostatic guiding ring 122 and the display area 11.
  • the non-display area 12 also includes a flexible printed circuit 124 that is electrically coupled to the flexible printed circuit 124 to form a loop to direct the electrostatic charge collected by the electrostatic guide ring 122.
  • an insulating layer 125 is further disposed on the base substrate 126 in the non-display area 12.
  • the insulating layer 125 covers the gate driving circuit 121, the electrostatic guiding ring 122, the driving integrated circuit 123, and the flexible printed circuit 124 disposed on the base substrate 126.
  • an electrostatic guiding layer 127 is further provided on the insulating layer 125 in the non-display area 12.
  • the static guiding layer 127 is electrically insulated from the display region 11.
  • a via hole (not shown) that is electrically connected to a ground signal terminal of the flexible printed circuit 124 is disposed in a portion of the insulating layer 125 above the flexible printed circuit 124, and the electrostatic guiding layer 127 is directly electrically connected through the via hole.
  • the static guiding layer 127 may be made of a transparent conductive material.
  • the electrostatic guiding layer 127 is formed of indium tin oxide used when the display region 11 is manufactured.
  • the static guiding layer 127 can be formed by a sputtering process.
  • the static guiding layer 127 may be formed using the same materials and processes as the conductive layers formed on the display region 11. Specifically, the metal layer and the insulating layer are sequentially formed by processes such as coating, photolithography, and development in the same manner as in the conventional process. In the final process, a transparent electrostatic guiding layer 127 is formed over the original electrostatic guiding ring 122 and the gate driving circuit 121 by using the last mask without adding a mask.
  • Embodiments of the present invention also provide a TFT display device including the above array substrate 1.
  • the electrostatic guiding layer according to the embodiment of the present invention does not additionally increase the manufacturing process of the array substrate, and does not increase the manufacturing cost of the array substrate, but the increased electrostatic guiding layer allows the array substrate to have a larger surface area for collecting static electricity, so that almost the entire non- The display area can be used to collect electrostatic charges and direct the collected electrostatic charge directly through the flexible printed circuit, significantly improving the array substrate's ability to resist static electricity.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种阵列基板（1）和包括阵列基板（1）的显示装置，阵列基板（1）包括显示区（11）和围绕显示区（11）的非显示区（12），其中，在非显示区（12）上设置有静电引导层（127），静电引导层（127）与显示区（11）电绝缘。

Description

阵列基板及包括该阵列基板的TFT显示装置 技术领域
本发明的实施例涉及一种阵列基板和包括该阵列基板的TFT显示装置。
背景技术
用于TFT显示屏的传统的阵列基板1如图1-2所示。阵列基板1包括显示区11和非显示区12。非显示区12中设置有栅极驱动电路(GOA)121、静电引导环(GND)122、数据驱动电路123、柔性印刷电路(FPC)124、衬底基板126和绝缘层125。传统的阵列基板1主要通过静电引导环122来抵抗静电以便保护显示屏。但具有上述结构的传统的阵列基板1存在TFT显示屏对静电电荷的抵抗能力弱的问题。
发明内容
本发明的实施例的一个目的是提高TFT显示屏疏导静电电荷的能力。
根据本发明的实施例，提供一种阵列基板，所述阵列基板包括显示区和围绕显示区的非显示区，其中，在非显示区上设置有静电引导层，所述静电引导层与显示区电绝缘。
根据本发明的实施例，非显示区是与在显示区周围的暴露的衬底基板对应的平面区域，在衬底基板上设置有绝缘层，其中绝缘层位于衬底基板和静电引导层之间。
根据本发明的实施例，在所述非显示区上设置有围绕显示区的静电引导环，在所述静电引导环与所述显示区之间设置有栅极驱动电路和数据驱动电路；所述非显示区还包括柔性印刷电路，所述静电引导环与所述柔性印刷电路电连接，静电引导环位于衬底基板和绝缘层之间。
根据本发明的实施例，在所述非显示区上设置有围绕显示区的静电引导环，所述非显示区还包括柔性印刷电路，所述静电引导环与所 述柔性印刷电路电连接，静电引导环位于衬底基板和绝缘层之间。
根据本发明的实施例，静电引导层电连接至柔性印刷电路的接地信号端子。
根据本发明的实施例，静电引导层通过设置于绝缘层的在柔性印刷电路上方的部分中的导通孔直接电连接至柔性印刷电路的接地信号端子。
根据本发明的实施例，静电引导层由透明导电材料形成。
根据本发明的实施例，静电引导层由氧化铟锡形成。
根据本发明的实施例，静电引导层通过溅射工艺形成。
根据本发明的实施例，提供一种TFT显示装置，所述显示装置包括上述的一种阵列基板。
根据本发明的实施例的阵列基板和显示装置，具有大面积的用于收集电荷的静电引导层，增强了存储电荷的能力，能够及时导走静电，在利用静电引导环引导电荷的基础上，进一步增强了抗静电能力，从而有效保护显示屏。而且，采用的材料和工艺与传统的制造阵列基板采用的材料和工艺通用，几乎不额外增加成本，但能够显著提高静电疏导能力。
附图说明
图1是传统阵列基板的结构示意图。
图2是图1的阵列基板沿线A-A’截取的剖面图。
图3是根据本发明一个实施例的阵列基板的结构示意图。
图4是图3的阵列基板沿线A-A’截取的剖面图。
具体实施方式
下面结合附图详细描述本发明的实施例。
图3是根据本发明一个实施例的用于TFT显示装置的阵列基板1(也称为TFT基板)的结构示意图。图4是图3的阵列基板1沿线A-A’截取的剖面图。图3所示的阵列基板1包括显示区11和围绕显示区11的非显示区12。非显示区12对应于在显示区11周围的暴露 的衬底基板126的区域(如图4中所示)。在所述非显示区12上设置有围绕显示区11的静电引导环122，在所述静电引导环122与所述显示区11之间设置有栅极驱动电路121和数据驱动电路123。所述非显示区12还包括柔性印刷电路124，所述静电引导环12与所述柔性印刷电路124电连接以形成回路，从而将由静电引导环122收集的静电电荷引导走。
如图4中所示，在非显示区12中的衬底基板126上还设置有一层绝缘层125。绝缘层125覆盖设置在衬底基板126上的栅极驱动电路121、静电引导环122、驱动集成电路123和柔性印刷电路124。此外，在非显示区12中的绝缘层125上还设置有静电引导层127。静电引导层127与显示区11电绝缘。在绝缘层125的在柔性印刷电路124上方的部分中设置有与柔性印刷电路124的接地信号端子导通的导通孔(图中未示出)，静电引导层127通过该导通孔直接电连接至柔性印刷电路124的接地信号端子。所述静电引导层127可以由透明的导电材料制成。例如，所述静电引导层127由与制造显示区11时使用的氧化铟锡形成。静电引导层127可以通过溅射工艺形成。例如，静电引导层127可以与在形成显示区11上的导电层采用相同的材料和工艺形成。具体地，与传统工艺完全一样，依次通过涂覆、光刻、显影等工序依次形成各金属层和绝缘层。在最后一道工序，在不增加掩膜板(mask)的基础上，利用最后一张掩膜板，在原有静电引导环122和栅极驱动电路121上方形成透明的静电引导层127。
本发明的实施例还提供包括上述阵列基板1的TFT显示装置。
根据本发明的实施例的静电引导层不额外增加阵列基板的制造工艺，不会增加阵列基板的制造成本，但是增加的静电引导层使得阵列基板具有更大的收集静电的表面积，使得几乎整个非显示区都可以用来收集静电电荷，并将收集的静电电荷通过柔性印刷电路直接引导走，显著提升阵列基板抵抗静电的能力。
本领域技术人员可以理解的是，上述的形成本发明的实施例的静电引导层的材料和工艺是示例性的，可以对静电引导层的材料和工艺做出修改和改变。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (10)

  1. 一种阵列基板，所述阵列基板包括：
    显示区和围绕显示区的非显示区，
    其中在非显示区上设置有静电引导层，所述静电引导层与显示区电绝缘。
  2. 根据权利要求1所述的阵列基板，其中：
    非显示区是与在显示区周围的暴露的衬底基板对应的平面区域，在衬底基板上设置有绝缘层，其中绝缘层位于衬底基板和静电引导层之间。
  3. 根据权利要求2所述的阵列基板，其中：
    在所述非显示区上设置有围绕显示区的静电引导环，在所述静电引导环与所述显示区之间设置有栅极驱动电路和数据驱动电路；所述非显示区还包括柔性印刷电路，所述静电引导环与所述柔性印刷电路电连接，静电引导环位于衬底基板和绝缘层之间。
  4. 根据权利要求2所述的阵列基板，其中：
    在所述非显示区上设置有围绕显示区的静电引导环，所述非显示区还包括柔性印刷电路，所述静电引导环与所述柔性印刷电路电连接，静电引导环位于衬底基板和绝缘层之间。
  5. 根据权利要求3或4所述的阵列基板，其中：
    静电引导层电连接至柔性印刷电路的接地信号端子。
  6. 根据权利要求5所述的阵列基板，其中：
    静电引导层通过设置于绝缘层的在柔性印刷电路上方的部分中的导通孔直接电连接至柔性印刷电路的接地信号端子。
  7. 根据权利要求1所述的阵列基板，其中：
    静电引导层由透明导电材料形成。
  8. 根据权利要求7所述的阵列基板，其中：
    静电引导层由氧化铟锡形成。
  9. 根据权利要求8所述的阵列基板，其中：
    静电引导层通过溅射工艺形成。
  10. 一种显示装置，包括根据权利要求1-9中任一项所述的阵列基板。
PCT/CN2016/090992 2015-11-03 2016-07-22 阵列基板及包括该阵列基板的tft显示装置 WO2017076071A1 (zh)

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CN201520881760.8U CN205069639U (zh) 2015-11-03 2015-11-03 阵列基板及包括该阵列基板的tft显示装置
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