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WO2017051635A1 - Semiconductor substrate, photoelectric conversion element, method for manufacturing semiconductor substrate, and method for manufacturing photoelectric conversion element - Google Patents

Semiconductor substrate, photoelectric conversion element, method for manufacturing semiconductor substrate, and method for manufacturing photoelectric conversion element Download PDF

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Publication number
WO2017051635A1
WO2017051635A1 PCT/JP2016/073889 JP2016073889W WO2017051635A1 WO 2017051635 A1 WO2017051635 A1 WO 2017051635A1 JP 2016073889 W JP2016073889 W JP 2016073889W WO 2017051635 A1 WO2017051635 A1 WO 2017051635A1
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Prior art keywords
semiconductor substrate
manufacturing
forming
photoelectric conversion
conversion element
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PCT/JP2016/073889
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French (fr)
Japanese (ja)
Inventor
健史 森
真人 石井
親扶 岡本
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シャープ株式会社
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Publication of WO2017051635A1 publication Critical patent/WO2017051635A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00Individual photovoltaic cells, e.g. solar cells
    • H10F10/10Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00Constructional details of devices covered by this subclass
    • H10F77/70Surface textures, e.g. pyramid structures
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Definitions

  • the present invention relates to a semiconductor substrate, a method for manufacturing a semiconductor substrate, and a method for manufacturing a photoelectric conversion element.
  • the most manufactured and sold solar cells have a structure in which electrodes are formed on a light receiving surface that is a surface on which sunlight is incident and a back surface that is opposite to the light receiving surface, respectively.
  • Patent Document 1 discloses a crystalline silicon substrate having a large number of pyramidal irregularities formed on the surface by anisotropic etching, and a chemical vapor deposition method on the irregularities.
  • a photovoltaic element comprising: an amorphous or microcrystalline silicon layer provided by the step; and a valley portion of a pyramidal uneven portion provided on a surface of a substrate is formed in a round shape. (For example, claim 1 of Patent Document 1).
  • the embodiment disclosed herein includes a plurality of convex portions and a concave portion between the convex portions on the surface, the convex portion includes an inclined surface, the concave portion includes a curved bottom, and the angle of the inclined surface is 49.5. It is a semiconductor substrate that is larger than 5 ° and smaller than or equal to 55.2 ° and has a curved radius of curvature larger than 13 nm.
  • the embodiment disclosed herein includes the above-described semiconductor substrate, and a first conductivity type amorphous semiconductor film and a second conductivity type amorphous semiconductor film on a second surface opposite to the surface of the semiconductor substrate, A photoelectric conversion element comprising a first electrode on the first conductive type amorphous semiconductor film and a second electrode on the second conductive type amorphous semiconductor film.
  • the embodiment disclosed herein includes the semiconductor substrate, the first conductivity type region and the second conductivity type region on the second surface opposite to the surface of the semiconductor substrate, and the first conductivity type region on the first conductivity type region. It is a photoelectric conversion element provided with 1 electrode and the 2nd electrode on a 2nd conductivity type area
  • the embodiment disclosed herein includes the semiconductor substrate, the first conductivity type region on the surface of the semiconductor substrate, the second conductivity type region on the second surface opposite to the surface of the semiconductor substrate, and the first It is a photoelectric conversion element provided with the 1st electrode on a conductivity type area
  • Embodiment disclosed here is a photoelectric conversion element provided with said semiconductor substrate.
  • the embodiment disclosed herein includes a step of forming a plurality of convex portions and concave portions between the convex portions on the surface of the semiconductor substrate, a step of performing acid etching of the surface on which the convex portions and the concave portions are formed, Performing a round etching of the surface after the acid etching, and in the step of performing the round etching, the angle of the inclined surface of the convex portion is set to be larger than 49.5 ° and not more than 55.2 °, and the curved surface of the bottom of the concave portion
  • This is a method for manufacturing a semiconductor substrate in which the radius of curvature is larger than 13 nm.
  • the embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the above-described method of manufacturing a semiconductor substrate, and a side opposite to the surface of the semiconductor substrate Forming a first conductive type amorphous semiconductor film and a second conductive type amorphous semiconductor film on the second surface, and forming a first electrode on the first conductive type amorphous semiconductor film And a step of forming a second electrode on the second conductivity type amorphous semiconductor film.
  • the embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the above-described method of manufacturing a semiconductor substrate, and a side opposite to the surface of the semiconductor substrate Forming a first conductivity type region and a second conductivity type region on the second surface, forming a first electrode on the first conductivity type region, and forming a second electrode on the second conductivity type region.
  • a process for forming the photoelectric conversion element is forming a photoelectric conversion element.
  • the embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method for manufacturing a semiconductor substrate, and a first conductive material on the surface of the semiconductor substrate.
  • a photoelectric conversion element having high characteristics can be manufactured.
  • FIG. 3 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1.
  • FIG. 3 is a schematic enlarged perspective view of an example of a convex portion of a light receiving surface of a semiconductor substrate of the heterojunction back contact cell of Embodiment 1.
  • FIG. 3 is a schematic enlarged cross-sectional view of an example of a convex portion of a light receiving surface of a semiconductor substrate of a heterojunction back contact cell according to Embodiment 1.
  • FIG. 3 is a schematic enlarged cross-sectional view of an example of a recess of a light receiving surface of a semiconductor substrate of a heterojunction back contact cell according to Embodiment 1.
  • FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view of a heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 3.
  • FIG. 6 is a schematic cross-sectional view of a back electrode type solar battery cell according to Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4.
  • FIG. 6 is a schematic cross-sectional view of a double-sided electrode type solar battery cell of Embodiment 5.
  • FIG. FIG. 6 is a result of investigating the relationship between the wavelength of light incident on the substrates of Experimental Examples 1 to 4 and the reflectance.
  • FIG. FIG. 6 is a result of investigating the relationship between the wavelength of light incident on the substrates of Experimental Examples 1 to 4 and the reflectance.
  • FIG. FIG. 6 is a result of investigating the relationship between the wavelength of light incident
  • FIG. 6 is a diagram showing an average value of angles ⁇ of inclined surfaces of convex portions on the surface of substrates in Experimental Examples 1 to 4.
  • FIG. 7 shows the relative values of the reverse saturation current densities of Experimental Example 2 and 5-7, where the reverse saturation current density of the heterojunction back contact cell of Experimental Example 1 is 1.
  • FIG. 4 is a schematic enlarged cross-sectional view of a substrate of Experimental Example 1.
  • FIG. 10 is a schematic enlarged cross-sectional view of a substrate of Experimental Example 5.
  • FIG. 10 is a schematic enlarged cross-sectional view of a substrate of Experimental Example 8.
  • FIG. It is a typical expanded sectional view of the board
  • FIG. It is a measurement result of the curvature radius of the curved surface of the bottom of the recessed part of the surface of the board
  • FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1 which is an example of the photoelectric conversion element of the embodiment.
  • the heterojunction back contact cell of Embodiment 1 includes a semiconductor substrate 1, a plurality of convex portions 11 provided on a light receiving surface that is a first surface of the semiconductor substrate 1, and concave portions 12 between the convex portions 11. And an amorphous silicon film 9 a on the convex portion 11 and the concave portion 12.
  • amorphous silicon film 9a for example, an i-type amorphous silicon film, an n-type amorphous silicon film, or an i-type amorphous silicon film and an n-type amorphous silicon film from the light receiving surface side are used. Can be used.
  • the heterojunction back contact cell of Embodiment 1 includes the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 2 on the back surface 1a which is the second surface opposite to the first surface of the semiconductor substrate 1.
  • 2 i-type amorphous semiconductor film 4 first conductivity-type amorphous semiconductor film 3 on first i-type amorphous semiconductor film 2, and second i-type amorphous semiconductor film 4
  • a second conductive type amorphous semiconductor film 5 a first electrode 6 on the first conductive type amorphous semiconductor film 3, and a second electrode 7 on the second conductive type amorphous semiconductor film 5 are provided. Yes.
  • the semiconductor substrate 1 is an n-type single crystal silicon substrate, and the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 4 are respectively i-type amorphous.
  • the first conductive type amorphous semiconductor film 3 is a p-type amorphous silicon film and the second conductive type amorphous semiconductor film 5 is an n-type amorphous silicon film will be described.
  • the present invention is not limited to this.
  • i-type is not only a completely intrinsic state but also a sufficiently low concentration (n-type impurity concentration is less than 1 ⁇ 10 15 / cm 3 and p-type impurity concentration is 1 ⁇ (Less than 10 15 / cm 3 ) is meant to include n-type or p-type impurities.
  • n-type means a state where the n-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more
  • p-type means that the p-type impurity concentration is 1 ⁇ 10 15 / cm 3. It means a state of cm 3 or more.
  • the n-type impurity concentration and the p-type impurity concentration can be measured by, for example, secondary ion mass spectrometry (SIMS).
  • amorphous silicon includes not only amorphous silicon in which the dangling bonds of silicon atoms are not terminated with hydrogen, but also dangling of silicon atoms such as hydrogenated amorphous silicon. It also includes those whose hands are terminated with hydrogen or the like.
  • FIG. 2 shows a schematic enlarged perspective view of an example of the convex portion 11 of the light receiving surface of the semiconductor substrate 1 of the heterojunction back contact cell of the first embodiment.
  • a texture structure is provided on the light receiving surface of the semiconductor substrate 1
  • the convex part 11 of the light-receiving surface of the semiconductor substrate 1 may have a quadrangular pyramid shape.
  • the convex portion 11 includes a quadrangular bottom surface 11d substantially parallel to the back surface 1a of the semiconductor substrate 1, and four triangular inclined surfaces 11c provided on the bottom surface 11d so as to incline to the bottom surface 11d. And have.
  • One inclined surface 11c is adjacent to and in contact with one inclined surface 11c on each side thereof.
  • the convex portion 11 has four lines 11e where two adjacent inclined surfaces 11c are in contact with each other, and a vertex 11f which is an intersection of these four lines 11e.
  • FIG. 3 shows a schematic enlarged cross-sectional view of an example of the convex portion 11 of the light receiving surface of the semiconductor substrate of the heterojunction back contact cell of the first embodiment.
  • the angle of the inclined surface 11c of the convex portion 11 is defined as an angle ⁇ formed by the line 11e and the bottom surface 11d of the convex portion 11, for example, as shown in FIG.
  • FIG. 4 shows a schematic enlarged cross-sectional view of an example of the recess 12 on the light receiving surface of the semiconductor substrate of the heterojunction back contact cell of the first embodiment.
  • the radius of curvature of the curved surface at the bottom of the recess 12 is defined as the radius r of the virtual circle 11g having the line 11e of the projection 11 located on both sides of the recess 12 as a tangent.
  • the angle of the inclined surface 11c of the convex portion 11 is greater than 49.5 ° and not greater than 55.2 °.
  • the angle of the inclined surface 11c of the convex portion 11 is larger than 49.5 ° and not larger than 55.2 °, the light incident on the light receiving surface of the semiconductor substrate 1 can be sufficiently taken into the semiconductor substrate 1. Therefore, high characteristics can be obtained.
  • the angle of the inclined surface 11c of the convex portion 11 is preferably 50 ° or more, and more preferably 52.9 ° or more. In this case, since more light incident on the light receiving surface of the semiconductor substrate 1 can be taken into the semiconductor substrate 1, higher characteristics can be obtained.
  • the angle of the inclined surface 11c of the convex part 11 is 53.5 degrees or less.
  • the angle of the inclined surface 11c of the convex portion 11 is 53.5 ° or less, more light incident on the light receiving surface of the semiconductor substrate 1 can be taken into the semiconductor substrate 1, and thus higher characteristics can be obtained. Can be obtained.
  • the curvature radius of the curved surface at the bottom of the recess 12 is set to be larger than 13 nm.
  • the curvature radius of the curved surface at the bottom of the recess 12 is larger than 13 nm, it is possible to reduce the occurrence of cracks in the film on the recess 12, and therefore cracks are formed in the film on the recess 12.
  • the resulting deterioration in characteristics can be suppressed.
  • the deterioration of the characteristics due to the formation of cracks in the film includes, for example, the deterioration of the characteristics due to the decrease in reflectivity and the deterioration of the characteristics due to the decrease in the passivation property of the film. Can be mentioned.
  • the radius of curvature of the curved surface at the bottom of the recess 12 is preferably 80 nm or less. In this case, since it is possible to further reduce the occurrence of cracks in the film on the recess 12, it is possible to further suppress deterioration in characteristics due to the formation of cracks in the film on the recess 12. .
  • the radius of curvature of the curved surface at the bottom of the recess 12 is preferably 65 nm or less. In this case, since it is possible to further reduce the occurrence of cracks in the film on the recess 12, it is possible to further suppress deterioration in characteristics due to the formation of cracks in the film on the recess 12. .
  • the film on the convex portion 11 and the concave portion 12 is set by setting the angle of the inclined surface 11c of the convex portion 11 and the radius of curvature of the curved surface at the bottom of the concave portion 12 as described above.
  • the average value of the angle of the inclined surface 11c of the convex part 11 should just satisfy
  • the number of the inclined surfaces 11c of the convex portion 11 satisfying the above-mentioned angle is larger than the number of the inclined surfaces 11c of the convex portion 11 not satisfying the above-described angle. .
  • the number of curvature radii of the bottom curved surface of the recess 12 that satisfies the above-described curvature radius is the number of curvature radii of the bottom curved surface of the recess 12 that does not satisfy the above-described curvature radius. More is preferable.
  • a semiconductor substrate 1 is prepared.
  • a plurality of convex portions 11 and concave portions 12 between the convex portions 11 are formed on the light receiving surface of the semiconductor substrate 1.
  • the method of forming the convex portions 11 and the concave portions 12 on the light receiving surface of the semiconductor substrate 1 is not particularly limited, but can be formed by, for example, texture etching the light receiving surface of the semiconductor substrate 1.
  • the texture etching of the light receiving surface of the semiconductor substrate 1 can be performed, for example, by alkali etching the light receiving surface of the semiconductor substrate 1.
  • Alkali etching is performed using, for example, an alkaline solution containing at least one of a sodium hydroxide aqueous solution and a potassium hydroxide aqueous solution.
  • acid etching of the light receiving surface of the semiconductor substrate 1 is performed.
  • the acid etching of the light receiving surface of the semiconductor substrate 1 is performed using, for example, a hydrogen fluoride aqueous solution on the light receiving surface of the semiconductor substrate 1.
  • round etching of the light receiving surface of the semiconductor substrate 1 is performed.
  • the round etching of the light receiving surface of the semiconductor substrate 1 is performed using, for example, a mixed acid containing hydrofluoric acid, nitric acid, and water on the light receiving surface of the semiconductor substrate 1.
  • the angle of the inclined surface 11c of the convex portion 11 is the above-mentioned angle (greater than 49.5 °, 55.2 ° or less, preferably 50 ° or more, more preferably 52.9).
  • the curvature radius of the curved surface at the bottom of the recess 12 satisfies the above-mentioned curvature radius (greater than 13 nm, preferably less than 80 nm, more preferably less than 65 nm). Done.
  • a mixed acid containing hydrofluoric acid (HF), nitric acid (HNO 3 ), and water (H 2 O) at 30 ° C. to 60 ° C. is used for 30 seconds.
  • the conditions for performing etching for ⁇ 90 seconds can be mentioned, but not limited thereto.
  • the ratio of the volume of nitric acid to the volume of hydrofluoric acid in the mixed acid is preferably 70 or more and 100 or less, and the ratio of the volume of water to the volume of hydrofluoric acid is 35 or more. It is preferable that it is 50 or less.
  • hydrofluoric acid means a hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50% by mass
  • nitric acid means a nitric acid aqueous solution having a nitric acid concentration of 60% by mass.
  • an amorphous silicon film 9 a is formed so as to be in contact with the entire light receiving surface of the semiconductor substrate 1.
  • the formation method of the amorphous silicon film 9a is not particularly limited, but for example, a plasma CVD (Chemical Vapor Deposition) method can be used.
  • a first i-type amorphous semiconductor film 2 is formed so as to be in contact with the entire back surface 1a of the semiconductor substrate 1, and subsequently, as shown in FIG. A type amorphous semiconductor film 3 is formed.
  • a method for forming the first i-type amorphous semiconductor film 2 and the first conductive type amorphous semiconductor film 3 is not particularly limited, and for example, a plasma CVD method can be used.
  • the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous semiconductor film 3 are formed on the first conductivity-type amorphous semiconductor film 3 in the thickness direction.
  • An etching mask 31 having an opening at a location to be etched is formed.
  • the etching mask 31 As a mask, the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 are etched in the thickness direction, A part of the back surface 1a of the semiconductor substrate 1 is exposed. Thereafter, as shown in FIG. 12, the etching mask 31 is removed.
  • the second surface is formed so as to cover the exposed surface of the back surface 1 a of the semiconductor substrate 1 and the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3.
  • An i-type amorphous semiconductor film 4 is formed, and subsequently, a second conductive type amorphous semiconductor film 5 is formed as shown in FIG.
  • a method for forming the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is not particularly limited, and for example, a plasma CVD method can be used.
  • an etching mask 32 is formed only on the portion where the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 are left on the back surface 1 a of the semiconductor substrate 1. Form.
  • the etching mask 32 as a mask, the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 are etched in the thickness direction, A part of the first conductive type amorphous semiconductor film 3 is exposed.
  • the etching mask 32 is removed, and the first electrode 6 is formed on the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5 is formed on the second conductive type amorphous semiconductor film 5 as shown in FIG.
  • the two electrodes 7 the heterojunction back contact cell of Embodiment 1 can be obtained.
  • FIG. 17 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 2, which is another example of the photoelectric conversion element of the embodiment.
  • the heterojunction back contact cell according to the second embodiment is characterized in that a silicon nitride (SiN) film 9 b is provided as a film on the convex portion 11 and the concave portion 12 of the light receiving surface of the semiconductor substrate 1.
  • a silicon nitride (SiN) film 9 b is provided as a film on the convex portion 11 and the concave portion 12 of the light receiving surface of the semiconductor substrate 1.
  • the semiconductor substrate for example, an n-type single crystal silicon substrate similar to that of the first embodiment is used.
  • SiC x N y O z F v H w (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1) , 0 ⁇ z ⁇ 1, 0 ⁇ v ⁇ 1, 0 ⁇ w ⁇ 1, (x + y + z + v + w)> 0
  • the formation method of these films is not particularly limited, but can be formed by, for example, a plasma CVD method.
  • Si represents silicon
  • C represents carbon
  • N represents nitrogen
  • O oxygen
  • F represents fluorine
  • H represents hydrogen
  • x represents the atomic ratio of carbon
  • y represents the atomic ratio of nitrogen
  • z represents the atomic ratio of oxygen
  • v represents the atomic ratio of fluorine
  • w represents hydrogen. Shows the atomic ratio.
  • FIG. 18 is a schematic cross-sectional view of a heterojunction back contact cell of Embodiment 3, which is another example of the photoelectric conversion element of the embodiment.
  • the heterojunction back contact cell of Embodiment 3 is characterized in that a silicon carbide (SiC) film 9 c is provided as a film on the convex portion 11 and the concave portion 12 of the light receiving surface of the semiconductor substrate 1.
  • SiC silicon carbide
  • the semiconductor substrate for example, an n-type single crystal silicon substrate similar to that of the first embodiment is used.
  • the back electrode type solar cell of Embodiment 4 includes a semiconductor substrate 1, a first conductivity type region 63 provided at a distance from the back surface 1 a of the semiconductor substrate 1, and a second conductivity. And a mold region 65.
  • the first electrode 6 is provided on the first conductivity type region 63
  • the second electrode 7 is provided on the second conductivity type region 65.
  • the semiconductor substrate for example, an n-type single crystal silicon substrate similar to that of the first embodiment is used.
  • SiC x N y O z F v H w (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1, 0 ⁇ v ⁇ 1, 0 ⁇ w ⁇ 1, (x + y + z + v + w)> 0) is provided, and the back surface 1a of the semiconductor substrate 1 is also provided with a dielectric such as a silicon oxide film or a silicon nitride film.
  • a body membrane 67 is provided.
  • a diffusion mask 62 is provided on each of the light receiving surface and the back surface 1a of the semiconductor substrate 1, and an opening 61a is provided in a part of the diffusion suppression mask 62 on the back surface 1a of the semiconductor substrate 1.
  • the formation method of the opening part 61a is not specifically limited, For example, methods, such as photolithography, can be used.
  • An n-type impurity is diffused to form a first conductivity type region 63 which is an n-type impurity diffusion region.
  • the n-type impurity-containing gas 64 for example, POCl 3 containing phosphorus which is an n-type impurity can be used.
  • the n-type impurity diffusion region may be a region having an n-type impurity concentration higher than that of the semiconductor substrate 1.
  • the diffusion suppression mask 62 is provided again on the entire surface of the light receiving surface and the back surface 1a of the semiconductor substrate 1, and FIG. As shown, an opening 61 b is provided in a part of the diffusion suppression mask 62 on the back surface 1 a of the semiconductor substrate 1.
  • p-type impurity-containing gas 66 by flowing a p-type impurity-containing gas 66, p-type is applied to the back surface 1 a of the semiconductor substrate 1 exposed from the opening 61 b of the diffusion suppression mask 62 on the back surface 1 a of the semiconductor substrate 1. Impurities are diffused to form a second conductivity type region 65 which is a p-type impurity diffusion region.
  • the light receiving surface of the semiconductor substrate 1 is subjected to texture etching, acid etching, and round etching in this order on the light receiving surface of the semiconductor substrate 1 in the same manner as in the first to third embodiments.
  • a plurality of convex portions 11 and concave portions 12 between the convex portions 11 are formed on the surface.
  • the angle of the inclined surface 11c of the convex portion 11 is the above-mentioned angle (greater than 49.5 °, 55.2 ° or less, preferably 50 ° or more, more preferably 52.9 ° or more, preferably Is 53.5 ° or less), and the curvature radius of the curved surface at the bottom of the recess 12 is such that the above-mentioned curvature radius (greater than 13 nm, preferably 80 nm or less, more preferably 65 nm or less) is satisfied.
  • contact holes 70 and 71 are formed by removing a part of the dielectric film 67 on the back surface 1 a of the semiconductor substrate 1.
  • the formation method of the contact holes 70 and 71 is not specifically limited, For example, methods, such as photolithography, can be used.
  • the first electrode 6 is formed on the first conductivity type region 63 through the contact hole 70, and the second electrode 7 is formed on the second conductivity type region 65 through the contact hole 71. . Thereby, the back electrode type solar cell of Embodiment 4 can be obtained.
  • an n-type impurity diffusion region is formed as the first conductivity type region 63 and a p-type impurity diffusion region is formed as the second conductivity type region 65.
  • a p-type impurity diffusion is used as the first conductivity type region 63.
  • a region may be formed, and an n-type impurity diffusion region may be formed as the second conductivity type region 65.
  • FIG. 29 is a schematic cross-sectional view of a double-sided electrode type solar battery cell of Embodiment 5, which is another example of the photoelectric conversion element of the embodiment.
  • a double-sided electrode solar cell of Embodiment 5 includes a semiconductor substrate 1 made of a single crystal silicon substrate such as an n-type single crystal silicon substrate similar to that of Embodiment 1, and the semiconductor substrate 1
  • a first conductivity type region 63 on the back surface 1 a serving as the back surface and a second conductivity type region 65 on the light receiving surface of the semiconductor substrate 1 are provided.
  • a first electrode 7 is provided on the first conductivity type region 63, and a second electrode 8 is provided on the second conductivity type region 65.
  • the double-sided electrode type solar battery cell of Embodiment 5 can be manufactured as follows, for example. First, similarly to the first to fourth embodiments, by performing texture etching, acid etching, and round etching in this order on the light receiving surface of the semiconductor substrate 1, a plurality of protrusions 11 are formed on the light receiving surface of the semiconductor substrate 1. And the concave portion 12 between the convex portions 11.
  • the angle of the inclined surface 11c of the convex portion 11 is the above-mentioned angle (greater than 49.5 °, 55.2 ° or less, preferably 50 ° or more, more preferably 52.9 ° or more, preferably Is 53.5 ° or less), and the curvature radius of the curved surface at the bottom of the recess 12 is such that the above-mentioned curvature radius (greater than 13 nm, preferably 80 nm or less, more preferably 65 nm or less) is satisfied.
  • the first conductivity type region 63 is formed on the back surface 1 a of the semiconductor substrate 1, and the second conductivity type region 65 is formed on the light receiving surface of the semiconductor substrate 1. Thereafter, a dielectric film 9 d is formed on the second conductivity type region 65.
  • the double-sided electrode solar cell of Embodiment 5 can be obtained.
  • n-type silicon single crystal ingot was cut with a wire saw to cut out an n-type silicon single crystal substrate.
  • texture etching is performed on the surface of the n-type silicon single crystal substrate by alkaline etching using an aqueous sodium hydroxide solution, and a plurality of quadrangular pyramidal convex portions and convex portions are formed on the surface of the n-type silicon single crystal substrate. A recess was formed between them.
  • substrate of Experimental example 1 was obtained by performing the acid etching using the hydrogen fluoride aqueous solution about the surface of the n-type silicon single crystal substrate in which the convex part and the recessed part were formed by texture etching.
  • a volume of (a nitric acid aqueous solution having a nitric acid concentration of 60 mass%): volume of water 1: 100: 50) for 180 seconds to obtain a substrate of Experimental Example 2.
  • a mixed acid hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass
  • the substrate of Experimental Example 1 had the highest reflectance with respect to incident light. Further, the substrate of Experimental Example 3 had the lowest reflectance, and the reflectance increased in the order of Experimental Example 4 and Experimental Example 2.
  • the average value of the angle ⁇ of the inclined surface of the convex portion of the substrate of Experimental Example 1 is 49.5 °
  • the average value of the angle ⁇ of the inclined surface of the convex portion of the substrate of Experimental Example 2 is It was confirmed to be 52.9 °.
  • the average value of the angle ⁇ of the inclined surface of the convex portion of the substrate of Experimental Example 3 is 55.2 °
  • the average value of the angle ⁇ of the inclined surface of the convex portion of the substrate of Experimental Example 4 is 54.3 °. It was confirmed that there was.
  • the angle ⁇ of the inclined surface of the convex portion of the substrate is more than 49.5 °. It was confirmed that it was 55.2 ° or less, preferably 52.9 ° or more and 55.2 ° or less.
  • the surface of the substrate after the acid etching in Experimental Example 1 was further mixed with about 42 ° C. mixed acid (hydrofluoric acid (hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass%)) containing hydrofluoric acid, nitric acid, and water.
  • Mixed acid hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass%
  • the surface of the substrate after acid etching in Experimental Example 1 is further mixed with about 42 ° C. mixed acid (hydrofluoric acid (hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass%)) containing hydrofluoric acid, nitric acid, and water.
  • mixed acid hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass%
  • FIG. 33 shows a schematic enlarged cross-sectional view of the substrate of Experimental Example 1
  • FIG. 34 shows a schematic enlarged cross-sectional view of the cross section of the substrate of Experimental Example 5.
  • FIG. 35 shows a schematic enlarged cross-sectional view of the substrate of Experimental Example 8
  • FIG. 36 shows a schematic enlarged cross-sectional view of the substrate of Experimental Example 9.
  • the embodiment disclosed herein includes a plurality of convex portions and concave portions between the convex portions on the surface, the convex portions include an inclined surface, the concave portion includes a curved bottom, and the angle of the inclined surface.
  • the convex portions include an inclined surface
  • the concave portion includes a curved bottom
  • the angle of the inclined surface Is a semiconductor substrate having a curvature radius of the curved surface larger than 13 nm. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the angle is preferably 50 ° or more, and more preferably 52.9 ° or more. In this case, a photoelectric conversion element with higher characteristics can be obtained.
  • the angle is preferably 53.5 ° or less. In this case, a photoelectric conversion element with higher characteristics can be obtained.
  • the radius of curvature is preferably 80 nm or more. In this case, a photoelectric conversion element with higher characteristics can be obtained.
  • the radius of curvature is preferably 65 nm or less. In this case, it is possible to obtain a photoelectric conversion element having higher characteristics.
  • the convex portion may have a quadrangular pyramid shape. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the semiconductor substrate of the embodiment disclosed herein may include a film on the recess. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the film is made of SiC x N y O z F v H w (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1, 0 ⁇ v).
  • ⁇ 1, 0 ⁇ w ⁇ 1, (x + y + z + v + w)> 0) may be included. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the film may include an amorphous semiconductor film. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the amorphous semiconductor film may include amorphous silicon. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the semiconductor substrate of the embodiment disclosed herein may have an n-type or p-type conductivity type. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the semiconductor substrate of the embodiment disclosed herein may be an n-type single crystal silicon substrate.
  • the semiconductor substrate of the embodiment disclosed herein may include the above-described semiconductor substrate.
  • a photoelectric conversion element includes a semiconductor film, a first electrode on a first conductive amorphous semiconductor film, and a second electrode on a second conductive amorphous semiconductor film. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the photoelectric conversion element of the embodiment disclosed herein may further include a first i-type amorphous semiconductor film between the first conductive type amorphous semiconductor film and the second surface. Good. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the photoelectric conversion element of the embodiment disclosed herein may further include a second i-type amorphous semiconductor film between the second conductive type amorphous semiconductor film and the second surface. Good. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the embodiment disclosed herein includes the semiconductor substrate, the first conductivity type region and the second conductivity type region on the second surface opposite to the surface of the semiconductor substrate, and the first conductivity type region.
  • a photoelectric conversion element comprising the upper first electrode and the second electrode on the second conductivity type region. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • An embodiment disclosed herein includes the above-described semiconductor substrate, a first conductivity type region on a surface of the semiconductor substrate, and a second conductivity type region on a second surface opposite to the surface of the semiconductor substrate.
  • a photoelectric conversion element including a first electrode on the first conductivity type region and a second electrode on the second conductivity type region. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the embodiment disclosed herein includes a step of forming a plurality of convex portions and concave portions between the convex portions on the surface of the semiconductor substrate, and a step of performing acid etching on the surface where the convex portions and the concave portions are formed. And a step of performing round etching of the surface after acid etching, and in the step of performing round etching, the angle of the inclined surface of the convex portion is set to be larger than 49.5 ° and not larger than 55.2 °, and the bottom of the concave portion.
  • This is a method for manufacturing a semiconductor substrate, wherein the radius of curvature of the curved surface is larger than 13 nm. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the angle is preferably 50 ° or more, and more preferably 52.9 ° or more. In this case, a photoelectric conversion element with higher characteristics can be obtained.
  • the angle is preferably 53.5 ° or less. In this case, a photoelectric conversion element with higher characteristics can be obtained.
  • the radius of curvature is 80 nm or less. In this case, a photoelectric conversion element with higher characteristics can be obtained.
  • the radius of curvature is 65 nm or less. In this case, it is possible to obtain a photoelectric conversion element having higher characteristics.
  • the semiconductor substrate manufacturing method of the embodiment disclosed herein may further include a step of forming a film on the recess. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the film is made of SiC x N y O z F v H w (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1, 0 ⁇ v ⁇ 1, 0 ⁇ w ⁇ 1, (x + y + z + v + w)> 0) may be included. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the film may include an amorphous semiconductor film. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the amorphous semiconductor film may contain amorphous silicon. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the semiconductor substrate may have an n-type or p-type conductivity type. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the semiconductor substrate includes silicon, and the step of forming the convex portion and the concave portion may include a step of alkali etching the surface of the semiconductor substrate. Good. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the alkali etching step may be performed using an alkaline solution containing at least one of a sodium hydroxide aqueous solution and a potassium hydroxide aqueous solution. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the step of performing acid etching may be performed using a hydrogen fluoride aqueous solution. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the step of performing round etching is preferably performed using a mixed acid containing hydrofluoric acid, nitric acid, and water. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the ratio of the volume of nitric acid to the volume of hydrofluoric acid is preferably 70 or more and 100 or less. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the ratio of the volume of water to the volume of hydrofluoric acid is preferably 35 or more and 50 or less. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method for manufacturing a semiconductor substrate, and a surface of the semiconductor substrate.
  • a method for manufacturing a photoelectric conversion element includes a step of forming and a step of forming a second electrode on a second conductivity type amorphous semiconductor film. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the method for manufacturing a photoelectric conversion element according to the embodiment disclosed herein further includes a step of forming a first i-type amorphous semiconductor film on the second surface, and the first conductivity-type amorphous
  • the semiconductor film may be formed on the first i-type amorphous semiconductor film. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein further includes a step of forming a second i-type amorphous semiconductor film on the second surface, and the second conductivity-type amorphous
  • the semiconductor film may be formed on the second i-type amorphous semiconductor film. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • the embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method for manufacturing a semiconductor substrate, and a surface of the semiconductor substrate. Forming a first conductivity type region and a second conductivity type region on the second surface on the opposite side, forming a first electrode on the first conductivity type region, and forming a first electrode on the second conductivity type region. And a process of forming two electrodes. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • An embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method for manufacturing a semiconductor substrate, and Forming a first conductivity type region; forming a second conductivity type region on a second surface opposite to the surface of the semiconductor substrate; and forming a first electrode on the first conductivity type region. And a step of forming a second electrode on the second conductivity type region. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.
  • inventions disclosed herein can be used for semiconductor substrates such as silicon substrates and their manufacture, and photoelectric conversion elements such as solar cells and their manufacture.
  • SYMBOLS 1 Semiconductor substrate, 1a back surface, 1st i-type amorphous semiconductor film, 3rd 1st conductivity type amorphous semiconductor film, 4th 2nd i-type amorphous semiconductor film, 5nd 2nd conductivity type amorphous Semiconductor film, 6 first electrode, 7 second electrode, 9a amorphous silicon film, 9b SiN film, 9c silicon carbide (SiC) film, 9d dielectric film, 11 convex portion, 11c inclined surface, 11d bottom surface, 11e line , 11f apex, 12 recesses, 31, 32 etching mask, 61a, 61b opening, 62 diffusion suppression mask, 63 first conductivity type region, 64 n-type impurity containing gas, 65 second conductivity type region, 66 p-type impurity containing Gas, 67 dielectric film, 70, 71 contact holes.

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Abstract

This semiconductor substrate is provided with, in the surface thereof, a plurality of protruding sections (11) and recessed sections (12) among the protruding sections (11). Each of the protruding sections (11) is provided with sloped surfaces (11c). Each of the recessed sections (12) is provided with the bottom of a bent surface. The angle of the sloped surfaces (11c) of the protruding sections (11) is larger than 49.5° but equal to or smaller than 55.2°. The curvature radius of the bent surface of each of the recessed sections (12) is larger than 13 nm.

Description

半導体基板、光電変換素子、半導体基板の製造方法および光電変換素子の製造方法Semiconductor substrate, photoelectric conversion element, semiconductor substrate manufacturing method, and photoelectric conversion element manufacturing method

 本出願は、2015年9月24日に出願された特願2015-186521号に対して、優先権の利益を主張するものであり、それを参照することにより、その内容のすべてを本書に含める。 This application claims the benefit of priority to Japanese Patent Application No. 2015-186521 filed on Sep. 24, 2015, and the contents of which are incorporated herein by reference. .

 本発明は、半導体基板、半導体基板の製造方法および光電変換素子の製造方法に関する。 The present invention relates to a semiconductor substrate, a method for manufacturing a semiconductor substrate, and a method for manufacturing a photoelectric conversion element.

 太陽光エネルギを電気エネルギに直接変換する太陽電池は、近年、特に、地球環境問題の観点から、次世代のエネルギ源としての期待が急激に高まっている。太陽電池には、化合物半導体または有機材料を用いたものなど様々な種類のものがあるが、現在、主流となっているのは、シリコン結晶を用いたものである。 In recent years, expectations for solar cells that directly convert solar energy into electrical energy have increased rapidly, especially from the viewpoint of global environmental problems. There are various types of solar cells, such as those using compound semiconductors or organic materials, but the mainstream is currently using silicon crystals.

 現在、最も多く製造および販売されている太陽電池は、太陽光が入射する側の面である受光面と、受光面の反対側である裏面とにそれぞれ電極が形成された構造のものである。 Currently, the most manufactured and sold solar cells have a structure in which electrodes are formed on a light receiving surface that is a surface on which sunlight is incident and a back surface that is opposite to the light receiving surface, respectively.

 しかしながら、受光面に電極を形成した場合には、電極における太陽光の反射および吸収があることから、電極の面積分だけ入射する太陽光の量が減少する。そのため、裏面のみに電極を形成した太陽電池の開発も進められている。 However, when an electrode is formed on the light receiving surface, sunlight is reflected and absorbed by the electrode, so that the amount of incident sunlight is reduced by the area of the electrode. For this reason, development of solar cells in which electrodes are formed only on the back surface is also underway.

 たとえば、特許第3271990号公報(特許文献1)には、異方性エッチングにより表面に多数のピラミッド状の凹凸部が形成された結晶系シリコン基板と、この凹凸部上に化学的気相成長法により設けられた非晶質或いは微結晶シリコン層と、を備え、基板の表面に設けられたピラミッド状の凹凸部の谷の部分が丸く形成されていることを特徴とする光起電力素子が開示されている(たとえば特許文献1の請求項1等)。 For example, Japanese Patent No. 3271990 (Patent Document 1) discloses a crystalline silicon substrate having a large number of pyramidal irregularities formed on the surface by anisotropic etching, and a chemical vapor deposition method on the irregularities. A photovoltaic element comprising: an amorphous or microcrystalline silicon layer provided by the step; and a valley portion of a pyramidal uneven portion provided on a surface of a substrate is formed in a round shape. (For example, claim 1 of Patent Document 1).

特許第3271990号公報Japanese Patent No. 3271990

 しかしながら、特許文献1に記載の光起電力素子においては、高い特性が得られないことがあった。 However, in the photovoltaic element described in Patent Document 1, high characteristics may not be obtained.

 また、特許文献1に記載の光起電力素子の凹凸部上に膜を形成した場合には、当該凹凸部上に形成された膜にクラックが入り、特性が低下することもあった。 In addition, when a film is formed on the concavo-convex portion of the photovoltaic element described in Patent Document 1, the film formed on the concavo-convex portion may crack and the characteristics may deteriorate.

 ここで開示された実施形態は、複数の凸部と凸部の間の凹部とを表面に備え、凸部は傾斜面を備え、凹部は曲面の底を備え、傾斜面の角度が49.5°よりも大きく55.2°以下であって、曲面の曲率半径が13nmよりも大きい半導体基板である。 The embodiment disclosed herein includes a plurality of convex portions and a concave portion between the convex portions on the surface, the convex portion includes an inclined surface, the concave portion includes a curved bottom, and the angle of the inclined surface is 49.5. It is a semiconductor substrate that is larger than 5 ° and smaller than or equal to 55.2 ° and has a curved radius of curvature larger than 13 nm.

 ここで開示された実施形態は、上記の半導体基板と、半導体基板の表面とは反対側の第2の表面上の第1導電型非晶質半導体膜および第2導電型非晶質半導体膜と、第1導電型非晶質半導体膜上の第1電極と、第2導電型非晶質半導体膜上の第2電極と、を備えた、光電変換素子である。 The embodiment disclosed herein includes the above-described semiconductor substrate, and a first conductivity type amorphous semiconductor film and a second conductivity type amorphous semiconductor film on a second surface opposite to the surface of the semiconductor substrate, A photoelectric conversion element comprising a first electrode on the first conductive type amorphous semiconductor film and a second electrode on the second conductive type amorphous semiconductor film.

 ここで開示された実施形態は、上記の半導体基板と、半導体基板の表面とは反対側の第2の表面の第1導電型領域および第2導電型領域と、第1導電型領域上の第1電極と、第2導電型領域上の第2電極と、を備えた、光電変換素子である。 The embodiment disclosed herein includes the semiconductor substrate, the first conductivity type region and the second conductivity type region on the second surface opposite to the surface of the semiconductor substrate, and the first conductivity type region on the first conductivity type region. It is a photoelectric conversion element provided with 1 electrode and the 2nd electrode on a 2nd conductivity type area | region.

 ここで開示された実施形態は、上記の半導体基板と、半導体基板の表面の第1導電型領域と、半導体基板の表面とは反対側の第2の表面の第2導電型領域と、第1導電型領域上の第1電極と、第2導電型領域上の第2電極と、を備えた、光電変換素子である。 The embodiment disclosed herein includes the semiconductor substrate, the first conductivity type region on the surface of the semiconductor substrate, the second conductivity type region on the second surface opposite to the surface of the semiconductor substrate, and the first It is a photoelectric conversion element provided with the 1st electrode on a conductivity type area | region, and the 2nd electrode on a 2nd conductivity type area | region.

 ここで開示された実施形態は、上記の半導体基板を備えた、光電変換素子である。
 ここで開示された実施形態は、半導体基板の表面に、複数の凸部と凸部の間の凹部とを形成する工程と、凸部および凹部が形成された表面の酸エッチングを行う工程と、酸エッチング後の表面のラウンドエッチングを行う工程と、を含み、ラウンドエッチングを行う工程において、凸部の傾斜面の角度を49.5°よりも大きく55.2°以下とし、凹部の底の曲面の曲率半径を13nmよりも大きくする半導体基板の製造方法である。
Embodiment disclosed here is a photoelectric conversion element provided with said semiconductor substrate.
The embodiment disclosed herein includes a step of forming a plurality of convex portions and concave portions between the convex portions on the surface of the semiconductor substrate, a step of performing acid etching of the surface on which the convex portions and the concave portions are formed, Performing a round etching of the surface after the acid etching, and in the step of performing the round etching, the angle of the inclined surface of the convex portion is set to be larger than 49.5 ° and not more than 55.2 °, and the curved surface of the bottom of the concave portion This is a method for manufacturing a semiconductor substrate in which the radius of curvature is larger than 13 nm.

 ここで開示された実施形態は、上記の半導体基板の製造方法により表面に複数の凸部と凸部の間の凹部とを備えた半導体基板を形成する工程と、半導体基板の表面とは反対側の第2の表面上に第1導電型非晶質半導体膜および第2導電型非晶質半導体膜を形成する工程と、第1導電型非晶質半導体膜上に第1電極を形成する工程と、第2導電型非晶質半導体膜上に第2電極を形成する工程と、を含む、光電変換素子の製造方法である。 The embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the above-described method of manufacturing a semiconductor substrate, and a side opposite to the surface of the semiconductor substrate Forming a first conductive type amorphous semiconductor film and a second conductive type amorphous semiconductor film on the second surface, and forming a first electrode on the first conductive type amorphous semiconductor film And a step of forming a second electrode on the second conductivity type amorphous semiconductor film.

 ここで開示された実施形態は、上記の半導体基板の製造方法により表面に複数の凸部と凸部の間の凹部とを備えた半導体基板を形成する工程と、半導体基板の表面とは反対側の第2の表面に第1導電型領域および第2導電型領域を形成する工程と、第1導電型領域上に第1電極を形成する工程と、第2導電型領域上に第2電極を形成する工程と、を含む、光電変換素子の製造方法である。 The embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the above-described method of manufacturing a semiconductor substrate, and a side opposite to the surface of the semiconductor substrate Forming a first conductivity type region and a second conductivity type region on the second surface, forming a first electrode on the first conductivity type region, and forming a second electrode on the second conductivity type region. A process for forming the photoelectric conversion element.

 ここで開示された実施形態は、上記の半導体基板の製造方法により表面に複数の凸部と凸部の間の凹部とを備えた半導体基板を形成する工程と、半導体基板の表面に第1導電型領域を形成する工程と、半導体基板の表面とは反対側の第2の表面に第2導電型領域を形成する工程と、第1導電型領域上に第1電極を形成する工程と、第2導電型領域上に第2電極を形成する工程と、を含む、光電変換素子の製造方法である。 The embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method for manufacturing a semiconductor substrate, and a first conductive material on the surface of the semiconductor substrate. A step of forming a mold region, a step of forming a second conductivity type region on a second surface opposite to the surface of the semiconductor substrate, a step of forming a first electrode on the first conductivity type region, And a step of forming a second electrode on the two-conductivity type region.

 ここで開示された実施形態によれば、高い特性の光電変換素子を製造することができる。 According to the embodiment disclosed herein, a photoelectric conversion element having high characteristics can be manufactured.

実施形態1のヘテロ接合バックコンタクトセルの模式的な断面図である。3 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの半導体基板の受光面の凸部の一例の模式的な拡大斜視図である。3 is a schematic enlarged perspective view of an example of a convex portion of a light receiving surface of a semiconductor substrate of the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの半導体基板の受光面の凸部の一例の模式的な拡大断面図である。3 is a schematic enlarged cross-sectional view of an example of a convex portion of a light receiving surface of a semiconductor substrate of a heterojunction back contact cell according to Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの半導体基板の受光面の凹部の一例の模式的な拡大断面図である。3 is a schematic enlarged cross-sectional view of an example of a recess of a light receiving surface of a semiconductor substrate of a heterojunction back contact cell according to Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態2のヘテロ接合型バックコンタクトセルの模式的な断面図である。6 is a schematic cross-sectional view of a heterojunction back contact cell of Embodiment 2. FIG. 実施形態3のヘテロ接合型バックコンタクトセルの模式的な断面図である。6 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 3. FIG. 実施形態4の裏面電極型太陽電池セルの模式的な断面図である。6 is a schematic cross-sectional view of a back electrode type solar battery cell according to Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態4の裏面電極型太陽電池セルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。10 is a schematic cross-sectional view illustrating a part of the manufacturing process of an example of the manufacturing method of the back electrode type solar battery cell of Embodiment 4. FIG. 実施形態5の両面電極型太陽電池セルの模式的な断面図である。6 is a schematic cross-sectional view of a double-sided electrode type solar battery cell of Embodiment 5. FIG. 実験例1~4の基板に入射する光の波長と反射率との関係の調査結果である。FIG. 6 is a result of investigating the relationship between the wavelength of light incident on the substrates of Experimental Examples 1 to 4 and the reflectance. FIG. 実験例1~4の基板の表面の凸部の傾斜面の角度αの平均値を示す図である。FIG. 6 is a diagram showing an average value of angles α of inclined surfaces of convex portions on the surface of substrates in Experimental Examples 1 to 4. 実験例1のヘテロ接合型バックコンタクトセルの逆方向飽和電流密度を1としたときの実験例2および5~7のヘテロ接合型バックコンタクトセルの逆方向飽和電流密度のそれぞれの相対値である。FIG. 7 shows the relative values of the reverse saturation current densities of Experimental Example 2 and 5-7, where the reverse saturation current density of the heterojunction back contact cell of Experimental Example 1 is 1. FIG. 実験例1の基板の模式的な拡大断面図である。4 is a schematic enlarged cross-sectional view of a substrate of Experimental Example 1. FIG. 実験例5の基板の模式的な拡大断面図である。10 is a schematic enlarged cross-sectional view of a substrate of Experimental Example 5. FIG. 実験例8の基板の模式的な拡大断面図である。10 is a schematic enlarged cross-sectional view of a substrate of Experimental Example 8. FIG. 実験例9の基板の模式的な拡大断面図である。It is a typical expanded sectional view of the board | substrate of Experimental example 9. FIG. 実験例1、5、8および9の基板の表面の凹部の底の曲面の曲率半径の測定結果である。It is a measurement result of the curvature radius of the curved surface of the bottom of the recessed part of the surface of the board | substrate of Experimental example 1, 5, 8 and 9. FIG.

 以下、実施形態について説明する。なお、実施形態の説明に用いられる図面において、同一の参照符号は、同一部分または相当部分を表わすものとする。 Hereinafter, embodiments will be described. In the drawings used to describe the embodiments, the same reference numerals represent the same or corresponding parts.

 [実施形態1]
 図1に、実施形態の光電変換素子の一例である実施形態1のヘテロ接合バックコンタクトセルの模式的な断面図を示す。実施形態1のヘテロ接合型バックコンタクトセルは、半導体基板1と、半導体基板1の第1の表面である受光面に設けられた複数の凸部11と、凸部11の間の凹部12と、凸部11および凹部12上の非晶質シリコン膜9aと、を備えている。なお、非晶質シリコン膜9aとしては、たとえば、i型非晶質シリコン膜、n型非晶質シリコン膜、または受光面側からi型非晶質シリコン膜とn型非晶質シリコン膜とがこの順に積層された積層体などを用いることができる。
[Embodiment 1]
FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1 which is an example of the photoelectric conversion element of the embodiment. The heterojunction back contact cell of Embodiment 1 includes a semiconductor substrate 1, a plurality of convex portions 11 provided on a light receiving surface that is a first surface of the semiconductor substrate 1, and concave portions 12 between the convex portions 11. And an amorphous silicon film 9 a on the convex portion 11 and the concave portion 12. As the amorphous silicon film 9a, for example, an i-type amorphous silicon film, an n-type amorphous silicon film, or an i-type amorphous silicon film and an n-type amorphous silicon film from the light receiving surface side are used. Can be used.

 また、実施形態1のヘテロ接合型バックコンタクトセルは、半導体基板1の第1の表面とは反対側の第2の表面である裏面1a上の第1のi型非晶質半導体膜2および第2のi型非晶質半導体膜4と、第1のi型非晶質半導体膜2上の第1導電型非晶質半導体膜3と、第2のi型非晶質半導体膜4上の第2導電型非晶質半導体膜5と、第1導電型非晶質半導体膜3上の第1電極6と、第2導電型非晶質半導体膜5上の第2電極7とを備えている。 Further, the heterojunction back contact cell of Embodiment 1 includes the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 2 on the back surface 1a which is the second surface opposite to the first surface of the semiconductor substrate 1. 2 i-type amorphous semiconductor film 4, first conductivity-type amorphous semiconductor film 3 on first i-type amorphous semiconductor film 2, and second i-type amorphous semiconductor film 4 A second conductive type amorphous semiconductor film 5, a first electrode 6 on the first conductive type amorphous semiconductor film 3, and a second electrode 7 on the second conductive type amorphous semiconductor film 5 are provided. Yes.

 実施形態1においては、半導体基板1はn型の単結晶シリコン基板であり、第1のi型非晶質半導体膜2および第2のi型非晶質半導体膜4はそれぞれi型非晶質シリコン膜であり、第1導電型非晶質半導体膜3はp型非晶質シリコン膜であり、第2導電型非晶質半導体膜5はn型非晶質シリコン膜である場合について説明するが、これに限定されないことは言うまでもない。 In the first embodiment, the semiconductor substrate 1 is an n-type single crystal silicon substrate, and the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 4 are respectively i-type amorphous. A case where the first conductive type amorphous semiconductor film 3 is a p-type amorphous silicon film and the second conductive type amorphous semiconductor film 5 is an n-type amorphous silicon film will be described. However, it goes without saying that the present invention is not limited to this.

 なお、本実施形態において、「i型」は、完全な真性の状態だけでなく、十分に低濃度(n型不純物濃度が1×1015個/cm3未満、かつp型不純物濃度が1×1015個/cm3未満)であればn型またはp型の不純物が混入された状態のものも含む意味である。また、本実施形態において、「n型」は、n型不純物濃度が1×1015個/cm3以上の状態を意味し、「p型」は、p型不純物濃度が1×1015個/cm3以上の状態を意味する。n型不純物濃度およびp型不純物濃度は、たとえば二次イオン質量分析(SIMS)によって測定することができる。 In the present embodiment, “i-type” is not only a completely intrinsic state but also a sufficiently low concentration (n-type impurity concentration is less than 1 × 10 15 / cm 3 and p-type impurity concentration is 1 × (Less than 10 15 / cm 3 ) is meant to include n-type or p-type impurities. In the present embodiment, “n-type” means a state where the n-type impurity concentration is 1 × 10 15 / cm 3 or more, and “p-type” means that the p-type impurity concentration is 1 × 10 15 / cm 3. It means a state of cm 3 or more. The n-type impurity concentration and the p-type impurity concentration can be measured by, for example, secondary ion mass spectrometry (SIMS).

 また、本実施形態において、「非晶質シリコン」には、シリコン原子の未結合手が水素で終端されていない非晶質シリコンだけでなく、水素化非晶質シリコンなどのシリコン原子の未結合手が水素等で終端されたものも含まれるものとする。 In this embodiment, “amorphous silicon” includes not only amorphous silicon in which the dangling bonds of silicon atoms are not terminated with hydrogen, but also dangling of silicon atoms such as hydrogenated amorphous silicon. It also includes those whose hands are terminated with hydrogen or the like.

 図2に、実施形態1のヘテロ接合型バックコンタクトセルの半導体基板1の受光面の凸部11の一例の模式的な拡大斜視図を示す。本実施形態においては、半導体基板1の受光面にテクスチャ構造が設けられた場合について説明するが、これに限定されない。なお、半導体基板1の受光面にテクスチャ構造が設けられた場合には、半導体基板1の受光面の凸部11は四角錐形状を有し得る。 FIG. 2 shows a schematic enlarged perspective view of an example of the convex portion 11 of the light receiving surface of the semiconductor substrate 1 of the heterojunction back contact cell of the first embodiment. In the present embodiment, a case where a texture structure is provided on the light receiving surface of the semiconductor substrate 1 will be described, but the present invention is not limited to this. In addition, when the texture structure is provided in the light-receiving surface of the semiconductor substrate 1, the convex part 11 of the light-receiving surface of the semiconductor substrate 1 may have a quadrangular pyramid shape.

 本実施形態において、凸部11は、半導体基板1の裏面1aに略平行な四角形状の底面11dと、底面11d上に底面11dに傾斜するようにして設けられた三角形状の4つの傾斜面11cとを有している。1つの傾斜面11cは、その両側にそれぞれ1つずつの傾斜面11cと隣り合って接している。また、凸部11は、隣り合う2つの傾斜面11cが互いに接する線11eを4本と、これらの4本の線11eの交点である頂点11fとを有している。 In the present embodiment, the convex portion 11 includes a quadrangular bottom surface 11d substantially parallel to the back surface 1a of the semiconductor substrate 1, and four triangular inclined surfaces 11c provided on the bottom surface 11d so as to incline to the bottom surface 11d. And have. One inclined surface 11c is adjacent to and in contact with one inclined surface 11c on each side thereof. The convex portion 11 has four lines 11e where two adjacent inclined surfaces 11c are in contact with each other, and a vertex 11f which is an intersection of these four lines 11e.

 図3に、実施形態1のヘテロ接合型バックコンタクトセルの半導体基板の受光面の凸部11の一例の模式的な拡大断面図を示す。本実施形態において、凸部11の傾斜面11cの角度は、たとえば図3に示すように、凸部11の線11eと底面11dとが為す角度αと定義される。 FIG. 3 shows a schematic enlarged cross-sectional view of an example of the convex portion 11 of the light receiving surface of the semiconductor substrate of the heterojunction back contact cell of the first embodiment. In the present embodiment, the angle of the inclined surface 11c of the convex portion 11 is defined as an angle α formed by the line 11e and the bottom surface 11d of the convex portion 11, for example, as shown in FIG.

 図4に、実施形態1のヘテロ接合型バックコンタクトセルの半導体基板の受光面の凹部12の一例の模式的な拡大断面図を示す。本実施形態において、凹部12の底の曲面の曲率半径は凹部12の両側に位置する凸部11の線11eを接線とする仮想円11gの半径rと定義される。 FIG. 4 shows a schematic enlarged cross-sectional view of an example of the recess 12 on the light receiving surface of the semiconductor substrate of the heterojunction back contact cell of the first embodiment. In the present embodiment, the radius of curvature of the curved surface at the bottom of the recess 12 is defined as the radius r of the virtual circle 11g having the line 11e of the projection 11 located on both sides of the recess 12 as a tangent.

 本実施形態において、凸部11の傾斜面11cの角度は、49.5°よりも大きく55.2°以下とされる。凸部11の傾斜面11cの角度が49.5°よりも大きく55.2°以下である場合には、半導体基板1の受光面に入射した光を十分に半導体基板1の内部に取り入れることができるため、高い特性を得ることが可能となる。 In the present embodiment, the angle of the inclined surface 11c of the convex portion 11 is greater than 49.5 ° and not greater than 55.2 °. When the angle of the inclined surface 11c of the convex portion 11 is larger than 49.5 ° and not larger than 55.2 °, the light incident on the light receiving surface of the semiconductor substrate 1 can be sufficiently taken into the semiconductor substrate 1. Therefore, high characteristics can be obtained.

 また、本実施形態において、凸部11の傾斜面11cの角度は、50°以上であることが好ましく、52.9°以上であることがより好ましい。この場合には、半導体基板1の受光面に入射した光をより多く半導体基板1の内部に取り入れることができるため、より高い特性を得ることが可能となる。 Further, in the present embodiment, the angle of the inclined surface 11c of the convex portion 11 is preferably 50 ° or more, and more preferably 52.9 ° or more. In this case, since more light incident on the light receiving surface of the semiconductor substrate 1 can be taken into the semiconductor substrate 1, higher characteristics can be obtained.

 また、本実施形態において、凸部11の傾斜面11cの角度は、53.5°以下であることが好ましい。凸部11の傾斜面11cの角度が53.5°以下である場合には、半導体基板1の受光面に入射した光をより多く半導体基板1の内部に取り入れることができるため、より高い特性を得ることが可能となる。 Moreover, in this embodiment, it is preferable that the angle of the inclined surface 11c of the convex part 11 is 53.5 degrees or less. When the angle of the inclined surface 11c of the convex portion 11 is 53.5 ° or less, more light incident on the light receiving surface of the semiconductor substrate 1 can be taken into the semiconductor substrate 1, and thus higher characteristics can be obtained. Can be obtained.

 本実施形態において、凹部12の底の曲面の曲率半径は、13nmよりも大きくされる。凹部12の底の曲面の曲率半径が13nmよりも大きい場合には、凹部12上の膜にクラックが発生するのを低減することができるため、凹部12上の膜にクラックが形成されることに起因する特性の低下を抑制することができる。なお、本実施形態において、膜にクラックが形成されることに起因する特性の低下としては、たとえば反射率の低下に起因する特性の低下、および膜のパッシベーション性の低下に起因する特性の低下などを挙げることができる。 In this embodiment, the curvature radius of the curved surface at the bottom of the recess 12 is set to be larger than 13 nm. When the curvature radius of the curved surface at the bottom of the recess 12 is larger than 13 nm, it is possible to reduce the occurrence of cracks in the film on the recess 12, and therefore cracks are formed in the film on the recess 12. The resulting deterioration in characteristics can be suppressed. In this embodiment, the deterioration of the characteristics due to the formation of cracks in the film includes, for example, the deterioration of the characteristics due to the decrease in reflectivity and the deterioration of the characteristics due to the decrease in the passivation property of the film. Can be mentioned.

 また、本実施形態において、凹部12の底の曲面の曲率半径は、80nm以下であることが好ましい。この場合には、凹部12上の膜にクラックが発生するのをより低減することができるため、凹部12上の膜にクラックが形成されることに起因する特性の低下をより抑制することができる。 In the present embodiment, the radius of curvature of the curved surface at the bottom of the recess 12 is preferably 80 nm or less. In this case, since it is possible to further reduce the occurrence of cracks in the film on the recess 12, it is possible to further suppress deterioration in characteristics due to the formation of cracks in the film on the recess 12. .

 また、本実施形態において、凹部12の底の曲面の曲率半径は、65nm以下であることが好ましい。この場合には、凹部12上の膜にクラックが発生するのをさらに低減することができるため、凹部12上の膜にクラックが形成されることに起因する特性の低下をさらに抑制することができる。 In the present embodiment, the radius of curvature of the curved surface at the bottom of the recess 12 is preferably 65 nm or less. In this case, since it is possible to further reduce the occurrence of cracks in the film on the recess 12, it is possible to further suppress deterioration in characteristics due to the formation of cracks in the film on the recess 12. .

 上述のように、本実施形態においては、凸部11の傾斜面11cの角度および凹部12の底の曲面の曲率半径をそれぞれ上述のように設定することにより、凸部11および凹部12上の膜にクラックが発生することを抑えて反射率およびパッシベーション性の向上を図るとともに、半導体基板1の内部に多くの光を取り入れることによって、高い特性を得ることが可能となる。 As described above, in the present embodiment, the film on the convex portion 11 and the concave portion 12 is set by setting the angle of the inclined surface 11c of the convex portion 11 and the radius of curvature of the curved surface at the bottom of the concave portion 12 as described above. By suppressing the occurrence of cracks in the semiconductor substrate 1 and improving the reflectance and passivation properties, it is possible to obtain high characteristics by incorporating a large amount of light into the semiconductor substrate 1.

 なお、本実施形態において、凸部11の傾斜面11cの角度の平均値が上述の角度を満たしていればよい。ただし、高い特性を得る観点からは、上述の角度を満たしている凸部11の傾斜面11cの数が、上述の角度を満たしていない凸部11の傾斜面11cの数よりも多い方が好ましい。 In addition, in this embodiment, the average value of the angle of the inclined surface 11c of the convex part 11 should just satisfy | fill the above-mentioned angle. However, from the viewpoint of obtaining high characteristics, it is preferable that the number of the inclined surfaces 11c of the convex portion 11 satisfying the above-mentioned angle is larger than the number of the inclined surfaces 11c of the convex portion 11 not satisfying the above-described angle. .

 また、本実施形態において、凹部12の底の曲面の曲率半径の少なくとも1つが上述の曲率半径を満たしていればよい。ただし、高い特性を得る観点からは、上述の曲率半径を満たしている凹部12の底の曲面の曲率半径の数が、上述の曲率半径を満たしていない凹部12の底の曲面の曲率半径の数よりも多い方が好ましい。 In this embodiment, it is only necessary that at least one of the curvature radii of the curved surface at the bottom of the recess 12 satisfies the above-described curvature radius. However, from the viewpoint of obtaining high characteristics, the number of curvature radii of the bottom curved surface of the recess 12 that satisfies the above-described curvature radius is the number of curvature radii of the bottom curved surface of the recess 12 that does not satisfy the above-described curvature radius. More is preferable.

 <ヘテロ接合型バックコンタクトセルの製造方法>
 以下、図5~図16の模式的断面図を参照して、実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例について説明する。
<Method for manufacturing heterojunction back contact cell>
Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1 will be described with reference to schematic cross-sectional views of FIGS.

 まず、図5に示すように、半導体基板1を用意する。次に、図6に示すように、半導体基板1の受光面に複数の凸部11と、凸部11の間の凹部12とを形成する。半導体基板1の受光面の凸部11および凹部12の形成方法は特に限定されないが、たとえば半導体基板1の受光面をテクスチャエッチングすることにより形成することができる。 First, as shown in FIG. 5, a semiconductor substrate 1 is prepared. Next, as shown in FIG. 6, a plurality of convex portions 11 and concave portions 12 between the convex portions 11 are formed on the light receiving surface of the semiconductor substrate 1. The method of forming the convex portions 11 and the concave portions 12 on the light receiving surface of the semiconductor substrate 1 is not particularly limited, but can be formed by, for example, texture etching the light receiving surface of the semiconductor substrate 1.

 半導体基板1の受光面のテクスチャエッチングは、たとえば、半導体基板1の受光面をアルカリエッチングすることにより行うことができる。アルカリエッチングは、たとえば、水酸化ナトリウム水溶液および水酸化カリウム水溶液の少なくとも一方を含むアルカリ液を用いて行われる。 The texture etching of the light receiving surface of the semiconductor substrate 1 can be performed, for example, by alkali etching the light receiving surface of the semiconductor substrate 1. Alkali etching is performed using, for example, an alkaline solution containing at least one of a sodium hydroxide aqueous solution and a potassium hydroxide aqueous solution.

 半導体基板1の受光面に凸部11と凹部12とを形成した後には、半導体基板1の受光面の酸エッチングが行われる。半導体基板1の受光面の酸エッチングは、たとえば半導体基板1の受光面をフッ化水素水溶液を用いて行われる。 After the convex portions 11 and the concave portions 12 are formed on the light receiving surface of the semiconductor substrate 1, acid etching of the light receiving surface of the semiconductor substrate 1 is performed. The acid etching of the light receiving surface of the semiconductor substrate 1 is performed using, for example, a hydrogen fluoride aqueous solution on the light receiving surface of the semiconductor substrate 1.

 半導体基板1の受光面の酸エッチングを行った後には、半導体基板1の受光面のラウンドエッチングが行われる。半導体基板1の受光面のラウンドエッチングは、たとえば半導体基板1の受光面をフッ酸と硝酸と水とを含む混酸を用いて行われる。半導体基板1の受光面のラウンドエッチングは、凸部11の傾斜面11cの角度が上述の角度(49.5°よりも大きく55.2°以下、好ましくは50°以上、より好ましくは52.9°以上、好ましくは53.5°以下)を満たすとともに、凹部12の底の曲面の曲率半径が上述の曲率半径(13nmよりも大きく、好ましくは80nm以下、より好ましくは65nm以下)を満たすように行われる。 After acid etching of the light receiving surface of the semiconductor substrate 1, round etching of the light receiving surface of the semiconductor substrate 1 is performed. The round etching of the light receiving surface of the semiconductor substrate 1 is performed using, for example, a mixed acid containing hydrofluoric acid, nitric acid, and water on the light receiving surface of the semiconductor substrate 1. In the round etching of the light receiving surface of the semiconductor substrate 1, the angle of the inclined surface 11c of the convex portion 11 is the above-mentioned angle (greater than 49.5 °, 55.2 ° or less, preferably 50 ° or more, more preferably 52.9). And the curvature radius of the curved surface at the bottom of the recess 12 satisfies the above-mentioned curvature radius (greater than 13 nm, preferably less than 80 nm, more preferably less than 65 nm). Done.

 このようなラウンドエッチングを好適に行う条件の一例としては、たとえば、30℃~60℃のフッ酸(HF)と硝酸(HNO3)と水(H2O)とを含む混酸を用いて30秒~90秒エッチングを行う条件が挙げられるがこれには限定されない。また、ラウンドエッチングを好適に行う観点からは上記の混酸中のフッ酸の体積に対する硝酸の体積の比は70以上100以下であることが好ましく、フッ酸の体積に対する水の体積の比は35以上50以下であることが好ましい。本実施形態において、フッ酸は、フッ化水素濃度が50質量%のフッ化水素水溶液を意味するものとし、硝酸は、硝酸濃度が60質量%の硝酸水溶液を意味するものとする。 As an example of conditions for suitably performing such round etching, for example, a mixed acid containing hydrofluoric acid (HF), nitric acid (HNO 3 ), and water (H 2 O) at 30 ° C. to 60 ° C. is used for 30 seconds. The conditions for performing etching for ˜90 seconds can be mentioned, but not limited thereto. From the viewpoint of suitably performing round etching, the ratio of the volume of nitric acid to the volume of hydrofluoric acid in the mixed acid is preferably 70 or more and 100 or less, and the ratio of the volume of water to the volume of hydrofluoric acid is 35 or more. It is preferable that it is 50 or less. In this embodiment, hydrofluoric acid means a hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50% by mass, and nitric acid means a nitric acid aqueous solution having a nitric acid concentration of 60% by mass.

 次に、図7に示すように、半導体基板1の受光面の全面に接するように非晶質シリコン膜9aを形成する。非晶質シリコン膜9aの形成方法は特に限定されないが、たとえばプラズマCVD(Chemical Vapor Deposition)法を用いることができる。 Next, as shown in FIG. 7, an amorphous silicon film 9 a is formed so as to be in contact with the entire light receiving surface of the semiconductor substrate 1. The formation method of the amorphous silicon film 9a is not particularly limited, but for example, a plasma CVD (Chemical Vapor Deposition) method can be used.

 次に、図8に示すように、半導体基板1の裏面1aの全面に接するように第1のi型非晶質半導体膜2を形成し、引き続いて、図9に示すように、第1導電型非晶質半導体膜3を形成する。第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3の形成方法は特に限定されないが、たとえばプラズマCVD法を用いることができる。 Next, as shown in FIG. 8, a first i-type amorphous semiconductor film 2 is formed so as to be in contact with the entire back surface 1a of the semiconductor substrate 1, and subsequently, as shown in FIG. A type amorphous semiconductor film 3 is formed. A method for forming the first i-type amorphous semiconductor film 2 and the first conductive type amorphous semiconductor film 3 is not particularly limited, and for example, a plasma CVD method can be used.

 次に、図10に示すように、第1導電型非晶質半導体膜3上に、第1のi型非晶質半導体膜2と第1導電型非晶質半導体膜3とを厚さ方向にエッチングする箇所に開口部を有するエッチングマスク31を形成する。 Next, as shown in FIG. 10, the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous semiconductor film 3 are formed on the first conductivity-type amorphous semiconductor film 3 in the thickness direction. An etching mask 31 having an opening at a location to be etched is formed.

 次に、図11に示すように、エッチングマスク31をマスクとして、第1のi型非晶質半導体膜2と第1導電型非晶質半導体膜3とを厚さ方向にエッチングすることによって、半導体基板1の裏面1aの一部を露出させる。その後、図12に示すように、エッチングマスク31を除去する。 Next, as shown in FIG. 11, by using the etching mask 31 as a mask, the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 are etched in the thickness direction, A part of the back surface 1a of the semiconductor substrate 1 is exposed. Thereafter, as shown in FIG. 12, the etching mask 31 is removed.

 次に、図13に示すように、半導体基板1の裏面1aの露出面、ならびに第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3を覆うように第2のi型非晶質半導体膜4を形成し、引き続いて、図14に示すように、第2導電型非晶質半導体膜5を形成する。第2のi型非晶質半導体膜4および第2導電型非晶質半導体膜5の形成方法は特に限定されないが、たとえばプラズマCVD法を用いることができる。 Next, as illustrated in FIG. 13, the second surface is formed so as to cover the exposed surface of the back surface 1 a of the semiconductor substrate 1 and the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3. An i-type amorphous semiconductor film 4 is formed, and subsequently, a second conductive type amorphous semiconductor film 5 is formed as shown in FIG. A method for forming the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is not particularly limited, and for example, a plasma CVD method can be used.

 次に、図15に示すように、半導体基板1の裏面1a上の第2のi型非晶質半導体膜4と第2導電型非晶質半導体膜5とを残す部分にのみエッチングマスク32を形成する。 Next, as shown in FIG. 15, an etching mask 32 is formed only on the portion where the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 are left on the back surface 1 a of the semiconductor substrate 1. Form.

 次に、図16に示すように、エッチングマスク32をマスクとして、第2のi型非晶質半導体膜4と第2導電型非晶質半導体膜5とを厚さ方向にエッチングすることによって、第1導電型非晶質半導体膜3の一部を露出させる。 Next, as shown in FIG. 16, by using the etching mask 32 as a mask, the second i-type amorphous semiconductor film 4 and the second conductive amorphous semiconductor film 5 are etched in the thickness direction, A part of the first conductive type amorphous semiconductor film 3 is exposed.

 その後、エッチングマスク32が除去され、図1に示すように、第1導電型非晶質半導体膜3上に第1電極6を形成するとともに、第2導電型非晶質半導体膜5上に第2電極7を形成することによって、実施形態1のヘテロ接合型バックコンタクトセルを得ることができる。 Thereafter, the etching mask 32 is removed, and the first electrode 6 is formed on the first conductive type amorphous semiconductor film 3 and the second conductive type amorphous semiconductor film 5 is formed on the second conductive type amorphous semiconductor film 5 as shown in FIG. By forming the two electrodes 7, the heterojunction back contact cell of Embodiment 1 can be obtained.

 [実施形態2]
 図17に、実施形態の光電変換素子の他の一例である実施形態2のヘテロ接合型バックコンタクトセルの模式的な断面図を示す。実施形態2のヘテロ接合型バックコンタクトセルは、半導体基板1の受光面の凸部11および凹部12上の膜として窒化珪素(SiN)膜9bを備えていることを特徴とする。半導体基板1としては、たとえば実施形態1と同様のn型の単結晶シリコン基板が用いられる。
[Embodiment 2]
FIG. 17 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 2, which is another example of the photoelectric conversion element of the embodiment. The heterojunction back contact cell according to the second embodiment is characterized in that a silicon nitride (SiN) film 9 b is provided as a film on the convex portion 11 and the concave portion 12 of the light receiving surface of the semiconductor substrate 1. As the semiconductor substrate 1, for example, an n-type single crystal silicon substrate similar to that of the first embodiment is used.

 なお、半導体基板1の受光面の凸部11および凹部12上の膜としては、SiN膜9b以外にも、SiCxyzvw(0≦x≦1、0≦y≦1、0≦z≦1、0≦v≦1、0≦w≦1、(x+y+z+v+w)>0)の式で表わされる膜であってもよく、当該式で表される膜と非晶質シリコンなどの非晶質半導体膜との複合膜であってもよい。これらの膜の形成方法は特に限定されないが、たとえばプラズマCVD法により形成することができる。なお、上記の式において、Siはシリコンを示し、Cは炭素を示し、Nは窒素を示し、Oは酸素を示し、Fはフッ素を示し、Hは水素を示している。また、上記の式において、xは炭素の原子数比を示し、yは窒素の原子数比を示し、zは酸素の原子数比を示し、vはフッ素の原子数比を示し、wは水素の原子数比を示している。 In addition to the SiN film 9b, as the film on the light receiving surface of the semiconductor substrate 1 on the light receiving surface 11 and the concave portion 12, SiC x N y O z F v H w (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) , 0 ≦ z ≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, (x + y + z + v + w)> 0), a film represented by the formula, amorphous silicon, etc. It may be a composite film with an amorphous semiconductor film. The formation method of these films is not particularly limited, but can be formed by, for example, a plasma CVD method. In the above formula, Si represents silicon, C represents carbon, N represents nitrogen, O represents oxygen, F represents fluorine, and H represents hydrogen. In the above formula, x represents the atomic ratio of carbon, y represents the atomic ratio of nitrogen, z represents the atomic ratio of oxygen, v represents the atomic ratio of fluorine, and w represents hydrogen. Shows the atomic ratio.

 実施形態2における上記以外の説明は実施形態1と同様であるため、その説明については繰り返さない。 Since the description other than the above in the second embodiment is the same as that in the first embodiment, the description thereof will not be repeated.

 [実施形態3]
 図18に、実施形態の光電変換素子の他の一例である実施形態3のヘテロ接合型バックコンタクトセルの模式的な断面図を示す。実施形態3のヘテロ接合型バックコンタクトセルは、半導体基板1の受光面の凸部11および凹部12上の膜として炭化珪素(SiC)膜9cが設けられていることを特徴とする。半導体基板1としては、たとえば実施形態1と同様のn型の単結晶シリコン基板が用いられる。
[Embodiment 3]
FIG. 18 is a schematic cross-sectional view of a heterojunction back contact cell of Embodiment 3, which is another example of the photoelectric conversion element of the embodiment. The heterojunction back contact cell of Embodiment 3 is characterized in that a silicon carbide (SiC) film 9 c is provided as a film on the convex portion 11 and the concave portion 12 of the light receiving surface of the semiconductor substrate 1. As the semiconductor substrate 1, for example, an n-type single crystal silicon substrate similar to that of the first embodiment is used.

 実施形態3における上記以外の説明は実施形態1および実施形態2と同様であるため、その説明については繰り返さない。 Since the description other than the above in the third embodiment is the same as that in the first and second embodiments, the description thereof will not be repeated.

 [実施形態4]
 図19に、実施形態の光電変換素子の他の一例である実施形態4の裏面電極型太陽電池セルの模式的な断面図を示す。図19に示すように、実施形態4の裏面電極型太陽電池セルは、半導体基板1と、半導体基板1の裏面1aに間隔を空けて設けられた、第1導電型領域63と、第2導電型領域65とを備えている。また、第1導電型領域63上には第1電極6が設けられており、第2導電型領域65上には第2電極7が設けられている。半導体基板1としては、たとえば実施形態1と同様のn型の単結晶シリコン基板が用いられる。
[Embodiment 4]
In FIG. 19, the typical sectional drawing of the back surface electrode type photovoltaic cell of Embodiment 4 which is another example of the photoelectric conversion element of Embodiment is shown. As shown in FIG. 19, the back electrode type solar cell of Embodiment 4 includes a semiconductor substrate 1, a first conductivity type region 63 provided at a distance from the back surface 1 a of the semiconductor substrate 1, and a second conductivity. And a mold region 65. The first electrode 6 is provided on the first conductivity type region 63, and the second electrode 7 is provided on the second conductivity type region 65. As the semiconductor substrate 1, for example, an n-type single crystal silicon substrate similar to that of the first embodiment is used.

 また、半導体基板1の受光面の凸部11および凹部12上には、SiCxyzvw(0≦x≦1、0≦y≦1、0≦z≦1、0≦v≦1、0≦w≦1、(x+y+z+v+w)>0)の式で表わされる誘電体膜9dが設けられており、半導体基板1の裏面1aにもたとえば酸化シリコン膜または窒化シリコン膜等の誘電体膜67が設けられている。 Further, on the convex portion 11 and the concave portion 12 of the light receiving surface of the semiconductor substrate 1, SiC x N y O z F v H w (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, (x + y + z + v + w)> 0) is provided, and the back surface 1a of the semiconductor substrate 1 is also provided with a dielectric such as a silicon oxide film or a silicon nitride film. A body membrane 67 is provided.

 以下、図20~図28の模式的断面図を参照して、実施形態4の裏面電極型太陽電池セルの製造方法の一例について説明する。 Hereinafter, an example of a method for manufacturing the back electrode type solar battery cell of Embodiment 4 will be described with reference to schematic cross-sectional views of FIGS.

 まず、図20に示すように、半導体基板1の受光面および裏面1aのそれぞれの全面に拡散マスク62を設置し、半導体基板1の裏面1aの拡散抑制マスク62の一部に開口部61aを設ける。なお、開口部61aの形成方法は、特に限定されず、たとえばフォトリソグラフィ等の方法を用いることができる。 First, as shown in FIG. 20, a diffusion mask 62 is provided on each of the light receiving surface and the back surface 1a of the semiconductor substrate 1, and an opening 61a is provided in a part of the diffusion suppression mask 62 on the back surface 1a of the semiconductor substrate 1. . In addition, the formation method of the opening part 61a is not specifically limited, For example, methods, such as photolithography, can be used.

 次に、図21に示すように、n型不純物含有ガス64を流すことによって、半導体基板1の第1主面1bの拡散抑制マスク62の開口部61aから露出している半導体基板1の裏面1aにn型不純物を拡散させてn型不純物拡散領域である第1導電型領域63を形成する。なお、n型不純物含有ガス64としては、たとえばn型不純物であるリンを含むPOCl3などを用いることができる。また、n型不純物拡散領域は、半導体基板1よりもn型不純物濃度が高い領域であればよい。 Next, as shown in FIG. 21, the back surface 1 a of the semiconductor substrate 1 exposed from the opening 61 a of the diffusion suppression mask 62 of the first main surface 1 b of the semiconductor substrate 1 by flowing an n-type impurity-containing gas 64. An n-type impurity is diffused to form a first conductivity type region 63 which is an n-type impurity diffusion region. As the n-type impurity-containing gas 64, for example, POCl 3 containing phosphorus which is an n-type impurity can be used. The n-type impurity diffusion region may be a region having an n-type impurity concentration higher than that of the semiconductor substrate 1.

 次に、半導体基板1の受光面および裏面1aの拡散抑制マスク62を一旦すべて除去した後に、半導体基板1の受光面および裏面1aのそれぞれの全面に拡散抑制マスク62を再度設置し、図22に示すように、半導体基板1の裏面1aの拡散抑制マスク62の一部に開口部61bを設ける。 Next, after once removing all of the diffusion suppression mask 62 on the light receiving surface and the back surface 1a of the semiconductor substrate 1, the diffusion suppression mask 62 is provided again on the entire surface of the light receiving surface and the back surface 1a of the semiconductor substrate 1, and FIG. As shown, an opening 61 b is provided in a part of the diffusion suppression mask 62 on the back surface 1 a of the semiconductor substrate 1.

 次に、図23に示すように、p型不純物含有ガス66を流すことによって、半導体基板1の裏面1aの拡散抑制マスク62の開口部61bから露出している半導体基板1の裏面1aにp型不純物を拡散させてp型不純物拡散領域である第2導電型領域65を形成する。 Next, as shown in FIG. 23, by flowing a p-type impurity-containing gas 66, p-type is applied to the back surface 1 a of the semiconductor substrate 1 exposed from the opening 61 b of the diffusion suppression mask 62 on the back surface 1 a of the semiconductor substrate 1. Impurities are diffused to form a second conductivity type region 65 which is a p-type impurity diffusion region.

 次に、図24に示すように、半導体基板1の受光面および裏面1aの拡散抑制マスク62をすべて除去する。次に、図25に示すように、半導体基板1の裏面1aの全面に誘電体膜67を形成する。 Next, as shown in FIG. 24, all the diffusion suppression masks 62 on the light receiving surface and the back surface 1a of the semiconductor substrate 1 are removed. Next, as shown in FIG. 25, a dielectric film 67 is formed on the entire back surface 1 a of the semiconductor substrate 1.

 次に、図26に示すように、半導体基板1の受光面について、実施形態1~実施形態3と同様に、テクスチャエッチング、酸エッチング、およびラウンドエッチングをこの順に行うことによって、半導体基板1の受光面に複数の凸部11と、凸部11の間の凹部12とを形成する。ここで、ラウンドエッチングは、凸部11の傾斜面11cの角度が上述の角度(49.5°よりも大きく55.2°以下、好ましくは50°以上、より好ましくは52.9°以上、好ましくは53.5°以下)を満たすとともに、凹部12の底の曲面の曲率半径が上述の曲率半径(13nmよりも大きく、好ましくは80nm以下、より好ましくは65nm以下)を満たすように行われる。 Next, as shown in FIG. 26, the light receiving surface of the semiconductor substrate 1 is subjected to texture etching, acid etching, and round etching in this order on the light receiving surface of the semiconductor substrate 1 in the same manner as in the first to third embodiments. A plurality of convex portions 11 and concave portions 12 between the convex portions 11 are formed on the surface. Here, in the round etching, the angle of the inclined surface 11c of the convex portion 11 is the above-mentioned angle (greater than 49.5 °, 55.2 ° or less, preferably 50 ° or more, more preferably 52.9 ° or more, preferably Is 53.5 ° or less), and the curvature radius of the curved surface at the bottom of the recess 12 is such that the above-mentioned curvature radius (greater than 13 nm, preferably 80 nm or less, more preferably 65 nm or less) is satisfied.

 次に、図27に示すように、半導体基板1の受光面の凸部11および凹部12上に誘電体膜9dを形成する。次に、図28に示すように、半導体基板1の裏面1aの誘電体膜67の一部を除去することによってコンタクトホール70,71を形成する。なお、コンタクトホール70,71の形成方法は、特に限定されず、たとえばフォトリソグラフィ等の方法を用いることができる。 Next, as shown in FIG. 27, a dielectric film 9d is formed on the convex portion 11 and the concave portion 12 of the light receiving surface of the semiconductor substrate 1. Next, as shown in FIG. 28, contact holes 70 and 71 are formed by removing a part of the dielectric film 67 on the back surface 1 a of the semiconductor substrate 1. In addition, the formation method of the contact holes 70 and 71 is not specifically limited, For example, methods, such as photolithography, can be used.

 次に、図19に示すように、コンタクトホール70を通して第1導電型領域63上に第1電極6を形成するとともに、コンタクトホール71を通して第2導電型領域65上に第2電極7を形成する。これにより、実施形態4の裏面電極型太陽電池セルを得ることができる。 Next, as shown in FIG. 19, the first electrode 6 is formed on the first conductivity type region 63 through the contact hole 70, and the second electrode 7 is formed on the second conductivity type region 65 through the contact hole 71. . Thereby, the back electrode type solar cell of Embodiment 4 can be obtained.

 なお、上記においては、第1導電型領域63としてn型不純物拡散領域を形成し、第2導電型領域65としてp型不純物拡散領域を形成したが、第1導電型領域63としてp型不純物拡散領域を形成し、第2導電型領域65としてn型不純物拡散領域を形成してもよい。 In the above description, an n-type impurity diffusion region is formed as the first conductivity type region 63 and a p-type impurity diffusion region is formed as the second conductivity type region 65. However, a p-type impurity diffusion is used as the first conductivity type region 63. A region may be formed, and an n-type impurity diffusion region may be formed as the second conductivity type region 65.

 実施形態4における上記以外の説明は、実施形態1~実施形態3と同様であるため、その説明については繰り返さない。 Since the description other than the above in the fourth embodiment is the same as that in the first to third embodiments, the description thereof will not be repeated.

 [実施形態5]
 図29に、実施形態の光電変換素子の他の一例である実施形態5の両面電極型太陽電池セルの模式的な断面図を示す。図29に示すように、実施形態5の両面電極型太陽電池セルは、たとえば実施形態1と同様のn型の単結晶シリコン基板等の単結晶シリコン基板からなる半導体基板1と、半導体基板1の裏面となる裏面1aの第1導電型領域63と、半導体基板1の受光面の第2導電型領域65とを備えている。第1導電型領域63上には第1電極7が設けられており、第2導電型領域65上には第2電極8が設けられている。
[Embodiment 5]
FIG. 29 is a schematic cross-sectional view of a double-sided electrode type solar battery cell of Embodiment 5, which is another example of the photoelectric conversion element of the embodiment. As shown in FIG. 29, a double-sided electrode solar cell of Embodiment 5 includes a semiconductor substrate 1 made of a single crystal silicon substrate such as an n-type single crystal silicon substrate similar to that of Embodiment 1, and the semiconductor substrate 1 A first conductivity type region 63 on the back surface 1 a serving as the back surface and a second conductivity type region 65 on the light receiving surface of the semiconductor substrate 1 are provided. A first electrode 7 is provided on the first conductivity type region 63, and a second electrode 8 is provided on the second conductivity type region 65.

 実施形態5の両面電極型太陽電池セルは、たとえば、以下のようにして作製することができる。まず、実施形態1~実施形態4と同様に、半導体基板1の受光面について、テクスチャエッチング、酸エッチング、およびラウンドエッチングをこの順に行うことによって、半導体基板1の受光面に複数の凸部11と、凸部11の間の凹部12とを形成する。ここで、ラウンドエッチングは、凸部11の傾斜面11cの角度が上述の角度(49.5°よりも大きく55.2°以下、好ましくは50°以上、より好ましくは52.9°以上、好ましくは53.5°以下)を満たすとともに、凹部12の底の曲面の曲率半径が上述の曲率半径(13nmよりも大きく、好ましくは80nm以下、より好ましくは65nm以下)を満たすように行われる。 The double-sided electrode type solar battery cell of Embodiment 5 can be manufactured as follows, for example. First, similarly to the first to fourth embodiments, by performing texture etching, acid etching, and round etching in this order on the light receiving surface of the semiconductor substrate 1, a plurality of protrusions 11 are formed on the light receiving surface of the semiconductor substrate 1. And the concave portion 12 between the convex portions 11. Here, in the round etching, the angle of the inclined surface 11c of the convex portion 11 is the above-mentioned angle (greater than 49.5 °, 55.2 ° or less, preferably 50 ° or more, more preferably 52.9 ° or more, preferably Is 53.5 ° or less), and the curvature radius of the curved surface at the bottom of the recess 12 is such that the above-mentioned curvature radius (greater than 13 nm, preferably 80 nm or less, more preferably 65 nm or less) is satisfied.

 次に、半導体基板1の裏面1aに第1導電型領域63を形成し、半導体基板1の受光面に第2導電型領域65を形成する。その後、第2導電型領域65上に誘電体膜9dを形成する。以上の工程を経ることにより、実施形態5の両面電極型太陽電池セルを得ることができる。 Next, the first conductivity type region 63 is formed on the back surface 1 a of the semiconductor substrate 1, and the second conductivity type region 65 is formed on the light receiving surface of the semiconductor substrate 1. Thereafter, a dielectric film 9 d is formed on the second conductivity type region 65. By undergoing the above steps, the double-sided electrode solar cell of Embodiment 5 can be obtained.

 実施形態5における上記以外の説明は、実施形態1~実施形態4と同様であるため、その説明については繰り返さない。 Since the description other than the above in the fifth embodiment is the same as in the first to fourth embodiments, the description thereof will not be repeated.

 <実験例1の基板の作製>
 まず、n型シリコン単結晶インゴットをワイヤソーにより切断して、n型シリコン単結晶基板を切り出した。次に、n型シリコン単結晶基板の表面について、水酸化ナトリウム水溶液を用いたアルカリエッチングによりテクスチャエッチングを行い、n型シリコン単結晶基板の表面に複数の四角錘形状の凸部と、凸部の間の凹部とを形成した。その後、テクスチャエッチングにより凸部および凹部が形成されたn型シリコン単結晶基板の表面についてフッ化水素水溶液を用いた酸エッチングを行うことによって、実験例1の基板を得た。
<Preparation of the substrate of Experimental Example 1>
First, an n-type silicon single crystal ingot was cut with a wire saw to cut out an n-type silicon single crystal substrate. Next, texture etching is performed on the surface of the n-type silicon single crystal substrate by alkaline etching using an aqueous sodium hydroxide solution, and a plurality of quadrangular pyramidal convex portions and convex portions are formed on the surface of the n-type silicon single crystal substrate. A recess was formed between them. Then, the board | substrate of Experimental example 1 was obtained by performing the acid etching using the hydrogen fluoride aqueous solution about the surface of the n-type silicon single crystal substrate in which the convex part and the recessed part were formed by texture etching.

 <実験例2の基板の作製>
 実験例1の酸エッチング後の基板の表面を、さらにフッ酸と硝酸と水とを含む約42℃の混酸(フッ酸(フッ化水素濃度が50質量%のフッ化水素水溶液)の体積:硝酸(硝酸濃度が60質量%の硝酸水溶液)の体積:水の体積=1:100:50)に180秒間浸漬させることによってラウンドエッチングを行い、実験例2の基板を得た。
<Preparation of the substrate of Experimental Example 2>
The surface of the substrate after the acid etching in Experimental Example 1 was further mixed with about 42 ° C. mixed acid (hydrofluoric acid (hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50% by mass)) containing nitric acid and water: nitric acid Round etching was performed by dipping in a volume of (a nitric acid aqueous solution having a nitric acid concentration of 60 mass%): volume of water = 1: 100: 50) for 180 seconds to obtain a substrate of Experimental Example 2.

 <実験例3の基板の作製>
 実験例1の酸エッチング後の基板の表面について、さらにフッ酸と硝酸と水とを含む約42℃の混酸(フッ酸(フッ化水素濃度が50質量%のフッ化水素水溶液)の体積:硝酸(硝酸濃度が60質量%の硝酸水溶液)の体積:水の体積=1:70:35)に180秒間浸漬させることによってラウンドエッチングを行い、実験例3の基板を得た。
<Preparation of the substrate of Experimental Example 3>
About the surface of the substrate after acid etching in Experimental Example 1, the volume of a mixed acid (hydrofluoric acid (hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass%)) of about 42 ° C. further containing hydrofluoric acid, nitric acid, and water: nitric acid Round etching was performed by dipping in a volume of (a nitric acid aqueous solution having a nitric acid concentration of 60% by mass): volume of water = 1: 70: 35 for 180 seconds to obtain a substrate of Experimental Example 3.

 <実験例4の基板の作製>
 実験例1の酸エッチング後の基板の表面について、さらにフッ酸と硝酸と水とを含む約42℃の混酸(フッ酸(フッ化水素濃度が50質量%のフッ化水素水溶液)の体積:硝酸(硝酸濃度が60質量%の硝酸水溶液)の体積:水の体積=1:50:25)に180秒間浸漬させることによってラウンドエッチングを行い、実験例4の基板を得た。
<Preparation of the substrate of Experimental Example 4>
About the surface of the substrate after acid etching in Experimental Example 1, the volume of a mixed acid (hydrofluoric acid (hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass%)) of about 42 ° C. further containing hydrofluoric acid, nitric acid, and water: nitric acid Round etching was performed by dipping in a volume of (a nitric acid aqueous solution having a nitric acid concentration of 60 mass%): volume of water = 1: 50: 25) for 180 seconds to obtain a substrate of Experimental Example 4.

 <実験例1~4の基板の表面の反射率の測定>
 上述のようにして作製した実験例1~4の基板に入射する光の波長と反射率との関係について調査した。その結果を図30に示す。なお、図30において、横軸が実験例1~4の基板に入射する光の波長[nm]を示し、縦軸が実験例1~4の基板のそれぞれの波長を有する入射光に対する反射率[%]を示している。
<Measurement of reflectivity of substrate surface of Experimental Examples 1 to 4>
The relationship between the wavelength of light incident on the substrates of Experimental Examples 1 to 4 fabricated as described above and the reflectance was investigated. The result is shown in FIG. In FIG. 30, the horizontal axis indicates the wavelength [nm] of the light incident on the substrates of Experimental Examples 1 to 4, and the vertical axis indicates the reflectance [% of incident light having the respective wavelengths of the substrates of Experimental Examples 1 to 4]. %].

 図30に示すように、実験例1の基板が入射光に対する反射率が最も高くなっていた。また、実験例3の基板が最も反射率が低くなっており、実験例4および実験例2の順に反射率が高くなっていた。 As shown in FIG. 30, the substrate of Experimental Example 1 had the highest reflectance with respect to incident light. Further, the substrate of Experimental Example 3 had the lowest reflectance, and the reflectance increased in the order of Experimental Example 4 and Experimental Example 2.

 <実験例1および5~7の基板の凸部の傾斜面の角度の測定>
 次に、実験例1~4の基板の四角錐形状の隣り合う2つの傾斜面が互いに接する線に沿った断面を形成し、その断面のSEM写真を撮った。そして、実験例1~4の基板の断面のSEM写真から、実験例1~4のそれぞれの基板の凸部の傾斜面の角度αを測定し、実験例1~4のそれぞれの基板の凸部の傾斜面の角度αの平均値を算出した。その結果を図31に示す。なお、図31において、横軸が実験例1~4のそれぞれの基板を示し、縦軸が実験例1および5~7のそれぞれの基板の凸部の傾斜面の角度α[°]の平均値を示している。
<Measurement of the angle of the inclined surface of the convex portion of the substrates of Experimental Examples 1 and 5 to 7>
Next, a cross section along a line in which two adjacent inclined surfaces of the quadrangular pyramid shape of the substrates of Experimental Examples 1 to 4 contact each other was formed, and an SEM photograph of the cross section was taken. Then, from the SEM photographs of the cross sections of the substrates of Experimental Examples 1 to 4, the angle α of the inclined surfaces of the convex portions of the substrates of Experimental Examples 1 to 4 was measured, and the convex portions of the substrates of Experimental Examples 1 to 4 were measured. The average value of the angle α of the inclined surfaces was calculated. The result is shown in FIG. In FIG. 31, the horizontal axis indicates the substrates of Experimental Examples 1 to 4, and the vertical axis indicates the average value of the angle α [°] of the inclined surface of the convex portion of each of the substrates of Experimental Examples 1 and 5 to 7. Is shown.

 図31に示す結果から、実験例1の基板の凸部の傾斜面の角度αの平均値は49.5°であり、実験例2の基板の凸部の傾斜面の角度αの平均値は52.9°であることが確認された。また、実験例3の基板の凸部の傾斜面の角度αの平均値は55.2°であり、実験例4の基板の凸部の傾斜面の角度αの平均値は54.3°であることが確認された。 From the results shown in FIG. 31, the average value of the angle α of the inclined surface of the convex portion of the substrate of Experimental Example 1 is 49.5 °, and the average value of the angle α of the inclined surface of the convex portion of the substrate of Experimental Example 2 is It was confirmed to be 52.9 °. Moreover, the average value of the angle α of the inclined surface of the convex portion of the substrate of Experimental Example 3 is 55.2 °, and the average value of the angle α of the inclined surface of the convex portion of the substrate of Experimental Example 4 is 54.3 °. It was confirmed that there was.

 <まとめ>
 図30および図31に示す結果から、基板の表面での反射率を低減して、基板の内部に光を取り込む観点からは、基板の凸部の傾斜面の角度αは49.5°よりも大きく55.2°以下であること、好ましくは52.9°以上55.2°以下であることが確認された。
<Summary>
From the results shown in FIGS. 30 and 31, from the viewpoint of reducing the reflectance on the surface of the substrate and taking light into the substrate, the angle α of the inclined surface of the convex portion of the substrate is more than 49.5 °. It was confirmed that it was 55.2 ° or less, preferably 52.9 ° or more and 55.2 ° or less.

 <実験例5~7の基板の作製>
 実験例1の酸エッチング後の基板の表面を、さらにフッ酸と硝酸と水とを含む約42℃の混酸(フッ酸(フッ化水素濃度が50質量%のフッ化水素水溶液)の体積:硝酸(硝酸濃度が60質量%の硝酸水溶液)の体積:水の体積=1:70:35)に30秒間浸漬させることによってラウンドエッチングを行い、実験例5の基板を得た。
<Preparation of Substrates for Experimental Examples 5-7>
The surface of the substrate after the acid etching in Experimental Example 1 was further mixed with about 42 ° C. mixed acid (hydrofluoric acid (hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50% by mass)) containing nitric acid and water: nitric acid Round etching was performed by dipping in a volume of (a nitric acid aqueous solution having a nitric acid concentration of 60 mass%): volume of water = 1: 70: 35) for 30 seconds to obtain a substrate of Experimental Example 5.

 また、実験例1の酸エッチング後の基板の表面を、さらにフッ酸と硝酸と水とを含む約42℃の混酸(フッ酸(フッ化水素濃度が50質量%のフッ化水素水溶液)の体積:硝酸(硝酸濃度が60質量%の硝酸水溶液)の体積:水の体積=1:70:35)に15秒間浸漬させることによってラウンドエッチングを行い、実験例6の基板を得た。 Further, the surface of the substrate after the acid etching in Experimental Example 1 was further mixed with about 42 ° C. mixed acid (hydrofluoric acid (hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass%)) containing hydrofluoric acid, nitric acid, and water. : Round etching was carried out by dipping in nitric acid (volume of nitric acid aqueous solution having a nitric acid concentration of 60% by mass: volume of water = 1:70:35) for 15 seconds to obtain a substrate of Experimental Example 6.

 さらに、実験例1の酸エッチング後の基板の表面を、さらにフッ酸と硝酸と水とを含む約42℃の混酸(フッ酸(フッ化水素濃度が50質量%のフッ化水素水溶液)の体積:硝酸(硝酸濃度が60質量%の硝酸水溶液)の体積:水の体積=1:100:50)に270秒間浸漬させることによってラウンドエッチングを行い、実験例7の基板を得た。 Furthermore, the surface of the substrate after acid etching in Experimental Example 1 is further mixed with about 42 ° C. mixed acid (hydrofluoric acid (hydrogen fluoride aqueous solution having a hydrogen fluoride concentration of 50 mass%)) containing hydrofluoric acid, nitric acid, and water. : Round etching was performed by immersing in nitric acid (volume of nitric acid aqueous solution having a nitric acid concentration of 60% by mass: volume of water = 1: 100: 50) for 270 seconds to obtain a substrate of Experimental Example 7.

 <実験例1、2および5~7のセルの逆方向飽和電流密度の測定>
 上述のようにして作製した実験例1、2および5~7のそれぞれの基板を用いて、図17に示す構造の実験例1、2および5~7のそれぞれのヘテロ接合型バックコンタクトセル(基板の受光面上の膜はSiN膜)を作製した。そして、実験例1、2および5~7のそれぞれのヘテロ接合型バックコンタクトセルについて、逆方向飽和電流密度[fA/cm2]を測定した。その結果を図32に示す。なお、図32において、横軸が実験例1、2および5~7のそれぞれのヘテロ接合型バックコンタクトセルを示し、縦軸が実験例1のヘテロ接合型バックコンタクトセルの逆方向飽和電流密度を1としたときの実験例2および5~7のそれぞれのヘテロ接合型バックコンタクトセルの逆方向飽和電流密度の相対値を示している。
<Measurement of Reverse Saturation Current Density of Cells of Experimental Examples 1, 2, and 5-7>
Using the substrates of Experimental Examples 1, 2, and 5 to 7 manufactured as described above, the heterojunction back contact cells (Substrate) of Experimental Examples 1, 2, and 5 to 7 having the structure shown in FIG. The film on the light receiving surface was made of SiN film). Then, the reverse saturation current density [fA / cm 2 ] was measured for each of the heterojunction back contact cells of Experimental Examples 1, 2, and 5 to 7. The result is shown in FIG. In FIG. 32, the horizontal axis represents the heterojunction back contact cell of each of Experimental Examples 1, 2, and 5 to 7, and the vertical axis represents the reverse saturation current density of the heterojunction back contact cell of Experimental Example 1. 2 shows the relative values of the reverse saturation current densities of the heterojunction back contact cells of Experimental Examples 2 and 5 to 7 when 1.

 図32に示す結果から、ラウンドエッチングが行われた実験例2および5~7の基板をそれぞれ用いて作製された実験例2および5~7のヘテロ接合型バックコンタクトセルは、ラウンドエッチングが行われていない実験例1の基板を用いて作製された実験例1のヘテロ接合型バックコンタクトセルと比べて、逆方向飽和電流密度を低減できることが確認された。 From the results shown in FIG. 32, the heterojunction back contact cells of Experimental Examples 2 and 5 to 7 fabricated using the substrates of Experimental Examples 2 and 5 to 7 that were subjected to round etching were subjected to round etching. It was confirmed that the reverse saturation current density can be reduced as compared with the heterojunction back contact cell of Experimental Example 1 manufactured using the substrate of Experimental Example 1 that was not used.

 <実験例1、5、8および9の基板の凹部の底の曲面の曲率半径の測定>
 実験例5の基板のラウンドエッチング時間をそれぞれ60秒間および90秒間に変更したこと以外は実験例5と同様にして、実験例8および9の基板をそれぞれ作製した。
<Measurement of curvature radius of curved surface of bottom of recess of substrate of Experimental Examples 1, 5, 8 and 9>
Substrates of Experimental Examples 8 and 9 were prepared in the same manner as Experimental Example 5 except that the round etching time of the substrate of Experimental Example 5 was changed to 60 seconds and 90 seconds, respectively.

 そして、上述のようにして得られた実験例1、5、8および9の基板のそれぞれの四角錐形状の隣り合う2つの傾斜面が互いに接する線に沿った断面を形成した。図33に、実験例1の基板の模式的な拡大断面図を示し、図34に、実験例5の基板の断面の模式的な拡大断面図を示す。また、図35に、実験例8の基板の模式的な拡大断面図を示し、図36に、実験例9の基板の模式的な拡大断面図を示す。 Then, a cross section was formed along a line in which two adjacent pyramid-shaped inclined surfaces of the substrates of Experimental Examples 1, 5, 8 and 9 obtained as described above were in contact with each other. FIG. 33 shows a schematic enlarged cross-sectional view of the substrate of Experimental Example 1, and FIG. 34 shows a schematic enlarged cross-sectional view of the cross section of the substrate of Experimental Example 5. FIG. 35 shows a schematic enlarged cross-sectional view of the substrate of Experimental Example 8, and FIG. 36 shows a schematic enlarged cross-sectional view of the substrate of Experimental Example 9.

 そして、実験例1、5、8および9の基板の断面から、実験例1、5、8および9の基板のそれぞれの基板の表面の凹部の底の曲面の曲率半径を測定した。その結果を図37に示す。なお、図37の横軸が実験例1、5、8および9の基板のそれぞれの基板のラウンドエッチング時間[秒]を示し、縦軸が実験例1、5、8および9の基板のそれぞれの基板の表面の凹部の底の曲面の曲率半径[nm]を示している。 Then, from the cross-sections of the substrates of Experimental Examples 1, 5, 8, and 9, the curvature radii of the curved surfaces of the bottoms of the recesses on the surface of each of the substrates of Experimental Examples 1, 5, 8, and 9 were measured. The result is shown in FIG. Note that the horizontal axis of FIG. 37 represents the round etching time [seconds] of each of the substrates of Experimental Examples 1, 5, 8, and 9, and the vertical axis represents each of the substrates of Experimental Examples 1, 5, 8, and 9. The curvature radius [nm] of the curved surface of the bottom of the recess on the surface of the substrate is shown.

 図37に示す結果から、実験例1の基板の凹部の底の曲面の曲率半径は13nmであり、実験例5の基板の凹部の底の曲面の曲率半径は45nmであることが確認された。また、実験例8の基板の凹部の底の曲面の曲率半径は68nmであり、実験例9の基板の凹部の底の曲面の曲率半径は73nmであることが確認された。 37, it was confirmed that the curvature radius of the curved surface at the bottom of the concave portion of the substrate of Experimental Example 1 was 13 nm, and the curvature radius of the curved surface at the bottom of the concave portion of the substrate of Experimental Example 5 was 45 nm. Further, it was confirmed that the radius of curvature of the curved surface of the bottom of the concave portion of the substrate of Experimental Example 8 was 68 nm, and the radius of curvature of the curved surface of the bottom of the concave portion of the substrate of Experimental Example 9 was 73 nm.

 <まとめ>
 図32および図37に示す結果から、基板の表面の凹部上の膜に形成されるクラックの発生を低減して、逆方向飽和電流密度を低減する観点からは、基板の凹部の底の曲面の曲率半径は13nmよりも大きいことが好ましいことが確認された。
<Summary>
From the results shown in FIGS. 32 and 37, from the viewpoint of reducing the occurrence of cracks formed in the film on the concave portion on the surface of the substrate and reducing the reverse saturation current density, the curved surface at the bottom of the concave portion of the substrate is used. It was confirmed that the radius of curvature is preferably larger than 13 nm.

 [付記]
 (1)ここで開示された実施形態は、複数の凸部と、凸部の間の凹部とを表面に備え、凸部は傾斜面を備え、凹部は曲面の底を備え、傾斜面の角度が49.5°よりも大きく55.2°以下であって、曲面の曲率半径が13nmよりも大きい半導体基板である。この場合には、高い特性の光電変換素子を得ることが可能となる。
[Appendix]
(1) The embodiment disclosed herein includes a plurality of convex portions and concave portions between the convex portions on the surface, the convex portions include an inclined surface, the concave portion includes a curved bottom, and the angle of the inclined surface. Is a semiconductor substrate having a curvature radius of the curved surface larger than 13 nm. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (2)ここで開示された実施形態の半導体基板において、上記の角度は50°以上であることが好ましく、上記の角度は52.9°以上であることがより好ましい。この場合には、より高い特性の光電変換素子を得ることが可能となる。 (2) In the semiconductor substrate of the embodiment disclosed herein, the angle is preferably 50 ° or more, and more preferably 52.9 ° or more. In this case, a photoelectric conversion element with higher characteristics can be obtained.

 (3)ここで開示された実施形態の半導体基板において、上記の角度は、53.5°以下であることが好ましい。この場合には、より高い特性の光電変換素子を得ることが可能となる。 (3) In the semiconductor substrate of the embodiment disclosed herein, the angle is preferably 53.5 ° or less. In this case, a photoelectric conversion element with higher characteristics can be obtained.

 (4)ここで開示された実施形態の半導体基板において、上記の曲率半径は80nm以上であることが好ましい。この場合には、より高い特性の光電変換素子を得ることが可能となる。 (4) In the semiconductor substrate of the embodiment disclosed herein, the radius of curvature is preferably 80 nm or more. In this case, a photoelectric conversion element with higher characteristics can be obtained.

 (5)ここで開示された実施形態の半導体基板において、上記の曲率半径は65nm以下であることが好ましい。この場合には、さらに高い特性の光電変換素子を得ることが可能となる。 (5) In the semiconductor substrate according to the embodiment disclosed herein, the radius of curvature is preferably 65 nm or less. In this case, it is possible to obtain a photoelectric conversion element having higher characteristics.

 (6)ここで開示された実施形態の半導体基板において、凸部は、四角錐形状を有していてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (6) In the semiconductor substrate of the embodiment disclosed herein, the convex portion may have a quadrangular pyramid shape. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (7)ここで開示された実施形態の半導体基板は、凹部上に膜を備えていてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (7) The semiconductor substrate of the embodiment disclosed herein may include a film on the recess. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (8)ここで開示された実施形態の半導体基板において、膜は、SiCxyzvw(0≦x≦1、0≦y≦1、0≦z≦1、0≦v≦1、0≦w≦1、(x+y+z+v+w)>0)の式で表わされる膜を含んでいてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (8) In the semiconductor substrate of the embodiment disclosed herein, the film is made of SiC x N y O z F v H w (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ v). ≦ 1, 0 ≦ w ≦ 1, (x + y + z + v + w)> 0) may be included. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (9)ここで開示された実施形態の半導体基板において、膜は、非晶質半導体膜を含んでいてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (9) In the semiconductor substrate of the embodiment disclosed herein, the film may include an amorphous semiconductor film. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (10)ここで開示された実施形態の半導体基板において、非晶質半導体膜は、非晶質シリコンを含んでいてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (10) In the semiconductor substrate of the embodiment disclosed herein, the amorphous semiconductor film may include amorphous silicon. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (11)ここで開示された実施形態の半導体基板は、n型またはp型の導電型を有していてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (11) The semiconductor substrate of the embodiment disclosed herein may have an n-type or p-type conductivity type. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (12)ここで開示された実施形態の半導体基板は、n型の単結晶シリコン基板であってもよい。 (12) The semiconductor substrate of the embodiment disclosed herein may be an n-type single crystal silicon substrate.

 (13)ここで開示された実施形態の半導体基板は、上記の半導体基板を備えていてもよい。 (13) The semiconductor substrate of the embodiment disclosed herein may include the above-described semiconductor substrate.

 (14)ここで開示された実施形態は、上記の半導体基板と、半導体基板の表面とは反対側の第2の表面上の第1導電型非晶質半導体膜および第2導電型非晶質半導体膜と、第1導電型非晶質半導体膜上の第1電極と、第2導電型非晶質半導体膜上の第2電極と、を備えた、光電変換素子である。この場合には、高い特性の光電変換素子を得ることが可能となる。 (14) In the embodiment disclosed herein, the semiconductor substrate, the first conductive type amorphous semiconductor film and the second conductive type amorphous semiconductor on the second surface opposite to the surface of the semiconductor substrate are provided. A photoelectric conversion element includes a semiconductor film, a first electrode on a first conductive amorphous semiconductor film, and a second electrode on a second conductive amorphous semiconductor film. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (15)ここで開示された実施形態の光電変換素子は、第1導電型非晶質半導体膜と第2の表面との間の第1のi型非晶質半導体膜をさらに備えていてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (15) The photoelectric conversion element of the embodiment disclosed herein may further include a first i-type amorphous semiconductor film between the first conductive type amorphous semiconductor film and the second surface. Good. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (16)ここで開示された実施形態の光電変換素子は、第2導電型非晶質半導体膜と第2の表面との間の第2のi型非晶質半導体膜をさらに備えていてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (16) The photoelectric conversion element of the embodiment disclosed herein may further include a second i-type amorphous semiconductor film between the second conductive type amorphous semiconductor film and the second surface. Good. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (17)ここで開示された実施形態は、上記の半導体基板と、半導体基板の表面とは反対側の第2の表面の第1導電型領域および第2導電型領域と、第1導電型領域上の第1電極と、第2導電型領域上の第2電極と、を備えた、光電変換素子である。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (17) The embodiment disclosed herein includes the semiconductor substrate, the first conductivity type region and the second conductivity type region on the second surface opposite to the surface of the semiconductor substrate, and the first conductivity type region. A photoelectric conversion element comprising the upper first electrode and the second electrode on the second conductivity type region. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (18)ここで開示された実施形態は、上記の半導体基板と、半導体基板の表面の第1導電型領域と、半導体基板の表面とは反対側の第2の表面の第2導電型領域と、第1導電型領域上の第1電極と、第2導電型領域上の第2電極と、を備えた、光電変換素子である。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (18) An embodiment disclosed herein includes the above-described semiconductor substrate, a first conductivity type region on a surface of the semiconductor substrate, and a second conductivity type region on a second surface opposite to the surface of the semiconductor substrate. A photoelectric conversion element including a first electrode on the first conductivity type region and a second electrode on the second conductivity type region. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (19)ここで開示された実施形態は、半導体基板の表面に複数の凸部と凸部の間の凹部とを形成する工程と、凸部および凹部が形成された表面の酸エッチングを行う工程と、酸エッチング後の表面のラウンドエッチングを行う工程と、を含み、ラウンドエッチングを行う工程において、凸部の傾斜面の角度を49.5°よりも大きく55.2°以下とし、凹部の底の曲面の曲率半径を13nmよりも大きくする、半導体基板の製造方法である。この場合には、高い特性の光電変換素子を得ることが可能となる。 (19) The embodiment disclosed herein includes a step of forming a plurality of convex portions and concave portions between the convex portions on the surface of the semiconductor substrate, and a step of performing acid etching on the surface where the convex portions and the concave portions are formed. And a step of performing round etching of the surface after acid etching, and in the step of performing round etching, the angle of the inclined surface of the convex portion is set to be larger than 49.5 ° and not larger than 55.2 °, and the bottom of the concave portion This is a method for manufacturing a semiconductor substrate, wherein the radius of curvature of the curved surface is larger than 13 nm. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (20)ここで開示された実施形態の半導体基板の製造方法においては、上記の角度を50°以上とすることが好ましく、52.9°以上であることがより好ましい。この場合には、より高い特性の光電変換素子を得ることが可能となる。 (20) In the method of manufacturing a semiconductor substrate according to the embodiment disclosed herein, the angle is preferably 50 ° or more, and more preferably 52.9 ° or more. In this case, a photoelectric conversion element with higher characteristics can be obtained.

 (21)ここで開示された実施形態の半導体基板の製造方法においては、上記の角度は、53.5°以下であることが好ましい。この場合には、より高い特性の光電変換素子を得ることが可能となる。 (21) In the method of manufacturing a semiconductor substrate according to the embodiment disclosed herein, the angle is preferably 53.5 ° or less. In this case, a photoelectric conversion element with higher characteristics can be obtained.

 (22)ここで開示された実施形態の半導体基板の製造方法においては、上記の曲率半径を80nm以下とすることが好ましい。この場合には、より高い特性の光電変換素子を得ることが可能となる。 (22) In the method of manufacturing a semiconductor substrate according to the embodiment disclosed herein, it is preferable that the radius of curvature is 80 nm or less. In this case, a photoelectric conversion element with higher characteristics can be obtained.

 (23)ここで開示された実施形態の半導体基板の製造方法においては、上記の曲率半径を65nm以下とすることが好ましい。この場合には、さらに高い特性の光電変換素子を得ることが可能となる。 (23) In the method of manufacturing a semiconductor substrate according to the embodiment disclosed herein, it is preferable that the radius of curvature is 65 nm or less. In this case, it is possible to obtain a photoelectric conversion element having higher characteristics.

 (24)ここで開示された実施形態の半導体基板の製造方法は、凹部上に膜を形成する工程をさらに含んでいてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (24) The semiconductor substrate manufacturing method of the embodiment disclosed herein may further include a step of forming a film on the recess. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (25)ここで開示された実施形態の半導体基板の製造方法において、膜はSiCxyzvw(0≦x≦1、0≦y≦1、0≦z≦1、0≦v≦1、0≦w≦1、(x+y+z+v+w)>0)の式で表わされる膜を含んでいてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (25) In the method of manufacturing a semiconductor substrate according to the embodiment disclosed herein, the film is made of SiC x N y O z F v H w (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, (x + y + z + v + w)> 0) may be included. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (26)ここで開示された実施形態の半導体基板の製造方法において、膜は、非晶質半導体膜を含んでいてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (26) In the semiconductor substrate manufacturing method of the embodiment disclosed herein, the film may include an amorphous semiconductor film. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (27)ここで開示された実施形態の半導体基板の製造方法において、非晶質半導体膜は、非晶質シリコンを含んでいてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (27) In the semiconductor substrate manufacturing method of the embodiment disclosed herein, the amorphous semiconductor film may contain amorphous silicon. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (28)ここで開示された実施形態の半導体基板の製造方法において、半導体基板は、n型またはp型の導電型を有していてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (28) In the method of manufacturing a semiconductor substrate according to the embodiment disclosed herein, the semiconductor substrate may have an n-type or p-type conductivity type. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (29)ここで開示された実施形態の半導体基板の製造方法において、半導体基板はシリコンを含み、凸部と凹部とを形成する工程は、半導体基板の表面をアルカリエッチングする工程を含んでいてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (29) In the method of manufacturing a semiconductor substrate according to the embodiment disclosed herein, the semiconductor substrate includes silicon, and the step of forming the convex portion and the concave portion may include a step of alkali etching the surface of the semiconductor substrate. Good. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (30)ここで開示された実施形態の半導体基板の製造方法において、アルカリエッチングする工程は、水酸化ナトリウム水溶液および水酸化カリウム水溶液の少なくとも一方を含むアルカリ液を用いて行われてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (30) In the method for manufacturing a semiconductor substrate of the embodiment disclosed herein, the alkali etching step may be performed using an alkaline solution containing at least one of a sodium hydroxide aqueous solution and a potassium hydroxide aqueous solution. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (31)ここで開示された実施形態の半導体基板の製造方法において、酸エッチングを行う工程は、フッ化水素水溶液を用いて行われてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (31) In the method of manufacturing a semiconductor substrate according to the embodiment disclosed herein, the step of performing acid etching may be performed using a hydrogen fluoride aqueous solution. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (32)ここで開示された実施形態の半導体基板の製造方法において、ラウンドエッチングを行う工程は、フッ酸と硝酸と水とを含む混酸を用いて行われることが好ましい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (32) In the semiconductor substrate manufacturing method of the embodiment disclosed herein, the step of performing round etching is preferably performed using a mixed acid containing hydrofluoric acid, nitric acid, and water. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (33)ここで開示された実施形態の半導体基板の製造方法において、フッ酸の体積に対する硝酸の体積の比は、70以上100以下であることが好ましい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (33) In the method for manufacturing a semiconductor substrate according to the embodiment disclosed herein, the ratio of the volume of nitric acid to the volume of hydrofluoric acid is preferably 70 or more and 100 or less. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (34)ここで開示された実施形態の半導体基板の製造方法において、フッ酸の体積に対する水の体積の比は、35以上50以下であることが好ましい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (34) In the method for manufacturing a semiconductor substrate according to the embodiment disclosed herein, the ratio of the volume of water to the volume of hydrofluoric acid is preferably 35 or more and 50 or less. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (35)ここで開示された実施形態は、上記の半導体基板の製造方法により表面に複数の凸部と凸部の間の凹部とを備えた半導体基板を形成する工程と、半導体基板の表面とは反対側の第2の表面上に第1導電型非晶質半導体膜および第2導電型非晶質半導体膜を形成する工程と、第1導電型非晶質半導体膜上に第1電極を形成する工程と、第2導電型非晶質半導体膜上に第2電極を形成する工程と、を含む、光電変換素子の製造方法である。この場合には、高い特性の光電変換素子を得ることが可能となる。 (35) The embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method for manufacturing a semiconductor substrate, and a surface of the semiconductor substrate. Forming a first conductive type amorphous semiconductor film and a second conductive type amorphous semiconductor film on the second surface on the opposite side, and forming a first electrode on the first conductive type amorphous semiconductor film A method for manufacturing a photoelectric conversion element includes a step of forming and a step of forming a second electrode on a second conductivity type amorphous semiconductor film. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (36)ここで開示された実施形態の光電変換素子の製造方法は、第2の表面上に第1のi型非晶質半導体膜を形成する工程をさらに含み、第1導電型非晶質半導体膜は第1のi型非晶質半導体膜上に形成されてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (36) The method for manufacturing a photoelectric conversion element according to the embodiment disclosed herein further includes a step of forming a first i-type amorphous semiconductor film on the second surface, and the first conductivity-type amorphous The semiconductor film may be formed on the first i-type amorphous semiconductor film. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (37)ここで開示された実施形態の光電変換素子の製造方法は、第2の表面上に第2のi型非晶質半導体膜を形成する工程をさらに含み、第2導電型非晶質半導体膜は第2のi型非晶質半導体膜上に形成されてもよい。この場合にも、高い特性の光電変換素子を得ることが可能となる。 (37) The method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein further includes a step of forming a second i-type amorphous semiconductor film on the second surface, and the second conductivity-type amorphous The semiconductor film may be formed on the second i-type amorphous semiconductor film. Also in this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (38)ここで開示された実施形態は、上記の半導体基板の製造方法により表面に複数の凸部と凸部の間の凹部とを備えた半導体基板を形成する工程と、半導体基板の表面とは反対側の第2の表面に第1導電型領域および第2導電型領域を形成する工程と、第1導電型領域上に第1電極を形成する工程と、第2導電型領域上に第2電極を形成する工程と、を含む、光電変換素子の製造方法である。この場合には、高い特性の光電変換素子を得ることが可能となる。 (38) The embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method for manufacturing a semiconductor substrate, and a surface of the semiconductor substrate. Forming a first conductivity type region and a second conductivity type region on the second surface on the opposite side, forming a first electrode on the first conductivity type region, and forming a first electrode on the second conductivity type region. And a process of forming two electrodes. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 (39)ここで開示された実施形態は、上記の半導体基板の製造方法により表面に複数の凸部と凸部の間の凹部とを備えた半導体基板を形成する工程と、半導体基板の表面に第1導電型領域を形成する工程と、半導体基板の表面とは反対側の第2の表面に第2導電型領域を形成する工程と、第1導電型領域上に第1電極を形成する工程と、第2導電型領域上に第2電極を形成する工程と、を含む、光電変換素子の製造方法である。この場合には、高い特性の光電変換素子を得ることが可能となる。 (39) An embodiment disclosed herein includes a step of forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method for manufacturing a semiconductor substrate, and Forming a first conductivity type region; forming a second conductivity type region on a second surface opposite to the surface of the semiconductor substrate; and forming a first electrode on the first conductivity type region. And a step of forming a second electrode on the second conductivity type region. In this case, it is possible to obtain a photoelectric conversion element having high characteristics.

 以上のように本発明の実施形態および実施例について説明を行なったが、上述の各実施形態および実施例の構成を適宜組み合わせることも当初から予定している。 Although the embodiments and examples of the present invention have been described as described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments and examples.

 今回開示された実施形態および実施例はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiments and examples disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

 ここで開示された実施形態は、シリコン基板などの半導体基板およびその製造、ならびに太陽電池などの光電変換素子およびその製造に利用することができる。 The embodiments disclosed herein can be used for semiconductor substrates such as silicon substrates and their manufacture, and photoelectric conversion elements such as solar cells and their manufacture.

 1 半導体基板、1a 裏面、2 第1のi型非晶質半導体膜、3 第1導電型非晶質半導体膜、4 第2のi型非晶質半導体膜、5 第2導電型非晶質半導体膜、6 第1電極、7 第2電極、9a 非晶質シリコン膜、9b SiN膜、9c 炭化珪素(SiC)膜、9d 誘電体膜、11 凸部、11c 傾斜面、11d 底面、11e 線、11f 頂点、12 凹部、31,32 エッチングマスク、61a,61b 開口部、62 拡散抑制マスク、63 第1導電型領域、64 n型不純物含有ガス、65 第2導電型領域、66 p型不純物含有ガス、67 誘電体膜、70,71 コンタクトホール。 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a back surface, 1st i-type amorphous semiconductor film, 3rd 1st conductivity type amorphous semiconductor film, 4th 2nd i-type amorphous semiconductor film, 5nd 2nd conductivity type amorphous Semiconductor film, 6 first electrode, 7 second electrode, 9a amorphous silicon film, 9b SiN film, 9c silicon carbide (SiC) film, 9d dielectric film, 11 convex portion, 11c inclined surface, 11d bottom surface, 11e line , 11f apex, 12 recesses, 31, 32 etching mask, 61a, 61b opening, 62 diffusion suppression mask, 63 first conductivity type region, 64 n-type impurity containing gas, 65 second conductivity type region, 66 p-type impurity containing Gas, 67 dielectric film, 70, 71 contact holes.

Claims (10)

 複数の凸部と、前記凸部の間の凹部と、を表面に備え、
 前記凸部は傾斜面を備え、前記凹部は曲面の底を備え、
 前記傾斜面の角度が49.5°よりも大きく55.2°以下であって、
 前記曲面の曲率半径が13nmよりも大きい、半導体基板。
Provided on the surface with a plurality of convex portions and concave portions between the convex portions,
The convex portion includes an inclined surface, and the concave portion includes a curved bottom,
The angle of the inclined surface is greater than 49.5 ° and less than or equal to 55.2 °,
A semiconductor substrate having a radius of curvature of the curved surface larger than 13 nm.
 前記凸部は、四角錐形状を有する、請求項1に記載の半導体基板。 The semiconductor substrate according to claim 1, wherein the convex portion has a quadrangular pyramid shape.  前記凹部上に膜を備えた、請求項1または請求項2に記載の半導体基板。 3. The semiconductor substrate according to claim 1, wherein a film is provided on the recess.  前記半導体基板は、n型の単結晶シリコン基板である、請求項1~請求項3のいずれか1項に記載の半導体基板。 The semiconductor substrate according to any one of claims 1 to 3, wherein the semiconductor substrate is an n-type single crystal silicon substrate.  請求項1~請求項4のいずれか1項に記載の半導体基板を備えた、光電変換素子。 A photoelectric conversion element comprising the semiconductor substrate according to any one of claims 1 to 4.  半導体基板の表面に、複数の凸部と、前記凸部の間の凹部とを形成する工程と、
 前記凸部および前記凹部が形成された前記表面の酸エッチングを行う工程と、
 前記酸エッチング後の前記表面のラウンドエッチングを行う工程と、を含み、
 前記ラウンドエッチングを行う工程において、前記凸部の傾斜面の角度を49.5°よりも大きく55.2°以下とし、前記凹部の底の曲面の曲率半径を13nmよりも大きくする、半導体基板の製造方法。
Forming a plurality of convex portions and concave portions between the convex portions on the surface of the semiconductor substrate;
Performing acid etching of the surface on which the convex portions and the concave portions are formed;
Performing a round etching of the surface after the acid etching,
In the step of performing the round etching, the angle of the inclined surface of the convex portion is set to be larger than 49.5 ° and 55.2 ° or smaller, and the curvature radius of the curved surface at the bottom of the concave portion is set to be larger than 13 nm. Production method.
 前記ラウンドエッチングを行う工程は、フッ酸と硝酸と水とを含む混酸を用いて行われる、請求項6に記載の半導体基板の製造方法。 The method for manufacturing a semiconductor substrate according to claim 6, wherein the step of performing the round etching is performed using a mixed acid containing hydrofluoric acid, nitric acid, and water.  請求項6または請求項7に記載の半導体基板の製造方法により表面に複数の凸部と前記凸部の間の凹部とを備えた半導体基板を形成する工程と、
 前記半導体基板の前記表面とは反対側の第2の表面上に第1導電型非晶質半導体膜および第2導電型非晶質半導体膜を形成する工程と、
 前記第1導電型非晶質半導体膜上に第1電極を形成する工程と、
 前記第2導電型非晶質半導体膜上に第2電極を形成する工程と、を含む、光電変換素子の製造方法。
Forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method of manufacturing a semiconductor substrate according to claim 6 or 7;
Forming a first conductive amorphous semiconductor film and a second conductive amorphous semiconductor film on a second surface opposite to the surface of the semiconductor substrate;
Forming a first electrode on the first conductive type amorphous semiconductor film;
Forming a second electrode on the second conductive type amorphous semiconductor film. A method for manufacturing a photoelectric conversion element.
 請求項6または請求項7に記載の半導体基板の製造方法により表面に複数の凸部と前記凸部の間の凹部とを備えた半導体基板を形成する工程と、
 前記半導体基板の前記表面とは反対側の第2の表面に第1導電型領域および第2導電型領域を形成する工程と、
 前記第1導電型領域上に第1電極を形成する工程と、
 前記第2導電型領域上に第2電極を形成する工程と、を含む、光電変換素子の製造方法。
Forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method of manufacturing a semiconductor substrate according to claim 6 or 7;
Forming a first conductivity type region and a second conductivity type region on a second surface opposite to the surface of the semiconductor substrate;
Forming a first electrode on the first conductivity type region;
Forming a second electrode on the second conductivity type region. A method for manufacturing a photoelectric conversion element.
 請求項6または請求項7に記載の半導体基板の製造方法により表面に複数の凸部と前記凸部の間の凹部とを備えた半導体基板を形成する工程と、
 前記半導体基板の前記表面に第1導電型領域を形成する工程と、
 前記半導体基板の前記表面とは反対側の第2の表面に第2導電型領域を形成する工程と、
 前記第1導電型領域上に第1電極を形成する工程と、
 前記第2導電型領域上に第2電極を形成する工程と、を含む、光電変換素子の製造方法。
Forming a semiconductor substrate having a plurality of convex portions and concave portions between the convex portions on the surface by the method of manufacturing a semiconductor substrate according to claim 6 or 7;
Forming a first conductivity type region on the surface of the semiconductor substrate;
Forming a second conductivity type region on a second surface opposite to the surface of the semiconductor substrate;
Forming a first electrode on the first conductivity type region;
Forming a second electrode on the second conductivity type region. A method for manufacturing a photoelectric conversion element.
PCT/JP2016/073889 2015-09-24 2016-08-16 Semiconductor substrate, photoelectric conversion element, method for manufacturing semiconductor substrate, and method for manufacturing photoelectric conversion element WO2017051635A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998043304A1 (en) * 1997-03-21 1998-10-01 Sanyo Electric Co., Ltd. Photovoltaic element and method for manufacture thereof
JP2013503475A (en) * 2009-08-25 2013-01-31 シュティヒティン・エネルギーオンデルツォイク・セントラム・ネーデルランド Solar cell and method for producing such a solar cell
JP2013518425A (en) * 2010-01-27 2013-05-20 コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブ Method for producing photovoltaic cell including pretreatment of the surface of a crystalline silicon substrate
WO2014083804A1 (en) * 2012-11-29 2014-06-05 三洋電機株式会社 Solar cell
WO2015122257A1 (en) * 2014-02-13 2015-08-20 シャープ株式会社 Photoelectric conversion element

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998043304A1 (en) * 1997-03-21 1998-10-01 Sanyo Electric Co., Ltd. Photovoltaic element and method for manufacture thereof
JP2013503475A (en) * 2009-08-25 2013-01-31 シュティヒティン・エネルギーオンデルツォイク・セントラム・ネーデルランド Solar cell and method for producing such a solar cell
JP2013518425A (en) * 2010-01-27 2013-05-20 コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブ Method for producing photovoltaic cell including pretreatment of the surface of a crystalline silicon substrate
WO2014083804A1 (en) * 2012-11-29 2014-06-05 三洋電機株式会社 Solar cell
WO2015122257A1 (en) * 2014-02-13 2015-08-20 シャープ株式会社 Photoelectric conversion element

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