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WO2017049714A1 - 降低内嵌式触摸液晶面板的漏电流的方法及设备 - Google Patents

降低内嵌式触摸液晶面板的漏电流的方法及设备 Download PDF

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Publication number
WO2017049714A1
WO2017049714A1 PCT/CN2015/093351 CN2015093351W WO2017049714A1 WO 2017049714 A1 WO2017049714 A1 WO 2017049714A1 CN 2015093351 W CN2015093351 W CN 2015093351W WO 2017049714 A1 WO2017049714 A1 WO 2017049714A1
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voltage
indicates
signal
data
pixel
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PCT/CN2015/093351
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English (en)
French (fr)
Inventor
林建宏
蔡育徵
黄耀立
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/902,029 priority Critical patent/US9778773B2/en
Publication of WO2017049714A1 publication Critical patent/WO2017049714A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance

Definitions

  • the present invention generally relates to the field of in-cell touch liquid crystal panel technologies, and more particularly to a method and apparatus for reducing leakage current of an in-cell touch liquid crystal panel.
  • Liquid crystal display with touch panel is currently the most widely used portable flat panel display, and has gradually become widely used in various electronic devices (for example, mobile communication terminals, personal digital assistants (PDAs), digital cameras, computers, notebook computers, etc.).
  • PDAs personal digital assistants
  • an original external touch panel component is integrated with a liquid crystal panel (in-cell touch), thereby achieving thinning and weight reduction of the panel, and embedding a touch in the pixel.
  • the sensor also saves on manufacturing costs.
  • the currently popular in cell touch liquid crystal display usually consists of an upper and lower substrate and an intermediate liquid crystal layer, and the substrate is composed of glass, electrodes and the like. If the upper and lower substrates have electrodes, a vertical electric field mode display can be formed, for example, TN (Twist Nematic) mode, VA (Vertical Alignment) mode, and MVA (Multidomain Vertical Alignment) mode developed to solve the narrow viewing angle.
  • TN Transmission Nematic
  • VA Very Alignment
  • MVA Multidomain Vertical Alignment
  • the electrodes are located only on one side of the substrate, and a display of a transverse electric field mode is formed, for example, an IPS (In-plane switching) mode, an FFS (Fringe Field Switching) mode, or the like.
  • the electrodes used often share an electrode of a longitudinal electric field or a transverse electric field, that is, a common electrode, and the operation principle is: when scanning the touch signal, the original input to the common electrode is displayed for the display. The signal is converted into a signal for scanning the touch signal, and after the touch signal is scanned, it is converted into a signal for display by the display.
  • FIG. 1 shows a schematic diagram of a pixel array of an in-cell touch liquid crystal panel.
  • D1-D5 indicate data lines
  • G1-G5 indicate scan lines.
  • 2 is a schematic diagram of a pixel circuit.
  • the pixel circuit includes: a thin film transistor, a liquid crystal capacitor (Clc), a storage capacitor (Cst), and a parasitic capacitance (Cgs) between a gate and a source of the thin film transistor.
  • An exemplary embodiment of the present invention is to provide a method and apparatus for reducing leakage current of an in-cell touch liquid crystal panel to overcome the problem of large leakage current of the existing in-cell touch liquid crystal panel.
  • a method of reducing leakage current of an in-cell touch liquid crystal panel wherein the panel includes a pixel array and scan lines and data lines connected to respective pixels in the pixel array, wherein The method includes: adjusting, according to a voltage on a data line connected to the pixel and a signal for scanning a touch signal input to a common electrode of the pixel, through the data line output during a period of scanning the touch signal A signal after the voltage to lower the drain-source voltage of the thin film transistor in the pixel.
  • the thin film transistor is a P-type transistor, wherein a voltage on a data line connected to the pixel is in a positive half cycle, and a signal input to the common electrode of the pixel for scanning a touch signal is low When the level is turned to the pulse signal of the high level, the signal after the voltage increase is output through the data line during the period in which the touch signal is scanned.
  • the voltage interval of the signal after the voltage is increased is: [V data(min) +(Vgh-Vgl)*Cgs/(Clc min +Cst)] to [V data(max) +(Vgh- Vgl)*Cgs/(Clc max +Cst)], where Vdata(min) indicates the minimum voltage on the data line, V data(max) indicates the maximum voltage on the data line, and Vgh indicates the maximum voltage on the scan line, Vgl Indicates the minimum voltage on the scan line, Cgs indicates the capacitance value of the parasitic capacitance between the gate and source of the thin film transistor, Cst indicates the capacitance value of the storage capacitor, Clc min indicates the minimum capacitance value of the liquid crystal capacitor, and Clc max indicates the liquid crystal capacitance The maximum capacitance value.
  • the thin film transistor is an N-type transistor, wherein a voltage on a data line connected to the pixel is in a negative half cycle, and a signal input to a common electrode of the pixel for scanning a touch signal is high When the level is turned to the pulse signal of the low level, the signal after the voltage is reduced is output through the data line during the period in which the touch signal is scanned.
  • the voltage interval of the signal after the voltage reduction is: [-V data(min) -(Vgh-Vgl)*Cgs/(Clc min +Cst)] to [-V data(max) -(Vgh -Vgl)*Cgs/(Clc max +Cst)], where Vdata(min) indicates the minimum voltage on the data line, Vdata (max) indicates the maximum voltage on the data line, and Vgh indicates the maximum voltage on the scan line.
  • Vgl indicates the minimum voltage on the scan line
  • Cgs indicates the capacitance value of the parasitic capacitance between the gate and the source of the thin film transistor
  • Cst indicates the capacitance value of the storage capacitor
  • Clc min indicates the minimum capacitance value of the liquid crystal capacitor
  • Clc max indicates the liquid crystal The maximum capacitance of the capacitor.
  • an apparatus for reducing leakage current of an in-cell touch liquid crystal panel wherein the panel includes a pixel array and scan lines and data lines connected to respective pixels in the pixel array
  • the device includes: a voltage control unit that passes the voltage for scanning the touch signal according to the voltage on the data line connected to the pixel and the signal input to the common electrode of the pixel, during the scanning of the touch signal
  • the data line outputs a signal after adjusting the voltage to reduce a drain-source voltage of the thin film transistor in the pixel.
  • the thin film transistor is a P-type transistor, wherein a voltage control unit is in a positive half cycle when a voltage on a data line connected to the pixel, and a signal input to the common electrode of the pixel for scanning a touch signal
  • a voltage control unit is in a positive half cycle when a voltage on a data line connected to the pixel, and a signal input to the common electrode of the pixel for scanning a touch signal
  • the voltage interval of the signal after the voltage is increased is: [V data(min) +(Vgh-Vgl)*Cgs/(Clc min +Cst)] to [V data(max) +(Vgh- Vgl)*Cgs/(Clc max +Cst)], where Vdata(min) indicates the minimum voltage on the data line, V data(max) indicates the maximum voltage on the data line, and Vgh indicates the maximum voltage on the scan line, Vgl Indicates the minimum voltage on the scan line, Cgs indicates the capacitance value of the parasitic capacitance between the gate and source of the thin film transistor, Cst indicates the capacitance value of the storage capacitor, Clc min indicates the minimum capacitance value of the liquid crystal capacitor, and Clc max indicates the liquid crystal capacitance The maximum capacitance value.
  • the thin film transistor is an N-type transistor, wherein the voltage control unit is in a negative half cycle when the voltage on the data line connected to the pixel is input to the common electrode of the pixel for scanning
  • the signal of the touch signal is a pulse signal that is turned from a high level to a low level
  • the signal after the voltage is reduced is output through the data line during a period in which the touch signal is scanned.
  • the voltage interval of the signal after the voltage reduction is: [-V data(min) -(Vgh-Vgl)*Cgs/(Clc min +Cst)] to [-V data(max) -(Vgh -Vgl)*Cgs/(Clc max +Cst)], where Vdata(min) indicates the minimum voltage on the data line, Vdata (max) indicates the maximum voltage on the data line, and Vgh indicates the maximum voltage on the scan line.
  • Vgl indicates the minimum voltage on the scan line
  • Cgs indicates the capacitance value of the parasitic capacitance between the gate and the source of the thin film transistor
  • Cst indicates the capacitance value of the storage capacitor
  • Clc min indicates the minimum capacitance value of the liquid crystal capacitor
  • Clc max indicates the liquid crystal The maximum capacitance of the capacitor.
  • the drain-source voltage of the thin film transistor in the pixel can be reduced, thereby effectively reducing leakage current and improving picture quality.
  • FIG. 1 shows a schematic diagram of a pixel array of an in-cell touch liquid crystal panel
  • Figure 2 shows a schematic diagram of a pixel circuit
  • FIG. 3 illustrates a flow chart of a method of reducing leakage current of an in-cell touch liquid crystal panel, according to an exemplary embodiment of the present invention
  • FIG. 4 illustrates a schematic diagram of leakage current for a P-type transistor, in accordance with an exemplary embodiment of the present invention
  • FIG. 5 illustrates a comparison diagram before and after an increased voltage for a P-type transistor, according to an exemplary embodiment of the present invention
  • FIG. 6 illustrates a schematic diagram of leakage current for an N-type transistor, according to an exemplary embodiment of the present invention
  • FIG. 7 illustrates pairs before and after voltage reduction for an N-type transistor, according to an exemplary embodiment of the present invention.
  • FIG. 8 illustrates a block diagram of an apparatus for reducing leakage current of an in-cell touch liquid crystal panel, according to an exemplary embodiment of the present invention.
  • FIG. 3 illustrates a flow chart of a method of reducing leakage current of an in-cell touch liquid crystal panel, according to an exemplary embodiment of the present invention.
  • the in-cell touch liquid crystal panel includes a pixel array and scan lines and data lines connected to respective pixels in the pixel array.
  • the method can be implemented by an in-line touch liquid crystal panel or by a computer program, so that the above method is implemented when the program is run.
  • step S10 according to a voltage on a data line connected to a pixel and a signal for scanning a touch signal input to a common electrode of the pixel, the data line is passed during a period in which the touch signal is scanned.
  • a signal after adjusting the voltage is output to reduce a drain-source voltage of the thin film transistor in the pixel.
  • the pixel voltage will have a strong coupling effect as the signal for scanning the touch signal is input to the common electrode during the period in which the touch signal is scanned.
  • a large leakage current occurs, so according to an exemplary embodiment of the present invention, the drain-source voltage is lowered by adjusting the voltage on the data line, thereby forming a lower leakage current.
  • the thin film transistor in the pixel is a P-type transistor (eg, a PMOS transistor)
  • the signal for scanning the touch signal is a pulse signal that is turned from a low level to a high level
  • the signal after the voltage is increased may be output through the data line during a period in which the touch signal is scanned.
  • the voltage is in the positive half cycle, that is, the voltage is greater than or equal to 0, and the pulse signal that is turned from the low level to the high level is a pulse signal that is turned from the negative voltage or the ground voltage to the positive voltage.
  • the voltage interval of the signal after increasing the voltage may be: [V data(min) +(Vgh-Vgl)*Cgs/(Clc min +Cst)] to [V data(max) +(Vgh- Vgl)*Cgs/(Clc max +Cst)], where Vdata(min) indicates the minimum voltage on the data line, V data(max) indicates the maximum voltage on the data line, and Vgh indicates the maximum voltage on the scan line, Vgl Indicates the minimum voltage on the scan line, Cgs indicates the capacitance value of the parasitic capacitance between the gate and source of the thin film transistor, Cst indicates the capacitance value of the storage capacitor, Clc min indicates the minimum capacitance value of the liquid crystal capacitor, and Clc max indicates the liquid crystal capacitance The maximum capacitance value.
  • FIG. 4 illustrates a schematic diagram of leakage current for a P-type transistor, in accordance with an exemplary embodiment of the present invention.
  • the abscissa indicates the gate-source voltage (Vgs) of the thin film transistor
  • the ordinate indicates the drain-source current (Ids) of the thin film transistor
  • L 1 indicates the IV curve when the drain-source voltage of the thin film transistor is high
  • L 2 indicates the thin film transistor
  • L 3 indicates the IV curve when the drain-source voltage of the thin film transistor is low
  • the circle indicates the corresponding position when the LCD display (that is, the signal input to the common electrode is the signal for display display)
  • the triangle indicates a position at which the scan touch signal (ie, the signal input to the common electrode is a signal for scanning the touch signal) and does not increase the voltage on the data line
  • the diamond indicates scanning the touch signal and increasing the data line.
  • the drain-source voltage is low, and therefore, the leakage current is small; and when input to the common electrode
  • the signal is used to scan the signal of the touch signal and the voltage on the data line is not increased (ie, the position indicated by the triangle)
  • the drain-source voltage is high, and therefore, the leakage current is large.
  • the voltage on the data line i.e., the position indicated by the diamond
  • the drain-source voltage is lowered, thereby reducing the leakage current.
  • FIG. 5 illustrates a comparison diagram before and after an increased voltage for a P-type transistor according to an exemplary embodiment of the present invention.
  • a voltage on a data line is not increased during scanning of a touch signal, a coupling effect occurs. , a significant voltage drop ( ⁇ V (leakage)) is generated, and a large leakage current is formed, resulting in an increase in power consumption and poor picture quality.
  • ⁇ V leakage
  • the voltage on the data line is increased during the scanning of the touch signal, a lower voltage drop will be formed, resulting in a lower leakage current.
  • the thin film transistor in the pixel is an N-type transistor (eg, an NMOS transistor)
  • the signal for scanning the touch signal is a pulse signal that is turned from a high level to a low level
  • the signal after the voltage is reduced can be output through the data line during the period in which the touch signal is scanned.
  • the voltage is in the negative half cycle, that is, the voltage is less than or equal to 0, and the pulse signal that is turned from the high level to the low level is a pulse signal that is turned from the positive voltage or the ground voltage to the negative voltage.
  • the voltage interval of the voltage-reduced signal may be: [-V data(min) -(Vgh-Vgl)*Cgs/(Clc min +Cst)] to [-V data(max) -(Vgh -Vgl)*Cgs/(Clc max +Cst)], where Vdata(min) indicates the minimum voltage on the data line, Vdata (max) indicates the maximum voltage on the data line, and Vgh indicates the maximum voltage on the scan line.
  • Vgl indicates the minimum voltage on the scan line
  • Cgs indicates the capacitance value of the parasitic capacitance between the gate and the source of the thin film transistor
  • Cst indicates the capacitance value of the storage capacitor
  • Clc min indicates the minimum capacitance value of the liquid crystal capacitor
  • Clc max indicates the liquid crystal The maximum capacitance of the capacitor.
  • FIG. 6 illustrates a schematic diagram of leakage current for an N-type transistor, according to an exemplary embodiment of the present invention.
  • the abscissa indicates the gate-source voltage (Vgs) of the thin film transistor
  • the ordinate indicates the drain-source current (Ids) of the thin film transistor
  • L 1 indicates the IV curve when the drain-source voltage of the thin film transistor is high
  • L 2 indicates the thin film transistor
  • L 3 indicates the IV curve when the drain-source voltage of the thin film transistor is low
  • the circle indicates the corresponding position when the LCD display (that is, the signal input to the common electrode is the signal for display display)
  • the triangle indicates a position at which the scanning touch signal (ie, the signal input to the common electrode is a signal for scanning the touch signal) and does not lower the voltage on the data line
  • the diamond indicates that the touch signal is scanned and the voltage on the data line is lowered.
  • the signal input to the common electrode is a signal for display display (ie, the position indicated by the circle)
  • the drain-source voltage is low, and therefore, the leakage current is small
  • the signal is used to scan the signal of the touch signal and the voltage on the data line is not lowered (ie, the position indicated by the triangle)
  • the drain-source voltage is high, and therefore, the leakage current is large.
  • the voltage on the data line i.e., the position indicated by the diamond
  • the drain-source voltage is lowered, thereby reducing the leakage current.
  • FIG. 7 illustrates a comparison diagram before and after a voltage reduction for an N-type transistor according to an exemplary embodiment of the present invention.
  • ⁇ V leakage
  • FIG. 8 illustrates a block diagram of an apparatus for reducing leakage current of an in-cell touch liquid crystal panel, according to an exemplary embodiment of the present invention.
  • the in-cell touch liquid crystal panel includes a pixel array and scan lines and data lines connected to respective pixels in the pixel array.
  • an apparatus for reducing leakage current of an in-cell touch liquid crystal panel includes a voltage control unit 10.
  • the unit may be implemented by a general-purpose hardware processor such as a digital signal processor, a field programmable gate array, or a dedicated hardware processor such as a dedicated chip, or may be implemented by a computer program entirely by software, for example, Implemented as a module in software installed in an in-line touch LCD panel.
  • the voltage control unit 10 is configured to output an adjustment through the data line during a period of scanning the touch signal according to a voltage on the data line connected to the pixel and a signal for scanning the touch signal input to the common electrode of the pixel. A signal after the voltage to lower the drain-source voltage of the thin film transistor in the pixel.
  • the voltage control unit 10 reduces the drain-source voltage by adjusting the voltage on the data line, thereby forming a lower leakage current.
  • the signal for scanning the touch signal of the electrode is a pulse signal that is turned from a low level to a high level
  • the signal after the voltage is increased may be output through the data line during a period in which the touch signal is scanned.
  • the voltage interval of the signal after increasing the voltage may be: [V data(min) +(Vgh-Vgl)*Cgs/(Clc min +Cst)] to [V data(max) +(Vgh- Vgl)*Cgs/(Clc max +Cst)], where Vdata(min) indicates the minimum voltage on the data line, V data(max) indicates the maximum voltage on the data line, and Vgh indicates the maximum voltage on the scan line, Vgl Indicates the minimum voltage on the scan line, Cgs indicates the capacitance value of the parasitic capacitance between the gate and source of the thin film transistor, Cst indicates the capacitance value of the storage capacitor, Clc min indicates the minimum capacitance value of the liquid crystal capacitor, and Clc max indicates the liquid crystal capacitance The maximum capacitance value.
  • the voltage of the voltage control unit 10 when the data line connected to the pixel is in a negative half cycle, and is input to the pixel
  • the signal for scanning the touch signal of the common electrode is a pulse signal that is turned from a high level to a low level
  • the voltage-reduced signal can be output through the data line during a period in which the touch signal is scanned.
  • the voltage interval of the voltage-reduced signal may be: [-V data(min) -(Vgh-Vgl)*Cgs/(Clc min +Cst)] to [-V data(max) -(Vgh -Vgl)*Cgs/(Clc max +Cst)], where Vdata(min) indicates the minimum voltage on the data line, Vdata (max) indicates the maximum voltage on the data line, and Vgh indicates the maximum voltage on the scan line.
  • Vgl indicates the minimum voltage on the scan line
  • Cgs indicates the capacitance value of the parasitic capacitance between the gate and the source of the thin film transistor
  • Cst indicates the capacitance value of the storage capacitor
  • Clc min indicates the minimum capacitance value of the liquid crystal capacitor
  • Clc max indicates the liquid crystal The maximum capacitance of the capacitor.
  • a method and apparatus for reducing leakage current of an in-cell touch liquid crystal panel can reduce a drain-source voltage of a thin film transistor in a pixel, thereby effectively reducing leakage current and improving picture quality.

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Abstract

提供一种降低内嵌式触摸液晶面板的漏电流的方法及设备。该方法包括：根据与像素连接的数据线上的电压和输入到像素的共用电极的用于扫描触摸信号的信号，在扫描触摸信号的时间段内，通过数据线输出调整电压后的信号（S10），以降低像素的薄膜晶体管的漏源电压。根据该方法及其设备，能够有效降低内嵌式触摸液晶面板的漏电流。

Description

降低内嵌式触摸液晶面板的漏电流的方法及设备 技术领域
本发明总体说来涉及内嵌式触摸液晶面板技术领域，更具体地讲，涉及一种降低内嵌式触摸液晶面板的漏电流的方法及设备。
背景技术
液晶显示器搭配触摸面板是目前使用最广泛的一种便携式平板显示器，已经逐渐成为各种电子设备(例如，移动通信终端、个人数字助理(PDA)、数字相机、计算机、笔记本电脑等)所广泛应用的具有高分辨率彩色屏幕的显示器，近年来，原本外置的触摸面板部件与液晶面板实现一体化(in-cell touch)，从而实现面板的薄型化和轻量化，并因为在像素内嵌入触摸传感器也节省了制造成本。
目前普遍的in cell touch液晶显示器，通常由上下衬底和中间液晶层组成，衬底由玻璃、电极等组成。如果上下衬底都有电极，可以形成纵向电场模式的显示器，例如，TN(Twist Nematic)模式，VA(Vertical Alignment)模式，以及为了解决视角过窄开发的MVA(Multidomain Vertical Alignment)模式。另外一类与上述显示器不同，电极只位于一侧衬底，形成横向电场模式的显示器，例如，IPS(In-plane switching)模式、FFS(Fringe Field Switching)模式等。由于in-cell touch液晶面板的架构，其所使用的电极常共用纵向电场或横向电场的一个电极，也就是共用电极，其运作原理为：当扫描触摸信号时，原本输入到共用电极供显示器显示的信号就转变成用于扫描触摸信号的信号，待扫描触摸信号结束后，再转变成供显示器显示的信号。
图1示出内嵌式触摸液晶面板的像素阵列的示意图，如图1所示，D1-D5指示数据线，G1-G5指示扫描线。图2示出像素电路的示意图，如图2所示，像素电路包括：薄膜晶体管、液晶电容(Clc)、储存电容(Cst)、薄膜晶体管的栅极和源极之间的寄生电容(Cgs)、像素电极(pixel ITO)、滤色器层侧的共用电极、阵列层侧的共用电极，由于在横向电场模式的面板中，没有滤色器层侧的共用电极，只有阵列层侧的共用电极，因此，液晶电容和储存电容都连 接到阵列层侧的共用电极。
在现有的内嵌式触摸液晶面板中，还存在较大的漏电流，导致电耗增加、画面品质差等问题。
发明内容
本发明的示例性实施例在于提供一种降低内嵌式触摸液晶面板的漏电流的方法及设备，以克服现有的内嵌式触摸液晶面板的漏电流较大的问题。
根据本发明的示例性实施例，提供一种降低内嵌式触摸液晶面板的漏电流的方法，其中，所述面板包括像素阵列以及与像素阵列中的各个像素连接的扫描线和数据线，其中，所述方法包括：根据与像素连接的数据线上的电压和输入到所述像素的共用电极的用于扫描触摸信号的信号，在扫描触摸信号的时间段内，通过所述数据线输出调整电压后的信号，以降低所述像素中的薄膜晶体管的漏源电压。
可选地，所述薄膜晶体管为P型晶体管，其中，当与像素连接的数据线上的电压在正半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由低电平转向高电平的脉冲信号时，在扫描触摸信号的时间段内，通过所述数据线输出增大电压后的信号。
可选地，所述增大电压后的信号的电压区间为：[Vdata(min)+(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[Vdata(max)+(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
可选地，所述薄膜晶体管为N型晶体管，其中，当与像素连接的数据线上的电压在负半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由高电平转向低电平的脉冲信号时，在扫描触摸信号的时间段内，通过所述数据线输出降低电压后的信号。
可选地，所述降低电压后的信号的电压区间为：[-Vdata(min)-(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[-Vdata(max)-(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
根据本发明的另一示例性实施例，提供一种降低内嵌式触摸液晶面板的漏电流的设备，其中，所述面板包括像素阵列以及与像素阵列中的各个像素连接的扫描线和数据线，其中，所述设备包括：电压控制单元，根据与像素连接的数据线上的电压和输入到所述像素的共用电极的用于扫描触摸信号的信号，在扫描触摸信号的时间段内，通过所述数据线输出调整电压后的信号，以降低所述像素中的薄膜晶体管的漏源电压。
可选地，所述薄膜晶体管为P型晶体管，其中，电压控制单元当与像素连接的数据线上的电压在正半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由低电平转向高电平的脉冲信号时，在扫描触摸信号的时间段内，通过所述数据线输出增大电压后的信号。
可选地，所述增大电压后的信号的电压区间为：[Vdata(min)+(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[Vdata(max)+(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
可选地，所述薄膜晶体管为N型晶体管，其中，电压控制单元当与像素连接的数据线上的电压在负半周期，并且输入到所述像素的共用电极的用于扫描 触摸信号的信号为由高电平转向低电平的脉冲信号时，在扫描触摸信号的时间段内，通过所述数据线输出降低电压后的信号。
可选地，所述降低电压后的信号的电压区间为：[-Vdata(min)-(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[-Vdata(max)-(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
在根据本发明示例性实施例的降低内嵌式触摸液晶面板的漏电流的方法及设备中，能够降低像素中的薄膜晶体管的漏源电压，从而有效降低漏电流，提高画面品质。
将在接下来的描述中部分阐述本发明总体构思另外的方面和/或优点，还有一部分通过描述将是清楚的，或者可以经过本发明总体构思的实施而得知。
附图说明
图1示出内嵌式触摸液晶面板的像素阵列的示意图；
图2示出像素电路的示意图；
图3示出根据本发明示例性实施例的降低内嵌式触摸液晶面板的漏电流的方法的流程图；
图4示出根据本发明示例性实施例的针对P型晶体管的漏电流的示意图；
图5示出根据本发明示例性实施例的针对P型晶体管的增大电压前后的对比图；
图6示出根据本发明示例性实施例的针对N型晶体管的漏电流的示意图；
图7示出根据本发明示例性实施例的针对N型晶体管的降低电压前后的对 比图；
图8示出根据本发明示例性实施例的降低内嵌式触摸液晶面板的漏电流的设备的框图。
具体实施方式
现将详细参照本发明的实施例，所述实施例的示例在附图中示出，其中，相同的标号始终指的是相同的部件。以下将通过参照附图来说明所述实施例，以便解释本发明。
图3示出根据本发明示例性实施例的降低内嵌式触摸液晶面板的漏电流的方法的流程图。这里，所述内嵌式触摸液晶面板包括像素阵列以及与像素阵列中的各个像素连接的扫描线和数据线。所述方法可由内嵌式触摸液晶面板来完成，也可通过计算机程序来实现，从而当运行该程序时，实现上述方法。
参照图3，在步骤S10，根据与像素连接的数据线上的电压和输入到所述像素的共用电极的用于扫描触摸信号的信号，在扫描触摸信号的时间段内，通过所述数据线输出调整电压后的信号，以降低所述像素中的薄膜晶体管的漏源电压。
由于像素电极与共用电极形成的电容占整个像素电容的大部分，因此，在扫描触摸信号的时间段内，像素电压将随着向共用电极输入用于扫描触摸信号的信号产生强大的耦合效应，出现较大的漏电流，所以根据本发明的示例性实施例，通过调整数据线上的电压来降低漏源电压，从而形成较低的漏电流。
作为示例，在像素中的薄膜晶体管为P型晶体管(例如，PMOS管)的情况下，当与像素连接的数据线上的电压在正半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由低电平转向高电平的脉冲信号时，可在扫描触摸信号的时间段内，通过所述数据线输出增大电压后的信号。
这里，电压在正半周期即电压大于等于0，由低电平转向高电平的脉冲信号即由负电压或地电压转向正电压的脉冲信号。
作为示例，所述增大电压后的信号的电压区间可为：[Vdata(min)+(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至 [Vdata(max)+(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
图4示出根据本发明示例性实施例的针对P型晶体管的漏电流的示意图。这里，横坐标指示薄膜晶体管的栅源电压(Vgs)，纵坐标指示薄膜晶体管的漏源电流(Ids)，L1指示薄膜晶体管的漏源电压较高时的IV曲线，L2指示薄膜晶体管的漏源电压中等时的IV曲线，L3指示薄膜晶体管的漏源电压较低时的IV曲线，圆圈指示LCD显示(即，输入到共用电极的信号为用于显示器显示的信号)时对应的位置，三角形指示扫描触摸信号(即，输入到共用电极的信号为用于扫描触摸信号的信号)且未增大数据线上的电压时对应的位置，菱形指示扫描触摸信号且增大数据线上的电压时对应的位置。如图4所示，当输入到共用电极的信号为用于显示器显示的信号时(即，圆圈所指示的位置)，漏源电压较低，因此，漏电流较小；而当输入到共用电极的信号为用于扫描触摸信号的信号且未增大数据线上的电压时(即，三角形所指示的位置)，漏源电压较高，因此，漏电流较大。在根据本发明的示例性实施例中，由于在扫描触摸信号期间增大了数据线上的电压(即，菱形所指示的位置)，因此降低了漏源电压，从而降低了漏电流。
图5示出根据本发明示例性实施例的针对P型晶体管的增大电压前后的对比图，如图5所示，如果在扫描触摸信号期间未增大数据线上的电压，由于发生耦合效应，则产生明显的电压压降(△V(leakage))，形成较大的漏电流，从而导致电耗增加，画面品质差。而如果在扫描触摸信号期间增大数据线上的电压，则将形成较低的电压压降，从而形成较低的漏电流。
作为另一示例，在像素中的薄膜晶体管为N型晶体管(例如，NMOS管)的情况下，当与像素连接的数据线上的电压在负半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由高电平转向低电平的脉冲信号时，可在扫描触摸信号的时间段内，通过所述数据线输出降低电压后的信号。
这里，电压在负半周期即电压小于等于0，由高电平转向低电平的脉冲信号即由正电压或地电压转向负电压的脉冲信号。
作为示例，所述降低电压后的信号的电压区间可为：[-Vdata(min)-(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[-Vdata(max)-(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
图6示出根据本发明示例性实施例的针对N型晶体管的漏电流的示意图。这里，横坐标指示薄膜晶体管的栅源电压(Vgs)，纵坐标指示薄膜晶体管的漏源电流(Ids)，L1指示薄膜晶体管的漏源电压较高时的IV曲线，L2指示薄膜晶体管的漏源电压中等时的IV曲线，L3指示薄膜晶体管的漏源电压较低时的IV曲线，圆圈指示LCD显示(即，输入到共用电极的信号为用于显示器显示的信号)时对应的位置，三角形指示扫描触摸信号(即，输入到共用电极的信号为用于扫描触摸信号的信号)且未降低数据线上的电压时对应的位置，菱形指示扫描触摸信号且降低数据线上的电压时对应的位置。如图6所示，当输入到共用电极的信号为用于显示器显示的信号时(即，圆圈所指示的位置)，漏源电压较低，因此，漏电流较小；而当输入到共用电极的信号为用于扫描触摸信号的信号且未降低数据线上的电压时(即，三角形所指示的位置)，漏源电压较高，因此，漏电流较大。在根据本发明的示例性实施例中，由于在扫描触摸信号期间降低了数据线上的电压(即，菱形所指示的位置)，因此降低了漏源电压，从而降低了漏电流。
图7示出根据本发明示例性实施例的针对N型晶体管的降低电压前后的对比图，如图7所示，如果在扫描触摸信号期间未降低数据线上的电压，由于发生耦合效应，则产生明显的电压压降(△V(leakage))，形成较大的漏电流，从而导致电耗增加，画面品质差。而如果在扫描触摸信号期间降低数据线上的电压，则将形成较低的电压压降，从而形成较低的漏电流。
图8示出根据本发明示例性实施例的降低内嵌式触摸液晶面板的漏电流的设备的框图。这里，所述内嵌式触摸液晶面板包括像素阵列以及与像素阵列中的各个像素连接的扫描线和数据线。
如图8所示，根据本发明示例性实施例的降低内嵌式触摸液晶面板的漏电流的设备包括：电压控制单元10。所述单元可由数字信号处理器、现场可编程门阵列等通用硬件处理器来实现，也可通过专用芯片等专用硬件处理器来实现，还可完全通过计算机程序来以软件方式实现，例如，被实现为安装在内嵌式触摸液晶面板中的软件中的模块。
电压控制单元10用于根据与像素连接的数据线上的电压和输入到所述像素的共用电极的用于扫描触摸信号的信号，在扫描触摸信号的时间段内，通过所述数据线输出调整电压后的信号，以降低所述像素中的薄膜晶体管的漏源电压。
由于像素电极与共用电极形成的电容占整个像素电容的大部分，因此，在扫描触摸信号的时间段内，像素电压将随着向共用电极输入用于扫描触摸信号的信号产生强大的耦合效应，出现较大的漏电流，所以根据本发明的示例性实施例，电压控制单元10通过调整数据线上的电压来降低漏源电压，从而形成较低的漏电流。
作为示例，在像素中的薄膜晶体管为P型晶体管(例如，PMOS管)的情况下，电压控制单元10当与像素连接的数据线上的电压在正半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由低电平转向高电平的脉冲信号时，可在扫描触摸信号的时间段内，通过所述数据线输出增大电压后的信号。
作为示例，所述增大电压后的信号的电压区间可为：[Vdata(min)+(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[Vdata(max)+(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电 容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
作为另一示例，在像素中的薄膜晶体管为N型晶体管(例如，NMOS管)的情况下，电压控制单元10当与像素连接的数据线上的电压在负半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由高电平转向低电平的脉冲信号时，可在扫描触摸信号的时间段内，通过所述数据线输出降低电压后的信号。
作为示例，所述降低电压后的信号的电压区间可为：[-Vdata(min)-(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[-Vdata(max)-(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
根据本发明示例性实施例的降低内嵌式触摸液晶面板的漏电流的方法及设备，能够降低像素中的薄膜晶体管的漏源电压，从而有效降低漏电流，提高画面品质。
虽然已表示和描述了本发明的一些示例性实施例，但本领域技术人员应该理解，在不脱离由权利要求及其等同物限定其范围的本发明的原理和精神的情况下，可以对这些实施例进行修改。

Claims (10)

  1. 一种降低内嵌式触摸液晶面板的漏电流的方法，其中，所述面板包括像素阵列以及与像素阵列中的各个像素连接的扫描线和数据线，其中，所述方法包括：
    根据与像素连接的数据线上的电压和输入到所述像素的共用电极的用于扫描触摸信号的信号，在扫描触摸信号的时间段内，通过所述数据线输出调整电压后的信号，以降低所述像素中的薄膜晶体管的漏源电压。
  2. 根据权利要求1所述的方法，其中，所述薄膜晶体管为P型晶体管，
    其中，当与像素连接的数据线上的电压在正半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由低电平转向高电平的脉冲信号时，在扫描触摸信号的时间段内，通过所述数据线输出增大电压后的信号。
  3. 根据权利要求2所述的方法，其中，所述增大电压后的信号的电压区间为：[Vdata(min)+(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[Vdata(max)+(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
  4. 根据权利要求1所述的方法，其中，所述薄膜晶体管为N型晶体管，
    其中，当与像素连接的数据线上的电压在负半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由高电平转向低电平的脉冲信号时，在扫描触摸信号的时间段内，通过所述数据线输出降低电压后的信号。
  5. 根据权利要求4所述的方法，其中，所述降低电压后的信号的电压区间为：[-Vdata(min)-(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至 [-Vdata(max)-(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
  6. 一种降低内嵌式触摸液晶面板的漏电流的设备，其中，所述面板包括像素阵列以及与像素阵列中的各个像素连接的扫描线和数据线，其中，所述设备包括：
    电压控制单元，根据与像素连接的数据线上的电压和输入到所述像素的共用电极的用于扫描触摸信号的信号，在扫描触摸信号的时间段内，通过所述数据线输出调整电压后的信号，以降低所述像素中的薄膜晶体管的漏源电压。
  7. 根据权利要求6所述的设备，其中，所述薄膜晶体管为P型晶体管，
    其中，电压控制单元当与像素连接的数据线上的电压在正半周期，并且输入到所述像素的共用电极的用于扫描触摸信号的信号为由低电平转向高电平的脉冲信号时，在扫描触摸信号的时间段内，通过所述数据线输出增大电压后的信号。
  8. 根据权利要求7所述的设备，其中，所述增大电压后的信号的电压区间为：[Vdata(min)+(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[Vdata(max)+(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
  9. 根据权利要求6所述的设备，其中，所述薄膜晶体管为N型晶体管，
    其中，电压控制单元当与像素连接的数据线上的电压在负半周期，并且输 入到所述像素的共用电极的用于扫描触摸信号的信号为由高电平转向低电平的脉冲信号时，在扫描触摸信号的时间段内，通过所述数据线输出降低电压后的信号。
  10. 根据权利要求9所述的设备，其中，所述降低电压后的信号的电压区间为：[-Vdata(min)-(Vgh-Vgl)*Cgs/(Clcmin+Cst)]至[-Vdata(max)-(Vgh-Vgl)*Cgs/(Clcmax+Cst)]，其中，Vdata(min)指示数据线上的最小电压，Vdata(max)指示数据线上的最大电压，Vgh指示扫描线上的最大电压，Vgl指示扫描线上的最小电压，Cgs指示薄膜晶体管的栅极和源极之间的寄生电容的电容值，Cst指示储存电容的电容值，Clcmin指示液晶电容的最小电容值，Clcmax指示液晶电容的最大电容值。
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