WO2017038108A1

WO2017038108A1 - Semiconductor device and semiconductor device manufacturing method

Info

Publication number: WO2017038108A1
Application number: PCT/JP2016/053635
Authority: WO
Inventors: 光大平; 洋聡落水; 大和田　保
Original assignee: 株式会社ソシオネクスト
Priority date: 2015-08-31
Filing date: 2016-02-08
Publication date: 2017-03-09
Also published as: JP2017050340A

Abstract

Provided is a semiconductor device having a highly reliable through via hole. This semiconductor device has: a semiconductor substrate; first wiring formed in a first wiring layer on the semiconductor substrate; a through via hole, which is penetrating the semiconductor substrate, and is connected to the first wiring; and a first insulating film positioned at an area corresponding to an inter-wiring space of the first wiring, said area being at the interface between the through via hole and the first wiring layer.

Description

Semiconductor device and manufacturing method of semiconductor device

The present invention relates to a semiconductor device and a manufacturing method thereof.

In semiconductor device mounting technology, a through silicon via (TSV: Through-Silicon Via; hereinafter abbreviated as “TSV” as appropriate) is used. The TSV is an electrode that penetrates the substrate of the conductor chip in a direction perpendicular to the substrate, and is used for connection between upper and lower chips. In the three-dimensional mounting package using the TSV, the space for connection and the insertion of the interposer can be omitted, so that the package size can be reduced.

As a method of forming TSV, there is a method of embedding a conductor by forming a hole penetrating silicon from the back surface opposite to the device formation surface of the silicon substrate. Prior to the formation of the holes, the back side of the silicon substrate is polished to reduce the thickness.

A technique is known that uses an insulating film such as an STI (Shallow Trench Isolator) for element isolation as an etching stopper when forming TSV holes in a silicon substrate by etching (see, for example, Patent Document 1). In this technique, the via diameter is larger than the opening formed in the insulating film in the range from the back surface of the substrate to the interface with the insulating film, and the via diameter is the same as the size of the opening inside the opening.

JP 2013-89616 A

The thickness of the silicon varies within the wafer surface due to the polishing of the back surface of the silicon substrate. In the portion where the silicon is thin, the space portion between the wirings may be over-etched in the lowermost M1 wiring layer when the TSV hole is formed. Due to over-etching in the space between the M1 wires, there is a concern that the formation of a barrier metal or seed layer in the hole or the generation of voids may occur, and the reliability of the TSV may be reduced.

Therefore, the disclosed technology provides a semiconductor device having a highly reliable through via and a manufacturing method thereof.

In one embodiment of the present invention, a semiconductor device includes:
A semiconductor substrate;
A first wiring formed in a first wiring layer on the semiconductor substrate;
A through via passing through the semiconductor substrate and connected to the first wiring;
A first insulating film located at a location corresponding to an inter-wiring space of the first wiring at an interface between the through via and the first wiring layer;
Have

With the above configuration, a semiconductor device having a highly reliable through via and a manufacturing method thereof are realized.

It is a figure explaining the problem which arises in TSV. It is a figure explaining the problem which arises in TSV. It is a figure explaining the problem which arises in TSV. It is a figure explaining the problem which arises in TSV. It is a figure which shows the state before TSV formation of the semiconductor device of embodiment compared with a general structure. It is a figure which shows the state after TSV formation of the semiconductor device of embodiment compared with a general structure. It is a figure which shows the structure (before TSV formation) of the semiconductor device of 1st Embodiment. It is a figure which shows the structure (after TSV formation) of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 1st Embodiment. It is a figure which shows the structure (before TSV formation) of the semiconductor device of 2nd Embodiment. It is a figure which shows the structure (after TSV formation) of the semiconductor device of 2nd Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 2nd Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 2nd Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 2nd Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 2nd Embodiment. It is a figure which shows the manufacturing process of the semiconductor device of 2nd Embodiment. It is a figure which shows the example of a layout of a M1 wiring pattern and a STI pattern. It is a figure which shows the example of a layout of a M1 wiring pattern and a STI pattern. It is a figure which shows the example of a layout of a M1 wiring pattern and a STI pattern. It is a figure which shows the structural example of the electronic component using the semiconductor device of embodiment. It is a figure which shows the structural example of the electronic component using the semiconductor device of embodiment.

Prior to the embodiment, problems that occur in the through silicon via (TSV) found by the inventors will be described. In the state before TSV formation in FIG. 1A, circuit elements such as transistors (TR) are formed on the surface of the silicon substrate 101, and the M1 wiring 103 of the first wiring layer and the M2 wiring 104 of the second wiring layer are formed thereon. A multilayer wiring including the same is formed. Bump electrodes 106 as external connection terminals are formed on the outermost surface of the wafer. The STI insulating film 102 and the interlayer insulating film 107 are also etched in the process of forming holes for TSV from the back surface of the substrate in the TSV formation area A of the silicon substrate 101. As described above, overetching occurs in the space portion between the M1 wiring 103 and the M1 wiring 103 by the etching at this time.

FIG. 1B shows a state after the TSV 105 is formed. Problems arise in both the areas B1 and B2 enclosed by the square. In the region B1, a void 120 due to over-etching occurs in a space portion between the wirings of the M1 layer. In the region B2, the M2 wiring 104 is offset from the M1 wiring 103 in consideration of over-etching of the TSV 105 in advance, and is arranged above the space between the M1 wirings 103. Due to the restriction of the maximum line width rule, it is difficult to make the M1 wiring 103 connected to the TSV 105 as a solid film, and the line-and-space wiring pattern is maintained. The TSV 105 is received by the two layers M1 and M2, and the M2 wiring is used as an etching stopper. In this configuration, since the wiring to the circuit including the transistor (TR) can be drawn only in the layers after M2, the transmission speed is inferior.

Further, since the M2 wiring 104 is disposed as an etching stopper for the TSV 105 and offset with respect to the M1 wiring 103, a wiring area for connecting the TSV 105 and the bump electrode 106 is increased. Therefore, the chip area increases and the number of wiring layers routed to the circuit increases. Furthermore, there is little overlap between the M1 wiring 103 and the M2 wiring 104, and the number of vias connecting the M1 wiring 103 and the M2 wiring 104 is limited, which causes a reduction in allowable current.

2 and 3 are diagrams for explaining the generation of voids in the region B1. In FIG. 2, a hole 115 for TSV 105 is formed in the silicon substrate 101. At this time, the wafer is fixed to the support substrate 110 with the adhesive 109 with the bump electrode 106 facing down. For convenience of illustration, the wiring layers above the bump electrodes 106 and M2 are omitted. After the silicon substrate 101 is polished to a certain thickness, a hole 115 is formed using a hard mask 112 such as silicon nitride (SiN). By etching to form the holes 115, a part of the interlayer insulating film 108 is over-etched at a space between the M1 wirings 103 (hereinafter referred to as “M1 space” as appropriate).

2 is a top view when cut along a cut surface C passing through the STI insulating film 102. FIG. The M1 wiring 103 is exposed in the hole 115. The M2 wiring 104 is exposed at a location corresponding to the space between the M1 wirings 103. A part of the M2 wiring 104 is covered with the interlayer insulating film 108, but a portion where the M2 wiring 104 is exposed or a portion where the interlayer insulating film 108 is thin becomes a void generation portion.

As shown in FIG. 3, an insulating film 116 is formed on the inner wall of the hole 115, the insulating film 116 on the bottom surface of the hole 115 is etched back by anisotropic etching, and the hole 115 is then filled with a conductive film 118. A seed layer for forming a barrier metal or a conductive film 118 is difficult to be formed in a portion where the M2 wiring 104 is exposed in the M1 space portion by overetching, and it is difficult to completely fill the hole 115. The lower diagram in FIG. 3 is a top view when the STI insulating film 102 is cut along a cut surface D passing through the M1 wiring 103. A void is generated in the space portion between the M1 wirings 103, and the M2 wiring 104 remains exposed.

4 and 5 are diagrams showing the semiconductor device 10 of the embodiment in comparison with a general configuration. 4 and 5 are both cross-sectional views in a plane orthogonal to the direction in which the wiring extends. 4 shows a state before TSV formation, and FIG. 5 shows a state after TSV formation.

In the embodiment, in order to solve the problems of the general configuration described above, (1) the STI insulating film 12b is arranged at a position corresponding to the M1 space between the M1 wirings in the TSV formation area. (2) The M2 wiring 14 is formed at a position aligned with the M1 wiring 13 without being offset with respect to the M1 wiring 13.

By disposing the STI insulating film 12b at a position corresponding to the M1 space, overetching in the M1 space portion is suppressed. By suppressing over-etching in the M1 space portion, TSV can be received only by the M1 wiring 13 and the M2 wiring 14 can be overlapped at the same position as the M1 wiring 13. In addition, a lead-out wiring from the layer of the M1 wiring 13 to the circuit portion can be taken.

In the state before the TSV formation in FIG. 4, the STI insulating film 102 is formed in the entire TSV formation area in the general configuration shown in the figure below. On the other hand, in the semiconductor device 10 of the above embodiment, the STI insulating film 12b is formed on the silicon substrate 11 at a position corresponding to the M1 space of the TSV formation area with a predetermined width and a predetermined interval. The STI insulating film 12b is an elongated pattern corresponding to the space shape between the M1 wirings 13 and extending in the depth direction of the drawing. For convenience, the STI insulating film disposed inside the line and space pattern of the M1 wiring 13 is “STI insulating film 12b”, and the STI insulating film disposed outside the line and space pattern is “STI insulating film 12a”. " The

STI insulating films

12a and 12b are combined to form the STI insulating film 12.

4, the M2 wiring 104 is offset in the wiring width (line width) direction with respect to the M1 wiring 103, and the lead-out wiring 104d to the circuit portion extends in the M2 layer. On the other hand, in the semiconductor device 10 of the embodiment shown in the upper diagram of FIG. 4, the M2 wiring 14 is aligned with the M1 wiring 13, and the lead-out wiring 13d to the circuit portion extends in the M1 layer. This is because overetching in the M1 space portion is suppressed, and TSV can be received only by the M1 wiring 13.

In the state after the TSV formation in FIG. 5, the problem described above occurs in both the regions B1 and B2 in the general configuration in the lower diagram in FIG. That is, the void 120 is generated in the M1 space portion (B1), the offset arrangement of the M1 wiring 103 and the M2 wiring 104, and the arrangement limitation of the extraction wiring 104d (B2).

On the other hand, in the semiconductor device 10 of the embodiment in the upper diagram of FIG. 5, a part of the interlayer insulating film 23 remains as the insulating film 23s in the region X1 corresponding to the space between the M1 wirings 13. The insulating film 23s suppresses over-etching in the M1 space portion and causes the M1 wiring 13 to function as an etching stopper. Thereby, it is possible to prevent the formation of a barrier metal or a seed layer in the M1 space and the generation of voids in the TSV 15.

By suppressing over-etching of the M1 space portion, the M2 wiring 14 can be disposed immediately above the M1 wiring 13 and the TSV 15 can be received only by the M1 wiring 13. Since the lead-out wiring 13d to the circuit extends from the M1 layer, it is advantageous in terms of transmission speed. In addition, the wiring area connecting TSV 15 and bump electrode 106 can be reduced, and the chip area and the number of wiring layers drawn to the circuit can be reduced. Furthermore, since the overlap between the M1 wiring 13 and the M2 wiring 14 is large, the number of vias connecting the M1 wiring 13 and the M2 wiring 14 can be increased, and the allowable current increases.
<First Embodiment>
6A and 6B are configuration diagrams of the semiconductor device 10A of the first embodiment. The semiconductor device 10A is a type in which the edge of the TSV 15 (interface with the silicon substrate 11) does not cover the STI insulating film 12a outside the line-and-space pattern, like the semiconductor device 10 in the upper diagram of FIG. Before the TSV formation of FIG. 6A, the STI insulating film 12b is arranged so as to cover a portion corresponding to the M1 space in the TSV formation area. 6B, the insulating film 23s is located between the TSV15 and the M1 space. The configuration of the semiconductor device 10A is the same as that of the semiconductor device 10 in the upper diagram of FIG.

7 to 18 are manufacturing process diagrams of the semiconductor device 10A of FIG. In FIG. 7,

STI insulating films

12a and 12b are formed at predetermined positions on the silicon substrate 11, a circuit element such as a transistor (TR) on the silicon substrate 11, a multilayer wiring including an M1 wiring 13 and an M2 wiring 14, A bump electrode 106 (see FIGS. 6A and 6B) is formed. In FIG. 7, the bump electrodes 106 and the wiring layers after M3 are omitted for the sake of simplicity.

The STI insulating film 12b is formed at a predetermined position on the silicon substrate 11 simultaneously with the patterning of the element isolation (STI) insulating film 12 that partitions the circuit region. More specifically, the STI insulating film 12 b is formed at a position corresponding to the space between the M1 wirings 13. As an example, the line width Mw of the M1 wiring 13 is 2 μm, the space width Sw is 0.5 μm, the width of the STI insulating film 12b (indicated as “STI width” in the figure) Tw is 0.8 μm, and the space Lw between STIs is 1. 0.7 μm. The STI width Tw is larger than the space width Sw of the M1 wiring 13. The lower diagram in FIG. 7 is a diagram when the upper diagram in FIG. 7 is cut along the cut surface E and viewed from the substrate surface (opposite the back surface 11R). In the region corresponding to the wiring pattern of the M1 wiring 13, the STI insulating film 12b is not formed, and the silicon substrate 11 is exposed.

After edge trimming, the wafer is temporarily bonded (temporary bonding) to the support substrate 110 with the adhesive 109. Edge trimming is a process in which grooves are formed in the edge portion of a wafer in order to prevent cracking from the edge when the wafer is ground and thinned. In the temporary bonding, the surface on which the bump electrode 106 is formed is used as a bonding surface, and the back surface 11R of the silicon substrate 11 is directed upward in the drawing. The back surface 11R of the silicon substrate 11 is ground (back grind) so that the thickness T of the silicon substrate 11 is, for example, 50 to 70 μm.

Next, in FIG. 8, an insulating film 112 such as SiN is formed on the back surface of the thinned silicon substrate 11, and a resist 113 is applied and patterned to form a predetermined opening 114. The thickness of the insulating film 112 is, for example, 0.5 μm to 1 μm. The diameter φ of the opening 114 corresponds to the diameter of the TSV and is, for example, 10 μm.

Next, in FIG. 9, the silicon substrate 11 is etched by a Bosch process to form TSV holes 115. The diameter φ of the hole 115 is 10 μm. The width w1 of the line and space pattern of the M1 wiring 13 is, for example, 12 μm. In the conventional method, due to the thickness variation of the silicon substrate 11 after back grinding, over-etching of the M1 space in a thin portion of the silicon substrate 11 has been a problem. In the first embodiment, the STI insulating film 12b is formed at a position corresponding to the M1 space (see FIG. 8), and the STI insulating film 12b serves as a buffer against etching. As a result, after the etching is completed, a part of the interlayer insulating film 23 remains as the insulating film 23s in the M1 space position on the bottom surface of the hole 115. This insulating film 23s may include a part of the STI insulating film 12b. The insulating film 23s has a function of suppressing or controlling overetching of the M1 space portion. The M1 wiring 13 serves as an etching stopper.

9 is a top view when viewed from the side of the hole 115 by cutting along the cutting plane E in the upper diagram of FIG. The STI insulating film 12a outside the line and space pattern remains outside the hole 115. Inside the hole 115, the M1 wiring 13 is exposed. Between the adjacent M1 wirings 13, the insulating film 23 s remains in a stripe shape or a strip shape. The insulating film 23 s covers the edge of the M1 wiring 13 and is wider than the space width between the M1 wirings 13.

Next, in FIG. 10, an insulating film 116 is formed on the entire surface including the sidewalls of the hole 115 by a low temperature CVD (Chemical Vapor Deposition) method. A TEOS film may be used as the insulating film 116. The film thickness of the insulating film 116 on the bottom and side walls of the hole 115 is, for example, 0.2 to 0.5 μm. The film thickness of the insulating film 116 on the insulating film 112 is, for example, 1.0 to 1.5 μm.

Next, in FIG. 11, the insulating film 116 on the bottom surface of the hole 115 is etched back by anisotropic etching to expose the M1 wiring 13. A part of the insulating film 116 may be attached to the insulating film 23s at this stage. In this case, the adhesion portion 116b of the insulating film 116 is also used as the insulating film 23s. Next, in FIG. 12, a barrier metal and a seed layer are formed on the entire surface by PVD (Physical Vapor Deposition). . For simplicity of illustration, illustration of the barrier metal and the seed layer is omitted. The barrier metal is, for example, titanium (Ti) with a thickness of 0.1 to 0.5 μm, and the seed layer is copper (Cu) with a thickness of 0.5 to 1.0 μm, but other suitable metal materials may be used. Good. After the seed layer is formed, copper (Cu) 118 is filled into the holes 115 by electrolytic plating. Since the M1 space portion is covered with the insulating film 23s and the overetching is suppressed, the formation failure of the barrier metal and the seed layer and the generation of voids are suppressed.

Next, in FIG. 13, copper (Cu) 118 is planarized by CMP (Chemical Mechanical Polishing) to form TSV15. Subsequently, a barrier metal / seed layer 121 is formed by PVD, a resist 122 is applied, and an opening 123 corresponding to the backside wiring is patterned. The barrier metal is, for example, titanium (Ti) with a thickness of 0.1 to 0.5 μm, and the seed layer is copper (Cu) with a thickness of 0.5 to 1.0 μm. The width w4 of the opening 123 is, for example, 80 to 100 μm.

Next, in FIG. 14, the back wiring 125 is formed of copper (Cu) by electrolytic plating. The thickness of the back wiring 125 is, for example, 2 to 4 μm. Thereafter, the resist 122 is peeled off, and unnecessary layer stack (barrier metal / seed layer) 121 is removed by wet etching.

Next, in FIG. 15, a photosensitive resin 126 is applied, and the opening 127 corresponding to the back electrode is patterned. The width w5 of the back electrode is, for example, 60 to 80 μm.

Next, in FIG. 16, the back electrode 130 is formed by, for example, a nickel (Ni) film 131 and a gold (Au) film 132 by electroless plating. The thickness of the Ni film 131 is, for example, 2 to 4 μm, and the thickness of the Au film 132 is, for example, 0.03 to 0.1 μm.

Next, in FIG. 17, the back electrode 130 side is bonded to the dicing film 7 and the support substrate 110 is peeled (debonded). The adhesive 109 on the device surface side is washed away. The bump electrode 106 formed on the outermost surface of the multilayer wiring is omitted.

Next, dicing is performed with the dicing blade 5 in FIG. 18 to divide the wafer 2 into chips 3. Each chip 3 may be a semiconductor device 10A. By this method, overetching of the M1 space portion is suppressed by the insulating film 23s at the interface between the TSV15 and the M1 layer, and the semiconductor device 10A having the highly reliable TSV15 is realized. Further, since the M2 wiring 14 and the M1 wiring 13 are arranged in the direction perpendicular to the substrate, the wiring area and the number of stacked layers can be reduced. Since the overlap between the M1 wiring 13 and the M2 wiring 14 can be widened, the number of vias between the M1 wiring 13 and the M2 wiring 14 can be increased, and the allowable current can be increased. Since the lead-out wiring 13d to the circuit portion including the transistor (TR) can be taken out from the layer of the M1 wiring 13, the transmission speed is improved.

In the first embodiment, the M2 wiring 14 is stacked in the same layout as the M1 wiring, but the present invention is not limited to this example. The wiring layout after M2 is free as long as the design rule allows as long as the chip size is not significantly increased. Further, the bump electrode 106 on the most surface side of the multilayer wiring may be a solder bump or a copper (Cu) pillar-shaped electrode.
Second Embodiment
19A and 19B show a semiconductor device 10B of the second embodiment. In the second embodiment, there is provided a semiconductor device 10B of a type in which the STI insulating film 12a outside the line and space pattern of the M1 layer is located inside the TSV15.

Before the TSV formation in FIG. 19A, the edge of the TSV formation area is on the STI insulating film 12a outside the line and space pattern. The STI insulating film 12b inside the line and space pattern is formed at a position corresponding to the space between the M1 wires 13 (M1 space).

19B, after forming the TSV, the insulating film 23s is located between the TSV15 and the M1 space, and the insulating film 23t remains inside the TSV15 and outside the line and space pattern. The insulating film 23t exists along the circumference of the TSV 15 in the vicinity of the boundary between the TSV 15 and the M1 layer.

Even in this configuration, the insulating film 23s and the insulating film 23t suppress over-etching in the region corresponding to the M1 space and the region outside the line and space pattern in the TSV formation region. Thereby, formation failure of the barrier metal and the seed layer in the region along the arc of the M1 space portion and the TSV hole, and generation of voids in the TSV 15 can be suppressed. Further, the M2 wiring 14 is arranged immediately above the M1 wiring 13, so that the TSV 15 can be received only by the M1 wiring 13, and the lead wiring 13d to the circuit can be drawn from the M1 layer. As a result, the reliability of the TSV is improved, and the transmission speed is improved, the chip size is reduced, and the allowable current is increased.

20 to 24 are manufacturing process diagrams of the semiconductor device 10B of the second embodiment. In FIG. 20,

STI insulating films

12a and 12b are formed at predetermined positions on the silicon substrate 11, and a multilayer wiring including an element such as a transistor (TR), an M1 wiring 13, and an M2 wiring 14 in a circuit region on the silicon substrate 11. Then, bump electrodes 106 (see FIG. 19) are formed. In FIG. 20, the bump electrode 106 and the wiring layers after M3 are omitted for the sake of simplicity of illustration.

The STI insulating film 12b and the STI insulating film 12a are formed at predetermined positions on the silicon substrate 11 simultaneously with the patterning of the element isolation (STI) insulating film 12 that partitions the circuit region. In this example, the width (indicated as “STI width” in the figure) Tw of the STI insulating film 12b and the space width Lw between STI are 0.8 μm and 1.7 μm, respectively. The line width Mw of the first M1 wiring 13 is 2 μm, and the space width Sw is 0.5 μm.

The lower diagram in FIG. 20 is a diagram when the upper diagram in FIG. 20 is cut along the cut surface E and viewed from the substrate surface (opposite to the back surface 11R). In the region corresponding to the wiring pattern of the M1 wiring 13, the STI insulating film 12b is not formed, and the silicon substrate 11 is exposed.

Next, in FIG. 21, an insulating film 112 such as SiN is formed on the back surface of the thinned silicon substrate 11. A resist 113 is applied on the insulating film 112 and patterned to form a predetermined opening 114. The thickness of the insulating film 112 is, for example, 0.5 μm to 1 μm. The diameter φ of the opening 114 corresponds to the diameter of the TSV and is, for example, 10 μm.

Next, in FIG. 22, the silicon substrate 11 is etched by a Bosch process to form TSV holes 115. The diameter φ of the hole 115 is 10 μm. The width w6 of the line and space pattern of the M1 wiring 13 is, for example, 7 μm. The distance w7 from the outer edge in the width direction of the line and space pattern to the side wall of the hole 115 is 1.5 μm.

In the second embodiment, the STI insulating film 12b is formed at a position corresponding to the M1 space, and the STI insulating film 12a is formed outside the line and space pattern (see FIG. 21). The STI insulating film 12b and the STI insulating film 12a serve as a buffer material against etching when the hole 115 is formed. After the etching is completed, a part of the interlayer insulating film 23 remains as an insulating film 23s in the M1 space position on the bottom surface of the hole 115. Further, a part of the interlayer insulating film 23 remains as an insulating film 23t in a region along the arc in the hole outside the line and space pattern. The insulating film 23s may include a part of the STI insulating film 12b. The insulating film 23t may include a part of the STI insulating film 12a.

22 is a top view when viewed from the side of the hole 115 by cutting along the cutting plane E in the upper diagram of FIG. The STI insulating film 12 a outside the hole 115 and outside the line and space pattern remains on the silicon substrate 11. Inside the hole 115, the M1 wiring 13 is exposed, and between the adjacent M1 wirings 13, the insulating film 23s remains in a stripe shape or a strip shape. Further, the insulating film 23t remains in an arc shape outside the outermost M1 wiring 13 inside the hole 115.

Next, in FIG. 23, an insulating film 116 such as a TEOS film is formed on the entire surface including the sidewall of the hole 115 by a low temperature CVD (Chemical Vapor Deposition) method. The insulating film 116 on the bottom surface of the hole 115 is etched back by anisotropic etching to expose the M1 wiring 13. An insulating film 116 s remains on the sidewall of the hole 115. A part of the insulating film 116 may be attached to the insulating film 23s at this stage. In this case, the adhesion portion 116b of the insulating film 116 is also used as the insulating film 23s.

Next, in FIG. 24, a barrier metal and a seed layer (not shown) are formed, and the hole 115 is filled with copper (Cu) 118 by electrolytic plating. Since the M1 space portion and the outside of the line and space pattern are covered with the insulating film 23s and the insulating film 23t, respectively, and over-etching is suppressed, formation defects of the barrier metal and the seed layer and generation of voids are suppressed. Is done.

The subsequent processing is the same as in FIGS. 13 to 18 of the first embodiment. That is, copper (Cu) 118 is planarized by CMP (Chemical Mechanical Polishing) to form TSV 15. Subsequently, the back surface wiring 125 connected to the TSV 15 is formed, and the back surface electrode 130 is formed on the back surface wiring 125.

In the second embodiment, over-etching of the M1 space portion is suppressed by the insulating film 23s at the interface between the TSV 15 and the M1 layer, and over-etching is suppressed in the hole inner region outside the line and space pattern. Thereby, the semiconductor device 10A having the highly reliable TSV 15 is realized. Similar to the first embodiment, since the M2 wiring 14 and the M1 wiring 13 are arranged in the direction perpendicular to the substrate, the wiring area and the number of stacked layers can be reduced. Since the overlap between the M1 wiring 13 and the M2 wiring 14 can be widened, the number of vias can be increased and the allowable current can be increased. Since the lead-out wiring 13d to the circuit portion including the transistor (TR) can be taken out from the layer of the M1 wiring 13, the transmission speed is improved.

Also in the second embodiment, the M2 wiring 14 is overlapped in the same layout as the M1 wiring, but the wiring layout after M2 is free within the range allowed by the design rule as long as the chip size is not significantly increased.
<Wiring layout to receive TSV>
25 to 27 show the layout of the M1 wiring that receives TSV15. FIG. 25 shows strip-shaped M1 patterns and corresponding STI patterns. In the M1 pattern of FIG. 25A, the M1 width is 2 μm or more, and the space between M1 is 0.5 μm or more. In the STI pattern of FIG. 25B, the STI width is 0.8 μm or more, and the STI space is 1.7 μm or more. In FIG. 25C, when the outline of the M1 pattern is superimposed on the STI pattern, the STI width of the STI insulating film 12b in the TSV formation area is wider than the space between M1. This suppresses overetching in the space portion between the M1 wirings.

FIG. 25 shows an arrangement example in which the outer region of the line and space pattern does not cover the TSV as in the first embodiment, but the outer two M1 patterns are removed, and the second embodiment It may be applied to the configuration.

FIG. 26 shows an M1 pattern combining a strip and a frame (frame) and a corresponding STI pattern. Similarly to FIG. 25, the M1 width is 2 μm or more, the M1 space is 0.5 μm or more, the STI width is 0.8 μm or more, and the STI space is 1.7 μm or more. As shown in FIG. 26C, when the outline of the M1 pattern is superimposed on the STI pattern, the STI insulating film 12b in the TSV formation area is designed to completely cover the space between M1. This suppresses overetching in the space portion between the M1 wirings in the TSV formation area.

FIG. 27 shows a mesh-like M1 pattern and a corresponding STI pattern. In the M1 pattern of FIG. 27A, the M1 width A that is the wiring width of the TSV formation region is 1 μm or more, the M1 width B that is the wiring width of the outer frame portion is 2 μm or more, and the space between M1 is 1 μm or more. In the STI pattern of FIG. 27B, the STI width of the STI insulating film 12b in the TSV formation region is 1.3 μm or more, the STI space A in the TSV formation region is 0.7 μm or more, and the outer STI space B is 1. 7 μm or more. As shown in FIG. 27C, when the outline of the M1 pattern is superimposed on the STI pattern, the STI insulating film 12b is arranged so as to cover the space between M1.

The layout of the M1 wiring is not limited to the examples of FIGS. 25 to 27, and any layout can be adopted within the scope of the design rule. The wiring after M2 may be the same as or different from the layout of the M1 wiring. Arbitrary layouts can be adopted as the wiring layout after M2 within the range allowed by the design rule.
<Application example>
28 and 29 show a configuration example of an electronic component using the semiconductor device 10 (including 10A or 10B).

FIG. 28 shows an example of an electronic component 50A laminated face-to-face (facing the device surface). In the electronic component 50 </ b> A, the first semiconductor device 10 and the second semiconductor device 40 are stacked on the package substrate 51. The first semiconductor device 10 is the semiconductor device A of the first embodiment or the semiconductor device of the second embodiment, and has a TSV 15.

The first semiconductor device 10 is electrically connected to the electrode of the package substrate 51 or the copper (Cu) wiring 53 by the solder bump 136 joined to the back electrode 130. The device surface 10fc of the first semiconductor device is mounted upward with respect to the package substrate 51, and faces the device surface 40fc of the second semiconductor device. The bump electrode 106 of the first semiconductor device 10 is connected to the surface electrode of the second semiconductor device 40.

An underfill agent 55 is filled between the package substrate 51 and the first semiconductor device 10 and between the first semiconductor device 10 and the second semiconductor device 40, and the entire stacked structure is sealed with the mold resin 61. The

In the electronic component 50A, the first semiconductor device 10 and the package substrate 51, and the second semiconductor device 40 and the package substrate 51 are connected with high density at a short distance by the TSV15. In addition, the first semiconductor device 10 and the second semiconductor device 40 are connected with high density at a short distance by face-to-face lamination.

FIG. 29 shows an example of an electronic component 50B laminated face-to-back (device surface and back electrode face each other). In the electronic component 50 </ b> B, a first semiconductor device 10 and a second semiconductor device 40 are stacked on a package substrate 51. The first semiconductor device 10 is the semiconductor device A of the first embodiment or the semiconductor device of the second embodiment, and has a TSV 15.

The device surface 10 fc of the first semiconductor device 10 is mounted downward facing the package substrate 51, and is electrically connected to the electrode of the package substrate 51 or the copper (Cu) wiring 53 by the bump electrode 106 formed on the device surface 10 fc. Connected to. The device surface 40fc of the second semiconductor device 40 is stacked to face the back surface 10bc of the first semiconductor device. For example, the bump electrode 146 of the second semiconductor device 40 is electrically connected to the back electrode 130 of the first semiconductor device 10. An underfill agent 55 is filled between the package substrate 51 and the first semiconductor device 10 and between the first semiconductor device 10 and the second semiconductor device 40, and the entire stacked structure is sealed with the mold resin 61. The

In the electronic component 50B, the TSV 15 connects the first semiconductor device 10 and the second semiconductor device 40 and the second semiconductor device 40 and the package substrate 51 with high density at a short distance. Further, since the first semiconductor device 10 is mounted face-down on the package substrate 51, the first semiconductor device 10 and the package substrate 51 are also connected with high density over a short distance.

28 and 29, the number of stacked chips is not limited to two. Two or more first semiconductor devices 10 having the TSV 15 may be stacked to form a stacked structure of three or more layers. Since the TSV 15 of the embodiment suppresses voids and has high connection reliability, the reliability of the electronic component 50 can be maintained even when a laminated structure of three or more layers is used. In addition, the TSV 15 of the embodiment is advantageous in terms of transmission speed because it can take a lead wiring from the M1 wiring layer to the circuit unit.

In addition, through the first embodiment and the second embodiment, STI may be arranged between wiring spaces outside the region where the TSV 15 is formed. Thereby, it is possible to secure a manufacturing margin in consideration of misalignment and the like.

This application is based on Patent Application No. 2015-171056 filed with the Japan Patent Office on August 31, 2015, and includes the entire contents thereof.

10, 10A, 10B Semiconductor device 11

Silicon substrates

12, 12a, 12b STI insulating film 13 M1 wiring (first wiring)
13d Lead wiring 14 M2 wiring (second wiring)
15 TSV (through via)
23 Interlayer insulating film 23s Insulating film 106 Bump electrode 130 Back electrode TR Transistor

Claims

A semiconductor substrate;
A first wiring formed in a first wiring layer on the semiconductor substrate;
A through via passing through the semiconductor substrate and connected to the first wiring;
A first insulating film located at a location corresponding to an inter-wiring space of the first wiring at an interface between the through via and the first wiring layer;
A semiconductor device comprising:
A second insulating film formed on the semiconductor substrate and positioned below the first wiring layer;
The semiconductor device according to claim 1, wherein the second insulating film and the first insulating film have the same material.
2. The semiconductor device according to claim 1, wherein the first wiring has a first portion that overlaps the through via in a plan view and a second portion that does not overlap the through via in a plan view.
4. The semiconductor device according to claim 3, further comprising a third insulating film formed on the semiconductor substrate and positioned corresponding to an inter-wiring space of the first wiring in the second portion in plan view.
The first wiring has a line and space pattern;
The semiconductor device according to claim 1, wherein a width of the line and space pattern is larger than a diameter of the through via.
The first wiring has a line and space pattern;
The semiconductor device according to claim 1, wherein a width of the line and space pattern is smaller than a diameter of the through via.
7. The semiconductor according to claim 6, wherein the first insulating film is located in a portion corresponding to the inter-wiring space, and in a region outside the line and space pattern and inside the through via. apparatus.
The semiconductor device according to claim 1, wherein the first wiring includes a lead wiring electrically connected to a circuit element formed on the surface of the semiconductor substrate.
A second wiring formed in a second wiring layer above the first wiring layer;
The semiconductor device according to claim 1, wherein the second wiring is disposed at a position aligned with the first wiring.
2. The semiconductor device according to claim 1, wherein the first insulating film has a striped or strip shape in plan view.
A package substrate;
A first semiconductor device mounted on the package substrate;
A second semiconductor device mounted on the semiconductor device;
Have
The first semiconductor device includes a semiconductor substrate, a first wiring formed in a first wiring layer on the semiconductor substrate, a through via that penetrates the semiconductor substrate and is connected to the first wiring, An electronic component comprising: a first insulating film located at a location corresponding to an inter-wiring space of the first wiring at an interface between the through via and the first wiring layer.
12. The electronic component according to claim 11, wherein the first semiconductor device and the second semiconductor device are stacked so that device surfaces thereof are opposed to each other.
12. The electronic component according to claim 11, wherein the first semiconductor device and the second semiconductor device are laminated such that one device surface and the other substrate back surface face each other.
Forming a first insulating film in the semiconductor substrate;
After forming the first insulating film, forming a second insulating film on the semiconductor substrate,
A wiring pattern is formed on the second insulating film so that a space between the wirings is located at a position corresponding to the first insulating film in a plan view.
A hole penetrating the semiconductor substrate is formed from the back side of the semiconductor substrate, and the wiring pattern is exposed in the hole, and the second insulating film is formed at a position corresponding to the space between the wiring patterns. Leave a part,
A method of manufacturing a semiconductor device, wherein a through-via is formed by forming a conductive film in the hole.
The pattern of the first insulating film has a first width and is arranged at a first interval,
The wiring pattern has a second width and is arranged at a second interval,
The method of manufacturing a semiconductor device according to claim 14, wherein the first width is larger than the second width.
The pattern of the first insulating film has a first width and is arranged at a first interval,
The wiring pattern has a second width and is arranged at a second interval,
The method of manufacturing a semiconductor device according to claim 14, wherein the first interval is smaller than the second interval.
15. The method of manufacturing a semiconductor device according to claim 14, wherein the first insulating film is formed simultaneously with the formation of the insulating film for element isolation.
15. The method of manufacturing a semiconductor device according to claim 14, wherein the first insulating film includes a striped or striped pattern.
After the through via is formed, a part of the first insulating film is disposed at a position corresponding to the space between the wiring patterns in a plan view outside the region where the through via is formed. The method of manufacturing a semiconductor device according to claim 14.