WO2017019104A1

WO2017019104A1 - Network device emulation

Info

Publication number: WO2017019104A1
Application number: PCT/US2015/042996
Authority: WO
Inventors: Chris A. WINDLE; Vladimir Libershteyn; Richard Liu
Original assignee: Hewlett Packard Enterprise Development Lp
Priority date: 2015-07-30
Filing date: 2015-07-30
Publication date: 2017-02-02

Abstract

According to an example, network device emulation may include mapping an external peripheral bus memory on a first device to a Peripheral Component Interconnect (PCI) bus on a second device. The first and second devices may be connectable to each other by using the PCI bus.

Description

NETWORK DEVICE EMULATION

BACKGROUND

[0001] A Peripheral Component Interconnect (PCI) bus may be described as a local computer bus for attaching hardware devices in a computer. The PCI bus may support the functions found on a processor bus, but in a standardized format that is independent of any particular processor's native bus. Devices connected to the PCI bus may be assigned addresses in the processor's address space.

Attached devices may take either the form of an integrated circuit fitted onto a motherboard itself (called a planar device in the PCI specification), or an expansion card (i.e., adapter) that fits into a slot. Examples of PCI adapters used in personal computers (PCs) include network adapters, sound adapters, modems, television (TV) tuner adapters, and disk controllers.

BRIEF DESCRIPTION OF DRAWINGS

[0002] Features of the present disclosure are illustrated by way of example and not limited in the following figure(s), in which like numerals indicate like elements, in which:

[0003] Figure 1 illustrates an architecture of a network device emulation system, according to an example of the present disclosure;

[0004] Figure 2 illustrates an adapter driver interface block diagram for the network device emulation system of Figure 1 , according to an example of the present disclosure;

[0005] Figure 3 illustrates a transmit packet flowchart for the network device emulation system of Figure 1 , according to an example of the present disclosure;

[0006] Figure 4 illustrates a receive packet flowchart for the network device emulation system of Figure 1 , according to an example of the present disclosure;

[0007] Figure 5 illustrates a flowchart of a method for network device emulation, according to an example of the present disclosure;

[0008] Figure 6 illustrates a flowchart of the method for network device emulation, according to an example of the present disclosure;

[0009] Figure 7 illustrates a flowchart of the method for network device emulation, according to an example of the present disclosure; and

[0010] Figure 8 illustrates a computer system, according to an example of the present disclosure. DETAILED DESCRIPTION

[0011] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to examples. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be readily apparent however, that the present disclosure may be practiced without limitation to these specific details. In other instances, some methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0012] Throughout the present disclosure, the terms "a" and "an" are intended to denote at least one of a particular element. As used herein, the term "includes" means includes but not limited to, the term "including" means including but not limited to. The term "based on" means based at least in part on.

[0013] Various types of adapters may be connected to a PCI bus. According to examples, such adapters may be connected to the PCI bus of a device, such as a server. The device may provide power to a connected adapter via the PCI bus connection. In order for an application on the adapter to access the server or an application on the server to access the adapter, a communication link via a network interface card (NIC) or a serial port may be used. A NIC may be described as a computer circuit board or card that is installed in a computer so that the computer can be connected to a network. The use of the communication link via the NIC or the serial port may add inefficiencies to a communication process between the adapter and the device, which are directly connected via the PCI bus. That is, the use of the communication link via the NIC or the serial port may include the routing of traffic via a network for communication between the adapter and the device, instead of routing of traffic directly between the adapter and the device.

[0014] In order to address the technical challenges related to communication, for example, between two devices (e.g., Device-1 and Device-2, as disclosed herein) connected via a PCI bus, a network device emulation system and a method for network device emulation are disclosed herein. According to examples, the Device-1 may be an adapter, a server, or any type of computing device, which is connected via a PCI bus to the Device-2, which may be a server, or any type of computing device. Examples of adapters include network adapters, sound adapters, modems, TV tuner adapters, and disk controllers. Examples of applications as disclosed herein on the Device-1 and the Device-2 include any application that may need the services of the other device. For example, a Simple Network Management Protocol (SNMP) application on the Device-2 may gather information about the working status of the Device-1 (and vise-versa). According to another example, a Network Time Protocol (NTP) application on the Device-2 may perform time adjustments with respect to the Device-1 (and vise-versa). Thus, the applications may include any application on one device that may need to

communicate with another application on another device. According to examples, the system and method disclosed herein may provide for two devices that are connected via a PCI bus to directly communicate with each other using an industry- defined protocol. According to examples, the system and method disclosed herein may provide for an adapter to directly communicate with a server (i.e., a host server) using an industry-defined protocol. The aspect of direct communication may facilitate, for example, testing of applications on either device (e.g., the

Device-1 or the Device-2), and portability of applications, and eliminate the need for external equipment or cables for communication between such devices that are connected via a PCI bus. According to examples, the industry-defined protocol may include a Transmission Control Protocol/Internet Protocol (TCP/IP), and other such protocols.

[0015] According to examples, the system and method disclosed herein may include respective driver interfaces (i.e., disclosed herein as a Device-1 driver module and a Device-2 driver module) that operate on the Device-1 and the

Device-2, and use an external peripheral bus memory (i.e., a PCI mapped memory window for a physical memory on the Device-1 , which may be a PCI adapter) as a pseudo TCP/IP stack. The external peripheral bus memory may allow both the Device-1 and the Device-2 to communicate with each other using a TCP/IP socket interface, to thus provide for any network application to function as if the Device-1 and the Device-2 are connected via a network Ethernet connection. Thus, existing applications (e.g., PING, File Transfer Protocol (FTP), Telnet, Web-servers, etc.) may be used on the Device-1 and/or the Device-2 without any modification needed for such applications to communicate between the Device-1 and the Device-2.

[0016] According to examples, the system and method disclosed herein may provide for the emulation of a network device, such as a NIC, and use of a TCP/IP stack by using the external peripheral bus memory (i.e., the PCI mapped memory window), to thus provide for the use of an industry-standard protocol such as TCP/IP. In this regard, with respect to emulation, the system and method disclosed herein may provide for the implementation of the behavior of a NIC, without actual use of a NIC. Thus, applications on both the Device-1 and the Device-2 may communicate with each other using a respective PCI interface in the same manner as such applications would communicate with each other via external Ethernet network connections.

[0017] For an outgoing packet from the Device-2, the packet may be written to the PCI mapped memory window, for example, by the Device-2, and the receiving device (e.g., the Device-1 ) may determine the existence of the packet, and pull the packet to its TCP/IP stack. Similarly, for an outgoing packet from the Device-1 , the packet may be written to the PCI mapped memory window, for example, by the Device-1 , and the receiving device (e.g., the Device-2) may determine the existence of the packet, and pull the packet to its TCP/IP stack. Thus, instead of the Device-1 and the Device-2 communicating with each other via the NIC or the serial port, the Device-1 and the Device-2 may directly communicate with each other via the PCI mapped memory window.

[0018] Figure 1 illustrates an architecture of a network device emulation system (hereinafter also referred to as "system 100"), according to an example of the present disclosure. Referring to Figure 1 , the system 100 is depicted as including a mapping module 102 to map an external peripheral bus memory 104 on a first device (hereinafter designated as Device-1 ) to a PCI peripheral bus 106 on a second device (hereinafter designated as Device-2). The Device-1 and the Device- 2 may be connectable to each other by using the PCI peripheral bus 106.

[0019] A Device-2 driver module 108 may transmit Device-2 data 110 by using the mapped external peripheral bus memory 104 on the Device-1 , from the Device- 2 to the Device-1 . Similarly, a Device-1 driver module 112 may transmit Device-1 data 114 by using the mapped external peripheral bus memory 104 on the Device- 1 , from the Device-1 to the Device-2.

[0020] According to examples, the transmission of the Device-2 data 110 and/or the Device-1 data 114 may be performed by using TCP/IP, or other such protocols. For example, the transmission of the Device-2 data 110 and/or the Device-1 data 114 may be performed by writing to the mapped external peripheral bus memory 104, and respectively using a Device-2 TCP/IP stack 116 or a Device-1 TCP/IP stack 118.

[0021] Figure 2 illustrates an adapter driver interface block diagram for the system 100, according to an example of the present disclosure. For the example of Figure 2, the Device-1 may be an adapter which is connected via the PCI peripheral bus 106 to the Device-2 such as a server. Various components of the driver interface block diagram of Figure 2 may be implemented as part of the Device-1 driver module 112 and/or separately from the Device-1 driver module 112.

[0022] Referring to Figure 2, at 200, the Device-1 may include the external peripheral bus memory 104 mapped to the PCI peripheral bus 106.

[0023] At 202, an external peripheral bus chip select mapped to the PCI peripheral bus 106 may provide for accessibility of the external peripheral bus memory 104 from both the Device-1 and the Device-2.

[0024] An interrupt control logic 204 may generate an interrupt request (IRQ), for example, to the Device-1 when the Device-2 writes, for example, a packet, to the external peripheral bus memory 104, or receives, for example, a packet, from the Device-1 . Similarly, the interrupt control logic 204 may generate an IRQ, for example, to the Device-2 when the Device-1 writes, for example, a packet, to the external peripheral bus memory 104, or receives, for example, a packet, from the Device-2. When the Device-1 writes (e.g., a packet) to the external peripheral bus memory 104 for the Device-2, or receives (e.g., a packet) from the Device-2, the IRQ may be transmitted from the interrupt control logic 204 to a PCI Device-2 peripheral bus 208. Similarly, when the Device-2 writes (e.g., a packet) to the external peripheral bus memory 104 for the Device-1 , or receives (e.g., a packet) from the Device-1 , the IRQ may be transmitted from the interrupt control logic 204 to an external peripheral bus 210.

[0025] PCI configuration registers PCI INTA (IRQ to Device-2) at 206 may include the logic for mapping the external peripheral bus memory 104 to the PCI peripheral bus 106.

[0026] The PCI Device-2 peripheral bus 208 may represent a controller inside the Device-1 to provide for sharing of the external peripheral bus memory 104 between the Device-1 and the Device-2. The PCI Device-2 peripheral bus 208 may be configured as a connector on the Device-1 for connection to the PCI peripheral bus 106 on the Device-2. In a similar manner, the Device-2 may include a PCI Device-1 peripheral bus (not shown) that is configured as a connector on the Device-2 for connection to the Device-1 via the PCI peripheral bus 106 on the Device-2.

[0027] The external peripheral bus 210 may represent the bus via which the PCI interface of the PCI peripheral bus 106 communicates with the external peripheral bus memory 104 in the Device-1 .

[0028] Figure 3 illustrates a transmit packet flowchart for the system 100, according to an example of the present disclosure.

[0029] Referring to Figure 3, the flowchart of Figure 3 may represent a Device-2 (e.g., a host server) transmitting packets to a Device-1 (e.g., an adapter). The Device-1 may transmit packets to the Device-2 in a similar, but opposite, manner (i.e., with the terms Device-1 and Device-2 interchanged in the flowchart of Figure 3).

[0030] At block 300, the Device-2 driver module 108 may ascertain a packet that is ready to be transmitted. In this regard, the packet may be received at the Device-2 TCP/IP stack 116.

[0031] At block 302, the Device-2 driver module 108 may determine whether the Device-1 link is active, and whether the Device-1 mode (e.g., a packet mode or a block mode for data) is set correctly. The packet mode may be used for transmission of packets, and the block mode may be used for transmission of data in another format, such as a block. In this regard, the Device-2 driver module 108 may analyze a Device-1 link status register in the external peripheral bus memory 104 (e.g., at 200 in Figure 2) to determine whether the Device-1 link is active, and a Device-1 link configuration register in the external peripheral bus memory 104 to determine whether the Device-1 mode is set correctly.

[0032] In response to a determination at block 302 that the Device-1 link is not active, or the Device-1 mode is not set correctly, at block 304, the Device-2 driver module 108 may generate a communication link error. The communication link error may be transmitted to the Device-2 TCP/IP stack 116.

[0033] In response to a determination at block 302 that the Device-1 link is active, and the Device-1 mode is set correctly, at block 306, the Device-2 driver module 108 may read Device-1 input queue head and tail registers located in the external peripheral bus memory 104 (e.g., at 200 in Figure 2). In this regard, the Device-2 driver module 108 may read the Device-1 input queue head and tail registers to determine where to place the packet.

[0034] At block 308, the Device-2 driver module 108 may determine whether the Device-1 input queue head and tail registers indicate a full Device-1 queue. In this regard, if all of the locations in the Device-1 queue being analyzed are full, the Device-1 input queue head register may be disposed in front of the tail register. The Device-1 queue may represent a location where multiple packets may be received and processed in the order they were received (i.e., as they are placed into the Device-1 queue by the Device-2).

[0035] In response to a determination at block 308 that the Device-1 input queue head and tail registers do not indicate a full Device-1 queue, at block 310, the Device-2 driver module 108 may determine whether all of the data is written (i.e., all of the data that is to be transmitted from Device-2 to Device-1 , where a plurality of packets that include a size smaller than all of the data may be used to incrementally transmit all of the data). The data may be written to the external peripheral bus memory 104 mapped to the PCI peripheral bus 106.

[0036] In response to a determination at block 310 that all of the data is not written, at block 312, the Device-2 driver module 108 may write the data to a Device-1 input queue buffer specified in the Device-1 input queue head register, increment the Device-1 input queue head register, and generate a Device-1 receive IRQ via the interrupt control logic 204. In this regard, further processing may revert to block 306 until all of the data is written to the Device-1 input queue buffer.

[0037] In response to a determination at block 308 that the Device-1 input queue head and tail registers indicate a full Device-1 queue, at block 314, the Device-2 driver module 108 may wait for a Device-2 transmit complete IRQ. In this regard, the Device-2 driver module 108 may wait until there is room in the Device-1 queue. Alternatively, in response to a determination at block 318 that the Device-1 device input queue head and tail registers do not indicate an empty Device-1 queue, the Device-2 driver module 108 may wait for the Device-2 transmit complete IRQ.

[0038] At block 316, the Device-1 driver module 112 may remove a packet specified in the Device-1 input queue tail register from the Device-1 queue, increment the Device-1 input queue tail register, and generate a Device-2 transmit complete IRQ via the interrupt control logic 204. In this regard, the Device-1 driver module 112 may effectively create room in the Device-1 queue, if the Device-1 queue is determined to be full at block 308.

[0039] In response to a determination at block 310 that all of the data is written, at block 318, the Device-2 driver module 108 may determine whether the Device-1 input queue head and tail registers indicate an empty Device-1 queue. In this regard, the Device-2 driver module 108 may effectively determine whether the data that is written to the Device-1 queue has been received by the Device-1 .

[0040] In response to a determination at block 318 that the Device-1 input queue head and tail registers indicate an empty Device-1 queue, at block 320, the Device-2 driver module 108 may complete the request to transmit the data successfully.

[0041] Figure 4 illustrates a receive packet flowchart for the system 100, according to an example of the present disclosure.

[0042] Referring to Figure 4, the flowchart of Figure 4 may represent a Device-2 (e.g., a host server) receiving packets from a Device-1 (e.g., an adapter). The Device-1 may receive packets from the Device-2 in a similar, but opposite, manner (i.e., with the terms Device-1 and Device-2 interchanged in the flowchart of Figure 4). With reference to Figure 4, the Device-1 may transmit packets via the Device-2 queue. The Device-1 may receive packets via the Deivce-1 queue. Similarly, the Device-2 may transmit packets via the Device-1 queue. Further, the Device-2 may receive packets via the Device-2 queue. The Device-2 input queue head register may inform the Device-2 which packet is next to be processed. The Device-2 input queue tail register may inform the Device-1 where the next packet sent to the Device-2 should be placed. The Device-1 input queues may be used for the same purpose, but for packets being sent in the other direction.

[0043] At block 400, the Device-1 driver module 112 may add data to a Device- 2 input queue buffer specified in the Device-2 input queue head register, increment the Device-2 input queue head register, and generate a Device-2 receive IRQ via the interrupt control logic 204.

[0044] At block 402, the Device-2 driver module 108 may wait for a Device-2 receive IRQ (i.e., wait until the Device-1 driver module 112 adds data to the Device- 2 input queue buffer as specified in block 400). Further, in response to a

determination at block 406 that the Device-2 input queue head and tail registers indicate that the Device-2 queue is not empty, at block 402, the Device-2 driver module 108 may wait for a Device-2 receive IRQ.

[0045] At block 404, the Device-2 driver module 108 may read the Device-2 input queue head and tail registers, also located in the external peripheral bus memory 104 (e.g., at 200 in Figure 2). In this regard, the external peripheral bus memory 104 may include the Device-2 input queue head and tail registers described with respect to block 404, and the Device-1 input queue head and tail registers described with respect to block 306.

[0046] At block 406, the Device-2 driver module 108 may determine whether the Device-2 input queue head and tail registers indicate that the Device-2 queue is not empty.

[0047] In response to a determination at block 406 that the Device-2 input queue head and tail registers indicate the Device-2 queue is empty, at block 408, the Device-2 driver module 108 may read data from Device-2 input queue buffer specified in the Device-2 input queue tail register, increment the Device-2 input queue tail register, and generate a Device-1 transmit complete IRQ.

[0048] At block 410, the Device-2 driver module 108 may send the received packet, which may be delivered by the TCP/IP stack.

[0049] The modules and other elements of the system 100 may be machine readable instructions stored on a non-transitory computer readable medium. In this regard, the system 100 may include or be a non-transitory computer readable medium. In addition, or alternatively, the modules and other elements of the system 100 may be hardware or a combination of machine readable instructions and hardware.

[0050] Figures 5-7 respectively illustrate flowcharts of methods 500, 600, and 700 for network device emulation, corresponding to the example of the network device emulation system 100 whose construction is described in detail above. The methods 500, 600, and 700 may be implemented on the network device emulation system 100 with reference to Figures 1 -4 by way of example and not limitation. The methods 500, 600, and 700 may be practiced in other systems.

[0051] Further, although execution of the methods described herein is with reference to the system 100 of Figure 1 , other suitable devices for execution of these methods will be apparent to those of skill in the art. The methods described in the flowcharts of Figure 5-7 may be implemented in the form of executable instructions stored on a machine-readable storage medium, such as the memory 806 and/or the secondary data storage 808 of Figure 8, by one or more modules described herein, and/or in the form of electronic circuitry.

[0052] Referring to Figure 5, for the method 500, at block 502, the method may include mapping, by a computer system comprising a physical processor, an external peripheral bus memory on a first device to a PCI bus 106 on a second device, where the first and second devices may be connectable to each other by using the PCI bus 106.

[0053] Referring to Figure 5, for the method 500, at block 504, the method may include transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, data from the second device to the first device.

[0054] According to examples, the method 500 may include transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by using TCP/IP.

[0055] According to examples, the method 500 may include transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by transmitting, by the computer system comprising the physical processor, by writing the data to the mapped external peripheral bus memory on the first device, the data from the second device to the first device.

[0056] According to examples, the method 500 may include transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by determining, by the computer system comprising the physical processor, whether a first device link is active, and generating, by the computer system comprising the physical processor, in response to a determination that the first device link is not active, a communication link error.

[0057] According to examples, the method 500 may include transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by reading, by the computer system comprising the physical processor, first device input queue head and tail registers located in the mapped external peripheral bus memory, and determining, by the computer system comprising the physical processor, whether the first device input queue head and tail registers indicate a full first device queue. Further, the method 500 may include waiting, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers indicate the full first device queue, for a second device transmit complete IRQ.

[0058] According to examples, the second device transmit complete IRQ may be based on a first device removal of data specified in the first device input queue tail register from the first device queue, and increment of the first device input queue tail register.

[0059] According to examples, the method 500 may include transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by reading, by the computer system comprising the physical processor, first device input queue head and tail registers located in the mapped external peripheral bus memory, and determining, by the computer system comprising the physical processor, whether the first device input queue head and tail registers indicate a full first device queue. Further, the method 500 may include determining, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers do not indicate a full first device queue, whether all of the data is written, and in response to a determination that all of the data is not written writing, by the computer system comprising the physical processor, remaining data from the data to a first device input queue buffer specified in the first device input queue head register,

incrementing the first device input queue head register, and generating a first device receive IRQ.

[0060] According to examples, the method 500 may include transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by reading, by the computer system comprising the physical processor, first device input queue head and tail registers located in the mapped external peripheral bus memory, and determining, by the computer system comprising the physical processor, whether the first device input queue head and tail registers indicate a full first device queue. Further, the method 500 may include determining, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers do not indicate a full first device queue, whether all of the data is written, determining, by the computer system comprising the physical processor, in response to a determination that all of the data is written, whether the first device input queue head and tail registers indicate an empty first device queue, and completing, by the computer system comprising the physical processor, in response to a

determination that the first device input queue head and tail registers indicate the empty first device queue, transmission of the data.

[0061] According to examples, the method 500 may include transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by reading, by the computer system comprising the physical processor, first device input queue head and tail registers located in the mapped external peripheral bus memory, and determining, by the computer system comprising the physical processor, whether the first device input queue head and tail registers indicate a full first device queue. Further, the method 500 may include determining, by the computer system comprising the physical processor, in response to a determination that the head and tail registers do not indicate a full first device queue, whether all of the data is written, determining, by the computer system comprising the physical processor, in response to a determination that all of the data is written, whether the first device input queue head and tail registers indicate an empty first device queue, and waiting, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers indicate the empty first device queue, for a second device transmit complete IRQ.

[0062] Referring to Figure 6, for the method 600, at block 602, the method may include mapping an external peripheral bus memory on a first device to a PCI bus 106 on a second device, where the first and second devices may be connectable to each other by using the PCI bus 106.

[0063] At block 604, the method 600 may include receiving, by using the mapped external peripheral bus memory on the first device, data from the first device at the second device. [0064] According to examples, the method 600 may include receiving, by using the mapped external peripheral bus memory on the first device, the data from the first device at the second device by waiting for a second device receive IRQ prior to receiving, by using the mapped external peripheral bus memory on the first device, the data from the first device at the second device.

[0065] According to examples, the method 600 may include receiving, by using the mapped external peripheral bus memory on the first device, the data from the first device at the second device by reading second device input queue head and tail registers, determining whether the second device input queue head and tail registers indicate that a second device queue is not empty, and in response to a determination that the second device input queue head and tail registers indicate that the second device queue is not empty, continuing to wait for the second device receive IRQ.

[0066] According to examples, the method 600 may include receiving, by using the mapped external peripheral bus memory on the first device, the data from the first device at the second device by reading second device input queue head and tail registers, and determining whether the second device input queue head and tail registers indicate that a second device queue is not empty. Further, the method 600 may include in response to a determination that the second device input queue head and tail registers indicate that the second device queue is empty reading data from a second device input queue buffer specified in the second device input queue tail register, incrementing the second device input queue tail register, and generating a first device transmit complete IRQ, and sending the received data for delivery to a TCP/IP stack.

[0067] Referring to Figure 7, for the method 700, at block 702, the method may include mapping an external peripheral bus memory on a first device to a PCI bus 106 on a second device, where the first and second devices are connectable to each other by using the PCI bus 106.

[0068] At block 704, the method 700 may include transmitting, by using the mapped external peripheral bus memory on the first device, data from the second device to the first device.

[0069] At block 706, the method 700 may include receiving, by using the mapped external peripheral bus memory on the first device, further data from the first device at the second device.

[0070] Figure 8 shows a computer system 800 that may be used with the examples described herein. The computer system 800 may represent a generic platform that includes components that may be in a server or another computer system. The computer system 800 may be used as a platform for the system 100. The computer system 800 may execute, by a processor (e.g., a single or multiple processors) or other hardware processing circuit, the methods, functions and other processes described herein. These methods, functions and other processes may be embodied as machine readable instructions stored on a computer readable medium, which may be non-transitory, such as hardware storage devices (e.g., RAM (random access memory), ROM (read only memory), EPROM (erasable, programmable ROM), EEPROM (electrically erasable, programmable ROM), hard drives, and flash memory).

[0071] The computer system 800 may include a processor 802 that may implement or execute machine readable instructions performing some or all of the methods, functions and other processes described herein. Commands and data from the processor 802 may be communicated over a communication bus 804. The computer system may also include a main memory 806, such as a random access memory (RAM), where the machine readable instructions and data for the processor 802 may reside during runtime, and a secondary data storage 808, which may be non-volatile and stores machine readable instructions and data. The memory and data storage are examples of computer readable mediums. The memory 806 may include a network device emulation module 820 including machine readable instructions residing in the memory 806 during runtime and executed by the processor 802. The network device emulation module 820 may include the modules of the system 100 shown in Figure 1 .

[0072] The computer system 800 may include an I/O device 810, such as a keyboard, a mouse, a display, etc. The computer system may include a network interface 812 for connecting to a network. Other known electronic components may be added or substituted in the computer system.

[0073] The foregoing disclosure describes a number of examples for network device emulation. The disclosed examples may include systems, devices, computer-readable storage media, and methods for network device emulation. For purposes of explanation, certain examples are described with reference to the components illustrated in Figures 1 -8. The functionality of the illustrated

components may overlap, however, and may be present in a fewer or greater number of elements and components. Further, all or part of the functionality of illustrated elements may co-exist or be distributed among several geographically dispersed locations. Moreover, the disclosed examples may be implemented in various environments and are not limited to the illustrated examples.

[0074] Further, the sequence of operations described in connection with

Figures 1 -8 are examples and are not intended to be limiting. Additional or fewer operations or combinations of operations may be used or may vary without departing from the scope of the disclosed examples. Furthermore,

implementations consistent with the disclosed examples need not perform the sequence of operations in any particular order. Thus, the present disclosure merely sets forth possible examples of implementations, and many variations and modifications may be made to the described examples. All such modifications and variations are intended to be included within the scope of this disclosure and protected by the following claims.

Claims

What is claimed is:

1 . A method for network device emulation, the method comprising: mapping, by a computer system comprising a physical processor, an external peripheral bus memory on a first device to a Peripheral Component Interconnect (PCI) bus on a second device, wherein the first and second devices are

connectable to each other by using the PCI bus; and transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, data from the second device to the first device.

2. The method according to claim 1 , wherein the first device includes a PCI adapter, and the second device includes a server.

3. The method according to claim 1 , wherein transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device further comprises: transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device by using Transmission Control

Protocol/Internet Protocol (TCP/IP).

4. The method according to claim 1 , wherein transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device further comprises: transmitting, by the computer system comprising the physical processor, by writing the data to the mapped external peripheral bus memory on the first device, the data from the second device to the first device.

5. The method according to claim 1 , wherein transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device further comprises: determining, by the computer system comprising the physical processor, whether a first device link is active; and generating, by the computer system comprising the physical processor, in response to a determination that the first device link is not active, a communication link error.

6. The method according to claim 1 , wherein transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device further comprises: reading, by the computer system comprising the physical processor, first device input queue head and tail registers located in the mapped external peripheral bus memory; determining, by the computer system comprising the physical processor, whether the first device input queue head and tail registers indicate a full first device queue; and waiting, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers indicate the full first device queue, for a second device transmit complete interrupt request (IRQ).

7. The method according to claim 6, wherein the second device transmit complete IRQ is based on a first device removal of data specified in the first device input queue tail register from the first device queue, and increment of the first device input queue tail register.

8. The method according to claim 1 , wherein transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device further comprises: reading, by the computer system comprising the physical processor, first device input queue head and tail registers located in the mapped external peripheral bus memory; determining, by the computer system comprising the physical processor, whether the first device input queue head and tail registers indicate a full first device queue; determining, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers do not indicate a full first device queue, whether all of the data is written; and in response to a determination that all of the data is not written writing, by the computer system comprising the physical processor, remaining data from the data to a first device input queue buffer specified in the first device input queue head register, incrementing the first device input queue head register, and generating a first device receive interrupt request (IRQ).

9. The method according to claim 1 , wherein transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device further comprises: reading, by the computer system comprising the physical processor, first device input queue head and tail registers located in the mapped external peripheral bus memory; determining, by the computer system comprising the physical processor, whether the first device input queue head and tail registers indicate a full first device queue; determining, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers do not indicate a full first device queue, whether all of the data is written; determining, by the computer system comprising the physical processor, in response to a determination that all of the data is written, whether the first device input queue head and tail registers indicate an empty first device queue; and completing, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers indicate the empty first device queue, transmission of the data.

10. The method according to claim 1 , wherein transmitting, by the computer system comprising the physical processor, by using the mapped external peripheral bus memory on the first device, the data from the second device to the first device further comprises: reading, by the computer system comprising the physical processor, first device input queue head and tail registers located in the mapped external peripheral bus memory; determining, by the computer system comprising the physical processor, whether the first device input queue head and tail registers indicate a full first device queue; determining, by the computer system comprising the physical processor, in response to a determination that the head and tail registers do not indicate a full first device queue, whether all of the data is written; determining, by the computer system comprising the physical processor, in response to a determination that all of the data is written, whether the first device input queue head and tail registers indicate an empty first device queue; and waiting, by the computer system comprising the physical processor, in response to a determination that the first device input queue head and tail registers indicate the empty first device queue, for a second device transmit complete interrupt request (IRQ).

11 . A network device emulation system comprising: at least one processor; and a memory storing machine readable instructions that when executed by the at least one processor cause the at least one processor to: map an external peripheral bus memory on a first device to a Peripheral Component Interconnect (PCI) bus on a second device, wherein the first and second devices are connectable to each other by using the PCI bus; and receive, by using the mapped external peripheral bus memory on the first device, data from the first device at the second device.

12. The network device emulation system according to claim 11 , wherein the machine readable instructions to receive, by using the mapped external peripheral bus memory on the first device, the data from the first device at the second device further comprise instructions to: wait for a second device receive interrupt request (IRQ) prior to receiving, by using the mapped external peripheral bus memory on the first device, the data from the first device at the second device.

13. The network device emulation system according to claim 12, wherein the machine readable instructions to receive, by using the mapped external peripheral bus memory on the first device, the data from the first device at the second device further comprise instructions to: read second device input queue head and tail registers; determine whether the second device input queue head and tail registers indicate that a second device queue is not empty; and in response to a determination that the second device input queue head and tail registers indicate that the second device queue is not empty, continue to wait for the second device receive IRQ.

14. The network device emulation system according to claim 12, wherein the machine readable instructions to receive, by using the mapped external peripheral bus memory on the first device, the data from the first device at the second device further comprise instructions to: read second device input queue head and tail registers; determine whether the second device input queue head and tail registers indicate that a second device queue is not empty; in response to a determination that the second device input queue head and tail registers indicate that the second device queue is empty read data from a second device input queue buffer specified in the second device input queue tail register, increment the second device input queue tail register, and generate a first device transmit complete IRQ; and send the received data for delivery to a Transmission Control Protocol/Internet Protocol (TCP/IP) stack.

15. A non-transitory computer readable medium having stored thereon machine readable instructions to provide network device emulation, the machine readable instructions, when executed, cause at least one processor to: map an external peripheral bus memory on a first device to a Peripheral Component Interconnect (PCI) bus on a second device, wherein the first and second devices are connectable to each other by using the PCI bus; transmit, by using the mapped external peripheral bus memory on the first device, data from the second device to the first device; and receive, by using the mapped external peripheral bus memory on the first device, further data from the first device at the second device.