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WO2016123840A1 - Source drive circuit - Google Patents

Source drive circuit Download PDF

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Publication number
WO2016123840A1
WO2016123840A1 PCT/CN2015/074458 CN2015074458W WO2016123840A1 WO 2016123840 A1 WO2016123840 A1 WO 2016123840A1 CN 2015074458 W CN2015074458 W CN 2015074458W WO 2016123840 A1 WO2016123840 A1 WO 2016123840A1
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WO
WIPO (PCT)
Prior art keywords
register
digital
analog converter
channel
electrically connected
Prior art date
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PCT/CN2015/074458
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French (fr)
Chinese (zh)
Inventor
邢振周
郭星灵
国春朋
Original Assignee
深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司, 武汉华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2016123840A1 publication Critical patent/WO2016123840A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a source driving circuit of a liquid crystal display panel.
  • the liquid crystal driving circuit includes a source driving circuit and a gate driving circuit.
  • the source driving circuit includes a shift register 6, a first register (Latch) 11, a second register 12, a third register 13, a fourth register 14, and a first Level shifter 21 (Level Shifter), second level shifter 22, first digital to analog converter (DAC) 31, second digital to analog converter 32, first output buffer 41 (Output Buffer) And a second output buffer 42.
  • the first signal D1 is input to the first register 11 and the second signal D2 is input to the second register 12.
  • the shift register 6 is electrically connected to the first register 11 and the second register 12, respectively for sequentially strobing the first register 11 and the second register 12 to sequentially turn the first signal D1 and the first
  • the two signals D2 are correspondingly transmitted to the first channel 51 and the second channel 52.
  • the first register 11 is electrically connected to the third register 13 and the fourth register 14, respectively, and the second register 12 is electrically connected to the third register 13 and the fourth register 14, respectively.
  • the third register 13 is sequentially electrically connected to the first output buffer 41 through the first level shifter 21 and the first digital-to-analog converter 31, and the fourth register 14 sequentially passes through the second level shifter 22 and the
  • the second to digital converter 31 is electrically connected to the second output buffer 42.
  • the first output buffer 41 is electrically connected to the output of the first channel 51 and the output of the second channel 52, respectively, and the second output buffer 42 is electrically coupled to the output of the first channel 51 and the output of the second channel 52, respectively. connection.
  • FIG. 2 is a timing chart showing the input signal of the source driving circuit shown in FIG. 1.
  • the working principle of the source driving circuit in the prior art is described below with reference to FIG. 2: when the first channel 51 is required to output the source of the positive polarity.
  • the positive first signal D1 is sequentially input to the first level shifter 21 through the first register 11 and the third register 13, after the voltage of the first level shifter 21 is raised.
  • Input to the first digital to analog converter 31, the first digital to analog converter 31 As a voltage selection function block, the required positive polarity analog voltage (corresponding to the gray scale voltage) is selected according to the output voltage of the first level shifter 21, and then the positive polarity analog voltage is amplified by the first output buffer 41.
  • the first channel 51 is output such that the first channel 51 outputs a positive source control signal.
  • the positive first signal D1 is sequentially input to the second level shifter 22 through the first register 11 and the fourth register 14 through the first channel
  • the voltage boosting of the two-level converter 22 is input to the second digital-to-analog converter 32, and the second digital-to-analog converter 32 functions as a voltage selection function block, and selects the required voltage according to the output voltage of the second level shifter 22.
  • the negative polarity analog voltage (corresponding to the gray scale voltage) is then amplified by the second output buffer 42 and output from the first channel 51, so that the first channel 51 outputs a negative source control signal.
  • each two adjacent channels of the source driving circuit in the prior art need to be correspondingly provided with two digital-to-analog converters, resulting in the volume of the chip for carrying the source driving circuit. No further reductions, and it is difficult to achieve higher resolution on a fixed chip area.
  • the present invention provides a source driving circuit of a liquid crystal display panel.
  • a source driving circuit comprising:
  • First and second channels disposed adjacent to each other;
  • a channel selection module and a shift register electrically connected to the channel selection module, a first frequency multiplier, a second frequency multiplier, a third frequency multiplier and a fourth frequency multiplier, the shift register being set such that The first signal multiplied by the first frequency multiplier and the second signal multiplied by the second frequency multiplier are input to the channel selection module in a preset first period, and the frequency multiplied by the third frequency multiplier The three signals and the fourth signal multiplied by the fourth frequency multiplier are input to the channel selection module for a preset second time period, and the intersection of the first time period and the second time period is an empty set;
  • the terminals are electrically connected to the output of the fourth channel.
  • the first period is the first half of each period
  • the second period is the second half of each period
  • the first digital-to-analog converter and the second digital-to-analog converter are respectively a P-type digital-to-analog converter and an N-type digital-to-analog converter; or the first digital-to-analog converter and the second digital-to-analog
  • the converters are an N-type digital-to-analog converter and a P-type digital-to-analog converter, respectively.
  • the channel selection module includes a first temporary register, a second temporary register, a third temporary register, a fourth temporary register, a fifth temporary register, a sixth temporary register, and a seventh temporary storage.
  • eighth register is a first temporary register, a second temporary register, a third temporary register, a fourth temporary register, a fifth temporary register, a sixth temporary register, and a seventh temporary storage.
  • the first register is electrically connected to the shift register, the first frequency multiplier, the third register, and the fourth register; the second register is respectively associated with a shift register and a second frequency multiplier , the third register and the fourth register are electrically connected; the fifth register is electrically connected to the shift register, the third frequency multiplier, the seventh register and the eighth register respectively; The sixth register is electrically connected to the shift register, the fourth frequency multiplier, the seventh register, and the eighth register respectively;
  • the third register and the seventh register are both electrically connected to the first digital-to-analog converter; the fourth register and the eighth register are both electrically connected to the second digital-to-analog converter connection.
  • the output buffer module includes a first output buffer, a second output buffer, a third output buffer, and a fourth output buffer;
  • the first digital to analog converter is electrically coupled to an output of the first channel and an output of the second channel via the first output buffer; the first digital to analog converter is coupled to the third output buffer Electrically connected to the output of the third channel and the output of the fourth channel;
  • the second digital to analog converter is electrically coupled to the output of the first channel and the output of the second channel via the second output buffer; the second digital to analog converter is passed through the fourth output buffer They are electrically connected to the output of the third channel and the output of the fourth channel, respectively.
  • the source driving circuit further includes a first level shifter, a second level shifter, a third level shifter, and a fourth level shifter;
  • the third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter Connecting; the seventh register is electrically connected to the first digital-to-analog converter via the third level shifter; and the eighth register is converted by the fourth level shifter and the second digital-to-analog Electrical connection.
  • the channel selection module includes a first temporary register, a second temporary register, a third temporary register, a fourth temporary register, a fifth temporary register and a sixth temporary register;
  • the first register is electrically connected to the shift register, the first frequency multiplier, the third register, and the fourth register; the second register is respectively associated with a shift register and a second frequency multiplier , the third register and the fourth register are electrically connected; the fifth register is electrically connected to the shift register, the third frequency multiplier, the third register and the fourth register respectively; The sixth register is electrically connected to the shift register, the fourth frequency multiplier, the third register, and the fourth register, respectively;
  • the third register is electrically connected to the first digital to analog converter; the fourth register is electrically connected to the second digital to analog converter.
  • the output buffer module includes a first output buffer and a second output buffer
  • the first digital-to-analog converter is electrically coupled to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel via the first output buffer;
  • the second digital to analog converter is electrically coupled to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel via the second output buffer, respectively.
  • the source driving circuit further includes a first level shifter and a second level shifter;
  • the third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter connection.
  • At least four of all source line control channels of the array substrate of the liquid crystal display panel are driven by the source driving circuit of the present invention, combined with a technique of frequency-doubled processing of the input signal and time-multiplexed digital-to-analog converter. It can realize two digital-to-analog converters for every four channels, which effectively reduces the number of digital-to-analog converters in the source driver circuit, reduces the area and resources occupied by the digital-to-analog converter, and reduces the source drive. The cost of the circuit facilitates further reduction of the size of the chip used to carry the source driver circuit, enabling higher resolution over a fixed chip area.
  • FIG. 1 is a schematic view showing a source driving circuit of a liquid crystal display panel in the prior art
  • FIG. 2 is a timing chart showing an input signal of the source driving circuit shown in FIG. 1;
  • FIG. 3 is a schematic view showing a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 4 is a timing chart showing an input signal of the source driving circuit shown in FIG. 3;
  • FIG. 5 is a second schematic diagram showing a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 6 shows a third schematic diagram of a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention.
  • an embodiment of the present invention provides a source driving circuit of a liquid crystal display panel.
  • FIG. 3 is a schematic view showing a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention.
  • the source driving circuit includes a first channel 51, a second channel 52, a third channel 53, a fourth channel 54, a shift register 6, a first frequency multiplier 71, a second frequency multiplier 72, The third frequency multiplier 73, the fourth frequency multiplier 74, the channel selection module 1, the first digital to analog converter 31, the second digital to analog converter 32, and the output buffer module 4.
  • first passage 51 and the second passage 52 are disposed adjacent to each other, and the third passage 53 is disposed adjacent to the fourth passage 54.
  • the second passage 52 is disposed adjacent to the third passage 53, that is, the first passage 51, the second passage 52, the third passage 53 and the fourth passage 54 are sequentially disposed; or the fourth The passage 54 is disposed adjacent to the first passage 51, that is, the third passage 53, the fourth passage 54, the first passage 51, and the second passage 52 are sequentially disposed.
  • the frequency multiplier is a circuit that makes the output signal frequency equal to an integral multiple of the input signal frequency.
  • the first frequency multiplier 71, the second frequency multiplier 72, the third frequency multiplier 73, and the fourth frequency multiplier 74 are provided.
  • the frequencies of the first signal D1, the second signal D2, the third signal D3, and the fourth signal D4 are doubled in a one-to-one correspondence, respectively. For example, if the frequency of the first signal D1 is 60 Hz, the frequency of the first signal D1 multiplied by the first frequency multiplier 71 is raised to 120 Hz.
  • the first signal D1 (generally a digital signal) input to the first channel 51 is multiplied by the first frequency multiplier 71 and input to the channel selection module 1, and the second signal D2 input to the second channel 52 is subjected to the second frequency multiplication.
  • the device 72 is multiplied and input to the channel selection module 1.
  • the third signal D3 input to the third channel 53 is input to the channel selection module 1 by the multiplication of the third frequency multiplier 73, and is input to the fourth channel 54.
  • the signal D4 is multiplied by the fourth frequency multiplier 74 and input to the channel selection module 1.
  • the multiplied signals are assigned to the first digital-to-analog converter 31 and the second digital-to-analog converter 32 by the channel selection module 1.
  • the shift register 6 is a timing for controlling the input of each signal to the first digital-to-analog converter 31 and the second digital-to-analog converter 32. Circuit. Specifically, the program register is set to input the first signal D1 multiplied by the first frequency multiplier 71 and the second signal D2 multiplied by the second frequency multiplier 72 to the channel selection module 1 in a preset first time period. The third signal D3 multiplied by the third frequency multiplier 73 and the fourth signal D4 multiplied by the fourth frequency multiplier 74 are prohibited from being input to the channel selection module 1 during the first time period.
  • the program register is further configured to input the third signal D3 multiplied by the third frequency multiplier 73 and the fourth signal D4 multiplied by the fourth frequency multiplier 74 to the channel selection module 1 for a preset second time period,
  • the first signal D1 multiplied by the first frequency multiplier 71 and the second signal D2 multiplied by the second frequency multiplier 72 are prohibited from being input to the channel selection module 1 during the second period.
  • the intersection of the preset first time period and the preset second time period is an empty set to prevent the first signal D1, the second signal D2, the third signal D3, and the fourth signal D4 from interfering with each other.
  • the shift register 6 is preferably a bidirectional shift register.
  • the first time period is preferably the first half of each data transmission period
  • the second time period is preferably the second half of each data transmission period.
  • the first signal D1 and the second signal D2 are transmitted in the first half of the period
  • the third signal D3 and the fourth signal D4 are transmitted in the second half of the period.
  • the first signal D1 and the second signal D2 are complementary signals (ie, when the first signal D1 is at a high level, the second signal D2 is at a low level, and vice versa), and the two can multiplex two numbers.
  • the analog-to-digital converter ie, the first digital-to-analog converter 31 and the second digital-to-analog converter 32
  • the third signal D3 and the fourth signal D4 are also complementary signals (ie, when the third signal D3 is at a high level, The fourth signal D4 is at a low level, and vice versa.
  • the three signals D3 and the fourth signal D4 can also multiplex the two digital-to-analog converters (ie, the first digital-to-analog converter 31 and the second digital-to-analog converter 32), thereby implementing only two digital-to-analog converters.
  • the signal input of the four channels can be completed.
  • the signal input of the four channels refers to the signal input of the first channel 51, the signal input of the second channel 52, the signal input of the third channel 53, and the signal input of the fourth channel 54.
  • first digital-to-analog converter 31 and the second digital-to-analog converter 32 pass through the output buffer module 4 with the output end of the first channel 51, the output end of the second channel 52, the output end of the third channel 53, and the fourth.
  • the output end of the channel 54 is electrically connected, and the output buffer module 4 is configured to amplify the output signal of the first digital-to-analog converter 31, and output the amplified signals to the output end of the first channel 51 and the second channel 52, respectively.
  • the output buffer module 4 is further configured to amplify the output signal of the second digital-to-analog converter 32, and output the amplified signals to the first The output of one channel 51, the output of second channel 52, the output of third channel 53, and the output of fourth channel 54.
  • At least four channels of all the source line control channels of the array substrate of the liquid crystal display panel are driven by the source driving circuit described in this embodiment, and combined with frequency doubling processing and time division multiplexing of the input signal.
  • digital-to-analog converter technology it can realize two digital-to-analog converters for every four channels, thus effectively reducing the source drive power.
  • the number of digital-to-analog converters in the circuit reduces the area and resources occupied by the digital-to-analog converter, and also reduces the cost of the source driving circuit, which is advantageous for further reducing the size of the chip for carrying the source driving circuit. A higher resolution is achieved over a fixed chip area.
  • the channel pair composed of the first channel 51 and the second channel 52 and the channel pair composed of the third channel 53 and the fourth channel 54 may be adjacently disposed, or may be spaced apart.
  • the first channel 51, the second channel 52, the third channel 53, and the fourth channel 54 constitute a channel combination.
  • all the source line control channels of the array substrate of the liquid crystal display panel are divided into a plurality of channel combinations, and the source driving circuit of each channel combination is combined with FIG.
  • the circuit structure of the illustrated source driver circuit is the same.
  • all the channels of the array substrate are sequentially divided into a first channel pair (having adjacent first channel 51 and second channel 52) and a second a pair of channels (having a third channel 53 and a fourth channel 54 disposed adjacently, a second channel 52 disposed adjacent to the third channel 53), a third channel pair, a fourth channel pair, a fifth channel pair, and a sixth channel Correct,....
  • the driving method of the source driving circuit corresponding to the embodiment includes: inputting the video data of the odd pair of channel pairs in the preset first time period due to the doubling of the frequency of the input digital signal (ie, the first channel pair, the third channel) Channel data of the channel pair, the fifth channel pair, and the seventh channel pair. At this time, it is forbidden to input the video data of the even pair of channel pairs (ie, prohibiting the input of the second channel pair, the fourth channel pair, and the sixth in the first time period) Channel pair, eighth channel pair... video data).
  • the second time period has no intersection with the first time period, that is, the intersection of the second time period and the first time period is an empty set
  • the sixth channel pair, the eighth channel pair ... video data it is forbidden to input the video data of the odd pair of channel pairs (ie, the first channel pair, the third channel pair, and the fifth channel pair are prohibited from being input in the second time period) , the seventh channel to ... video data).
  • the design of multiplexing two digital-to-analog converters for every four channels can be realized, thereby halving the number of digital-to-analog converters in the source driving circuit, thereby greatly reducing the number of digital-to-analog converters in the source driving circuit.
  • the area and resources occupied by the digital-to-analog converter also greatly reduce the cost of the source driving circuit, and are particularly advantageous for further reducing the size of the chip for carrying the source driving circuit, and being able to complete higher on a fixed chip area. Resolution.
  • first digital-to-analog converter 31 and the second digital-to-analog converter 32 may each adopt a digital-to-analog converter structure formed of CMOS, or may preferably adopt a P-type digital-to-analog converter structure formed of a PMOS single tube or
  • the N-type digital-to-analog converter structure formed by the NMOS single-tube that is, the first digital-to-analog converter 31 and the second digital-to-analog converter 32 are respectively a P-type digital-to-analog converter and an N-type digital-to-analog converter; or the first number
  • the mode converter 31 and the second digital-to-analog converter 32 are an N-type digital-to-analog converter and a P-type digital-to-analog converter, respectively.
  • the area of the P-type digital-to-analog converter or the N-type digital-to-analog converter is much smaller than the area of the digital-to-analog converter formed by CMOS, the area and resources occupied by the digital-to-analog converter are further reduced by the embodiment. At the same time, the cost of the source driving circuit is further reduced, which is beneficial for further reduction.
  • the volume of the chip carrying the source driving circuit can achieve a higher resolution on a fixed chip area.
  • FIG. 5 a second schematic diagram and a third schematic diagram of the source driving circuit of the liquid crystal display panel are respectively given in conjunction with FIG. 5 and FIG.
  • the timing charts of the input signals of the source driving circuits shown in FIGS. 5 and 6 are as shown in FIG.
  • FIG. 5 is a second schematic diagram showing a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention.
  • the channel selection module 1 includes a first temporary storage unit 11, a second temporary storage unit 12, a third temporary storage unit 13, a fourth temporary storage unit 14, a fifth temporary storage unit 15, and a sixth temporary storage unit.
  • the first register 11 is electrically connected to the shift register 6, the first frequency multiplier 71, the third register 13 and the fourth register 14, respectively; the second register 12 and the shift register respectively 6.
  • the second frequency multiplier 72, the third temporary register 13 and the fourth temporary register 14 are electrically connected;
  • the fifth temporary register 15 is respectively connected to the shift register 6, the third frequency multiplier 73, and the seventh temporary register 17 and the eighth register 18 are electrically connected;
  • the sixth register 16 is electrically connected to the shift register 6, the fourth frequency multiplier 74, the seventh register 17, and the eighth register 18, respectively.
  • the third register 13 and the seventh register 17 are both electrically connected to the first digital-to-analog converter 31;
  • the fourth register 14 and the eighth register 18 are both electrically connected to the second digital-to-analog converter 32.
  • the output buffer module 4 includes a first output buffer 41, a second output buffer 42, a third output buffer 43, and a fourth output buffer 44.
  • the first digital-to-analog converter 31 is electrically connected to the output end of the first channel 51 and the output end of the second channel 52 via the first output buffer 41; the first digital-to-analog converter 31 passes through the third output buffer. 43 is electrically connected to the output end of the third channel 53 and the output end of the fourth channel 54, respectively;
  • the second digital-to-analog converter 32 is electrically coupled to the output of the first channel 51 and the output of the second channel 52 via the second output buffer 42; the second digital-to-analog converter 32 is coupled to the fourth output buffer 44 via the fourth output buffer 44, respectively.
  • the output of the third channel 53 is electrically coupled to the output of the fourth channel 54.
  • the source driving circuit further includes a first level shifter 21, a second level shifter 22, a third level shifter 23, and a fourth level shifter 24 to process the frequency doubling.
  • the signal is voltage boosted.
  • the third register 13 is electrically connected to the first digital-to-analog converter 31 via the first level shifter 21; the fourth register 14 is electrically connected to the second digital-to-analog converter 32 via the second level shifter 22;
  • the seventh register 17 is electrically coupled to the first digital to analog converter 31 via a third level shifter 23; the eighth register 18 is electrically coupled to the second digital to analog converter 32 via a fourth level shifter 24.
  • FIG. 6 shows a third schematic diagram of a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention.
  • the channel selection module 1 includes a first temporary storage unit 11, a second temporary storage unit 12, a third temporary storage unit 13, a fourth temporary storage unit 14, a fifth temporary storage unit 15, and a sixth temporary storage unit. 16.
  • the first register 11 is electrically connected to the shift register 6, the first frequency multiplier 71, the third register 13 and the fourth register 14, respectively; the second register 12 and the shift register respectively 6.
  • the second frequency multiplier 72, the third temporary register 13 and the fourth temporary register 14 are electrically connected; the fifth temporary register 15 is respectively connected to the shift register 6, the third frequency multiplier 73, and the third temporary storage.
  • the third register 16 is electrically connected to the fourth register 14; the sixth register 16 is electrically connected to the shift register 6, the fourth frequency multiplier 74, the third register 13 and the fourth register 14, respectively.
  • the third register 13 is electrically connected to the first digital-to-analog converter 31; the fourth register 14 is electrically connected to the second digital-to-analog converter 32.
  • the output buffer module 4 includes a first output buffer 41 and a second output buffer 42.
  • the first digital-to-analog converter 31 passes through the first output buffer 41 with the output of the first channel 51, the output of the second channel 52, the output of the third channel 53, and the output of the fourth channel 54, respectively. Electrically coupled; the second digital to analog converter 32 is coupled to the output of the first channel 51, the output of the second channel 52, the output of the third channel 53, and the output of the fourth channel 54 via the second output buffer 42 Electrical connection.
  • the source driving circuit further includes a first level shifter 21 and a second level shifter 22.
  • the third register 13 is electrically connected to the first digital-to-analog converter 31 via the first level shifter 21; the fourth register 14 is electrically connected to the second digital-to-analog converter 32 via the second level shifter 22.
  • the present invention can not only realize the multiplexing of two digital-to-analog converters in four adjacent channels, but also expand into two adjacent digital channels to multiplex two digital-to-analog converters.
  • the frequency is maximized when the processing speed allows, so that all the channels can be multiplexed with two digital-to-analog converters to complete the source driving, so that the digital-to-analog converter in the source driving circuit can be realized.
  • the number is minimized and the area of the source driver circuit is minimized and the cost is minimized.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

A source drive circuit. At least four channels of all source line control channels in an array substrate are driven by the circuit, and sharing of two DACs (Digital Analog Converter) by every four channels can be realized by means of technical means for frequency doubling of input signals and for time sharing multiplexing of the DACs; thus, the number of the DACs in the source drive circuit is effectively reduced, area and resources occupied by the DACs as well as circuit cost are lowered, chip volume is further advantageously diminished, and higher resolutions can be accomplished on an unchanged chip area.

Description

源极驱动电路Source drive circuit
本申请要求享有2015年2月4日提交的名称为“源极驱动电路”的中国专利申请CN201510059380.0的优先权，其全部内容通过引用并入本文中。The present application claims priority to Chinese Patent Application No. CN201510059380.0, filed on Jan. 4,,,,,,,,,,
技术领域Technical field
本发明涉及液晶显示技术领域，尤其涉及一种液晶显示面板的源极驱动电路。The present invention relates to the field of liquid crystal display technologies, and in particular, to a source driving circuit of a liquid crystal display panel.
背景技术Background technique
近年来，随着显示技术的不断进步，液晶显示器已成为市场上最常见的显示装置。对一般的液晶显示器而言，液晶驱动电路包括源极驱动电路和栅极驱动电路。In recent years, with the continuous advancement of display technology, liquid crystal displays have become the most common display devices on the market. For a general liquid crystal display, the liquid crystal driving circuit includes a source driving circuit and a gate driving circuit.
图1示出了现有技术中液晶显示面板的源极驱动电路的示意图，图中仅示出了涉及两个相邻通道的源极驱动电路。如图1所示，该源极驱动电路包括移位寄存器6、第一暂存器(Latch)11、第二暂存器12、第三暂存器13、第四暂存器14、第一电平转换器21(Level Shifter)、第二电平转换器22、第一数模转换器(Digital Analog Converter，DAC)31、第二数模转换器32、第一输出缓冲器41(Output Buffer)和第二输出缓冲器42。具体地，第一信号D1输入至第一暂存器11，第二信号D2输入至第二暂存器12。移位寄存器6分别与第一暂存器11和第二暂存器12电连接，用于依次选通第一暂存器11和第二暂存器12，以依次将第一信号D1和第二信号D2相应地传送到第一通道51和第二通道52上。1 is a schematic view showing a source driving circuit of a liquid crystal display panel in the prior art, and only a source driving circuit involving two adjacent channels is shown. As shown in FIG. 1, the source driving circuit includes a shift register 6, a first register (Latch) 11, a second register 12, a third register 13, a fourth register 14, and a first Level shifter 21 (Level Shifter), second level shifter 22, first digital to analog converter (DAC) 31, second digital to analog converter 32, first output buffer 41 (Output Buffer) And a second output buffer 42. Specifically, the first signal D1 is input to the first register 11 and the second signal D2 is input to the second register 12. The shift register 6 is electrically connected to the first register 11 and the second register 12, respectively for sequentially strobing the first register 11 and the second register 12 to sequentially turn the first signal D1 and the first The two signals D2 are correspondingly transmitted to the first channel 51 and the second channel 52.
第一暂存器11分别与第三暂存器13和第四暂存器14电连接，第二暂存器12分别与第三暂存器13和第四暂存器14电连接。第三暂存器13依次通过第一电平转换器21和第一数模转换器31与第一输出缓冲器41电连接，第四暂存器14依次通过第二电平转换器22和第二数模转换器31与第二输出缓冲器42电连接。第一输出缓冲器41分别与第一通道51的输出端和第二通道52的输出端电连接，第二输出缓冲器42分别与第一通道51的输出端和第二通道52的输出端电连接。The first register 11 is electrically connected to the third register 13 and the fourth register 14, respectively, and the second register 12 is electrically connected to the third register 13 and the fourth register 14, respectively. The third register 13 is sequentially electrically connected to the first output buffer 41 through the first level shifter 21 and the first digital-to-analog converter 31, and the fourth register 14 sequentially passes through the second level shifter 22 and the The second to digital converter 31 is electrically connected to the second output buffer 42. The first output buffer 41 is electrically connected to the output of the first channel 51 and the output of the second channel 52, respectively, and the second output buffer 42 is electrically coupled to the output of the first channel 51 and the output of the second channel 52, respectively. connection.
图2示出了图1所示的源极驱动电路的输入信号的时序图，下面结合图2，说明现有技术中源极驱动电路的工作原理：当需要第一通道51输出正极性的源极控制信号时，正极性的第一信号D1依次通过第一暂存器11和第三暂存器13输入至第一电平转换器21，经第一电平转换器21的电压抬升作用后输入至第一数模转换器31，第一数模转换器31 作为一个电压选择功能块，根据第一电平转换器21的输出电压选择所需的正极性的模拟电压(对应灰阶电压)，然后正极性的模拟电压经第一输出缓冲器41放大后从第一通道51输出，从而使第一通道51输出正极性的源极控制信号。2 is a timing chart showing the input signal of the source driving circuit shown in FIG. 1. The working principle of the source driving circuit in the prior art is described below with reference to FIG. 2: when the first channel 51 is required to output the source of the positive polarity. In the case of the pole control signal, the positive first signal D1 is sequentially input to the first level shifter 21 through the first register 11 and the third register 13, after the voltage of the first level shifter 21 is raised. Input to the first digital to analog converter 31, the first digital to analog converter 31 As a voltage selection function block, the required positive polarity analog voltage (corresponding to the gray scale voltage) is selected according to the output voltage of the first level shifter 21, and then the positive polarity analog voltage is amplified by the first output buffer 41. The first channel 51 is output such that the first channel 51 outputs a positive source control signal.
当需要第一通道51输出负极性的源极控制信号时，正极性的第一信号D1依次通过第一暂存器11和第四暂存器14输入至第二电平转换器22，经第二电平转换器22的电压抬升作用后输入至第二数模转换器32，第二数模转换器32作为一个电压选择功能块，根据第二电平转换器22的输出电压选择所需的负极性的模拟电压(对应灰阶电压)，然后负极性的模拟电压经第二输出缓冲器42放大后从第一通道51输出，从而使第一通道51输出负极性的源极控制信号。When the first channel 51 is required to output a negative source control signal, the positive first signal D1 is sequentially input to the second level shifter 22 through the first register 11 and the fourth register 14 through the first channel The voltage boosting of the two-level converter 22 is input to the second digital-to-analog converter 32, and the second digital-to-analog converter 32 functions as a voltage selection function block, and selects the required voltage according to the output voltage of the second level shifter 22. The negative polarity analog voltage (corresponding to the gray scale voltage) is then amplified by the second output buffer 42 and output from the first channel 51, so that the first channel 51 outputs a negative source control signal.
由上述可知：对于现有技术的源极驱动电路而言，每两个相邻的通道(例如第一通道51和第二通道52)需相对应地设置两个数模转换器(第一数模转换器31和第二数模转换器32)，以满足源极驱动电路的实际动作需求。然而，由于数模转换器的体积较大，所有数模转换器的面积之和约占整个源极驱动电路总面积的60％，因此这将导致用于承载源极驱动电路的芯片的体积无法进一步缩减；另外，随着显示分辨率的增加，显示数据通道必将增多，从而很难在固定的芯片面积上完成更高的解析度。It can be seen from the above that for the prior art source driving circuit, two adjacent digital channels (for example, the first channel 51 and the second channel 52) need to be correspondingly provided with two digital-to-analog converters (the first number) The analog converter 31 and the second digital to analog converter 32) meet the actual operational requirements of the source drive circuit. However, due to the large size of the digital-to-analog converter, the sum of the areas of all the digital-to-analog converters accounts for about 60% of the total area of the entire source drive circuit, so this will result in a volume of the chip for carrying the source drive circuit. Further reduction; in addition, as the display resolution increases, the display data channel is bound to increase, making it difficult to achieve higher resolution on a fixed chip area.
发明内容Summary of the invention
本发明所要解决的技术问题是：现有技术中的源极驱动电路的每两个相邻的通道需相对应地设置两个数模转换器，导致用于承载源极驱动电路的芯片的体积无法进一步缩减，并且很难在固定的芯片面积上完成更高的解析度。The technical problem to be solved by the present invention is that each two adjacent channels of the source driving circuit in the prior art need to be correspondingly provided with two digital-to-analog converters, resulting in the volume of the chip for carrying the source driving circuit. No further reductions, and it is difficult to achieve higher resolution on a fixed chip area.
为了解决上述技术问题，本发明提供了一种液晶显示面板的源极驱动电路。In order to solve the above technical problems, the present invention provides a source driving circuit of a liquid crystal display panel.
本发明的技术方案为：一种源极驱动电路，包括：The technical solution of the present invention is: a source driving circuit, comprising:
相邻设置的第一通道和第二通道；First and second channels disposed adjacent to each other;
相邻设置的第三通道和第四通道；a third channel and a fourth channel disposed adjacent to each other;
通道选择模块及均与所述通道选择模块电连接的移位寄存器、第一倍频器、第二倍频器、第三倍频器和第四倍频器，所述移位寄存器设置为使经第一倍频器倍频的第一信号和经第二倍频器倍频的第二信号在预设的第一时段输入至通道选择模块，并使经第三倍频器倍频的第三信号和经第四倍频器倍频的第四信号在预设的第二时段输入至通道选择模块，第一时段和第二时段的交集为空集；以及a channel selection module and a shift register electrically connected to the channel selection module, a first frequency multiplier, a second frequency multiplier, a third frequency multiplier and a fourth frequency multiplier, the shift register being set such that The first signal multiplied by the first frequency multiplier and the second signal multiplied by the second frequency multiplier are input to the channel selection module in a preset first period, and the frequency multiplied by the third frequency multiplier The three signals and the fourth signal multiplied by the fourth frequency multiplier are input to the channel selection module for a preset second time period, and the intersection of the first time period and the second time period is an empty set;
输出缓冲模块及分别与所述通道选择模块电连接的第一数模转换器和第二数模转换器，所述第一数模转换器经所述输出缓冲模块与第一通道的输出端、第二通道的输出端、 第三通道的输出端和第四通道的输出端电连接，所述第二数模转换器经所述输出缓冲模块与第一通道的输出端、第二通道的输出端、第三通道的输出端和第四通道的输出端电连接。An output buffer module and a first digital-to-analog converter and a second digital-to-analog converter respectively electrically connected to the channel selection module, the first digital-to-analog converter passing through the output buffer module and the output end of the first channel, The output of the second channel, The output of the third channel is electrically connected to the output of the fourth channel, and the output of the second digital-to-analog converter is outputted by the output buffer module and the output of the first channel, the output of the second channel, and the output of the third channel The terminals are electrically connected to the output of the fourth channel.
优选的是，所述第一时段为每个周期的前半个周期，所述第二时段为每个周期的后半个周期。Preferably, the first period is the first half of each period, and the second period is the second half of each period.
优选的是，所述第一数模转换器和第二数模转换器分别为P型数模转换器和N型数模转换器；或者，所述第一数模转换器和第二数模转换器分别为N型数模转换器和P型数模转换器。Preferably, the first digital-to-analog converter and the second digital-to-analog converter are respectively a P-type digital-to-analog converter and an N-type digital-to-analog converter; or the first digital-to-analog converter and the second digital-to-analog The converters are an N-type digital-to-analog converter and a P-type digital-to-analog converter, respectively.
优选的是，所述通道选择模块包括第一暂存器、第二暂存器、第三暂存器、第四暂存器、第五暂存器、第六暂存器、第七暂存器和第八暂存器；Preferably, the channel selection module includes a first temporary register, a second temporary register, a third temporary register, a fourth temporary register, a fifth temporary register, a sixth temporary register, and a seventh temporary storage. And eighth register;
所述第一暂存器分别与移位寄存器、第一倍频器、第三暂存器和第四暂存器电连接；所述第二暂存器分别与移位寄存器、第二倍频器、第三暂存器和第四暂存器电连接；所述第五暂存器分别与移位寄存器、第三倍频器、第七暂存器和第八暂存器电连接；所述第六暂存器分别与移位寄存器、第四倍频器、第七暂存器和第八暂存器电连接；The first register is electrically connected to the shift register, the first frequency multiplier, the third register, and the fourth register; the second register is respectively associated with a shift register and a second frequency multiplier , the third register and the fourth register are electrically connected; the fifth register is electrically connected to the shift register, the third frequency multiplier, the seventh register and the eighth register respectively; The sixth register is electrically connected to the shift register, the fourth frequency multiplier, the seventh register, and the eighth register respectively;
所述第三暂存器和第七暂存器均与所述第一数模转换器电连接；所述第四暂存器和第八暂存器均与所述第二数模转换器电连接。The third register and the seventh register are both electrically connected to the first digital-to-analog converter; the fourth register and the eighth register are both electrically connected to the second digital-to-analog converter connection.
优选的是，所述输出缓冲模块包括第一输出缓冲器、第二输出缓冲器、第三输出缓冲器和第四输出缓冲器；Preferably, the output buffer module includes a first output buffer, a second output buffer, a third output buffer, and a fourth output buffer;
所述第一数模转换器经所述第一输出缓冲器分别与第一通道的输出端和第二通道的输出端电连接；所述第一数模转换器经所述第三输出缓冲器分别与第三通道的输出端和第四通道的输出端电连接；The first digital to analog converter is electrically coupled to an output of the first channel and an output of the second channel via the first output buffer; the first digital to analog converter is coupled to the third output buffer Electrically connected to the output of the third channel and the output of the fourth channel;
所述第二数模转换器经所述第二输出缓冲器分别与第一通道的输出端和第二通道的输出端电连接；所述第二数模转换器经所述第四输出缓冲器分别与第三通道的输出端和第四通道的输出端电连接。The second digital to analog converter is electrically coupled to the output of the first channel and the output of the second channel via the second output buffer; the second digital to analog converter is passed through the fourth output buffer They are electrically connected to the output of the third channel and the output of the fourth channel, respectively.
优选的是，所述源极驱动电路还包括第一电平转换器、第二电平转换器、第三电平转换器和第四电平转换器；Preferably, the source driving circuit further includes a first level shifter, a second level shifter, a third level shifter, and a fourth level shifter;
所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接；所述第七暂存器经所述第三电平转换器与第一数模转换器电连接；所述第八暂存器经所述第四电平转换器与第二数模转换器电连接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter Connecting; the seventh register is electrically connected to the first digital-to-analog converter via the third level shifter; and the eighth register is converted by the fourth level shifter and the second digital-to-analog Electrical connection.
优选的是，所述通道选择模块包括第一暂存器、第二暂存器、第三暂存器、第四暂存器、第五暂存器和第六暂存器； Preferably, the channel selection module includes a first temporary register, a second temporary register, a third temporary register, a fourth temporary register, a fifth temporary register and a sixth temporary register;
所述第一暂存器分别与移位寄存器、第一倍频器、第三暂存器和第四暂存器电连接；所述第二暂存器分别与移位寄存器、第二倍频器、第三暂存器和第四暂存器电连接；所述第五暂存器分别与移位寄存器、第三倍频器、第三暂存器和第四暂存器电连接；所述第六暂存器分别与移位寄存器、第四倍频器、第三暂存器和第四暂存器电连接；The first register is electrically connected to the shift register, the first frequency multiplier, the third register, and the fourth register; the second register is respectively associated with a shift register and a second frequency multiplier , the third register and the fourth register are electrically connected; the fifth register is electrically connected to the shift register, the third frequency multiplier, the third register and the fourth register respectively; The sixth register is electrically connected to the shift register, the fourth frequency multiplier, the third register, and the fourth register, respectively;
所述第三暂存器与所述第一数模转换器电连接；所述第四暂存器与所述第二数模转换器电连接。The third register is electrically connected to the first digital to analog converter; the fourth register is electrically connected to the second digital to analog converter.
优选的是，所述输出缓冲模块包括第一输出缓冲器和第二输出缓冲器；Preferably, the output buffer module includes a first output buffer and a second output buffer;
所述第一数模转换器经所述第一输出缓冲器分别与第一通道的输出端、第二通道的输出端、第三通道的输出端和第四通道的输出端电连接；所述第二数模转换器经所述第二输出缓冲器分别与第一通道的输出端、第二通道的输出端、第三通道的输出端和第四通道的输出端电连接。The first digital-to-analog converter is electrically coupled to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel via the first output buffer; The second digital to analog converter is electrically coupled to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel via the second output buffer, respectively.
优选的是，所述源极驱动电路还包括第一电平转换器和第二电平转换器；Preferably, the source driving circuit further includes a first level shifter and a second level shifter;
所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter connection.
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：One or more of the above aspects may have the following advantages or benefits compared to the prior art:
液晶显示面板的阵列基板的所有源极线控制通道中的至少四个通道由本发明的源极驱动电路来驱动，结合对输入信号进行倍频处理以及分时复用数模转换器的技术手段，能够实现每四个通道共用两个数模转换器，从而有效减少了源极驱动电路中数模转换器的数量，降低了数模转换器所占用的面积和资源，同时也降低了源极驱动电路的成本，有利于进一步缩减用于承载源极驱动电路的芯片的体积，能够在固定的芯片面积上完成更高的解析度。At least four of all source line control channels of the array substrate of the liquid crystal display panel are driven by the source driving circuit of the present invention, combined with a technique of frequency-doubled processing of the input signal and time-multiplexed digital-to-analog converter. It can realize two digital-to-analog converters for every four channels, which effectively reduces the number of digital-to-analog converters in the source driver circuit, reduces the area and resources occupied by the digital-to-analog converter, and reduces the source drive. The cost of the circuit facilitates further reduction of the size of the chip used to carry the source driver circuit, enabling higher resolution over a fixed chip area.
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。Other features and advantages of the present invention will be set forth in the description in the description which follows. The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.
附图说明DRAWINGS
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：The drawings are intended to provide a further understanding of the invention, and are intended to be a part of the description of the invention. In the drawing:
图1示出了现有技术中液晶显示面板的源极驱动电路的示意图；1 is a schematic view showing a source driving circuit of a liquid crystal display panel in the prior art;
图2示出了图1所示的源极驱动电路的输入信号的时序图；2 is a timing chart showing an input signal of the source driving circuit shown in FIG. 1;
图3示出了本发明实施例液晶显示面板的源极驱动电路的一种示意图； 3 is a schematic view showing a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention;
图4示出了图3所示的源极驱动电路的输入信号的时序图；4 is a timing chart showing an input signal of the source driving circuit shown in FIG. 3;
图5示出了本发明实施例液晶显示面板的源极驱动电路的第二种示意图；FIG. 5 is a second schematic diagram showing a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention; FIG.
图6示出了本发明实施例液晶显示面板的源极驱动电路的第三种示意图。FIG. 6 shows a third schematic diagram of a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention.
具体实施方式detailed description
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and embodiments, in which the present invention can be applied to the technical problems, and the implementation of the technical effects can be fully understood and implemented. It should be noted that the various embodiments of the present invention and the various features of the various embodiments may be combined with each other, and the technical solutions formed are all within the scope of the present invention.
本发明要解决的技术问题是：现有技术中的源极驱动电路的每两个相邻的通道需相对应地设置两个数模转换器，导致用于承载源极驱动电路的芯片的体积无法进一步缩减，并且很难在固定的芯片面积上完成更高的解析度。为解决上述技术问题，本发明实施例提供了一种液晶显示面板的源极驱动电路。The technical problem to be solved by the present invention is that two adjacent digital channels of the source driving circuit in the prior art need to be correspondingly provided with two digital-to-analog converters, resulting in the volume of the chip for carrying the source driving circuit. No further reductions, and it is difficult to achieve higher resolution on a fixed chip area. To solve the above technical problem, an embodiment of the present invention provides a source driving circuit of a liquid crystal display panel.
图3示出了本发明实施例液晶显示面板的源极驱动电路的一种示意图。如图3所示，源极驱动电路包括第一通道51、第二通道52、第三通道53、第四通道54、移位寄存器6、第一倍频器71、第二倍频器72、第三倍频器73、第四倍频器74、通道选择模块1、第一数模转换器31、第二数模转换器32和输出缓冲模块4。FIG. 3 is a schematic view showing a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention. As shown in FIG. 3, the source driving circuit includes a first channel 51, a second channel 52, a third channel 53, a fourth channel 54, a shift register 6, a first frequency multiplier 71, a second frequency multiplier 72, The third frequency multiplier 73, the fourth frequency multiplier 74, the channel selection module 1, the first digital to analog converter 31, the second digital to analog converter 32, and the output buffer module 4.
具体地，第一通道51和第二通道52相邻设置，第三通道53与第四通道54相邻设置。在本发明一优选的实施例中，第二通道52与第三通道53相邻设置，即第一通道51、第二通道52、第三通道53和第四通道54顺次设置；或者第四通道54与第一通道51相邻设置，即第三通道53、第四通道54、第一通道51和第二通道52顺次设置。Specifically, the first passage 51 and the second passage 52 are disposed adjacent to each other, and the third passage 53 is disposed adjacent to the fourth passage 54. In a preferred embodiment of the present invention, the second passage 52 is disposed adjacent to the third passage 53, that is, the first passage 51, the second passage 52, the third passage 53 and the fourth passage 54 are sequentially disposed; or the fourth The passage 54 is disposed adjacent to the first passage 51, that is, the third passage 53, the fourth passage 54, the first passage 51, and the second passage 52 are sequentially disposed.
倍频器是使输出信号频率等于输入信号频率整数倍的电路，在本实施例中，第一倍频器71、第二倍频器72、第三倍频器73和第四倍频器74分别一一对应地使第一信号D1、第二信号D2、第三信号D3和第四信号D4的频率增加一倍。例如，如果第一信号D1的频率为60Hz，则经第一倍频器71倍频后的第一信号D1的频率提升至120Hz。输入至第一通道51的第一信号D1(一般为数字信号)经第一倍频器71倍频后输入至通道选择模块1，输入至第二通道52的第二信号D2经第二倍频器72倍频后输入至通道选择模块1，输入至第三通道53的第三信号D3经第三倍频器73的倍频后输入至通道选择模块1，输入至第四通道54的第四信号D4经第四倍频器74倍频后输入至通道选择模块1。由通道选择模块1将倍频后的各个信号分配给第一数模转换器31和第二数模转换器32。The frequency multiplier is a circuit that makes the output signal frequency equal to an integral multiple of the input signal frequency. In the present embodiment, the first frequency multiplier 71, the second frequency multiplier 72, the third frequency multiplier 73, and the fourth frequency multiplier 74 are provided. The frequencies of the first signal D1, the second signal D2, the third signal D3, and the fourth signal D4 are doubled in a one-to-one correspondence, respectively. For example, if the frequency of the first signal D1 is 60 Hz, the frequency of the first signal D1 multiplied by the first frequency multiplier 71 is raised to 120 Hz. The first signal D1 (generally a digital signal) input to the first channel 51 is multiplied by the first frequency multiplier 71 and input to the channel selection module 1, and the second signal D2 input to the second channel 52 is subjected to the second frequency multiplication. The device 72 is multiplied and input to the channel selection module 1. The third signal D3 input to the third channel 53 is input to the channel selection module 1 by the multiplication of the third frequency multiplier 73, and is input to the fourth channel 54. The signal D4 is multiplied by the fourth frequency multiplier 74 and input to the channel selection module 1. The multiplied signals are assigned to the first digital-to-analog converter 31 and the second digital-to-analog converter 32 by the channel selection module 1.
移位寄存器6是控制各个信号输入给第一数模转换器31和第二数模转换器32的时序 的电路。具体地，程序寄存器设置为使经第一倍频器71倍频的第一信号D1和经第二倍频器72倍频的第二信号D2在预设的第一时段输入至通道选择模块1，在第一时段内禁止将经第三倍频器73倍频的第三信号D3和经第四倍频器74倍频的第四信号D4输入至通道选择模块1。程序寄存器还设置为使经第三倍频器73倍频的第三信号D3和经第四倍频器74倍频的第四信号D4在预设的第二时段输入至通道选择模块1，在第二时段内禁止将使经第一倍频器71倍频的第一信号D1和经第二倍频器72倍频的第二信号D2输入至通道选择模块1。这里需要指出的是，预设的第一时段和预设的第二时段的交集为空集，以避免第一信号D1、第二信号D2、第三信号D3和第四信号D4彼此干扰。特别地，移位寄存器6优选为双向移位寄存器。The shift register 6 is a timing for controlling the input of each signal to the first digital-to-analog converter 31 and the second digital-to-analog converter 32. Circuit. Specifically, the program register is set to input the first signal D1 multiplied by the first frequency multiplier 71 and the second signal D2 multiplied by the second frequency multiplier 72 to the channel selection module 1 in a preset first time period. The third signal D3 multiplied by the third frequency multiplier 73 and the fourth signal D4 multiplied by the fourth frequency multiplier 74 are prohibited from being input to the channel selection module 1 during the first time period. The program register is further configured to input the third signal D3 multiplied by the third frequency multiplier 73 and the fourth signal D4 multiplied by the fourth frequency multiplier 74 to the channel selection module 1 for a preset second time period, The first signal D1 multiplied by the first frequency multiplier 71 and the second signal D2 multiplied by the second frequency multiplier 72 are prohibited from being input to the channel selection module 1 during the second period. It should be noted here that the intersection of the preset first time period and the preset second time period is an empty set to prevent the first signal D1, the second signal D2, the third signal D3, and the fourth signal D4 from interfering with each other. In particular, the shift register 6 is preferably a bidirectional shift register.
在本发明一优选的实施例中，参照图4，第一时段优选为每个数据传输周期的前半个周期，而第二时段优选为每个数据传输周期的后半个周期。换言之，对于一个数据传输周期而言，在其前半个周期传输第一信号D1和第二信号D2，在其后半个周期传输第三信号D3和第四信号D4。一般来说，第一信号D1和第二信号D2为互补信号(即当第一信号D1为高电平时，第二信号D2为低电平，反之亦然)，两者能够复用两个数模转换器(即第一数模转换器31和第二数模转换器32)；同样，第三信号D3和第四信号D4也为互补信号(即当第三信号D3为高电平时，第四信号D4为低电平，反之亦然)，由于输入第三信号D3和第四信号D4对应的第二时段与输入第一信号D1和第二信号D2对应的第一时段无交集，因此第三信号D3和第四信号D4也能够复用前述的两个数模转换器(即第一数模转换器31和第二数模转换器32)，从而实现了仅依靠两个数模转换器即可完成四个通道的信号输入。这里，四个通道的信号输入指的是第一通道51的信号输入、第二通道52的信号输入、第三通道53的信号输入和第四通道54的信号输入。In a preferred embodiment of the present invention, referring to FIG. 4, the first time period is preferably the first half of each data transmission period, and the second time period is preferably the second half of each data transmission period. In other words, for one data transmission period, the first signal D1 and the second signal D2 are transmitted in the first half of the period, and the third signal D3 and the fourth signal D4 are transmitted in the second half of the period. Generally, the first signal D1 and the second signal D2 are complementary signals (ie, when the first signal D1 is at a high level, the second signal D2 is at a low level, and vice versa), and the two can multiplex two numbers. The analog-to-digital converter (ie, the first digital-to-analog converter 31 and the second digital-to-analog converter 32); likewise, the third signal D3 and the fourth signal D4 are also complementary signals (ie, when the third signal D3 is at a high level, The fourth signal D4 is at a low level, and vice versa. Since the second period corresponding to the input third signal D3 and the fourth signal D4 has no intersection with the first period corresponding to the input first signal D1 and the second signal D2, The three signals D3 and the fourth signal D4 can also multiplex the two digital-to-analog converters (ie, the first digital-to-analog converter 31 and the second digital-to-analog converter 32), thereby implementing only two digital-to-analog converters. The signal input of the four channels can be completed. Here, the signal input of the four channels refers to the signal input of the first channel 51, the signal input of the second channel 52, the signal input of the third channel 53, and the signal input of the fourth channel 54.
另外，第一数模转换器31和第二数模转换器32经输出缓冲模块4分别与第一通道51的输出端、第二通道52的输出端、第三通道53的输出端和第四通道54的输出端电连接，输出缓冲模块4用于对第一数模转换器31的输出信号进行放大，并将经放大的信号分别输出至第一通道51的输出端、第二通道52的输出端、第三通道53的输出端和第四通道54的输出端；输出缓冲模块4还用于对第二数模转换器32的输出信号进行放大，并将经放大的信号分别输出至第一通道51的输出端、第二通道52的输出端、第三通道53的输出端和第四通道54的输出端。In addition, the first digital-to-analog converter 31 and the second digital-to-analog converter 32 pass through the output buffer module 4 with the output end of the first channel 51, the output end of the second channel 52, the output end of the third channel 53, and the fourth. The output end of the channel 54 is electrically connected, and the output buffer module 4 is configured to amplify the output signal of the first digital-to-analog converter 31, and output the amplified signals to the output end of the first channel 51 and the second channel 52, respectively. The output end, the output end of the third channel 53 and the output end of the fourth channel 54; the output buffer module 4 is further configured to amplify the output signal of the second digital-to-analog converter 32, and output the amplified signals to the first The output of one channel 51, the output of second channel 52, the output of third channel 53, and the output of fourth channel 54.
在本实施例中，液晶显示面板的阵列基板的所有源极线控制通道中的至少四个通道由本实施例所述的源极驱动电路来驱动，结合对输入信号进行倍频处理以及分时复用数模转换器的技术手段，能够实现每四个通道共用两个数模转换器，从而有效减少了源极驱动电 路中数模转换器的数量，降低了数模转换器所占用的面积和资源，同时也降低了源极驱动电路的成本，有利于进一步缩减用于承载源极驱动电路的芯片的体积，能够在固定的芯片面积上完成更高的解析度。In this embodiment, at least four channels of all the source line control channels of the array substrate of the liquid crystal display panel are driven by the source driving circuit described in this embodiment, and combined with frequency doubling processing and time division multiplexing of the input signal. Using digital-to-analog converter technology, it can realize two digital-to-analog converters for every four channels, thus effectively reducing the source drive power. The number of digital-to-analog converters in the circuit reduces the area and resources occupied by the digital-to-analog converter, and also reduces the cost of the source driving circuit, which is advantageous for further reducing the size of the chip for carrying the source driving circuit. A higher resolution is achieved over a fixed chip area.
需要指出的是，在上述实施例中，由第一通道51和第二通道52组成的通道对与由第三通道53和第四通道54组成的通道对可以相邻设置，也可以间隔设置，第一通道51、第二通道52、第三通道53和第四通道54构成一个通道组合。It should be noted that, in the above embodiment, the channel pair composed of the first channel 51 and the second channel 52 and the channel pair composed of the third channel 53 and the fourth channel 54 may be adjacently disposed, or may be spaced apart. The first channel 51, the second channel 52, the third channel 53, and the fourth channel 54 constitute a channel combination.
在本发明一优选的实施例中，对于液晶显示面板的阵列基板的所有源极线控制通道，将所有通道划分成多个通道组合，并使每个通道组合的源极驱动电路与图3所示的源极驱动电路的电路结构相同。为方便阐述本实施例所述的源极驱动电路的驱动方法，将阵列基板的所有通道顺次划分成第一通道对(具有相邻设置的第一通道51和第二通道52)、第二通道对(具有相邻设置的第三通道53和第四通道54，第二通道52与第三通道53相邻设置)、第三通道对、第四通道对、第五通道对和第六通道对，…。这样，对应本实施例所述的源极驱动电路的驱动方法包括：由于输入数字信号的频率加倍，在预设的第一时段输入奇数对通道对的视频数据(即第一通道对、第三通道对、第五通道对、第七通道对…的视频数据)，此时禁止输入偶数对通道对的视频数据(即在第一时段内禁止输入第二通道对、第四通道对、第六通道对、第八通道对…的视频数据)。在预设的第二时段(第二时段与第一时段无交集，即第二时段与第一时段的交集为空集)输入偶数对通道的视频数据(即第二通道对、第四通道对、第六通道对、第八通道对…的视频数据)，此时禁止输入奇数对通道对的视频数据(即在第二时段内禁止输入第一通道对、第三通道对、第五通道对、第七通道对…的视频数据)。采用上述源极驱动电路及相应的驱动方法，即可实现每四个通道复用两个数模转换器的设计，从而能够使源极驱动电路中数模转换器的数量减半，大大降低了数模转换器所占用的面积和资源，同时也大大降低了源极驱动电路的成本，特别有利于进一步缩减用于承载源极驱动电路的芯片的体积，能够在固定的芯片面积上完成更高的解析度。In a preferred embodiment of the present invention, all the source line control channels of the array substrate of the liquid crystal display panel are divided into a plurality of channel combinations, and the source driving circuit of each channel combination is combined with FIG. The circuit structure of the illustrated source driver circuit is the same. To facilitate the description of the driving method of the source driving circuit according to the embodiment, all the channels of the array substrate are sequentially divided into a first channel pair (having adjacent first channel 51 and second channel 52) and a second a pair of channels (having a third channel 53 and a fourth channel 54 disposed adjacently, a second channel 52 disposed adjacent to the third channel 53), a third channel pair, a fourth channel pair, a fifth channel pair, and a sixth channel Correct,…. In this way, the driving method of the source driving circuit corresponding to the embodiment includes: inputting the video data of the odd pair of channel pairs in the preset first time period due to the doubling of the frequency of the input digital signal (ie, the first channel pair, the third channel) Channel data of the channel pair, the fifth channel pair, and the seventh channel pair. At this time, it is forbidden to input the video data of the even pair of channel pairs (ie, prohibiting the input of the second channel pair, the fourth channel pair, and the sixth in the first time period) Channel pair, eighth channel pair... video data). Inputting the video data of the even-numbered pair of channels (ie, the second channel pair and the fourth channel pair) in the preset second time period (the second time period has no intersection with the first time period, that is, the intersection of the second time period and the first time period is an empty set) , the sixth channel pair, the eighth channel pair ... video data), at this time, it is forbidden to input the video data of the odd pair of channel pairs (ie, the first channel pair, the third channel pair, and the fifth channel pair are prohibited from being input in the second time period) , the seventh channel to ... video data). By adopting the above-mentioned source driving circuit and corresponding driving method, the design of multiplexing two digital-to-analog converters for every four channels can be realized, thereby halving the number of digital-to-analog converters in the source driving circuit, thereby greatly reducing the number of digital-to-analog converters in the source driving circuit. The area and resources occupied by the digital-to-analog converter also greatly reduce the cost of the source driving circuit, and are particularly advantageous for further reducing the size of the chip for carrying the source driving circuit, and being able to complete higher on a fixed chip area. Resolution.
进一步地，第一数模转换器31和第二数模转换器32可以均采用由CMOS形成的数模转换器结构，也可以优选地采用由PMOS单管形成的P型数模转换器结构或者由NMOS单管形成的N型数模转换器结构，即第一数模转换器31和第二数模转换器32分别为P型数模转换器和N型数模转换器；或者第一数模转换器31和第二数模转换器32分别为N型数模转换器和P型数模转换器。由于P型数模转换器或者N型数模转换器的面积要远小于由CMOS形成的数模转换器的面积，因此采用本实施例进一步地降低了数模转换器所占用的面积和资源，同时也进一步降低了源极驱动电路的成本，有利于进一步缩减用 于承载源极驱动电路的芯片的体积，能够在固定的芯片面积上完成更高的解析度。Further, the first digital-to-analog converter 31 and the second digital-to-analog converter 32 may each adopt a digital-to-analog converter structure formed of CMOS, or may preferably adopt a P-type digital-to-analog converter structure formed of a PMOS single tube or The N-type digital-to-analog converter structure formed by the NMOS single-tube, that is, the first digital-to-analog converter 31 and the second digital-to-analog converter 32 are respectively a P-type digital-to-analog converter and an N-type digital-to-analog converter; or the first number The mode converter 31 and the second digital-to-analog converter 32 are an N-type digital-to-analog converter and a P-type digital-to-analog converter, respectively. Since the area of the P-type digital-to-analog converter or the N-type digital-to-analog converter is much smaller than the area of the digital-to-analog converter formed by CMOS, the area and resources occupied by the digital-to-analog converter are further reduced by the embodiment. At the same time, the cost of the source driving circuit is further reduced, which is beneficial for further reduction. The volume of the chip carrying the source driving circuit can achieve a higher resolution on a fixed chip area.
下面结合图5和图6，分别给出液晶显示面板的源极驱动电路的第二种示意图和第三种示意图。图5和图6所示的源极驱动电路的输入信号的时序图均如图4所示。Next, a second schematic diagram and a third schematic diagram of the source driving circuit of the liquid crystal display panel are respectively given in conjunction with FIG. 5 and FIG. The timing charts of the input signals of the source driving circuits shown in FIGS. 5 and 6 are as shown in FIG.
图5示出了本发明实施例液晶显示面板的源极驱动电路的第二种示意图。如图5所示，通道选择模块1包括第一暂存器11、第二暂存器12、第三暂存器13、第四暂存器14、第五暂存器15、第六暂存器16、第七暂存器17和第八暂存器18。FIG. 5 is a second schematic diagram showing a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention. As shown in FIG. 5, the channel selection module 1 includes a first temporary storage unit 11, a second temporary storage unit 12, a third temporary storage unit 13, a fourth temporary storage unit 14, a fifth temporary storage unit 15, and a sixth temporary storage unit. The sixth register, the seventh register 17 and the eighth register 18.
具体地，第一暂存器11分别与移位寄存器6、第一倍频器71、第三暂存器13和第四暂存器14电连接；第二暂存器12分别与移位寄存器6、第二倍频器72、第三暂存器13和第四暂存器14电连接；第五暂存器15分别与移位寄存器6、第三倍频器73、第七暂存器17和第八暂存器18电连接；第六暂存器16分别与移位寄存器6、第四倍频器74、第七暂存器17和第八暂存器18电连接。第三暂存器13和第七暂存器17均与第一数模转换器31电连接；第四暂存器14和第八暂存器18均与第二数模转换器32电连接。Specifically, the first register 11 is electrically connected to the shift register 6, the first frequency multiplier 71, the third register 13 and the fourth register 14, respectively; the second register 12 and the shift register respectively 6. The second frequency multiplier 72, the third temporary register 13 and the fourth temporary register 14 are electrically connected; the fifth temporary register 15 is respectively connected to the shift register 6, the third frequency multiplier 73, and the seventh temporary register 17 and the eighth register 18 are electrically connected; the sixth register 16 is electrically connected to the shift register 6, the fourth frequency multiplier 74, the seventh register 17, and the eighth register 18, respectively. The third register 13 and the seventh register 17 are both electrically connected to the first digital-to-analog converter 31; the fourth register 14 and the eighth register 18 are both electrically connected to the second digital-to-analog converter 32.
特别地，输出缓冲模块4包括第一输出缓冲器41、第二输出缓冲器42、第三输出缓冲器43和第四输出缓冲器44。In particular, the output buffer module 4 includes a first output buffer 41, a second output buffer 42, a third output buffer 43, and a fourth output buffer 44.
具体地，第一数模转换器31经第一输出缓冲器41分别与第一通道51的输出端和第二通道52的输出端电连接；第一数模转换器31经第三输出缓冲器43分别与第三通道53的输出端和第四通道54的输出端电连接；Specifically, the first digital-to-analog converter 31 is electrically connected to the output end of the first channel 51 and the output end of the second channel 52 via the first output buffer 41; the first digital-to-analog converter 31 passes through the third output buffer. 43 is electrically connected to the output end of the third channel 53 and the output end of the fourth channel 54, respectively;
第二数模转换器32经第二输出缓冲器42分别与第一通道51的输出端和第二通道52的输出端电连接；第二数模转换器32经第四输出缓冲器44分别与第三通道53的输出端和第四通道54的输出端电连接。The second digital-to-analog converter 32 is electrically coupled to the output of the first channel 51 and the output of the second channel 52 via the second output buffer 42; the second digital-to-analog converter 32 is coupled to the fourth output buffer 44 via the fourth output buffer 44, respectively. The output of the third channel 53 is electrically coupled to the output of the fourth channel 54.
另外，参照图5，源极驱动电路还包括第一电平转换器21、第二电平转换器22、第三电平转换器23和第四电平转换器24，以对倍频处理后的信号进行电压抬升。第三暂存器13经第一电平转换器21与第一数模转换器31电连接；第四暂存器14经第二电平转换器22与第二数模转换器32电连接；第七暂存器17经第三电平转换器23与第一数模转换器31电连接；第八暂存器18经第四电平转换器24与第二数模转换器32电连接。In addition, referring to FIG. 5, the source driving circuit further includes a first level shifter 21, a second level shifter 22, a third level shifter 23, and a fourth level shifter 24 to process the frequency doubling. The signal is voltage boosted. The third register 13 is electrically connected to the first digital-to-analog converter 31 via the first level shifter 21; the fourth register 14 is electrically connected to the second digital-to-analog converter 32 via the second level shifter 22; The seventh register 17 is electrically coupled to the first digital to analog converter 31 via a third level shifter 23; the eighth register 18 is electrically coupled to the second digital to analog converter 32 via a fourth level shifter 24.
图6示出了本发明实施例液晶显示面板的源极驱动电路的第三种示意图。如图6所示，通道选择模块1包括第一暂存器11、第二暂存器12、第三暂存器13、第四暂存器14、第五暂存器15和第六暂存器16。FIG. 6 shows a third schematic diagram of a source driving circuit of a liquid crystal display panel according to an embodiment of the present invention. As shown in FIG. 6, the channel selection module 1 includes a first temporary storage unit 11, a second temporary storage unit 12, a third temporary storage unit 13, a fourth temporary storage unit 14, a fifth temporary storage unit 15, and a sixth temporary storage unit. 16.
具体地，第一暂存器11分别与移位寄存器6、第一倍频器71、第三暂存器13和第四暂存器14电连接；第二暂存器12分别与移位寄存器6、第二倍频器72、第三暂存器13和第四暂存器14电连接；第五暂存器15分别与移位寄存器6、第三倍频器73、第三暂存 器13和第四暂存器14电连接；第六暂存器16分别与移位寄存器6、第四倍频器74、第三暂存器13和第四暂存器14电连接。第三暂存器13与第一数模转换器31电连接；第四暂存器14与第二数模转换器32电连接。Specifically, the first register 11 is electrically connected to the shift register 6, the first frequency multiplier 71, the third register 13 and the fourth register 14, respectively; the second register 12 and the shift register respectively 6. The second frequency multiplier 72, the third temporary register 13 and the fourth temporary register 14 are electrically connected; the fifth temporary register 15 is respectively connected to the shift register 6, the third frequency multiplier 73, and the third temporary storage. The third register 16 is electrically connected to the fourth register 14; the sixth register 16 is electrically connected to the shift register 6, the fourth frequency multiplier 74, the third register 13 and the fourth register 14, respectively. The third register 13 is electrically connected to the first digital-to-analog converter 31; the fourth register 14 is electrically connected to the second digital-to-analog converter 32.
进一步地，输出缓冲模块4包括第一输出缓冲器41和第二输出缓冲器42。Further, the output buffer module 4 includes a first output buffer 41 and a second output buffer 42.
具体地，第一数模转换器31经第一输出缓冲器41分别与第一通道51的输出端、第二通道52的输出端、第三通道53的输出端和第四通道54的输出端电连接；第二数模转换器32经第二输出缓冲器42分别与第一通道51的输出端、第二通道52的输出端、第三通道53的输出端和第四通道54的输出端电连接。Specifically, the first digital-to-analog converter 31 passes through the first output buffer 41 with the output of the first channel 51, the output of the second channel 52, the output of the third channel 53, and the output of the fourth channel 54, respectively. Electrically coupled; the second digital to analog converter 32 is coupled to the output of the first channel 51, the output of the second channel 52, the output of the third channel 53, and the output of the fourth channel 54 via the second output buffer 42 Electrical connection.
另外，参照图6，源极驱动电路还包括第一电平转换器21和第二电平转换器22。第三暂存器13经第一电平转换器21与第一数模转换器31电连接；第四暂存器14经第二电平转换器22与第二数模转换器32电连接。In addition, referring to FIG. 6, the source driving circuit further includes a first level shifter 21 and a second level shifter 22. The third register 13 is electrically connected to the first digital-to-analog converter 31 via the first level shifter 21; the fourth register 14 is electrically connected to the second digital-to-analog converter 32 via the second level shifter 22.
值得注意的是，当频率足够高时，本发明不仅能实现相邻的四个通道复用两个数模转换器，还可拓展成相邻的八个通道复用两个数模转换器，理想中极致情况是当处理速度允许的情况下频率达到极致，这样就可以将全部通道都复用两个数模转换器来完成源极的驱动，这样能将源极驱动电路中数模转换器的数量降低到最小，并使源极驱动电路的面积降到最小、成本降到最低。It should be noted that when the frequency is sufficiently high, the present invention can not only realize the multiplexing of two digital-to-analog converters in four adjacent channels, but also expand into two adjacent digital channels to multiplex two digital-to-analog converters. In the ideal case, the frequency is maximized when the processing speed allows, so that all the channels can be multiplexed with two digital-to-analog converters to complete the source driving, so that the digital-to-analog converter in the source driving circuit can be realized. The number is minimized and the area of the source driver circuit is minimized and the cost is minimized.
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的保护范围，仍须以所附的权利要求书所界定的范围为准。 While the embodiments of the present invention have been described above, the described embodiments are merely illustrative of the embodiments of the invention and are not intended to limit the invention. Any modification and variation of the form and details of the embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, but the scope of protection of the present invention remains It is subject to the scope defined by the appended claims.

Claims (20)

  1. 一种源极驱动电路，包括：A source driving circuit includes:
    相邻设置的第一通道和第二通道；First and second channels disposed adjacent to each other;
    相邻设置的第三通道和第四通道；a third channel and a fourth channel disposed adjacent to each other;
    通道选择模块及均与所述通道选择模块电连接的移位寄存器、第一倍频器、第二倍频器、第三倍频器和第四倍频器，所述移位寄存器设置为使经第一倍频器倍频的第一信号和经第二倍频器倍频的第二信号在预设的第一时段输入至通道选择模块，并使经第三倍频器倍频的第三信号和经第四倍频器倍频的第四信号在预设的第二时段输入至通道选择模块，第一时段和第二时段的交集为空集；以及a channel selection module and a shift register electrically connected to the channel selection module, a first frequency multiplier, a second frequency multiplier, a third frequency multiplier and a fourth frequency multiplier, the shift register being set such that The first signal multiplied by the first frequency multiplier and the second signal multiplied by the second frequency multiplier are input to the channel selection module in a preset first period, and the frequency multiplied by the third frequency multiplier The three signals and the fourth signal multiplied by the fourth frequency multiplier are input to the channel selection module for a preset second time period, and the intersection of the first time period and the second time period is an empty set;
    输出缓冲模块及分别与所述通道选择模块电连接的第一数模转换器和第二数模转换器，所述第一数模转换器和第二数模转换器分别经所述输出缓冲模块与第一通道的输出端、第二通道的输出端、第三通道的输出端和第四通道的输出端电连接。An output buffer module and a first digital to analog converter and a second digital to analog converter respectively electrically connected to the channel selection module, wherein the first digital to analog converter and the second digital to analog converter respectively pass through the output buffer module It is electrically connected to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel.
  2. 根据权利要求1所述的源极驱动电路，其中，所述第一时段为每个周期的前半个周期，所述第二时段为每个周期的后半个周期。The source driving circuit according to claim 1, wherein said first period is a first half of each period, and said second period is a second half of each period.
  3. 根据权利要求1所述的源极驱动电路，其中，所述第一数模转换器和第二数模转换器分别为P型数模转换器和N型数模转换器；或者，所述第一数模转换器和第二数模转换器分别为N型数模转换器和P型数模转换器。The source driver circuit according to claim 1, wherein the first digital-to-analog converter and the second digital-to-analog converter are a P-type digital-to-analog converter and an N-type digital-to-analog converter, respectively; or A digital-to-analog converter and a second digital-to-analog converter are respectively an N-type digital-to-analog converter and a P-type digital-to-analog converter.
  4. 根据权利要求3所述的源极驱动电路，其中，所述通道选择模块包括第一暂存器、第二暂存器、第三暂存器、第四暂存器、第五暂存器、第六暂存器、第七暂存器和第八暂存器；The source driver circuit of claim 3, wherein the channel selection module comprises a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, and an eighth register;
    所述第一暂存器分别与移位寄存器、第一倍频器、第三暂存器和第四暂存器电连接；所述第二暂存器分别与移位寄存器、第二倍频器、第三暂存器和第四暂存器电连接；所述第五暂存器分别与移位寄存器、第三倍频器、第七暂存器和第八暂存器电连接；所述第六暂存器分别与移位寄存器、第四倍频器、第七暂存器和第八暂存器电连接；The first register is electrically connected to the shift register, the first frequency multiplier, the third register, and the fourth register; the second register is respectively associated with a shift register and a second frequency multiplier , the third register and the fourth register are electrically connected; the fifth register is electrically connected to the shift register, the third frequency multiplier, the seventh register and the eighth register respectively; The sixth register is electrically connected to the shift register, the fourth frequency multiplier, the seventh register, and the eighth register respectively;
    所述第三暂存器和第七暂存器均与所述第一数模转换器电连接；所述第四暂存器和第八暂存器均与所述第二数模转换器电连接。The third register and the seventh register are both electrically connected to the first digital-to-analog converter; the fourth register and the eighth register are both electrically connected to the second digital-to-analog converter connection.
  5. 根据权利要求4所述的源极驱动电路，其中，所述源极驱动电路还包括第一电平转换器、第二电平转换器、第三电平转换器和第四电平转换器；The source driving circuit according to claim 4, wherein said source driving circuit further comprises a first level shifter, a second level shifter, a third level shifter, and a fourth level shifter;
    所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接；所述第七暂存器经所述第三电平转换器与第一数模转换器电连接；所述第八暂存器经所述第四电平转换器与第二数模转换器电连 接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter Connecting; the seventh register is electrically connected to the first digital-to-analog converter via the third level shifter; and the eighth register is converted by the fourth level shifter and the second digital-to-analog Electrical connection Pick up.
  6. 根据权利要求4所述的源极驱动电路，其中，所述输出缓冲模块包括第一输出缓冲器、第二输出缓冲器、第三输出缓冲器和第四输出缓冲器；The source driver circuit of claim 4, wherein the output buffer module comprises a first output buffer, a second output buffer, a third output buffer, and a fourth output buffer;
    所述第一数模转换器经所述第一输出缓冲器分别与第一通道的输出端和第二通道的输出端电连接；所述第一数模转换器经所述第三输出缓冲器分别与第三通道的输出端和第四通道的输出端电连接；The first digital to analog converter is electrically coupled to an output of the first channel and an output of the second channel via the first output buffer; the first digital to analog converter is coupled to the third output buffer Electrically connected to the output of the third channel and the output of the fourth channel;
    所述第二数模转换器经所述第二输出缓冲器分别与第一通道的输出端和第二通道的输出端电连接；所述第二数模转换器经所述第四输出缓冲器分别与第三通道的输出端和第四通道的输出端电连接。The second digital to analog converter is electrically coupled to the output of the first channel and the output of the second channel via the second output buffer; the second digital to analog converter is passed through the fourth output buffer They are electrically connected to the output of the third channel and the output of the fourth channel, respectively.
  7. 根据权利要求6所述的源极驱动电路，其中，所述源极驱动电路还包括第一电平转换器、第二电平转换器、第三电平转换器和第四电平转换器；The source driving circuit according to claim 6, wherein said source driving circuit further comprises a first level shifter, a second level shifter, a third level shifter, and a fourth level shifter;
    所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接；所述第七暂存器经所述第三电平转换器与第一数模转换器电连接；所述第八暂存器经所述第四电平转换器与第二数模转换器电连接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter Connecting; the seventh register is electrically connected to the first digital-to-analog converter via the third level shifter; and the eighth register is converted by the fourth level shifter and the second digital-to-analog Electrical connection.
  8. 根据权利要求3所述的源极驱动电路，其中，所述通道选择模块包括第一暂存器、第二暂存器、第三暂存器、第四暂存器、第五暂存器和第六暂存器；The source driver circuit of claim 3, wherein the channel selection module comprises a first register, a second register, a third register, a fourth register, a fifth register, and Sixth register;
    所述第一暂存器分别与移位寄存器、第一倍频器、第三暂存器和第四暂存器电连接；所述第二暂存器分别与移位寄存器、第二倍频器、第三暂存器和第四暂存器电连接；所述第五暂存器分别与移位寄存器、第三倍频器、第三暂存器和第四暂存器电连接；所述第六暂存器分别与移位寄存器、第四倍频器、第三暂存器和第四暂存器电连接；The first register is electrically connected to the shift register, the first frequency multiplier, the third register, and the fourth register; the second register is respectively associated with a shift register and a second frequency multiplier , the third register and the fourth register are electrically connected; the fifth register is electrically connected to the shift register, the third frequency multiplier, the third register and the fourth register respectively; The sixth register is electrically connected to the shift register, the fourth frequency multiplier, the third register, and the fourth register, respectively;
    所述第三暂存器与所述第一数模转换器电连接；所述第四暂存器与所述第二数模转换器电连接。The third register is electrically connected to the first digital to analog converter; the fourth register is electrically connected to the second digital to analog converter.
  9. 根据权利要求8所述的源极驱动电路，其中，所述源极驱动电路还包括第一电平转换器和第二电平转换器；The source driver circuit of claim 8, wherein the source driver circuit further comprises a first level shifter and a second level shifter;
    所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter connection.
  10. 根据权利要求8所述的源极驱动电路，其中，所述输出缓冲模块包括第一输出缓冲器和第二输出缓冲器；The source driver circuit of claim 8, wherein the output buffer module comprises a first output buffer and a second output buffer;
    所述第一数模转换器经所述第一输出缓冲器分别与第一通道的输出端、第二通道的输出端、第三通道的输出端和第四通道的输出端电连接；所述第二数模转换器经所述第二输 出缓冲器分别与第一通道的输出端、第二通道的输出端、第三通道的输出端和第四通道的输出端电连接。The first digital-to-analog converter is electrically coupled to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel via the first output buffer; a second digital to analog converter via the second input The output buffers are electrically coupled to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel, respectively.
  11. 根据权利要求10所述的源极驱动电路，其中，所述源极驱动电路还包括第一电平转换器和第二电平转换器；The source driving circuit according to claim 10, wherein said source driving circuit further comprises a first level shifter and a second level shifter;
    所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter connection.
  12. 根据权利要求2所述的源极驱动电路，其中，所述第一数模转换器和第二数模转换器分别为P型数模转换器和N型数模转换器；或者，所述第一数模转换器和第二数模转换器分别为N型数模转换器和P型数模转换器。The source driving circuit according to claim 2, wherein said first digital-to-analog converter and said second digital-to-analog converter are respectively a P-type digital-to-analog converter and an N-type digital-to-analog converter; or A digital-to-analog converter and a second digital-to-analog converter are respectively an N-type digital-to-analog converter and a P-type digital-to-analog converter.
  13. 根据权利要求12所述的源极驱动电路，其中，所述通道选择模块包括第一暂存器、第二暂存器、第三暂存器、第四暂存器、第五暂存器、第六暂存器、第七暂存器和第八暂存器；The source driving circuit of claim 12, wherein the channel selection module comprises a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, and an eighth register;
    所述第一暂存器分别与移位寄存器、第一倍频器、第三暂存器和第四暂存器电连接；所述第二暂存器分别与移位寄存器、第二倍频器、第三暂存器和第四暂存器电连接；所述第五暂存器分别与移位寄存器、第三倍频器、第七暂存器和第八暂存器电连接；所述第六暂存器分别与移位寄存器、第四倍频器、第七暂存器和第八暂存器电连接；The first register is electrically connected to the shift register, the first frequency multiplier, the third register, and the fourth register; the second register is respectively associated with a shift register and a second frequency multiplier , the third register and the fourth register are electrically connected; the fifth register is electrically connected to the shift register, the third frequency multiplier, the seventh register and the eighth register respectively; The sixth register is electrically connected to the shift register, the fourth frequency multiplier, the seventh register, and the eighth register respectively;
    所述第三暂存器和第七暂存器均与所述第一数模转换器电连接；所述第四暂存器和第八暂存器均与所述第二数模转换器电连接。The third register and the seventh register are both electrically connected to the first digital-to-analog converter; the fourth register and the eighth register are both electrically connected to the second digital-to-analog converter connection.
  14. 根据权利要求13所述的源极驱动电路，其中，所述源极驱动电路还包括第一电平转换器、第二电平转换器、第三电平转换器和第四电平转换器；The source driving circuit according to claim 13, wherein said source driving circuit further comprises a first level shifter, a second level shifter, a third level shifter, and a fourth level shifter;
    所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接；所述第七暂存器经所述第三电平转换器与第一数模转换器电连接；所述第八暂存器经所述第四电平转换器与第二数模转换器电连接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter Connecting; the seventh register is electrically connected to the first digital-to-analog converter via the third level shifter; and the eighth register is converted by the fourth level shifter and the second digital-to-analog Electrical connection.
  15. 根据权利要求13所述的源极驱动电路，其中，所述输出缓冲模块包括第一输出缓冲器、第二输出缓冲器、第三输出缓冲器和第四输出缓冲器；The source driver circuit of claim 13, wherein the output buffer module comprises a first output buffer, a second output buffer, a third output buffer, and a fourth output buffer;
    所述第一数模转换器经所述第一输出缓冲器分别与第一通道的输出端和第二通道的输出端电连接；所述第一数模转换器经所述第三输出缓冲器分别与第三通道的输出端和第四通道的输出端电连接；The first digital to analog converter is electrically coupled to an output of the first channel and an output of the second channel via the first output buffer; the first digital to analog converter is coupled to the third output buffer Electrically connected to the output of the third channel and the output of the fourth channel;
    所述第二数模转换器经所述第二输出缓冲器分别与第一通道的输出端和第二通道的输出端电连接；所述第二数模转换器经所述第四输出缓冲器分别与第三通道的输出端和第 四通道的输出端电连接。The second digital to analog converter is electrically coupled to the output of the first channel and the output of the second channel via the second output buffer; the second digital to analog converter is passed through the fourth output buffer Separately with the output of the third channel and The four-channel output is electrically connected.
  16. 根据权利要求15所述的源极驱动电路，其中，所述源极驱动电路还包括第一电平转换器、第二电平转换器、第三电平转换器和第四电平转换器；The source driving circuit according to claim 15, wherein said source driving circuit further comprises a first level shifter, a second level shifter, a third level shifter, and a fourth level shifter;
    所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接；所述第七暂存器经所述第三电平转换器与第一数模转换器电连接；所述第八暂存器经所述第四电平转换器与第二数模转换器电连接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter Connecting; the seventh register is electrically connected to the first digital-to-analog converter via the third level shifter; and the eighth register is converted by the fourth level shifter and the second digital-to-analog Electrical connection.
  17. 根据权利要求12所述的源极驱动电路，其中，所述通道选择模块包括第一暂存器、第二暂存器、第三暂存器、第四暂存器、第五暂存器和第六暂存器；The source driver circuit of claim 12, wherein the channel selection module comprises a first register, a second register, a third register, a fourth register, a fifth register, and Sixth register;
    所述第一暂存器分别与移位寄存器、第一倍频器、第三暂存器和第四暂存器电连接；所述第二暂存器分别与移位寄存器、第二倍频器、第三暂存器和第四暂存器电连接；所述第五暂存器分别与移位寄存器、第三倍频器、第三暂存器和第四暂存器电连接；所述第六暂存器分别与移位寄存器、第四倍频器、第三暂存器和第四暂存器电连接；The first register is electrically connected to the shift register, the first frequency multiplier, the third register, and the fourth register; the second register is respectively associated with a shift register and a second frequency multiplier , the third register and the fourth register are electrically connected; the fifth register is electrically connected to the shift register, the third frequency multiplier, the third register and the fourth register respectively; The sixth register is electrically connected to the shift register, the fourth frequency multiplier, the third register, and the fourth register, respectively;
    所述第三暂存器与所述第一数模转换器电连接；所述第四暂存器与所述第二数模转换器电连接。The third register is electrically connected to the first digital to analog converter; the fourth register is electrically connected to the second digital to analog converter.
  18. 根据权利要求17所述的源极驱动电路，其中，所述源极驱动电路还包括第一电平转换器和第二电平转换器；The source driver circuit of claim 17, wherein the source driver circuit further comprises a first level shifter and a second level shifter;
    所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接。The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter connection.
  19. 根据权利要求17所述的源极驱动电路，其中，所述输出缓冲模块包括第一输出缓冲器和第二输出缓冲器；The source driver circuit of claim 17, wherein the output buffer module comprises a first output buffer and a second output buffer;
    所述第一数模转换器经所述第一输出缓冲器分别与第一通道的输出端、第二通道的输出端、第三通道的输出端和第四通道的输出端电连接；所述第二数模转换器经所述第二输出缓冲器分别与第一通道的输出端、第二通道的输出端、第三通道的输出端和第四通道的输出端电连接。The first digital-to-analog converter is electrically coupled to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel via the first output buffer; The second digital to analog converter is electrically coupled to the output of the first channel, the output of the second channel, the output of the third channel, and the output of the fourth channel via the second output buffer, respectively.
  20. 根据权利要求19所述的源极驱动电路，其中，所述源极驱动电路还包括第一电平转换器和第二电平转换器；The source driving circuit according to claim 19, wherein said source driving circuit further comprises a first level shifter and a second level shifter;
    所述第三暂存器经所述第一电平转换器与第一数模转换器电连接；所述第四暂存器经所述第二电平转换器与第二数模转换器电连接。 The third register is electrically connected to the first digital-to-analog converter via the first level shifter; the fourth register is electrically connected to the second level shifter and the second digital-to-analog converter connection.
PCT/CN2015/074458 2015-02-04 2015-03-18 Source drive circuit WO2016123840A1 (en)

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