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WO2016119467A1 - 驱动电路及其驱动方法、显示装置 - Google Patents

驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2016119467A1
WO2016119467A1 PCT/CN2015/089759 CN2015089759W WO2016119467A1 WO 2016119467 A1 WO2016119467 A1 WO 2016119467A1 CN 2015089759 W CN2015089759 W CN 2015089759W WO 2016119467 A1 WO2016119467 A1 WO 2016119467A1
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WIPO (PCT)
Prior art keywords
clock signal
driver
data signal
signal
timing
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PCT/CN2015/089759
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English (en)
French (fr)
Inventor
王洁琼
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/908,327 priority Critical patent/US20160372084A1/en
Publication of WO2016119467A1 publication Critical patent/WO2016119467A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a driving circuit, a driving method thereof, and a display device.
  • the data signal and the clock signal are outputted by the timing controller, the driver of the display panel receives the data signal and the clock signal, and performs based on the data signal and the clock signal A logic operation to generate a drive signal for driving the display panel.
  • the phase difference between the data signal and the clock signal is a predetermined value, that is, the data signal and the clock signal are mutually corresponding.
  • the data signal and the clock signal may have different degrees of signal delay, resulting in the data signal and the clock signal actually received by the driver. It does not match the data signal and the clock signal that it needs, which affects the display quality of the display device.
  • an embodiment of the present invention provides a driving circuit, a driving method thereof, and a display device, which are used to solve the problem that the data signal and the clock signal actually received by the driver in the prior art cannot be between the data signal and the clock signal required by the driver. Matching each other, thereby affecting the display quality of the display device.
  • Embodiments of the present invention provide a driving circuit including a timing controller, a timing regulator, and a driver, the timing regulator being connected to an output end of the timing controller, and an output end of the timing regulator being connected to the driver
  • the timing controller is configured to output a first data signal and a first clock signal
  • the timing adjuster is configured to adjust a phase of the first data signal and the first clock signal to generate a second data signal corresponding to each other
  • a second clock signal the driver is configured to generate a driving signal according to the second data signal and the second clock signal.
  • the timing adjuster may include a conversion unit and an synchronization unit, an input end of the conversion unit is connected to the timing controller, and a first output end of the conversion unit is connected to a first input end of the synchronization unit, a second output of the conversion unit is coupled to the driver, a second input of the synchronization unit is coupled to the timing controller, an output of the synchronization unit is coupled to the driver; Adjusting a phase of the first clock signal to generate the second clock signal; the synchronization unit is configured to adjust a phase of the first data signal according to the second clock signal to generate a second data signal, The second data signal and the second clock signal have a predetermined phase difference.
  • the conversion unit may include a plurality of delay circuits.
  • the delay circuit can include an inverter.
  • the inverter may be selected from the group consisting of an NMOS type inverter, a PMOS type inverter, and a CMOS type inverter.
  • the synchronization unit may include a D flip-flop.
  • the driver can include a source driver.
  • the driver and the timing adjuster can be integrated.
  • Embodiments of the present invention also provide a display device including a display panel and any of the above driving circuits.
  • the embodiment of the invention further provides a driving method of a driving circuit, the driving circuit includes a timing controller, a timing regulator and a driver, and the timing regulator is connected to an output end of the timing controller, and the timing regulator The output is connected to the driver; the driving method includes:
  • a drive signal is generated by the driver based on the second data signal and the second clock signal.
  • the timing adjuster may include a conversion unit and an synchronization unit, an input end of the conversion unit is connected to the timing controller, and a first output end of the conversion unit is connected to a first input end of the synchronization unit, a second output of the conversion unit is coupled to the driver, and a second input of the synchronization unit is coupled to the timing controller, the synchronization An output of the unit is coupled to the driver; wherein a phase of the first data signal and the first clock signal is adjusted by the timing adjuster to generate a second data signal and a second clock signal corresponding to each other
  • the steps include:
  • the conversion unit may include a plurality of delay circuits.
  • the delay circuit can include an inverter.
  • the inverter may be selected from the group consisting of an NMOS type inverter, a PMOS type inverter, and a CMOS type inverter.
  • the synchronization unit may include a D flip-flop.
  • the driver can include a source driver.
  • the driver and the timing adjuster can be integrated.
  • the driving circuit includes a timing controller, a timing controller and a driver, and the timing controller outputs a first data signal and a first clock signal, a timing adjuster adjusting a phase of the first data signal and the first clock signal to generate a second data signal and a second clock signal corresponding to each other, the driver according to the second data signal and the second The clock signal produces a drive signal.
  • the timing adjuster actively adjusts the first data signal and the first clock signal output by the timing controller to generate mutually corresponding second data signals and second clock signals actually needed by the driver, thereby implementing and displaying
  • the perfect matching of the panels further improves the display quality of the display device.
  • FIG. 1 is a schematic block diagram of a driving circuit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic block diagram of the timing adjuster shown in FIG. 1;
  • FIG. 3 is a flowchart of a driving method of a driving circuit according to Embodiment 3 of the present invention.
  • FIG. 1 is a schematic block diagram of a driving circuit according to Embodiment 1 of the present invention.
  • the driving circuit may include a timing controller 101, a timing regulator 102, and a driver 103.
  • the timing regulator 102 is connected to an output of the timing controller 101, and an output of the timing regulator 102 is connected to the driver 103.
  • the timing controller 101 is configured to output a first data signal and a first clock signal
  • the timing adjuster 102 is configured to adjust a phase of the first data signal and the first clock signal to generate a second data signal and a second clock signal corresponding to each other.
  • the driver 103 is configured to generate a driving signal according to the second data signal and the second clock signal.
  • the timing controller 101 generates a first data signal and a first clock signal, and transmits the first data signal and the first clock signal to the timing adjuster 102.
  • the phase difference between the first data signal and the first clock signal is a predetermined value.
  • factors such as circuit layout may cause the first data signal and the first clock signal to appear to different degrees.
  • the signal is delayed such that the phase difference between the first data signal and the first clock signal deviates from a predetermined value.
  • the timing adjuster 102 after receiving the first data signal and the first clock signal, adjusts the phases of the first data signal and the first clock signal to generate the phase-corrected second data signal and the second clock.
  • the signal, the second data signal and the second clock signal correspond to each other.
  • the driver 103 receives the second data signal and the second clock signal, and then generates a driving signal required by the display panel according to the second data signal and the second clock signal, thereby achieving perfect matching with the display panel, thereby improving the display quality of the display device.
  • the timing adjuster 102 is connected to the output of the timing controller 101, and the output of the timing adjuster 102 is connected to the driver 103.
  • the timing adjuster 102 can include a conversion unit 104 and a synchronization unit 105.
  • the input of the conversion unit 104 is connected to the timing controller 101, and the conversion unit
  • the first output of the 104 is coupled to the first input of the synchronization unit 105
  • the second output of the conversion unit 104 is coupled to the driver 103
  • the second input of the synchronization unit 105 is coupled to the timing controller 101.
  • the output of the synchronization unit 105 The terminal is connected to the drive 103.
  • the conversion unit 104 receives the first clock signal output from the timing controller 101, then adjusts the phase of the first clock signal to generate a second clock signal, and transmits the second clock signal to the synchronization unit 105 and the driver 103, respectively.
  • the synchronization unit 105 receives the first data signal output by the timing controller 101 and the second clock signal output by the conversion unit 104, and then adjusts the phase of the first data signal according to a predetermined phase difference to generate a corresponding to the second clock signal. The second data signal.
  • the predetermined phase difference refers to a phase difference between a clock signal and a data signal actually required by the driver of the display panel.
  • one or more predetermined phase differences may be pre-stored in a storage unit (not shown in the drawing) according to parameters such as the size of the display panel, and the predetermined phase difference is set according to actual conditions. So that when the synchronization unit receives the second clock signal, the phase of the first data signal can be adjusted according to a predetermined phase difference, thereby generating a driver corresponding to the second clock signal that is actually required by the driver driving the display panel. The second data signal.
  • the conversion unit 104 includes a plurality of delay circuits. Each delay circuit provides a different degree of signal delay to the first clock signal to adjust the phase of the first clock signal to produce a second clock signal.
  • the phase of the first clock signal may be delayed by any known delay circuit, which is not specifically limited herein.
  • the delay circuit typically includes an inverter.
  • the inverter is an NMOS type inverter or a PMOS type inverter. Since the NMOS type inverter or the PMOS type inverter only needs to use one type of transistor, the manufacturing cost of the drive circuit can be reduced.
  • the inverter is a CMOS type inverter.
  • the CMOS type inverter has a relatively low resistance value, which can reduce the power consumption of the circuit, and the CMOS type inverter has the advantage of high processing efficiency, and is more suitable for the driving circuit provided by the present invention.
  • the synchronization unit 105 includes a D flip-flop.
  • the D flip-flop includes a first input terminal for receiving the second clock signal, a second input terminal for receiving the first data signal, and an output terminal for outputting the first data signal to the driver 103. Two data signals.
  • the driver 103 includes a source driver.
  • the source driver receives the second clock signal generated by the conversion unit 104 and the second data signal generated by the synchronization unit 105, and then generates a drive signal based on the second clock signal and the second data signal. Since the second data signal and the second clock signal correspond to each other and are the data signals and clock signals actually needed by the driver, perfect matching with the display panel can be achieved, thereby improving the display quality of the display device.
  • the timing adjuster 102 is integrated with the driver 103, so that the influence of factors such as the circuit layout on the signal can be further reduced, and the driver 103 can obtain the data signal and the clock signal that are actually needed, thereby facilitating the improvement of the display device. Display quality.
  • the driving circuit includes a timing controller, a timing controller and a driver, and the timing controller outputs the first data signal and the first clock signal, and the timing adjuster adjusts the first data signal and the first clock signal Phases to generate mutually corresponding second data signals and second clock signals, and the driver generates drive signals based on the second data signals and the second clock signals.
  • the timing regulator actively adjusts the first data signal and the first clock signal output by the timing controller to generate a second data signal and a second clock signal that are actually required by the driver, thereby implementing the display panel Perfect matching, which in turn increases the display quality of the display device.
  • the present embodiment provides a display device, including a display panel and a driving circuit provided in Embodiment 1.
  • a display device including a display panel and a driving circuit provided in Embodiment 1.
  • the driving circuit includes a timing controller, a timing controller and a driver, and the timing controller outputs the first data signal and the first clock signal, and the timing adjuster adjusts the first data signal and the first clock signal Phases to generate mutually corresponding second data signals and second clock signals, and the driver generates drive signals based on the second data signals and the second clock signals.
  • the timing regulator actively adjusts the first data signal and the first clock signal output by the timing controller to generate a second data signal and a second clock signal that are actually required by the driver, thereby implementing the display panel Perfect matching, which in turn improves the display quality of the display device.
  • FIG. 3 is a flowchart of a driving method of a driving circuit according to Embodiment 3 of the present invention.
  • the driving circuit may include a timing controller, a timing regulator and a driver, the timing regulator is connected to the output of the timing controller, and the output of the timing regulator is connected to the driver.
  • the driving method may include the following steps 3001-3003.
  • Step 3001 Output a first data signal and a first clock signal through a timing controller.
  • the timing controller generates the first data signal and the first clock signal, and transmits the first data signal and the first clock signal to the timing adjuster.
  • the phase difference between the first data signal and the first clock signal is a predetermined value.
  • factors such as circuit layout may cause the first data signal and the first clock signal to appear to different degrees.
  • the signal is delayed such that the phase difference between the first data signal and the first clock signal deviates from a predetermined value.
  • Step 3002 Adjust a phase of the first data signal and the first clock signal by a timing adjuster to generate a second data signal and a second clock signal corresponding to each other.
  • the timing adjuster after receiving the first data signal and the first clock signal, the timing adjuster adjusts the phases of the first data signal and the first clock signal to generate the phase-corrected second data signal and the second The clock signal, the second data signal and the second clock signal correspond to each other.
  • the timing adjuster may include a conversion unit and an synchronization unit, the input end of the conversion unit being connected to the timing controller, the first output end of the conversion unit being connected to the first input end of the synchronization unit, and the second output end of the conversion unit Connected to the driver, the second input of the synchronization unit is connected to the timing controller, and the output of the synchronization unit is connected to the driver.
  • the conversion unit receives the first clock signal output by the timing controller, then adjusts the phase of the first clock signal to generate a second clock signal, and transmits the second clock signal to the synchronization unit and the driver, respectively.
  • the synchronization unit receives the first data signal output by the timing controller and the second clock signal output by the conversion unit, and then adjusts the phase of the first data signal according to the predetermined phase difference to generate second data corresponding to the second clock signal. signal.
  • the conversion unit may include a plurality of delay circuits. Each delay circuit provides a different degree of signal delay to the first clock signal to adjust the phase of the first clock signal to produce a second clock signal.
  • the phase of the first clock signal may be delayed by any known delay circuit, which is not specifically limited herein.
  • the delay circuit typically includes an inverter.
  • the inverter is an NMOS type inverter or a PMOS type inverter. Since the NMOS type inverter or the PMOS type inverter only needs to use one type of transistor, the manufacturing cost of the drive circuit can be reduced.
  • the inverter is a CMOS type inverter.
  • the CMOS type inverter has a relatively low resistance value, which can reduce the power consumption of the circuit, and the CMOS type inverter has the advantage of a higher processing rate, and is more suitable for the driving circuit provided by the present invention.
  • the synchronization unit includes a D flip-flop.
  • the D flip-flop includes a first input terminal for receiving the second clock signal, a second input terminal for receiving the first data signal, and an output terminal for outputting the second data to the driver. Data signal.
  • Step 3003 Generate a driving signal by the driver according to the second data signal and the second clock signal.
  • the driver receives the second data signal and the second clock signal, and then generates a driving signal required by the display panel according to the second data signal and the second clock signal, thereby achieving perfect matching with the display panel, thereby improving The display quality of the display device.
  • the driver includes a source driver.
  • the source driver receives the second clock signal generated by the conversion unit and the second data signal generated by the synchronization unit, and then generates a driving signal according to the second clock signal and the second data signal. Since the second data signal and the second clock signal correspond to each other and are the data signals and clock signals actually needed by the driver, perfect matching with the display panel can be achieved, thereby improving the display quality of the display device.
  • the timing adjuster is integrated with the driver, so that the influence of factors such as the circuit layout on the signal can be further reduced, and the driver can obtain the data signal and the clock signal that are actually needed by the driver, thereby facilitating the display quality of the display device.
  • the driving circuit includes a timing controller, a timing controller and a driver, the timing controller outputs a first data signal and a first clock signal, and the timing adjuster adjusts the first data signal and the first
  • the phases of the clock signals are used to generate mutually corresponding second data signals and second clock signals
  • the driver generates drive signals based on the second data signals and the second clock signals.
  • the timing regulator actively adjusts the first data signal and the first clock signal output by the timing controller to generate mutually corresponding second data signals and second clock signals actually needed by the driver, thereby implementing the display panel The perfect match, which in turn improves the display quality of the display device.

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Abstract

提供一种驱动电路及其驱动方法以及采用该驱动电路的显示装置，所述驱动电路包括时序控制器(101)、时序调节器(102)和驱动器(103)，所述时序控制器(101)输出第一数据信号和第一时钟信号，所述时序调节器(102)调节所述第一数据信号和所述第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号，所述驱动器(103)根据所述第二数据信号和所述第二时钟信号产生驱动信号；所述时序调节器(102)主动对时序控制器(101)输出的第一数据信号和第一时钟信号进行调节，以产生相互对应的、所述驱动器(103)实际需要的第二数据信号和第二时钟信号，从而实现与显示面板的完美匹配，进而提高了显示装置的显示质量。

Description

驱动电路及其驱动方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种驱动电路及其驱动方法、显示装置。
背景技术
在现有的显示面板的驱动过程中，通过时序控制器输出数据信号和时钟信号，所述显示面板的驱动器接收所述数据信号和所述时钟信号，并基于所述数据信号和时钟信号来执行逻辑运算，从而产生用于驱动所述显示面板的驱动信号。其中，所述数据信号和时钟信号之间的相位差为预定值，也就是说，所述数据信号和时钟信号之间是相互对应的。然而，在实际应用过程中，由于显示面板的尺寸的多样化以及电路布局等因素的影响，数据信号和时钟信号会出现不同程度的信号延迟，导致所述驱动器实际接收到的数据信号和时钟信号与其需要的数据信号和时钟信号之间不能相互匹配，从而影响显示装置的显示质量。
发明内容
为解决上述问题，本发明实施例提供一种驱动电路及其驱动方法、显示装置，用于解决现有技术中驱动器实际接收到的数据信号和时钟信号与其需要的数据信号和时钟信号之间不能相互匹配，从而影响显示装置的显示质量的问题。
本发明实施例提供一种驱动电路，包括时序控制器、时序调节器和驱动器，所述时序调节器与所述时序控制器的输出端连接，所述时序调节器的输出端与所述驱动器连接；所述时序控制器用于输出第一数据信号和第一时钟信号；所述时序调节器用于调节所述第一数据信号和所述第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号；所述驱动器用于根据所述第二数据信号和所述第二时钟信号产生驱动信号。
所述时序调节器可以包括转换单元和同步单元，所述转换单元的输入端与所述时序控制器连接，所述转换单元的第一输出端与所述同步单元的第一输入端连接，所述转换单元的第二输出端与所述驱动器连接，所述同步单元的第二输入端与所述时序控制器连接，所述同步单元的输出端与所述驱动器连接；所述转换单元用于调节所述第一时钟信号的相位以产生所述第二时钟信号；所述同步单元用于根据所述第二时钟信号对所述第一数据信号的相位进行调节，从而产生第二数据信号，所述第二数据信号与所述第二时钟信号具有预定的相位差。
所述转换单元可以包括多个延迟电路。
所述延迟电路可以包括反相器。
所述反相器可以选自NMOS型反相器、PMOS型反相器和CMOS型反相器。
所述同步单元可以包括D触发器。
所述驱动器可以包括源极驱动器。
所述驱动器和所述时序调节器可以集成设置。
本发明实施例还提供一种显示装置，包括显示面板和上述任一驱动电路。
本发明实施例还提供一种驱动电路的驱动方法，所述驱动电路包括时序控制器、时序调节器和驱动器，所述时序调节器与所述时序控制器的输出端连接，所述时序调节器的输出端与所述驱动器连接；所述驱动方法包括：
通过所述时序控制器输出第一数据信号和第一时钟信号；
通过所述时序调节器调节所述第一数据信号和所述第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号；以及
根据所述第二数据信号和所述第二时钟信号，通过所述驱动器产生驱动信号。
所述时序调节器可以包括转换单元和同步单元，所述转换单元的输入端与所述时序控制器连接，所述转换单元的第一输出端与所述同步单元的第一输入端连接，所述转换单元的第二输出端与所述驱动器连接，所述同步单元的第二输入端与所述时序控制器连接，所述同步 单元的输出端与所述驱动器连接；其中，通过所述时序调节器调节所述第一数据信号和所述第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号的步骤包括：
通过所述转换单元调节所述第一时钟信号的相位，以产生所述第二时钟信号；
根据所述第二时钟信号，通过所述同步单元对所述第一数据信号的相位进行调节，从而产生第二数据信号，所述第二数据信号与所述第二时钟信号具有预定的相位差。
所述转换单元可以包括多个延迟电路。
所述延迟电路可以包括反相器。
所述反相器可以选自NMOS型反相器、PMOS型反相器和CMOS型反相器。
所述同步单元可以包括D触发器。
所述驱动器可以包括源极驱动器。
所述驱动器和所述时序调节器可以集成设置。
本发明具有下述有益效果：
本发明实施例提供的驱动电路及其驱动方法、显示装置中，所述驱动电路包括时序控制器、时序调节器和驱动器，所述时序控制器输出第一数据信号和第一时钟信号，所述时序调节器调节所述第一数据信号和所述第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号，所述驱动器根据所述第二数据信号和所述第二时钟信号产生驱动信号。所述时序调节器主动对时序控制器输出的第一数据信号和第一时钟信号进行调节，以产生相互对应的、所述驱动器实际需要的第二数据信号和第二时钟信号，从而实现与显示面板的完美匹配，进而提高了显示装置的显示质量。
附图说明
图1为本发明实施例1提供的一种驱动电路的示意性框图；
图2为图1所示时序调节器的示意性框图；
图3为本发明实施例3提供的一种驱动电路的驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明实施例提供的驱动电路及其驱动方法、显示装置进行详细描述。
[实施例1]
图1为本发明实施例1提供的一种驱动电路的示意性框图。如图1所示，该驱动电路可以包括时序控制器101、时序调节器102和驱动器103，时序调节器102与时序控制器101的输出端连接，时序调节器102的输出端与驱动器103连接。时序控制器101用于输出第一数据信号和第一时钟信号，时序调节器102用于调节第一数据信号和第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号，驱动器103用于根据第二数据信号和第二时钟信号产生驱动信号。
本实施例中，时序控制器101产生第一数据信号和第一时钟信号，并将第一数据信号和第一时钟信号传输至时序调节器102。在理想状态下，第一数据信号和第一时钟信号之间的相位差为预定值，然而，在实际应用中，电路布局等因素会导致第一数据信号和第一时钟信号会出现不同程度的信号延迟，使得第一数据信号和第一时钟信号之间的相位差偏离预定值。在本实施例中，时序调节器102接收到第一数据信号和第一时钟信号后，调节第一数据信号和第一时钟信号的相位，以产生相位修正后的第二数据信号和第二时钟信号，第二数据信号和第二时钟信号相互对应。驱动器103接收第二数据信号和第二时钟信号，然后根据第二数据信号和第二时钟信号产生显示面板需要的驱动信号，从而实现与显示面板的完美匹配，进而提高显示装置的显示质量。
图2为图1所示时序调节器102的示意性框图。如图2所示，时序调节器102与时序控制器101的输出端连接，时序调节器102的输出端与驱动器103连接。时序调节器102可以包括转换单元104和同步单元105，转换单元104的输入端与时序控制器101连接，转换单元 104的第一输出端与同步单元105的第一输入端连接，转换单元104的第二输出端与驱动器103连接，同步单元105的第二输入端与时序控制器101连接，同步单元105的输出端与驱动器103连接。
转换单元104接收时序控制器101输出的第一时钟信号，然后调节第一时钟信号的相位以产生第二时钟信号，并将第二时钟信号分别传输至同步单元105和驱动器103。同步单元105接收时序控制器101输出的第一数据信号以及转换单元104输出的第二时钟信号，然后根据预定的相位差对第一数据信号的相位进行调节，以产生与第二时钟信号对应的第二数据信号。
其中，预定的相位差指的是显示面板的驱动器实际需要的时钟信号与数据信号之间的相位差。在实际应用中，可以根据显示面板的尺寸等参数将一个或多个预定的相位差预先存储在存储单元(附图中未示出)中，并且根据实际情况对预定的相位差进行设定，从而使得当所述同步单元接收到第二时钟信号时，可以根据预定的相位差对第一数据信号的相位进行调节，从而产生驱动显示面板的驱动器实际需要的、与第二时钟信号相对应的第二数据信号。
本实施例中，转换单元104包括多个延迟电路。各延迟电路为第一时钟信号提供不同程度的信号延迟，以调节第一时钟信号的相位，从而产生第二时钟信号。
在实际应用中，可以采用任何已知形式的延迟电路对第一时钟信号的相位进行延迟，在此不做具体限定。延迟电路通常包括反相器。可选的，反相器为NMOS型反相器或PMOS型反相器。由于NMOS型反相器或PMOS型反相器只需要使用一种类型的晶体管，因此可以降低驱动电路的制造成本。优选的，反相器为CMOS型反相器。CMOS型反相器的电阻值相对较低，可以降低电路的功耗，并且CMOS型反相器具有处理效率较高的优点，更适用于本发明提供的驱动电路。
可选的，同步单元105包括D触发器。D触发器包括第一输入端、第二输入端以及输出端，第一输入端用于接收第二时钟信号，第二输入端用于接收第一数据信号，输出端用于向驱动器103输出第二数据信号。
可选的，驱动器103包括源极驱动器。源极驱动器接收转换单元104产生的第二时钟信号和同步单元105产生的第二数据信号，然后根据第二时钟信号和第二数据信号产生驱动信号。由于第二数据信号与第二时钟信号相互对应，且为所述驱动器实际需要的数据信号和时钟信号，因此能够实现与显示面板的完美匹配，进而提高了显示装置的显示质量。
优选地，时序调节器102与驱动器103集成设置，如此可以进一步降低电路布局等因素对信号的影响，更有利于驱动器103获得其实际需要的数据信号和时钟信号，从而更有利于提高显示装置的显示质量。
本实施例提供的驱动电路中，驱动电路包括时序控制器、时序调节器和驱动器，时序控制器输出第一数据信号和第一时钟信号，时序调节器调节第一数据信号和第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号，驱动器根据第二数据信号和第二时钟信号产生驱动信号。时序调节器主动对时序控制器输出的第一数据信号和第一时钟信号进行调节，以产生相互对应的、所述驱动器实际需要的第二数据信号和第二时钟信号，从而实现与显示面板的完美匹配，提进而高了显示装置的显示质量。
[实施例2]
本实施例提供一种显示装置，包括显示面板和实施例1提供的驱动电路，其具体内容可参照上述实施例1中的描述，此处不再赘述。
本实施例提供的显示装置中，驱动电路包括时序控制器、时序调节器和驱动器，时序控制器输出第一数据信号和第一时钟信号，时序调节器调节第一数据信号和第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号，驱动器根据第二数据信号和第二时钟信号产生驱动信号。时序调节器主动对时序控制器输出的第一数据信号和第一时钟信号进行调节，以产生相互对应的、所述驱动器实际需要的第二数据信号和第二时钟信号，从而实现与显示面板的完美匹配，进而提高了显示装置的显示质量。
[实施例3]
图3为本发明实施例3提供的一种驱动电路的驱动方法的流程图。所述驱动电路可以包括时序控制器、时序调节器和驱动器，时序调节器与时序控制器的输出端连接，时序调节器的输出端与驱动器连接。
所述驱动方法可以包括如下步骤3001-3003。
步骤3001、通过时序控制器输出第一数据信号和第一时钟信号。
具体地，在该步骤中，时序控制器产生第一数据信号和第一时钟信号，并将第一数据信号和第一时钟信号传输至时序调节器。在理想状态下，第一数据信号和第一时钟信号之间的相位差为预定值，然而，在实际应用中，电路布局等因素会导致第一数据信号和第一时钟信号会出现不同程度的信号延迟，使得第一数据信号和第一时钟信号之间的相位差偏离预定值。
步骤3002、通过时序调节器调节第一数据信号和第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号。
具体地，在该步骤中，时序调节器接收到第一数据信号和第一时钟信号后，调节第一数据信号和第一时钟信号的相位，以产生相位修正后的第二数据信号和第二时钟信号，第二数据信号和第二时钟信号相互对应。
更具体地，时序调节器可以包括转换单元和同步单元，转换单元的输入端与时序控制器连接，转换单元的第一输出端与同步单元的第一输入端连接，转换单元的第二输出端与驱动器连接，同步单元的第二输入端与时序控制器连接，同步单元的输出端与驱动器连接。
转换单元接收时序控制器输出的第一时钟信号，然后调节第一时钟信号的相位以产生第二时钟信号，并将第二时钟信号分别传输至同步单元和驱动器。同步单元接收时序控制器输出的第一数据信号以及转换单元输出的第二时钟信号，然后根据预定的相位差对第一数据信号的相位进行调节，以产生与第二时钟信号对应的第二数据信号。
本实施例中，转换单元可以包括多个延迟电路。各延迟电路为第一时钟信号提供不同程度的信号延迟，以调节第一时钟信号的相位，从而产生第二时钟信号。
在实际应用中，可以采用任何已知形式的延迟电路对第一时钟信号的相位进行延迟，在此不做具体限定。延迟电路通常包括反相器。可选的，反相器为NMOS型反相器或PMOS型反相器。由于NMOS型反相器或PMOS型反相器只需要使用一种类型的晶体管，因此可以降低驱动电路的制造成本。优选的，反相器为CMOS型反相器。CMOS型反相器的电阻值相对较低，可以降低电路的功耗，并且CMOS型反相器具有处理速率较高的优点，更适用于本发明提供的驱动电路。
可选的，同步单元包括D触发器。D触发器包括第一输入端、第二输入端以及输出端，第一输入端用于接收第二时钟信号，第二输入端用于接收第一数据信号，输出端用于向驱动器输出第二数据信号。
步骤3003、根据第二数据信号和第二时钟信号，通过驱动器产生驱动信号。
具体地，在该步骤中，驱动器接收第二数据信号和第二时钟信号，然后根据第二数据信号和第二时钟信号产生显示面板需要的驱动信号，从而实现与显示面板的完美匹配，进而提高显示装置的显示质量。
可选的，驱动器包括源极驱动器。源极驱动器接收转换单元产生的第二时钟信号和同步单元产生的第二数据信号，然后根据第二时钟信号和第二数据信号产生驱动信号。由于第二数据信号与第二时钟信号相互对应，且为所述驱动器实际需要的数据信号和时钟信号，因此能够实现与显示面板的完美匹配，进而提高了显示装置的显示质量。
优选地，时序调节器与驱动器集成设置，如此可以进一步降低电路布局等因素对信号的影响，更有利于驱动器获得其实际需要的数据信号和时钟信号，从而更有利于提高显示装置的显示质量。
本实施例提供的驱动电路的驱动方法中，驱动电路包括时序控制器、时序调节器和驱动器，时序控制器输出第一数据信号和第一时钟信号，时序调节器调节第一数据信号和第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号，驱动器根据第二数据信号和第二时钟信号产生驱动信号。时序调节器主动对时序控制器输出的第一数据信号和第一时钟信号进行调节，以产生相互对应的、所述驱动器实际需要的第二数据信号和第二时钟信号，从而实现与显示面板 的完美匹配，进而提高了显示装置的显示质量。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (17)

  1. 一种驱动电路，包括时序控制器、时序调节器和驱动器，所述时序调节器与所述时序控制器的输出端连接，所述时序调节器的输出端与所述驱动器连接；
    所述时序控制器用于输出第一数据信号和第一时钟信号；
    所述时序调节器用于调节所述第一数据信号和所述第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号；
    所述驱动器用于根据所述第二数据信号和所述第二时钟信号产生驱动信号。
  2. 根据权利要求1所述的驱动电路，其中，所述时序调节器包括转换单元和同步单元，所述转换单元的输入端与所述时序控制器连接，所述转换单元的第一输出端与所述同步单元的第一输入端连接，所述转换单元的第二输出端与所述驱动器连接，所述同步单元的第二输入端与所述时序控制器连接，所述同步单元的输出端与所述驱动器连接；
    所述转换单元用于调节所述第一时钟信号的相位以产生所述第二时钟信号；
    所述同步单元用于根据所述第二时钟信号对所述第一数据信号的相位进行调节，从而产生第二数据信号，所述第二数据信号与所述第二时钟信号具有预定的相位差。
  3. 根据权利要求2所述的驱动电路，其中，所述转换单元包括多个延迟电路。
  4. 根据权利要求3所述的驱动电路，其中，所述延迟电路包括反相器。
  5. 根据权利要求4所述的驱动电路，其中，所述反相器选自NMOS型反相器、PMOS型反相器和CMOS型反相器。
  6. 根据权利要求2所述的驱动电路，其中，所述同步单元包括D触发器。
  7. 根据权利要求1所述的驱动电路，其中，所述驱动器包括源极驱动器。
  8. 根据权利要求1所述的驱动电路，其中，所述驱动器与所述时序调节器集成设置。
  9. 一种显示装置，包括显示面板和权利要求1-8任一所述的驱动电路。
  10. 一种驱动电路的驱动方法，所述驱动电路包括时序控制器、时序调节器和驱动器，所述时序调节器与所述时序控制器的输出端连接，所述时序调节器的输出端与所述驱动器连接；
    所述驱动方法包括：
    通过所述时序控制器输出第一数据信号和第一时钟信号；
    通过所述时序调节器调节所述第一数据信号和所述第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号；
    根据所述第二数据信号和所述第二时钟信号，通过所述驱动器产生驱动信号。
  11. 根据权利要求10所述的驱动电路的驱动方法，其中，所述时序调节器包括转换单元和同步单元，所述转换单元的输入端与所述时序控制器连接，所述转换单元的第一输出端与所述同步单元的第一输入端连接，所述转换单元的第二输出端与所述驱动器连接，所述同步单元的第二输入端与所述时序控制器连接，所述同步单元的输出端与所述驱动器连接；其中
    通过所述时序调节器调节所述第一数据信号和所述第一时钟信号的相位，以产生相互对应的第二数据信号和第二时钟信号的步骤包括：
    通过所述转换单元调节所述第一时钟信号的相位，以产生所述第二时钟信号；
    根据所述第二时钟信号，通过所述同步单元对所述第一数据信号的相位进行调节，从而产生第二数据信号，所述第二数据信号与所述第二时钟信号具有预定的相位差。
  12. 根据权利要求11所述的驱动电路的驱动方法，其中，所述转换单元包括多个延迟电路。
  13. 根据权利要求12所述的驱动电路的驱动方法，其中，所述延迟电路包括反相器。
  14. 根据权利要求13所述的驱动电路的驱动方法，其中，所述反相器选自NMOS型反相器、PMOS型反相器和CMOS型反相器。
  15. 根据权利要求11所述的驱动电路的驱动方法，其中，所述同步单元包括D触发器。
  16. 根据权利要求10所述的驱动电路的驱动方法，其中，所述驱动器包括源极驱动器。
  17. 根据权利要求10所述的驱动电路的驱动方法，其中，所述驱动器与所述时序调节器集成设置。
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Publication number Priority date Publication date Assignee Title
CN104505017A (zh) * 2015-01-26 2015-04-08 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示装置
CN107393491B (zh) * 2017-07-18 2018-08-14 深圳市华星光电半导体显示技术有限公司 时钟信号输出电路及液晶显示装置
CN107634752B (zh) * 2017-09-20 2024-07-16 北京集创北方科技股份有限公司 驱动装置和驱动方法
US10783842B2 (en) * 2017-10-06 2020-09-22 Japan Display Inc. Display device
JP2020030346A (ja) * 2018-08-23 2020-02-27 堺ディスプレイプロダクト株式会社 表示装置及び表示装置におけるデータ伝送方法
CN109192127B (zh) 2018-10-29 2022-06-24 合肥鑫晟光电科技有限公司 时序控制器及其驱动方法、显示装置
CN109493782A (zh) * 2018-12-19 2019-03-19 惠科股份有限公司 信号校正控制器、信号校正控制方法及显示装置
CN111179804B (zh) * 2020-01-13 2023-04-18 合肥鑫晟光电科技有限公司 一种时序控制器、显示装置、信号调整方法
CN111491162B (zh) * 2020-05-19 2021-08-13 京东方科技集团股份有限公司 一种检测驱动电路、驱动方法及检测装置
CN115083363B (zh) * 2022-06-15 2024-07-09 海宁奕斯伟集成电路设计有限公司 时序信号产生装置、方法及屏幕逻辑板和液晶显示器装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101042843A (zh) * 2006-03-21 2007-09-26 联詠科技股份有限公司 可自动调整信号偏移的显示系统及相关驱动方法
CN101089686A (zh) * 2006-06-16 2007-12-19 Lg.菲利浦Lcd株式会社 显示器件及其制造方法
CN101127199A (zh) * 2007-09-06 2008-02-20 友达光电股份有限公司 输出无重叠扫描信号的栅极驱动器、液晶显示器及方法
CN101202027A (zh) * 2006-12-13 2008-06-18 群康科技(深圳)有限公司 显示器屏幕显示控制系统与控制方法
US20080266477A1 (en) * 2007-04-27 2008-10-30 Samsung Electronics Co., Ltd. Gate driving circuit and liquid crystal display having the same
US20080284768A1 (en) * 2007-05-18 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Method for driving liquid crystal display device
CN104505017A (zh) * 2015-01-26 2015-04-08 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示装置
CN204375392U (zh) * 2015-01-26 2015-06-03 京东方科技集团股份有限公司 一种驱动电路和显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002196732A (ja) * 2000-04-27 2002-07-12 Toshiba Corp 表示装置、画像制御半導体装置、および表示装置の駆動方法
JP2002202760A (ja) * 2000-12-27 2002-07-19 Nec Corp 液晶表示装置の駆動方法及び駆動回路
JP3779687B2 (ja) * 2003-01-29 2006-05-31 Ｎｅｃエレクトロニクス株式会社 表示装置駆動回路
KR100542768B1 (ko) * 2003-06-21 2006-01-20 엘지.필립스 엘시디 주식회사 액정표시장치의 구동장치
JP4209430B2 (ja) * 2006-05-25 2009-01-14 パナソニック株式会社 ドライバ制御装置
JP5211591B2 (ja) * 2007-09-10 2013-06-12 セイコーエプソン株式会社 データ線駆動回路、電気光学装置及び電子機器
US8704805B2 (en) * 2010-04-19 2014-04-22 Himax Technologies Limited System and method for handling image data transfer in a display driver

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101042843A (zh) * 2006-03-21 2007-09-26 联詠科技股份有限公司 可自动调整信号偏移的显示系统及相关驱动方法
CN101089686A (zh) * 2006-06-16 2007-12-19 Lg.菲利浦Lcd株式会社 显示器件及其制造方法
CN101202027A (zh) * 2006-12-13 2008-06-18 群康科技(深圳)有限公司 显示器屏幕显示控制系统与控制方法
US20080266477A1 (en) * 2007-04-27 2008-10-30 Samsung Electronics Co., Ltd. Gate driving circuit and liquid crystal display having the same
US20080284768A1 (en) * 2007-05-18 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Method for driving liquid crystal display device
CN101127199A (zh) * 2007-09-06 2008-02-20 友达光电股份有限公司 输出无重叠扫描信号的栅极驱动器、液晶显示器及方法
CN104505017A (zh) * 2015-01-26 2015-04-08 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示装置
CN204375392U (zh) * 2015-01-26 2015-06-03 京东方科技集团股份有限公司 一种驱动电路和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109787724A (zh) * 2017-11-10 2019-05-21 京东方科技集团股份有限公司 传输参数配置信息的确定方法、装置及通信系统
CN109787724B (zh) * 2017-11-10 2021-12-14 京东方科技集团股份有限公司 传输参数配置信息的确定方法、装置及通信系统

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