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WO2016065763A1 - 一种跨域时钟同步方法、装置、系统及计算机存储介质 - Google Patents

一种跨域时钟同步方法、装置、系统及计算机存储介质 Download PDF

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Publication number
WO2016065763A1
WO2016065763A1 PCT/CN2015/072151 CN2015072151W WO2016065763A1 WO 2016065763 A1 WO2016065763 A1 WO 2016065763A1 CN 2015072151 W CN2015072151 W CN 2015072151W WO 2016065763 A1 WO2016065763 A1 WO 2016065763A1
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WIPO (PCT)
Prior art keywords
synchronization
information
pce
clock
clock synchronization
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PCT/CN2015/072151
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English (en)
French (fr)
Inventor
唐可心
付锡华
张君辉
Original Assignee
中兴通讯股份有限公司
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Priority to US15/523,086 priority Critical patent/US10084558B2/en
Priority to EP15854421.3A priority patent/EP3214795B1/en
Publication of WO2016065763A1 publication Critical patent/WO2016065763A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0647—Synchronisation among TDM nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0679—Clock or time synchronisation in a network by determining clock distribution path in a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/12—Shortest path evaluation
    • H04L45/122—Shortest path evaluation by minimising distances, e.g. by selecting a route with minimum of number of hops
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/64—Routing or path finding of packets in data switching networks using an overlay routing layer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/70—Admission control; Resource allocation
    • H04L47/78—Architectures of resource allocation
    • H04L47/783—Distributed allocation of resources, e.g. bandwidth brokers
    • H04L47/785—Distributed allocation of resources, e.g. bandwidth brokers among multiple network domains, e.g. multilateral agreements

Definitions

  • the present invention relates to communication technologies, and in particular, to a cross-domain clock synchronization method, apparatus, system, and computer storage medium.
  • Clock synchronization in communication networks is a very critical technology. Accurate and timely clock synchronization is directly related to the quality of the entire network.
  • clock synchronization also called phase synchronization
  • frequency synchronization requires the absolute time between points to be the same; frequency synchronization maintains the same frequency at each point, and they can be any phase. Since the clock device tracks the clock source, the local clock signal is the same as the clock source frequency, that is, there is tracking phase accumulation.
  • the types of networks are relatively simple. For example, only one type of network is generally included, and the range of a single network is not large. The number of network nodes and the number of hops between nodes are small, and clock synchronization is relatively easy to implement.
  • the structure of existing communication networks is increasingly complex, and the types of transmission networks are more and more, for example, packet switching networks such as IP/Multi-Protocol Label Switching (MPLS), optical networks such as Optical Transport Network (Optical Transport Network, OTN) and Synchronous Digital Hierarchy (SDH) networks; the scope of the network is also expanding rapidly.
  • MPLS IP/Multi-Protocol Label Switching
  • OTN Optical Transport Network
  • SDH Synchronous Digital Hierarchy
  • a single network evolves from a single network type to a network containing multiple types, such as a single network spanning packet transport network (Packet Transport) Network, PTN) and OTN hybrid networking networks, and the number of network nodes included in a single network is also increasing, and the topological relationship between nodes is gradually complicated.
  • Packet Transport Packet Transport
  • the current cross-domain clock synchronization method is manually configured.
  • the traditional communication network has a simple network, and the manual configuration can meet the network clock synchronization requirements.
  • the current network is increasingly complex, and the use of traditional manual configuration to achieve clock synchronization will lead to cumbersome maintenance workload, and the current network changes are more frequent, it is difficult to use a single manual configuration to complete the clock synchronization of the existing large network system.
  • the embodiments of the present invention provide a cross-domain clock synchronization method, device, system, and computer storage medium.
  • the embodiment of the invention provides a cross-domain clock synchronization method, which is applied to a cross-domain synchronization network, and the method includes:
  • the Path Calculate Element (PCE) and the controller participating in the clock synchronization path calculation exchange clock synchronization types, so that the PCE matches the clock synchronization type supported by the controller;
  • the PCE sends the clock synchronization path to the controller according to the physical topology information, so that the controller sends a clock synchronization instruction to a synchronization node on the clock synchronization path.
  • the PCE and the controller participating in the clock synchronization path calculation exchange clock synchronization types including:
  • the PCE and the controller participating in the clock synchronization path calculation exchange clock synchronization types through the SYN Type in the extended SYN TLV in the OPEN message.
  • the PCE acquires physical topology information of the cross-domain synchronization network, including:
  • the PCE acquires synchronization information of the synchronization node of the cross-domain synchronization network and/or hop count information between the synchronization nodes, including:
  • the PCE acquires the synchronization information from a controller by using a new SYN-INFORMATION object in the extended PCReq message, or the PCE acquires the synchronization information by using a network management system;
  • the PCE acquires the hop count information through a network management system.
  • the PCE calculates a clock synchronization path of the inter-domain synchronization network according to the physical topology information, the synchronization information, and/or the hop count information, including:
  • the clock synchronization path is calculated by a Backward-Recursive PCE-Based Computation (BRPC) method.
  • BRPC Backward-Recursive PCE-Based Computation
  • the PCE calculates a clock synchronization path of the inter-domain synchronization network according to the physical topology information, the synchronization information, and/or the hop count information, including:
  • Hierarchical PCE Hierarchy-PCE, H-PCE
  • the synchronization information includes clock quality level (QL) information and port priority information;
  • the PCE calculates a clock synchronization path of the inter-domain synchronization network according to the physical topology information, the synchronization information, and/or the hop count information, including:
  • the node with the highest QL is selected as the clock source output node;
  • a node having a higher priority port is selected as a clock source output node
  • a node with a smaller number of hops from the node is selected as the time The output node of the clock source.
  • the synchronization information includes clock QL information and port priority information.
  • the PCE calculates a clock synchronization path of the inter-domain synchronization network according to the physical topology information, the synchronization information, and/or the hop count information, including:
  • the node with the highest QL is preferentially selected as the clock source output node; if the QL is the same, the node with the higher priority port is preferentially selected as the node.
  • the PCE sends the clock synchronization path to the controller according to the physical topology information, including:
  • the PCE sends the clock synchronization path to the controller by using an extended PCRep message according to the physical topology information.
  • An embodiment of the present invention provides a cross-domain clock synchronization system, which is applied to a cross-domain synchronization network, where the system includes a path PCE and a controller participating in clock synchronization path calculation, where
  • the PCE is configured to exchange a clock synchronization type with the controller, to match the PCE with a clock synchronization type supported by the controller, acquire physical topology information of the cross-domain synchronization network, and acquire the cross-domain synchronization. Synchronization information of the synchronization node of the network and/or hop count information between the synchronization nodes; calculating the cross-domain synchronization network according to the physical topology information, and the synchronization information and/or the hop count information between the synchronization nodes a clock synchronization path; and sending the clock synchronization path to the controller according to the physical topology information;
  • the controller is configured to send a clock synchronization command to a synchronization node on the clock synchronization path.
  • the PCE is configured to exchange clock synchronization types with the SYN Type in the extended SYN TLV in the OPEN message.
  • the PCE is configured to be added by the extended PCReq message.
  • the SYN-INFORMATION object acquires the synchronization information from a controller, or acquires the synchronization information through a network management system.
  • the PCE is configured to send the clock synchronization path to the controller by using an extended PCRep message according to the physical topology information.
  • the embodiment of the present invention provides a PCE, which is applied to a cross-domain synchronization network, where the PCE includes:
  • a processing module configured to exchange a clock synchronization type with a controller participating in the clock synchronization path calculation, so that the PCE matches a clock synchronization type supported by the controller;
  • a first acquiring module configured to acquire physical topology information of the cross-domain synchronization network
  • a second acquiring module configured to acquire synchronization information of the synchronization node of the cross-domain synchronization network and/or hop count information between the synchronization nodes
  • a calculation module configured to calculate a clock synchronization path of the cross-domain synchronization network according to the physical topology information, and the synchronization information and/or the hop count information;
  • a sending module configured to send the clock synchronization path to the controller according to the physical topology information, so that the controller sends a clock synchronization instruction to a synchronization node on the clock synchronization path.
  • the processing module is configured to exchange clock synchronization types with the SYN Type in the extended SYN TLV in the OPEN message by the controller participating in the clock synchronization path calculation.
  • the second obtaining module is configured to acquire the synchronization information from a controller by using a new SYN-INFORMATION object in the extended PCReq message, or the PCE obtains the synchronization information by using a network management system.
  • the sending module is configured to send the clock synchronization path to the controller by using an extended PCRep message according to the physical topology information.
  • the embodiment of the invention provides a controller, which is applied to a cross-domain synchronization network, and the controller includes:
  • a processing module configured to exchange a clock synchronization type with the path calculation unit PCE, so that the control Matching the clock synchronization type supported by the PCE;
  • a receiving module configured to receive a clock synchronization path sent by the PCE
  • a sending module configured to send a clock synchronization command to the synchronization node on the clock synchronization path.
  • Embodiments of the present invention provide a computer storage medium, the computer storage medium comprising a set of instructions that, when executed, cause at least one processor to perform the cross-domain clock synchronization method described above.
  • the technical solution of the embodiment of the present invention includes a PCE and a controller that participates in clock synchronization path calculation to exchange clock synchronization types, so that the PCE matches a clock synchronization type supported by the controller; the PCE acquires the cross The physical topology information of the domain synchronization network; the PCE acquires synchronization information of the synchronization node of the cross-domain synchronization network and/or hop count information between the synchronization nodes; the PCE is based on the physical topology information, and the synchronization information And/or the hop count information, calculating a clock synchronization path of the cross-domain synchronization network; the PCE sending the clock synchronization path to the controller according to the physical topology information; the controller synchronizing a clock The instruction is sent to a synchronization node on the clock synchronization path.
  • the embodiment of the invention can automatically calculate the clock synchronization path of the cross-domain synchronization network composed of multiple synchronization sub-networks, thereby eliminating the need for manual configuration, effectively improving the synchronization performance of the entire network, and improving the clock synchronization efficiency of the cross-domain synchronization network.
  • FIG. 1 is a schematic flowchart diagram of an embodiment of a method for synchronizing a cross-domain clock according to the present invention
  • FIG. 2 is a schematic diagram of a format of an OPEN object according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an extended SYN TLV format according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of an extended RP object format according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a format of a new SYN-INFORMATION object according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a format of an IPv4 prefix sub-object of an extended ERO object according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a format of an IPv6 prefix sub-object of an extended ERO object according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of initializing a PCEP session according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a synchronization network across a PTN and an OTN domain according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a controller sending node synchronization information to a PCE according to an embodiment of the present invention
  • FIG. 11 is a schematic diagram of a synchronization path between a PTN and an OTN domain calculated by a PCE according to an embodiment of the present invention
  • FIG. 12 is a schematic diagram of a PCE transmitting a synchronization path to a controller according to an embodiment of the present invention
  • FIG. 13 is a schematic diagram of a non-direct-connected PTN and OTN domain synchronization network according to an embodiment of the present invention
  • FIG. 14 is a schematic diagram of a synchronization network across a PTN and an OTN domain according to an embodiment of the present invention
  • FIG. 15 is a schematic diagram of a synchronization path of a BRPC computing cross-domain synchronization network according to an embodiment of the present invention.
  • 16 is a schematic diagram of a synchronization path across a PTN and an OTN domain calculated by a PCE according to an embodiment of the present invention
  • FIG. 17 is a schematic structural diagram of an embodiment of a cross-domain clock synchronization system according to the present invention.
  • FIG. 18 is a schematic structural diagram of an embodiment of a PCE according to the present invention.
  • FIG. 19 is a schematic structural diagram of an embodiment of a controller provided by the present invention.
  • the cross-domain synchronization network includes at least two synchronization sub-networks. As shown in FIG. 1 , the method includes:
  • Step 101 The PCE and the controller participating in the clock synchronization path calculation exchange clock synchronization types, so that the PCE matches the clock synchronization type supported by the controller.
  • Step 102 The PCE acquires physical topology information of the cross-domain synchronization network.
  • the PCE acquires a physical topology of the cross-domain synchronization network through a controller or through a network management system.
  • Step 103 The PCE acquires synchronization information of a synchronization node of the cross-domain synchronization network and/or hop count information between synchronization nodes.
  • the synchronization information includes: clock QL information, port priority information, and synchronization capability information, where the synchronization capability information is information capable of indicating whether the synchronization node has the capability of supporting frequency synchronization and/or time synchronization, and further In other words, the synchronization capability information can indicate whether the port of the synchronization node has the capability of supporting frequency synchronization and/or time synchronization.
  • the PCE acquires the synchronization information from a controller by using a new SYN-INFORMATION object in the extended PCReq message, or the PCE acquires the synchronization information by using a network management system;
  • the PCE acquires the hop count information through a network management system.
  • Step 104 The PCE calculates a clock synchronization path of the cross-domain synchronization network according to the physical topology information, the synchronization information, and/or the hop count information.
  • the clock synchronization path is calculated using the BRPC method.
  • the calculating the clock synchronization path by using the BRPC method includes:
  • the PCE of the destination synchronization sub-network calculates the Virtual Shortest Path Tree (VSPT) of the local domain, and the VSPT includes the best of all the boundary nodes to the destination node of the local domain. Step path
  • VSPT Virtual Shortest Path Tree
  • the PCE of the previous synchronization sub-network calculates the VSPT of the local domain according to the received VSPT, and the VSPT includes an optimal synchronization path of all boundary nodes to the destination node in the local domain;
  • the PCE of the first synchronization sub-network calculates an optimal clock synchronization path according to the received VSPT.
  • the H-PCE method is used to calculate the clock synchronization path.
  • the H-PCE method is used to calculate a clock synchronization path, including:
  • the PCE calculates the optimal inter-domain clock synchronization path, and the PCE splices the optimal inter-domain clock synchronization path and the optimal intra-domain clock synchronization path calculated by the controller to obtain an optimal clock synchronization path.
  • the synchronization information includes clock QL information and port priority information
  • the node with the highest QL is selected as the clock source output node
  • a node with a higher priority port is selected as a clock source output node
  • a node with a smaller hop count from the local node is selected as the output node of the clock source.
  • the priority of the clock QL information, the port priority information, and the hop count information are arranged from high to low.
  • the node with the highest QL is preferentially selected as the clock source output node; if the QL is the same, the node with the higher priority port is preferentially selected as the node.
  • Step 105 The PCE sends the clock synchronization path to the controller according to the physical topology information.
  • the PCE sends the clock synchronization path to the controller by using an extended PCRep message according to the physical topology information.
  • Step 106 The controller sends a clock synchronization instruction to a synchronization node on the clock synchronization path.
  • Step 1 Exchanging a clock synchronization type with a controller participating in the clock synchronization path calculation, so that the PCE matches the clock synchronization type supported by the controller;
  • Step 2 Obtain physical topology information of the cross-domain synchronization network.
  • Step 3 Acquire synchronization information of the synchronization node of the cross-domain synchronization network and/or hop count information between synchronization nodes.
  • Step 4 Calculate a clock synchronization path of the cross-domain synchronization network according to the physical topology information, the synchronization information, and/or the hop count information.
  • Step 5 Send the clock synchronization path to the controller according to the physical topology information, so that the controller sends a clock synchronization instruction to the synchronization node on the clock synchronization path.
  • PCEP Path Calculate Element Protocol
  • the embodiment of the present invention implements clock synchronization in a cross-domain hybrid networking scenario by extending the PCEP so that the PCE can be applied to a cross-domain synchronous network composed of multiple synchronous networks.
  • the embodiment of the present invention extends PCEP as follows:
  • Extended OPEN object The OPEN object defined by RFC 5440, as shown in Figure 2, where the Optional TLVs section describes the PCC or PCE features.
  • a new Optional TLV-SYN TLV is extended to the OPEN object, as shown in FIG. 3, wherein the meanings of the fields are: Type field, indicating the type of the Optional TLV; and Length field, indicating the length of the Optional TLV. In bytes, where the length is 4 bytes; the Reserved field indicates the currently undefined reserved byte portion; the SYN Type field indicates the type of clock synchronization supported by the PCE. Currently, three values are defined: 0, 1. 2, respectively, indicates that the PCE supports the time synchronization network, supports the frequency synchronization network, and simultaneously supports the time synchronization network and the frequency synchronization network.
  • the OPEN message is exchanged.
  • the PCE can know the type of clock synchronization requested to be calculated, and the controller can learn the PCE.
  • the type of clock synchronization supported by the calculation is supported. Specifically, the type of clock synchronization is carried by the SYN Type field in the SYN TLV in the OPEN message.
  • the RP object of the extended PCReq message is added with a flag:S flag in the Flags field of the original RP object, indicating that the request calculates the clock synchronization path.
  • the extended RP object format is shown in Figure 4.
  • the original field meaning of the RP object is the same as that defined in RFC 5440, and is not described here.
  • the RP object contains the S flag, it indicates that the clock synchronization path is requested.
  • the PCReq message is extended, and the new SYN-INFORMATION object carries the parameters required for clock synchronization calculation:
  • Int Pri Port priority information, that is, the priority of each port connected to the cross-domain link; in Arabic numerals, the smaller the number, the higher the priority, the currently defined 8-bit priority, starting with the number 1. , that is, when the priority is 1, it indicates the highest priority;
  • Optional TLVs Optional TLVs, not currently defined.
  • the IPv4 prefix and the IPv6 prefix sub-object of the ERO object of the PCRep message are extended.
  • the two sub-objects add two fields: S, I/O, and the field meanings are respectively: S: indicates that the path calculation response is the returned clock synchronization path calculation result; I/O: This node acts as an input/output port for clock synchronization.
  • Two I/O values are currently defined: 1,0. When the I/O is 1, it indicates that the node is the clock synchronization input, and the clock synchronization is obtained from the port of the destination address included in the message; when the I/O value is 0, the node is used as the clock synchronization output, and the clock source signal is used.
  • IPv4prefix and IPv6prefix two sub-object formats of the extended ERO object See Figure 6 and Figure 7, respectively.
  • the original field meanings of the two sub-objects of the IPv4 prefix and the IPv6 prefix of the ERO object are the same as those defined in RFC 5440, and are not described here.
  • This embodiment is directed to the case where the domain sequence across the PTN and OTN domains (ie, the sequence of the synchronization subnetwork) is unknown.
  • FIG. 8 The schematic diagram of the cross-PTN and OTN domain synchronization network in this embodiment is shown in FIG. 8.
  • the clock synchronization implementation method in this embodiment is as follows:
  • controller and the PCE exchange OPEN messages to confirm the type of support for clock synchronization
  • FIG. 9 is a schematic diagram of the PCEP session initialization.
  • the PCE can calculate the clock synchronization type requested by the PCC, the matching is successful, and the PCEP session is established and sent.
  • the KeepAlive message keeps the session; when the match is unsuccessful, the PCErr message is sent to end the PECP session. The specific process is shown in Figure 9, and is not described here.
  • the PCE acquires a physical topology of the synchronous network across the PTN and the OTN domain;
  • the PCE acquires synchronization information of each synchronization node and hop count information between each synchronization node.
  • the clock QL information, the port priority information, and the hop count information of the node are obtained from the PCReq message sent by the controller of the PTN1, PTN2, and OTN to the PCE:
  • the synchronization information of the PTN1, PTN2, and OTN that the PCE can receive from the controller 1, the controller 2, and the controller 3 respectively is as follows:
  • the QL of PTN1 is 2, and the priorities of port B and port C are 1, 2;
  • the QL of PTN2 is 4, and the priorities of port D and port E are 1, 2;
  • the QL of the OTN is 4, and the priorities of the port G and the port I are 1, 2;
  • the PCE obtains the hop count information of each cross-domain synchronization node from the network management system, that is, it is directly connected.
  • the PCE calculates a synchronization path (that is, a clock synchronization path) of the inter-domain synchronization network according to the physical topology information of the cross-domain synchronization network, the synchronization information, and the hop count information.
  • the PCE obtains the synchronization information of the two nodes and obtains the hop count information. Because the QL information of the node PTN1 is the highest, the node PTN1 is preferentially selected as the clock synchronization output, that is, the clock of the node PTN1 is synchronized to the node PTN2 and the node. OTN, as shown in FIG. 11, the direction of the arrow indicates the path direction of the clock synchronization.
  • the PCE sends the calculation result of the cross-domain synchronization path to each controller according to the synchronization link topology information of the cross-domain synchronization network.
  • the PCE transmits the cross-domain synchronization path calculation result to the controller 1 of PTN1, the controller 2 of PTN2, and the controller 3 of the OTN.
  • Each controller sends a clock synchronization command to the synchronization node on the synchronization path according to the received calculation result;
  • Each controller then sends a clock synchronization command to the synchronization node in the synchronization sub-network in which it is located according to the calculation result.
  • This embodiment is directed to an indirect connection, where the domain sequence across the PTN and OTN domains is unknown.
  • FIG. 13 is a schematic diagram of a synchronization network of a non-directly connected PTN and an OTN domain according to the embodiment.
  • the difference between the embodiment and the synchronization network of the first embodiment is that the inter-domain links between the domain edge nodes of the two sub-networks (ie, the synchronization sub-networks) are non-directly connected links, that is, two clock synchronizations are required. There are other asynchronous networks between adjacent domains.
  • the difference between the non-directly connected cross-domain synchronization network and the direct-connected cross-domain synchronization network is that the hop count information of the synchronization nodes acquired by the PCE is different, and the remaining steps are the same. Therefore, the steps B1, B2, and B5 in this embodiment are the same as the embodiment. The steps of A1, A2, and A5 are not described here. This embodiment only describes B3 which is different from the first embodiment. The two steps of B4 are as follows:
  • the PCE acquires synchronization information of each synchronization node and hop count information between the synchronization nodes.
  • the synchronization information of the nodes PTN1, PTN2, and OTN that can be received by the PCE from the controller 1, the controller 2, and the controller 3 is as shown in FIG. 10, and reference may be made to the A3 step of the first embodiment, which is not described herein;
  • the hop count information between the PTN1 and the OTN is obtained from the network management system, and the hop count information between the PTN2 and the OTN is 1, and the hop count between the non-directly connected cross-domain synchronization nodes PTN1 and PTN2 is 3. .
  • the PCE calculates a synchronization path of the cross-domain synchronization network according to the physical topology information of the cross-domain synchronization network, the synchronization information, and the hop count information.
  • the PCE obtains the physical topology information of the synchronization network according to step B2, and obtains the synchronization information of each node in the cross-domain synchronization network and the number of hops between the nodes from the controller and the network management system in step B3, and calculates the cross-domain synchronization of the inter-domain synchronization network. path.
  • the PCE obtains the synchronization information of the three nodes and obtains the hop count information. Because the QL information of the node PTN1 is the highest, the node PTN1 is preferentially selected as the clock synchronization output, that is, the clock of the node PTN1 is synchronized to the node PTN2 and the node OTN. As shown in FIG. 11, the arrow direction indicates the path direction of the clock synchronization.
  • This embodiment is for a case where the domain sequence across the PTN and OTN domains is known.
  • the domain sequence through which the clock synchronization path passes is known as PTN-OTN, and PCE1 requests to calculate a cross-domain clock synchronization path between a PTN domain and an OTN domain.
  • the OPEN message is exchanged between the PCEs of each domain to confirm the type of support for clock synchronization.
  • the clock synchronization type information is carried by the SYN Type in the extended SYN TLV in the OPEN message; the process of exchanging the OPEN message between the PCE1 and the PCE2 is as shown in FIG. 9 , and is not described herein;
  • PCE acquires a physical topology of the synchronous network across the PTN and the OTN domain;
  • the PCE acquires synchronization information of each synchronization node and hop count information between each synchronization node.
  • the PCE obtains the clock QL information of the synchronization node, and acquires the hop count information between the synchronization nodes from the network management system.
  • the QL information of the synchronization nodes A, B, C, and D obtained by PCE1 are: 2, 4, 4, and 8, and the hop count information between the synchronization nodes is 1.
  • the QL information of the synchronization nodes E, F, and G obtained by PCE2 are: 4, 8, and 8, and the hop count information between the synchronization nodes is 1.
  • the PCE calculates a synchronization path of the inter-domain synchronization network by using a BRPC method according to the physical topology information of the synchronization network, the synchronization information, and the hop count information.
  • PCE1 sends a PCReq message to PCE2 requesting to calculate a clock synchronization path from the PTN to the OTN domain.
  • the PCE2 first calculates VSPT1 according to the physical topology information of the synchronization network acquired in step C2, and the synchronization information of the synchronization node acquired from the controller and the network management system in step C3 and the hop count information between the synchronization nodes.
  • the VSPT1 includes a virtual shortest path tree from each boundary node of the OTN domain to the destination node G: VSPT1 includes two paths: EG, FG, and the QLs of E and F are the same, both are 4; PCE2 passes through FIG. 5 and FIG.
  • the child object of the extended ERO passes VSPT1 to PCE1;
  • the PCE1 calculates VSPT2 according to VSPT1, and the physical topology information of the synchronization network acquired from step C2, and the synchronization information of the synchronization node acquired from the controller and the network management system in step C3 and the number of hops between the nodes.
  • the VSPT2 includes the shortest path tree from the synchronization node to the destination node G in the PTN domain: VSPT2 contains two paths: A-C-E-G, B-D-F-G, but A The QL is 2, and the QL of B is 4. According to the priority principle, PCE1 selects the QL high as the clock source on the cross-domain clock synchronization path, so the final cross-domain clock synchronization path obtained by PCE1 is as shown in Figure 16: AEEG .
  • the C5 and the PCE send the calculation result of the cross-domain synchronization path to the controller in the PTN and the OTN domain according to the synchronization link topology information of the cross-domain synchronization network.
  • Each controller sends a clock synchronization command to the synchronization node on the synchronization path according to the calculation result.
  • This embodiment is directed to the clock synchronization update of the cross-domain synchronization network.
  • the controller When the synchronization node detects that the current clock source is faulty, or the clock signal of the current clock source is weakened, etc., the synchronization information of the synchronization node changes, or the physical topology of the cross-domain synchronization network changes, the controller is required to request the PCE to recalculate the cross.
  • the domain synchronization path, and in the re-initiated calculation request, the synchronization information of the updated synchronization node is sent to the PCE, and the PCE also acquires the physical topology of the new cross-domain synchronization network, updates the previous synchronization path calculation result, and sends the result to the controller. And then sent by the controller to each synchronization node.
  • the controller re-establishes a PCEP session with the PCE and sends a calculation request and synchronization information of the synchronization node.
  • the PCE acquires the synchronous network physical topology and calculates the cross-domain synchronization path in combination with the synchronization information of the synchronization node, and then sends the calculation result to the controller, and each controller
  • the process of sending the clock synchronization command to the synchronization node on the synchronization path according to the calculation result is the same as the steps A1 to A5 of the first embodiment, and is not described herein.
  • FIG. 17 An embodiment of the cross-domain clock synchronization system provided by the present invention is applied to a cross-domain synchronization network. As shown in FIG. 17, the system includes a PCE 1701 and a controller 1702 participating in clock synchronization path calculation, where
  • the PCE 1701 is configured to exchange a clock synchronization type with the controller 1702 to match the PCE 1701 with a clock synchronization type supported by the controller 1702;
  • the controller 1702 is configured to send a clock synchronization command to a synchronization node on the clock synchronization path.
  • the PCE 1701 is specifically configured to exchange clock synchronization types with the SYN Type in the SYN TLV extended in the OPEN message by the controller 1702.
  • the clock synchronization type may also be exchanged in other manners.
  • the manner of exchanging clock synchronization type information is not limited.
  • the PCE 1701 is configured to acquire the synchronization information from a controller by using a new SYN-INFORMATION object in the extended PCReq message, or obtain the synchronization information by using a network management system.
  • the PCE 1701 is specifically configured to send the clock synchronization path to the controller by using an extended PCRep message according to the physical topology information.
  • PCE An embodiment of the PCE provided by the present invention is applied to a cross-domain synchronization network. As shown in FIG. 18, the PCE includes:
  • the processing module 1801 is configured to exchange a clock synchronization type with a controller participating in the clock synchronization path calculation, so that the PCE matches the clock synchronization type supported by the controller;
  • the first obtaining module 1802 is configured to acquire physical topology information of the cross-domain synchronization network.
  • the second obtaining module 1803 is configured to acquire synchronization information of the synchronization node of the cross-domain synchronization network and/or hop count information between the synchronization nodes;
  • a calculation module 1804 configured to be based on the physical topology information, and the synchronization information and And/or the hop count information, calculating a clock synchronization path of the cross-domain synchronization network;
  • the sending module 1805 is configured to send the clock synchronization path to the controller according to the physical topology information, so that the controller sends a clock synchronization instruction to the synchronization node on the clock synchronization path.
  • the processing module 1801 is specifically configured to exchange clock synchronization types with the SYN Type in the extended SYN TLV in the OPEN message by the controller participating in the clock synchronization path calculation.
  • the clock synchronization type may also be exchanged in other manners.
  • the manner of exchanging clock synchronization type information is not limited.
  • the second obtaining module 1803 is configured to acquire the synchronization information from a controller by using a new SYN-INFORMATION object in the extended PCReq message, or the PCE obtains the information by using a network management system. Synchronization information.
  • the sending module 1805 is specifically configured to send the clock synchronization path to the controller by using an extended PCRep message according to the physical topology information.
  • the processing module 1801, the first obtaining module 1802, and the second obtaining module 1803 may be implemented by a central processing unit (CPU), a microprocessor (MCU, a digital control unit), and a digital signal in the PCE.
  • a DSP Digital Signal Processor
  • FPGA Field-Programmable Gate Array
  • the computing module 1804 can be implemented by a CPU, an MCU, a DSP, or an FPGA in the PCE;
  • the 1805 can be implemented by a transmitter in the PCE.
  • the controller includes:
  • the processing module 1901 is configured to exchange a clock synchronization type with the PCE, so that the controller and the clock synchronization type supported by the PCE match;
  • the receiving module 1902 is configured to receive a clock synchronization path sent by the PCE.
  • a sending module 1903 configured to send a clock synchronization command to the clock synchronization path Synchronize nodes.
  • the processing module 1901 may be implemented by a CPU, an MCU, a DSP, or an FPGA in a controller in combination with a transceiver; the receiving module 1902 may be implemented by a receiver in a controller; the transmitting module 1903 may be implemented in a controller Transmitter implementation.
  • the embodiment of the present invention extends the PCEP so that the PCE can be applied to a cross-domain synchronization network composed of multiple synchronization sub-networks to calculate a clock synchronization path in a cross-domain hybrid networking scenario.
  • the invention compensates for the shortcomings of current clock synchronization and enhances the function of clock synchronization.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded into a computer or other programmable data processing device Having a series of operational steps performed on a computer or other programmable device to produce computer-implemented processing such that instructions executed on a computer or other programmable device are provided for implementing one or more processes in a flowchart and/or Or block diagram the steps of a function specified in a box or multiple boxes.
  • an embodiment of a computer storage medium provided by the present invention is applied to a cross-domain synchronization network, the computer storage medium comprising a set of instructions that, when executed, cause at least one processor to perform the cross-domain described above Clock synchronization method.

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Abstract

一种跨域时钟同步方法、装置、系统及计算机存储介质，应用于跨域同步网络，其中，方法包括：路径计算单元PCE和参与时钟同步路径计算的控制器交换时钟同步种类，使PCE与控制器支持的时钟同步种类匹配（101）；PCE获取跨域同步网络的物理拓扑信息（102），PCE获取跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息（103）；PCE根据物理拓扑信息，以及同步信息和/或跳数信息，计算跨域同步网络的时钟同步路径（104）；PCE根据物理拓扑信息，向控制器发送时钟同步路径（105），以使控制器将时钟同步指令发送给时钟同步路径上的同步节点（106）。

Description

一种跨域时钟同步方法、装置、系统及计算机存储介质 技术领域
本发明涉及通信技术，特别是一种跨域时钟同步方法、装置、系统及计算机存储介质。
背景技术
通讯网络中的时钟同步是一项非常关键的技术，时钟同步的准确和及时直接关系到整网业务的质量。当前通讯网络中的时钟同步包括两种：时间同步(也叫相位同步)和频率同步。其中，时间同步要求各点之间的绝对时间相同；频率同步维持各点的频率相同，它们可以是任意相位。由于不管相位，时钟设备在跟踪时钟源的过程中，只要调整本地时钟信号与时钟源频率相同即可，即会有跟踪的相位积累。
传统通讯网络中，网络种类比较单一，如一般只包含一种类型的网络，单个网络范围也不大，网络节点数量以及节点间间隔跳数不多，时钟同步实现比较容易。现有通讯网络的结构日益复杂，传送网络类型越来越多，例如，包交换网络如IP/多协议标签交换(Multi-Protocol Label Switching，MPLS)、光网络如光传送网(Optical Transport Network，OTN)和同步数字体系(Synchronous Digital Hierarchy，SDH)等类型的网络；网络的范围也扩展迅速，单个网络从单一网络类型发展到包含多种类型的网络，如单个网络跨越分组传送网(Packet Transport Network，PTN)和OTN混合组网的网络，而且单个网络包含的网络节点数目也越来越多，节点间的拓扑关系也逐渐复杂。
在包含多种类型的网络中，当前跨域的时钟同步方法是靠人工配置。传统通讯网由于网络较简单，人工配置能满足网络时钟同步需求。然而， 当前网络日益复杂，再采用传统人工配置来实现时钟同步将导致维护工作量繁琐，且当前网络变化较频繁，很难再采用单一的人工配置方式来完成现有庞大的网络体系的时钟同步。
发明内容
为解决现有存在的技术问题，本发明实施例提供一种跨域时钟同步方法、装置、系统及计算机存储介质。
本发明实施例提供一种跨域时钟同步方法，应用于跨域同步网络，所述方法包括：
路径计算单元(Path Calculate Element，PCE)和参与时钟同步路径计算的控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；
所述PCE获取所述跨域同步网络的物理拓扑信息；
所述PCE获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；
所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算所述跨域同步网络的时钟同步路径；
所述PCE根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径，以使所述控制器将时钟同步指令发送给所述时钟同步路径上的同步节点。
其中，所述PCE和参与时钟同步路径计算的控制器交换时钟同步种类，包括：
所述PCE和参与时钟同步路径计算的控制器通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类。
其中，所述PCE获取所述跨域同步网络的物理拓扑信息，包括：
所述PCE通过控制器或通过网络管理系统来获取所述跨域同步网络的 物理拓扑。
其中，所述PCE获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息，包括：
所述PCE通过扩展的PCReq消息中新增的SYN-INFORMATION对象从控制器获取所述同步信息，或者所述PCE通过络管理系统获取所述同步信息；
所述PCE通过网络管理系统获取所述跳数信息。
其中，所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算跨域同步网络的时钟同步路径，包括：
当时钟同步路径经过的同步子网络的序列已知时，采用反向递归路径计算(Backward-Recursive PCE-Based Computation，BRPC)方法计算所述时钟同步路径。
其中，所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算跨域同步网络的时钟同步路径，包括：
当时钟同步路径经过的同步子网络的序列未知时，采用层次PCE(Hierarchy-PCE，H-PCE)方法来计算时钟同步路径。
其中，所述同步信息包括时钟质量等级(Quality level，QL)信息和端口优先级信息；
所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算跨域同步网络的时钟同步路径，包括：
当只获取到所述时钟QL信息时，选择QL最高的节点作为时钟源输出节点；或者，
当只获取到所述端口优先级信息时，选择具有较高优先级端口的节点作为时钟源输出节点；或者，
当只获取到所述跳数信息时，选择距离本节点跳数较少的节点作为时 钟源的输出节点。
其中，所述同步信息包括时钟QL信息和端口优先级信息；
所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算跨域同步网络的时钟同步路径，包括：
当获取到所述时钟QL信息、所述端口优先级信息和所述跳数信息时，优先选择QL最高的节点作为时钟源输出节点；若QL相同，优先选择具有较高优先级端口的节点作为时钟源输出节点；若端口优先级相同，选择距离本节点跳数较少的节点作为时钟源的输出节点。
其中，所述PCE根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径，包括：
所述PCE根据所述物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
本发明实施例提供一种跨域时钟同步系统，应用于跨域同步网络，所述系统包括路PCE和参与时钟同步路径计算的控制器，其中，
所述PCE，配置为和所述控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；获取所述跨域同步网络的物理拓扑信息；获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；根据所述物理拓扑信息，以及所述同步信息和/或同步节点间的所述跳数信息，计算所述跨域同步网络的时钟同步路径；并根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径；
所述控制器，配置为将时钟同步指令发送给所述时钟同步路径上的同步节点。
其中，所述PCE，配置为和所述控制器通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类。
其中，所述PCE，配置为通过扩展的PCReq消息中新增的 SYN-INFORMATION对象从控制器获取所述同步信息，或者通过络管理系统获取所述同步信息。
其中，所述PCE，配置为根据所述物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
本发明实施例提供一种PCE，应用于跨域同步网络，所述PCE包括：
处理模块，配置为和参与时钟同步路径计算的控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；
第一获取模块，配置为获取所述跨域同步网络的物理拓扑信息；
第二获取模块，配置为获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；
计算模块，配置为根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算所述跨域同步网络的时钟同步路径；
发送模块，配置为根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径，以使所述控制器将时钟同步指令发送给所述时钟同步路径上的同步节点。
其中，所述处理模块，配置为和参与时钟同步路径计算的控制器通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类。
其中，所述第二获取模块，配置为通过扩展的PCReq消息中新增的SYN-INFORMATION对象从控制器获取所述同步信息，或者所述PCE通过络管理系统获取所述同步信息。
其中，所述发送模块，配置为根据所述物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
本发明实施例提供一种控制器，应用于跨域同步网络，所述控制器包括：
处理模块，配置为和路径计算单元PCE交换时钟同步种类，使所述控 制器和所述PCE支持的时钟同步种类匹配；
接收模块，配置为接收所述PCE发来的时钟同步路径；
发送模块，配置为将时钟同步指令发送给所述时钟同步路径上的同步节点。
本发明实施例提供一种计算机存储介质，所述计算机存储介质包括一组指令，当执行所述指令时，引起至少一个处理器执行上述的跨域时钟同步方法。
由上可知，本发明实施例的技术方案包括PCE和参与时钟同步路径计算的控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；所述PCE获取所述跨域同步网络的物理拓扑信息；所述PCE获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算所述跨域同步网络的时钟同步路径；所述PCE根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径；所述控制器将时钟同步指令发送给所述时钟同步路径上的同步节点。
本发明实施例能够自动计算由多个同步子网络组成的跨域同步网络的时钟同步路径，从而无需人工配置，有效地提高整网的同步性能，提高跨域同步网络的时钟同步效率。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本发明提供的一种跨域时钟同步方法的实施例的流程示意图；
图2为本发明实施例的OPEN对象格式示意图；
图3为本发明实施例扩展的SYN TLV格式示意图；
图4为本发明实施例扩展后的RP对象格式示意图；
图5为本发明实施例新增的SYN-INFORMATION对象格式示意图；
图6为本发明实施例扩展后的ERO对象的IPv4prefix子对象格式示意图；
图7为本发明实施例扩展后的ERO对象的IPv6prefix子对象格式示意图；
图8为本发明实施例中PCEP会话初始化示意图；
图9为本发明实施例中跨PTN和OTN域同步网络示意图；
图10为本发明实施例中控制器向PCE发送节点同步信息示意图；
图11为本发明实施例中PCE计算出的跨PTN和OTN域的同步路径示意图；
图12为本发明实施例中PCE向控制器发送同步路径示意图；
图13为本发明实施例中非直连跨PTN和OTN域同步网络示意图；
图14为本发明实施例中跨PTN和OTN域同步网络示意图；
图15为本发明实施例中BRPC计算跨域同步网络的同步路径示意图；
图16为本发明实施例中PCE计算出的跨PTN和OTN域的同步路径示意图；
图17为本发明提供的一种跨域时钟同步系统的实施例的结构示意图；
图18为本发明提供的一种PCE的实施例的结构示意图；
图19为本发明提供的一种控制器的实施例的结构示意图。
具体实施方式
本发明提供的一种跨域时钟同步方法的实施例，应用于跨域同步网络，所述跨域同步网络至少包括两个同步子网络，如图1所示，所述方法包括：
步骤101、PCE和参与时钟同步路径计算的控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；
具体地，所述PCE和参与时钟同步路径计算的控制器可以通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类，当然，也可以通过其他方式，这里不限定交换时钟同步种类信息的方式。
步骤102、所述PCE获取所述跨域同步网络的物理拓扑信息；
具体地，所述PCE通过控制器或通过网络管理系统来获取所述跨域同步网络的物理拓扑。
步骤103、所述PCE获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；
具体地，所述同步信息包括：时钟QL信息、端口优先级信息、同步能力信息，其中，所述同步能力信息是能够表明同步节点是否具有支持频率同步和/或时间同步的能力的信息，进一步来说，所述同步能力信息能够表明同步节点的端口是否具有支持频率同步和/或时间同步的能力。
在实际应用中，所述PCE通过扩展的PCReq消息中新增的SYN-INFORMATION对象从控制器获取所述同步信息，或者所述PCE通过络管理系统获取所述同步信息；
所述PCE通过网络管理系统获取所述跳数信息。
步骤104、所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算所述跨域同步网络的时钟同步路径；
具体地，当时钟同步路径经过的同步子网络的序列已知时，采用BRPC方法计算所述时钟同步路径。
所述采用BRPC方法计算所述时钟同步路径，包括：
目的同步子网络的PCE计算本域的虚拟最短路径树(Virtual Shortest Path Tree，VSPT)，所述VSPT包含本域所有边界节点至目的节点的最优同 步路径；
将所述VSPT传给所述序列中前一个同步子网络的PCE；
所述前一个同步子网络的PCE根据收到的所述VSPT计算本域的VSPT，所述VSPT包含本域所有边界节点至目的节点的最优同步路径；
将计算出的VSPT传给所述序列中前一个同步子网络的PCE，直至首同步子网络的PCE收到VSPT；
所述首同步子网络的PCE根据收到的VSPT计算得到最优的时钟同步路径。
此外，当时钟同步路径经过的同步子网络的序列未知时，采用H-PCE方法来计算时钟同步路径。
所述采用H-PCE方法来计算时钟同步路径，包括：
PCE计算最优域间时钟同步路径，PCE将所述最优域间时钟同步路径和控制器计算得到的最优域内时钟同步路径拼接起来，得到最优的时钟同步路径。
所述同步信息包括时钟QL信息和端口优先级信息；
在实际应用中，当只获取到所述时钟QL信息时，选择QL最高的节点作为时钟源输出节点；
当只获取到所述端口优先级信息时，选择具有较高优先级端口的节点作为时钟源输出节点；
当只获取到所述跳数信息时，选择距离本节点跳数较少的节点作为时钟源的输出节点。
这里要说明的是，时钟QL信息、端口优先级信息、跳数信息的优先级是从高到低排列的。当获取到所述时钟QL信息、所述端口优先级信息和所述跳数信息时，优先选择QL最高的节点作为时钟源输出节点；若QL相同，优先选择具有较高优先级端口的节点作为时钟源输出节点；若端口优先级 相同，选择距离本节点跳数较少的节点作为时钟源的输出节点。
步骤105、所述PCE根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径；
具体地，所述PCE根据所述物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
步骤106、所述控制器将时钟同步指令发送给所述时钟同步路径上的同步节点。
从上面的描述中可以看出，对于PCE来说，需要执行以下步骤：
步骤1、与参与时钟同步路径计算的控制器交换时钟同步种类，使PCE与所述控制器支持的时钟同步种类匹配；
步骤2、获取所述跨域同步网络的物理拓扑信息；
步骤3、获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；
步骤4、根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算所述跨域同步网络的时钟同步路径；
步骤5、根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径，以使所述控制器将时钟同步指令发送给所述时钟同步路径上的同步节点。
为便于理解，下面对本发明实施例的技术方案进行进一步说明。
互联网工程任务组(Internet Engineering Task Force，IETF)的请求评议(Request For Comment，RFC)5440定义了路径计算单元通信协议(Path Calculate Element Protocol，PCEP)，用于PCE与路径计算客户端(Path Calculate Client，PCC)之间的通信。
本发明实施例通过扩展PCEP，使得PCE能够应用在由多个同步网络组成的跨域同步网络中，实现跨域混合组网场景中的时钟同步。具体地，本发明实施例对PCEP扩展如下：
扩展OPEN对象：RFC 5440定义的OPEN对象，如图2所示，其中的Optional TLVs部分描述PCC或PCE特征。本发明实施例对OPEN对象扩展一种新的Optional TLV—SYN TLV，如图3所示，其中各字段含义分别为：Type字段，表示该Optional TLV的类型；Length字段，表示该Optional TLV的长度，以字节为单位，这里长度的值为4字节；Reserved字段表示当前未定义的预留字节部分；SYN Type字段表示PCE支持的时钟同步种类，当前定义了三个值：0、1、2，分别表示PCE支持时间同步网、支持频率同步网、同时支持时间同步网和频率同步网。
在PCE和控制器之间建立PCEP会话前，先交换OPEN消息，通过携带本发明实施例对OPEN对象扩展的新的SYN TLV，PCE能了解到请求计算的时钟同步种类，控制器能了解到PCE支持计算的时钟同步种类，具体地，时钟同步的种类通过OPEN消息中的SYN TLV中的SYN Type字段携带。
扩展PCReq消息的RP对象，在原有RP对象的Flags字段新增一个flag：S flag，表示此次请求计算的是时钟同步的路径。扩展后的RP对象格式如图4所示。RP对象的原有字段含义同RFC 5440定义，在此不为赘述。当RP对象包含S flag，则表示请求的是时钟同步路径。
扩展PCReq消息，新增的SYN-INFORMATION对象，携带时钟同步计算中需要的参数：
<PCReq Message>::＝<Common Header>
                    [<svec-list>]
                    <request-list>
其中<svec-list>::＝<SVEC>[<svec-list>]
    <request-list>::＝<request>[<request-list>]
   <request>::＝<RP>
                    <END-POINTS>
                  [<SYN-INFORMATION>]
                  [<LSPA>]
                  [<BANDWIDTH>]
                  [<metric-list>]
                  [<RRO>[<BANDWIDTH>]]
                  [<IRO>]
                  [<LOAD-BALANCING>]
其中，新增的SYN-INFORMATION对象如图5所示，定义的各个字段含义分别为：
QL:时钟QL信息，即同步子网络的域边缘节点的时钟质量等级；QL等级由高到低为：QL＝0000＝0表示同步质量不可知；QL＝0010＝2表示一级时钟；QL＝0100＝4表示二级时钟；QL＝1000＝8表示三级时钟；QL＝1011＝11表示SDH设备时钟；QL＝1111＝15表示不可用，即不可用作同步时钟；
Int Pri：端口优先级信息，即各节点与跨域链路相连的端口的优先级；用阿拉伯数字表示，数字越小，表示优先级越高，当前定义的8比特优先级，从数字1开始，即优先级为1时表示最高的优先级；
Reserved：预留字段，当前未定义；
Optional TLVs：可选TLV，当前未定义。
扩展PCRep消息的ERO对象的IPv4prefix和IPv6prefix子对象，两个子对象新增两个字段：S，I/O，字段含义分别为：S：表示此次路径计算回应是返回的时钟同步路径计算结果；I/O：本节点作为时钟同步的输入/输出端口。当前定义两个I/O值：1，0。当I/O为1，表示本节点作为时钟同步的输入，从消息中包含的目的地址的端口获得时钟同步；当I/O值为0，表示本节点作为时钟同步的输出，将时钟源信号同步给消息中包含的目的地址的端口。扩展后的ERO对象的IPv4prefix和IPv6prefix两个子对象格式 分别见图6和图7。ERO对象的IPv4prefix和IPv6prefix两个子对象的原有字段含义同RFC 5440定义，在此不为赘述。
下面结合附图和具体实施例对本发明的技术方案进一步详细阐述。
实施例一
本实施例针对跨PTN和OTN域的域序列(即同步子网络的序列)未知的情况
本实施例的跨PTN和OTN域同步网络的示意图如图8所示，本实施例的时钟同步实现方法如下：
A1、控制器和PCE交换OPEN消息，确认时钟同步的支持种类；
具体地，时钟同步种类信息通过OPEN消息中扩展的SYN TLV中的SYN Type携带；图9为PCEP会话初始化示意图，当PCE能够计算PCC请求的时钟同步种类时，则匹配成功，PCEP会话建立，发送KeepAlive消息保持会话；当匹配不成功时，则发送PCErr消息，结束PECP会话。具体过程如图9所示，此处不为赘述。
A2、PCE获取跨PTN和OTN域同步网络物理拓扑；
A3、PCE获取各同步节点的同步信息和各同步节点间的跳数信息；
具体地，从PTN1，PTN2，OTN的控制器向PCE发送的PCReq消息中获取节点的时钟QL信息、端口优先级信息和跳数信息：
如图10所示，PCE从控制器1、控制器2和控制器3处可分别接收到的PTN1，PTN2，OTN的同步信息如下：
PTN1的QL为2，端口B、端口C的优先级分别为1、2；
PTN2的QL为4，端口D、端口E的优先级分别为1、2；
OTN的QL为4，端口G、端口I的优先级分别为1、2；
PCE从网络管理系统获取到各跨域同步节点间的跳数信息均为1，即都是直连。
A4、PCE根据跨域同步网络的物理拓扑信息、所述同步信息和所述跳数信息，计算跨域同步网络的同步路径(即时钟同步路径)；
此处，PCE获取到了两种节点的同步信息，并获取到跳数信息，因为节点PTN1的QL信息最高，则优先选取节点PTN1作为时钟同步的输出，即节点PTN1的时钟同步给节点PTN2和节点OTN，如图11所示，箭头方向表示时钟同步的路径方向。
A5、PCE根据跨域同步网络的同步链路拓扑信息，向各控制器发送上述跨域同步路径的计算结果；
如图12中所示，PCE发送跨域同步路径计算结果给PTN1的控制器1，PTN2的控制器2，以及OTN的控制器3。
A6、各控制器根据收到的计算结果，将时钟同步指令发送给同步路径上的同步节点；
各控制器再根据计算结果，向其所在的同步子网络中的同步节点发送时钟同步指令。
实施例二
本实施例针对非直连，跨PTN和OTN域的域序列未知的情况
图13为本实施例的非直连跨PTN和OTN域的同步网络示意图。本实施例与实施例一的同步网络的区别在于：跨域的两个子网络(即同步子网络)的域边缘节点间的域间链路为非直连链路，即两个需要时钟同步的相邻域间还有其他非同步网络存在。
本实施例的时钟同步实现方法如下：
非直连的跨域同步网络和直连的跨域同步网络方法区别在于PCE获取的同步节点间的跳数信息不同，其余步骤均相同，因此本实施例的B1，B2，B5步骤同实施例一的A1，A2，A5步骤，此处不为赘述，本实施例仅描述区别于实施例一的B3，B4两个步骤如下：
B3、PCE获取各同步节点的同步信息和同步节点间的跳数信息；
从PTN1，PTN2，OTN的控制器向PCE发送的PCReq消息中获取节点的时钟QL信息、端口优先级信息和跳数信息：
PCE从控制器1、控制器2和控制器3处可分别接收到的节点PTN1，PTN2，OTN的同步信息如图10所示，可参考实施例一的A3步骤，此处不为赘述；
PCE从网络管理系统获取到直连的跨域同步节点PTN1和OTN间，以及PTN2和OTN间的跳数信息均为1，而非直连的跨域同步节点PTN1和PTN2间的跳数为3。
B4、PCE根据跨域同步网络的物理拓扑信息、所述同步信息和所述跳数信息，计算跨域同步网络的同步路径；
PCE根据步骤B2中获取同步网络的物理拓扑信息，以及步骤B3中从控制器和网络管理系统获取跨域同步网络中各节点的同步信息以及节点间跳数，计算跨域同步网络的跨域同步路径。
此处PCE获取到了三种节点的同步信息，并获取到跳数信息，因为节点PTN1的QL信息最高，则优先选取节点PTN1作为时钟同步的输出，即节点PTN1的时钟同步给节点PTN2和节点OTN，如图11所示，箭头方向表示时钟同步的路径方向。
实施例三
本实施例针对跨PTN和OTN域的域序列已知的情况
本实施例与实施例一的区别在于，本实施例中，已知时钟同步路径经过的域序列为PTN-OTN，PCE1请求计算一条PTN域和OTN域之间的跨域时钟同步路径。
本实施例的时钟同步实现方法如下：
C1、各域PCE之间交换OPEN消息，确认时钟同步的支持种类。
具体地，时钟同步种类信息通过OPEN消息中扩展的SYN TLV中的SYN Type携带；PCE1和PCE2交换OPEN消息过程如图9所示，此处不为赘述；
C2、PCE获取跨PTN和OTN域同步网络物理拓扑；
C3、PCE获取各同步节点的同步信息和各同步节点间的跳数信息。
本实施例中PCE获取到同步节点的时钟QL信息、并从网络管理系统处获取各同步节点间的跳数信息。
PCE1获取同步节点A、B、C，D的QL信息分别为：2、4、4、8，同步节点间的跳数信息均为1。
PCE2获取同步节点E、F、G的QL信息分别为：4、8、8，同步节点间的跳数信息均为1。
C4、PCE根据同步网络的物理拓扑信息、所述同步信息和所述跳数信息，采用BRPC的方法计算跨域同步网络的同步路径；
如图15所示跨域网络中，PCE1发送PCReq消息给PCE2，请求计算一条从PTN至OTN域的时钟同步路径。
PCE2先根据步骤C2中获取的同步网络的物理拓扑信息，以及步骤C3中从控制器和网络管理系统获取的同步节点的同步信息以及同步节点间的跳数信息，计算VSPT1。该VSPT1中包含OTN域的各边界节点至目的节点G的虚拟最短路径树：VSPT1中包含两条路径：E-G，F-G，且E和F的QL相同，均为4；PCE2通过图5和图6中扩展的ERO的子对象将VSPT1传给PCE1；
PCE1根据VSPT1，以及从步骤C2中获取的同步网络的物理拓扑信息，以及步骤C3中从控制器和网络管理系统获取的同步节点的同步信息以及节点间跳数，计算VSPT2。该VSPT2中包含PTN域各同步节点至目的节点G的最短路径树：VSPT2中包含两条路径：A-C-E-G，B-D-F-G，但是A 的QL为2，B的QL为4，根据优先级原则，PCE1选择QL高的为跨域时钟同步路径上的时钟源，因此PCE1得到的最终的跨域时钟同步路径如图16所示：A-E-E-G。
C5、PCE根据跨域同步网络的同步链路拓扑信息，发送上述跨域同步路径的计算结果给PTN和OTN域内的控制器；
C6、各控制器根据计算结果，将时钟同步指令发送给同步路径上的同步节点。
实施例四
本实施例针对跨域同步网络的时钟同步更新情况
当同步节点检测到当前时钟源故障，或者当前时钟源的时钟信号弱化等原因，造成同步节点的同步信息发生变化，或者跨域同步网络物理拓扑发生了变化，则需要控制器请求PCE重新计算跨域同步路径，并且在重新发起的计算请求中，发送更新的同步节点的同步信息给PCE，PCE也获取新的跨域同步网络的物理拓扑，更新之前的同步路径计算结果，并发送给控制器，再由控制器进一步发送给各同步节点。
控制器重新与PCE建立PCEP会话并发送计算请求以及同步节点的同步信息，PCE获取同步网络物理拓扑并结合同步节点的同步信息计算跨域同步路径后，将计算结果发送给控制器，各控制器再根据计算结果，将时钟同步指令发送给同步路径上的同步节点的过程，同实施例一的A1—A5步骤，在此不为赘述。
本发明提供的一种跨域时钟同步系统的实施例，应用于跨域同步网络，如图17所示，所述系统包括PCE 1701和参与时钟同步路径计算的控制器1702，其中，
所述PCE 1701，配置为和所述控制器1702交换时钟同步种类，使所述PCE 1701与所述控制器1702支持的时钟同步种类匹配；
获取所述跨域同步网络的物理拓扑信息；
获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；
根据所述物理拓扑信息，以及所述同步信息和/或同步节点间的所述跳数信息，计算所述跨域同步网络的时钟同步路径；
根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径；
所述控制器1702，配置为将时钟同步指令发送给所述时钟同步路径上的同步节点。
在一实施例中，所述PCE 1701，具体配置为和所述控制器1702通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类。当然，在实际应用中，也可以通过其他方式交换时钟同步种类，这里不限定交换时钟同步种类信息的方式。
在一实施例中，所述PCE 1701，具体配置为通过扩展的PCReq消息中新增的SYN-INFORMATION对象从控制器获取所述同步信息，或者通过络管理系统获取所述同步信息。
在一实施例中，所述PCE 1701，具体配置为根据所述物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
本发明提供的一种PCE的实施例，应用于跨域同步网络，如图18所示，所述PCE包括：
处理模块1801，配置为和参与时钟同步路径计算的控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；
第一获取模块1802，配置为获取所述跨域同步网络的物理拓扑信息；
第二获取模块1803，配置为获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；
计算模块1804，配置为根据所述物理拓扑信息，以及所述同步信息和 /或所述跳数信息，计算所述跨域同步网络的时钟同步路径；
发送模块1805，配置为根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径，以使所述控制器将时钟同步指令发送给所述时钟同步路径上的同步节点。
在一实施例中，所述处理模块1801，具体配置为和参与时钟同步路径计算的控制器通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类。当然，在实际应用中，也可以通过其他方式交换时钟同步种类，这里不限定交换时钟同步种类信息的方式。
在一实施例中，所述第二获取模块1803，具体配置为通过扩展的PCReq消息中新增的SYN-INFORMATION对象从控制器获取所述同步信息，或者所述PCE通过络管理系统获取所述同步信息。
在一实施例中，所述发送模块1805，具体配置为根据所述物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
实际应用时，所述处理模块1801、第一获取模块1802、以及第二获取模块1803可由PCE中的中央处理器(CPU，Central Processing Unit)、微处理器(MCU，Micro Control Unit)、数字信号处理器(DSP，Digital Signal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)结合收发机实现；所述计算模块1804可由PCE中的CPU、MCU、DSP或FPGA实现；所述发送模块1805可由PCE中的发射机实现。
本发明提供的一种控制器的实施例，应用于跨域同步网络，如图19所示，所述控制器包括：
处理模块1901，配置为和PCE交换时钟同步种类，使所述控制器和所述PCE支持的时钟同步种类匹配；
接收模块1902，配置为接收所述PCE发来的时钟同步路径；
发送模块1903，配置为将时钟同步指令发送给所述时钟同步路径上的 同步节点。
实际应用时，所述处理模块1901可由控制器中的CPU、MCU、DSP或FPGA结合收发机实现；所述接收模块1902可由控制器中的接收机实现；所述发送模块1903可由控制器中的发射机实现。
综上所示，本发明实施例通过扩展PCEP，使得PCE能够应用在由多个同步子网络组成的跨域同步网络中，计算跨域混合组网场景中的时钟同步路径。本发明弥补了当前时钟同步的不足，增强了时钟同步的功能。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备 上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
基于此，本发明提供的一种计算机存储介质的实施例，应用于跨域同步网络，所述计算机存储介质包括一组指令，当执行所述指令时，引起至少一个处理器执行上述的跨域时钟同步方法。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (19)

  1. 一种跨域时钟同步方法，应用于跨域同步网络，所述方法包括：
    路径计算单元PCE和参与时钟同步路径计算的控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；
    所述PCE获取所述跨域同步网络的物理拓扑信息；
    所述PCE获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；
    所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算所述跨域同步网络的时钟同步路径；
    所述PCE根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径，以使所述控制器将时钟同步指令发送给所述时钟同步路径上的同步节点。
  2. 根据权利要求1所述的方法，其中，所述PCE和参与时钟同步路径计算的控制器交换时钟同步种类，包括：
    所述PCE和参与时钟同步路径计算的控制器通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类。
  3. 根据权利要求1所述的方法，其中，所述PCE获取所述跨域同步网络的物理拓扑信息，包括：
    所述PCE通过控制器或通过网络管理系统来获取所述跨域同步网络的物理拓扑。
  4. 根据权利要求1所述的方法，其中，所述PCE获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息，包括：
    所述PCE通过扩展的PCReq消息中新增的SYN-INFORMATION对象从控制器获取所述同步信息，或者所述PCE通过络管理系统获取所述同步信息；
    所述PCE通过网络管理系统获取所述跳数信息。
  5. 根据权利要求1所述的方法，其中，所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算跨域同步网络的时钟同步路径，包括：
    当时钟同步路径经过的同步子网络的序列已知时，采用反向递归路径计算BRPC方法计算所述时钟同步路径。
  6. 根据权利要求1所述的方法，其中，所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算跨域同步网络的时钟同步路径，包括：
    当时钟同步路径经过的同步子网络的序列未知时，采用层次PCE H-PCE方法来计算时钟同步路径。
  7. 根据权利要求1所述的方法，其中，所述同步信息包括时钟质量等级QL信息和端口优先级信息；
    所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算跨域同步网络的时钟同步路径，包括：
    当只获取到所述时钟QL信息时，选择QL最高的节点作为时钟源输出节点；或者，
    当只获取到所述端口优先级信息时，选择具有较高优先级端口的节点作为时钟源输出节点；或者，
    当只获取到所述跳数信息时，选择距离本节点跳数较少的节点作为时钟源的输出节点。
  8. 根据权利要求1所述的方法，其中，所述同步信息包括时钟QL信息和端口优先级信息；
    所述PCE根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算跨域同步网络的时钟同步路径，包括：
    当获取到所述时钟QL信息、所述端口优先级信息和所述跳数信息时，优先选择QL最高的节点作为时钟源输出节点；若QL相同，优先选择具有较高优先级端口的节点作为时钟源输出节点；若端口优先级相同，选择距离本节点跳数较少的节点作为时钟源的输出节点。
  9. 根据权利要求1所述的方法，其中，所述PCE根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径，包括：
    所述PCE根据所述物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
  10. 一种跨域时钟同步系统，应用于跨域同步网络，其中，所述系统包括路径计算单元PCE和参与时钟同步路径计算的控制器，其中，
    所述PCE，配置为和所述控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；获取所述跨域同步网络的物理拓扑信息；获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；根据所述物理拓扑信息，以及所述同步信息和/或同步节点间的所述跳数信息，计算所述跨域同步网络的时钟同步路径；并根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径；
    所述控制器，配置为将时钟同步指令发送给所述时钟同步路径上的同步节点。
  11. 根据权利要求10所述的系统，其中，所述PCE，配置为和所述控制器通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类。
  12. 根据权利要求10所述的系统，其中，所述PCE，配置为通过扩展的PCReq消息中新增的SYN-INFORMATION对象从控制器获取所述同步信息，或者通过络管理系统获取所述同步信息。
  13. 根据权利要求10所述的系统，其中，所述PCE，配置为根据所述 物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
  14. 一种路径计算单元PCE，应用于跨域同步网络，所述PCE包括：
    处理模块，配置为和参与时钟同步路径计算的控制器交换时钟同步种类，使所述PCE与所述控制器支持的时钟同步种类匹配；
    第一获取模块，配置为获取所述跨域同步网络的物理拓扑信息；
    第二获取模块，配置为获取所述跨域同步网络的同步节点的同步信息和/或同步节点间的跳数信息；
    计算模块，配置为根据所述物理拓扑信息，以及所述同步信息和/或所述跳数信息，计算所述跨域同步网络的时钟同步路径；
    发送模块，配置为根据所述物理拓扑信息，向所述控制器发送所述时钟同步路径，以使所述控制器将时钟同步指令发送给所述时钟同步路径上的同步节点。
  15. 根据权利要求14所述的PCE，其中，所述处理模块，配置为和参与时钟同步路径计算的控制器通过OPEN消息中扩展的SYN TLV中的SYN Type交换时钟同步种类。
  16. 根据权利要求14所述的PCE，其中，所述第二获取模块，配置为通过扩展的PCReq消息中新增的SYN-INFORMATION对象从控制器获取所述同步信息，或者所述PCE通过络管理系统获取所述同步信息。
  17. 根据权利要求14所述的PCE，其中，所述发送模块，配置为根据所述物理拓扑信息，通过扩展的PCRep消息向所述控制器发送所述时钟同步路径。
  18. 一种控制器，应用于跨域同步网络，所述控制器包括：
    处理模块，配置为和路径计算单元PCE交换时钟同步种类，使所述控制器和所述PCE支持的时钟同步种类匹配；
    接收模块，配置为接收所述PCE发来的时钟同步路径；
    发送模块，配置为将时钟同步指令发送给所述时钟同步路径上的同步节点。
  19. 一种计算机存储介质，所述计算机存储介质包括一组指令，当执行所述指令时，引起至少一个处理器执行如权利要求1至9任一项所述的跨域时钟同步方法。
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