WO2016042644A1 - Control device for controlling writing of data to memory, program, and storage device - Google Patents

Abstract

In accordance with a data write request from a host device, a storage device writes data in parallel to a plurality of memory modules possessed by the storage device. The storage device divides the data to be written into blocks having a data size that is larger than a sector, which is the minimum access unit in the host device, cyclically allocates the data to the plurality of memory modules, and writes the allocated data in parallel to the plurality of memory modules, which are the allocation destination. As a result, latency due to overhead, in reading and writing of data by memory interleaving, is reduced.

Description

CONTROL DEVICE, PROGRAM, AND STORAGE DEVICE FOR CONTROLLING DATA WRITE TO MEMORY

The present invention relates to control of writing data to a memory.

There is a technology called memory interleaving that speeds up data reading and writing by reading and writing data to multiple memory banks in parallel.

According to memory interleaving, the power, the amount of heat, etc. that accompany data reading / writing change according to the number of data that are simultaneously reading / writing data. Therefore, the appropriate number of data simultaneously read and written in the memory interleave varies depending on various conditions such as the capacity of the power source that supplies power to the storage device and the temperature that the storage device can tolerate.

There is a technology that optimizes the number of data to be read and written at the same time in memory interleaving. For example, Patent Document 1 describes a technique that uses different interleaving ratios at the time of data writing and reading (a ratio represented by x: 1 when x is the number of data to be read and written simultaneously).

JP 2012-43451 A

In memory interleaving, reading and writing data can be speeded up by generally reducing the unit of reading and writing data and increasing the number of data to be read and written (number of channels) in parallel.

However, if the unit of data to be read and written at a time is too small compared to the overhead associated with data reading and writing, the effect of speeding up by memory interleaving is offset by the overhead, and rather the latency increases. Also, depending on the type of memory module, if the unit of data to be read / written at a time is reduced, there may be a disadvantage that the life of the memory module is shortened due to an increase in the number of times of reading / writing. An example of a memory module that has a relatively large overhead associated with reading and writing data is a flash memory that includes a memory controller and performs wear leveling by the memory controller, memory interleaving in the memory module, and the like.

In view of the above circumstances, an object of the present invention is to provide means for reducing latency due to overhead in reading and writing data by memory interleaving.

In order to solve the above-described problems, the present invention is a control device capable of instructing data reading / writing to a plurality of memory modules in i (i is a natural number satisfying 2 ≦ i) in parallel. An acquisition means for acquiring data to be written, a storage means for temporarily storing the data to be written, and a block of a data unit obtained by dividing the data into m of a predetermined data size When the data to be written temporarily stored in the storage means is allocated to j (where j is the number of the i memory modules) so that two consecutive blocks are allocated to different memory modules. 2 ≦ j ≦ i is a natural number) memory module, and writing of the allocated data is instructed to the allocation destination memory module at a time That handles to propose a control device comprising an instruction unit for performing in parallel relates the j memory module as a first embodiment.

According to the present invention, in the first embodiment, the acquisition unit acquires a logical address of the data to be written, the instruction unit acquires the logical address acquired by the acquisition unit, the block address An allocation destination of the data to be written according to a predetermined rule based on m that is a data size, j that is the number of memory modules that the instruction means instructs to write data in parallel, and i that is the total number of memory modules The address of the write destination of the data in the memory module and the memory module of the allocation destination, and instructing the memory module of the allocation destination of the data to be written to write data at the address of the specified write destination. This configuration is proposed as a second embodiment.

According to the present invention, in the first embodiment, when the instruction unit sets a cluster of k blocks (k is a natural number satisfying 2 ≦ k) as a cluster, the instruction unit temporarily stores the block in the storage unit. Data to be written is allocated to the i memory modules in cluster units, and j pieces are selected from the i memory modules according to a predetermined rule (j is a natural number satisfying 2 ≦ j <i). As a third embodiment, a configuration in which writing of allocated data to the memory modules is instructed in parallel is proposed.

The acquisition unit acquires a logical address of the data to be written, the instruction unit includes a logical address acquired by the acquisition unit, m which is the data size of the block, and the instruction unit stores data in parallel. Based on j which is the number of memory modules instructing writing, k which is the number of blocks included in the cluster, and i which is the total number of memory modules, a memory module to which the data to be written is allocated according to a predetermined rule And specifying the address of the data write destination in the memory module of the allocation destination, and instructing the memory module of the allocation destination of the data to be written to write data at the specified address of the write destination. This is proposed as a fourth embodiment.

According to the present invention, in any of the first to fourth embodiments, each of the i memory modules is any one of h data buses (h is a natural number satisfying 2 ≦ h <i). And the instruction means is selected so that two or more memory modules connected to the same data bus are not included (j is a natural number satisfying 2 ≦ j ≦ h). On the other hand, a configuration in which writing of allocated data is instructed in parallel is proposed as a fifth embodiment.

In the fifth embodiment of the present invention, n memory modules are connected to each of the h data buses (n is a natural number satisfying 2 ≦), and the instruction means includes: Based on j, which is the number of memory modules instructed to write data in parallel by the instruction means, and n, which is the number of memory modules connected to one data bus, according to a predetermined rule, A configuration of selecting j memory modules instructing writing is proposed as a sixth embodiment.

Further, the present invention acquires data to be written to a processor capable of instructing data read / write in parallel to a plurality of memory modules of i (i is a natural number satisfying 2 ≦ i). Processing, processing for temporarily storing the data to be written in the storage means, and when the data unit obtained by dividing the data into m of a predetermined data size is a block, the storage means temporarily Of the i memory modules so that two consecutive blocks are allocated to different memory modules (j is a natural number satisfying 2 ≦ j ≦ i). Process for instructing the allocated memory module to write the allocated data at a time to j memory modules. We propose a program for executing the processing performed in parallel relates Yuru a seventh embodiment.

In addition, the present invention provides a control device capable of instructing to read / write data in parallel to i memory modules (i is a natural number satisfying 2 ≦ i) and a plurality of memory modules in the i memory modules. The control device includes: an acquisition unit that acquires data to be written; a storage unit that temporarily stores the data to be written; and a data obtained by dividing the data every m of a predetermined data size. When the data unit to be processed is a block, the write target data temporarily stored in the storage means is stored in the i memory modules so that two consecutive blocks are allocated to different memory modules. Are allocated to j memory modules (j is a natural number satisfying 2 ≦ j ≦ i), and writing of the allocated data is allocated to the memory module of the allocation destination. Suggest a process to instruct the 1 ° with respect Lumpur memory device including an instruction unit configured to perform in parallel relates the j memory module as the eighth embodiment.

According to the present invention, data to be written is written to each of the plurality of memory modules in units of blocks. Accordingly, in continuous data reading, data is read from a plurality of memory modules in parallel, so that high-speed data reading is performed. Even when the size of data written to each memory module exceeds the size of the block, data is written by one write instruction. Therefore, latency due to overhead associated with data writing processing can be reduced.

The figure which showed the structure of the data storage system concerning 1st Embodiment. The figure which showed the structure part of the control apparatus (at the time of data writing) concerning 1st Embodiment. The figure which showed the structure part of the control apparatus (at the time of data reading) concerning 1st Embodiment. The figure which showed the correspondence of the logical address managed in the host device concerning 1st Embodiment, and the block managed in a memory | storage device. The figure which showed the position of the cluster read / written in the memory module concerning 1st Embodiment. The figure which showed the block contained in the cluster read / written in the memory module concerning 1st Embodiment, and its order. The figure which showed the flow of the process (at the time of data writing) of the memory | storage device concerning 1st Embodiment. The figure which showed the information used in the process of the memory | storage device concerning 1st Embodiment. The figure which showed the flow of the process (at the time of data reading) of the memory | storage device concerning 1st Embodiment. The figure which showed the structure of the data storage system concerning 2nd Embodiment. The figure which showed the position of the cluster read / written in the memory module concerning 2nd Embodiment. The figure which showed the position of the cluster read / written in the memory module concerning 2nd Embodiment. The figure which showed the block contained in the cluster read / written in the memory module concerning 2nd Embodiment, and the order. The figure which showed the block contained in the cluster read / written in the memory module concerning 2nd Embodiment, and the order. The figure which showed the information used in the process of the memory | storage device concerning 2nd Embodiment. The figure which showed the information used in the process of the memory | storage device concerning 2nd Embodiment. The figure which showed the block contained in the cluster read / written in the memory module concerning one modification, and its order.

[First Embodiment]
A data storage system 1 according to an embodiment of the present invention will be described below. FIG. 1 is a diagram showing the configuration of the data storage system 1. The data storage system 1 includes a host device 11 that makes a request for reading and writing data, and a storage device 12 that reads and writes data in response to a request from the host device 11.

In response to a data read / write request from the host device 11, the storage device 12 instructs the memory device to read / write data from / to the memory module, and i units read / write data according to the instruction from the control device 121 (i is 2 ≦ 2). i) is a natural number) memory modules 122 (1) to 122 (i). Hereinafter, the memory modules 122 (1) to 122 (i) are collectively referred to as “memory module 122”.

The control device 121 and the memory module 122 (1) are connected by a data bus 123 (1). Similarly, the controller 121 and the memory modules 122 (2) to 122 (i) are connected by data buses 123 (2) to 123 (i), respectively. Hereinafter, the data buses 123 (1) to 123 (i) are collectively referred to as “data bus 123”. Since each of the control device 121 and the memory module 122 is connected by the independent data bus 123 as described above, the control device 121 can instruct each of the memory modules 122 to read and write data in parallel. .

The memory module 122 (1) includes a memory controller 1221 (1) and a memory chip 1222 (1). Similarly, the memory modules 122 (2) to 122 (i) include memory controllers 1221 (2) to 1221 (i) and memory chips 1222 (2) to 1222 (i), respectively. Hereinafter, the memory controllers 1221 (1) to 1221 (i) are collectively referred to as “memory controller 1221”, and the memory chips 1222 (1) to 1222 (i) are collectively referred to as “memory chips 1222”.

The memory controller 1221 instructs the memory chip 1222 to read / write data in accordance with instructions from the control device 121 and manages wear leveling and interleaving in the memory chip 1222. Note that the number of memory chips 1222 provided in each of the memory modules 122 is not limited to one and may be two or more.

The control device 121 includes a data processing device and a buffer memory. The data processing device included in the control device 121 may be configured as dedicated hardware by an ASIC, FPGA, or the like, or may be realized by a general-purpose processor performing processing according to a program.

FIG. 2 is a diagram illustrating a configuration unit of the control device 121 that operates when the control device 121 instructs the memory module 122 to write data in response to a data write request from the host device 11. When the control device 121 is operated by a general-purpose processor, the processor functions as a device including the components illustrated in FIG. 2 by executing processing according to a program.

The control device 121 obtains the write target data from the host device 11, the storage unit 1212 that temporarily stores the write target data acquired by the acquisition unit 1211, and temporarily stores the data in the storage unit 1212. Processing for allocating the written data to be written to the memory modules 122 (1) to 122 (i) in units of blocks of a predetermined data size and instructing the allocated memory module 122 to write the allocated data at a time Are instructed in parallel with respect to a plurality of allocation destination memory modules 122. In the present application, when “instructing data writing to a plurality of memory modules is performed in parallel”, other memory can be used without waiting for completion of data writing in accordance with the data writing instruction to a certain memory module. This is an instruction to write data to a module, and these instructions do not necessarily have to be performed strictly at the same time. The memory controller 1221 of the memory module 122 instructed to write data by the instruction unit 1213 writes data to the memory chip 1222 in accordance with the instruction.

FIG. 3 is a diagram illustrating a configuration unit of the control device 121 that operates when the control device 121 instructs the memory module 122 to read data in response to a data read request from the host device 11. In addition, when the control apparatus 121 operates by a general-purpose processor, the processor functions as an apparatus including the components illustrated in FIG. 3 by executing processing according to a program.

The control device 121 obtains the first logical address and data size of the data to be read from the host device 11, and stores the data to be read based on the logical address and data size obtained by the acquisition device 1215. The memory module 122 and the start address and data size of the data are specified, the reading means 1216 for reading the data according to the specified start address and data size from the specified memory module 122, and the data read by the reading means 1216 as the data The storage unit 1217 temporarily stores the contained blocks in a rearranged state, and the transfer unit 1218 delivers the data temporarily stored in the storage unit 1217 to the host device 11.

In the data storage system 1, continuous data in the host device 11 is allocated and written to the plurality of memory chips 1222 in units of blocks in the storage device 12. That is, a block is a data unit in a process of distributing read / write data among a plurality of memory modules 122.

FIG. 4 is a diagram showing a correspondence relationship between logical addresses managed in the host device 11 and blocks managed in the storage device 12. In the host device 11, data is managed in units of sectors having a predetermined data size s (hereinafter referred to as “sector size s”). Ss shown in FIG. 4 is a sector serial number for identifying each sector among all sectors managed by the host device 11. The host device 11 uses the sector serial number Ss as a logical address, for example. Hereinafter, as an example, it is assumed that the sector size s = 512 bytes.

Bs shown in FIG. 4 is a block serial number for identifying each block among all the blocks managed by the storage device 12. As described above, a block is a unit for data distribution in the storage device 12, and each block is associated with a predetermined number of consecutive sectors. That is, the block data size m (hereinafter referred to as “block size m”) is a multiple of the sector size s. Hereinafter, as an example, it is assumed that the block size m = 64 KB. In this case, 128 consecutive sectors are associated with each block. Specifically, the block with the block serial number Bs = 1 is associated with the sector with the sector serial number Ss = 1 to 128, and the block with the block serial number Bs = 2 is associated with the sector serial number Ss = 129. ˜256 sectors are associated with each other.

The storage area of each of the plurality of memory modules 122 included in the storage device 12 is divided into a plurality of clusters. The control device 121 instructs the memory module 122 to read / write data read / written from / to the same cluster at a time. On the other hand, for data read / written to / from different clusters, a read / write instruction is issued for each cluster. Hereinafter, as an example, it is assumed that the cluster size c (hereinafter referred to as “cluster size c”) = 4 MB. In this case, if the number of blocks that can be stored in one cluster is k, k = 64.

FIG. 5 is a diagram showing the arrangement of clusters in the storage device 12. Ms shown in FIG. 5 is a module serial number that identifies each of the i memory modules 122 by the storage device 12. The module serial number Ms = 1 identifies the memory module 122 (1), the module serial number Ms = 2 identifies the memory module 122 (2), and so on. Therefore, FIG. 5 exemplifies the arrangement of clusters when the number of memory modules 122 is i = 4.

Cs shown in FIG. 5 is a cluster serial number that identifies each cluster among all the clusters managed by the storage device 12. The cluster serial numbers are cyclically allocated to the clusters of the memory modules 122 according to the order of the module serial numbers Ms. As illustrated in FIG. 5, when the number of memory modules 122 is i = 4, the cluster serial number Cs is assigned to the first cluster of each of the memory modules 122 identified by the module serial number Ms = 1, 2, 3, 4. = 1, 2, 3, 4 are assigned, the cluster serial number Cs = 5, 6, 7, 8 is assigned to the second cluster, and so on, and the cluster serial number Cs is assigned to each cluster. .

The blocks stored in each cluster and their arrangement are uniquely determined according to a predetermined rule. FIG. 6 is a diagram showing the arrangement of blocks in the storage device 12. F shown in FIG. 6 is a write group number that identifies a group of clusters in which data is written in parallel in the storage device 12 (hereinafter referred to as “simultaneous write cluster group”). As described above, the storage device 12 can write data to each of the i memory modules 122 in parallel. However, in consideration of power consumption, heat generation, data transmission speed between the host device 11 and the storage device 12, etc., the number of memory modules 122 that simultaneously write data (hereinafter referred to as “simultaneous writing module number j”). May be less than i. FIG. 6 illustrates the arrangement of blocks when the number of simultaneous writing modules j = 3. Note that the number j of simultaneous writing modules may be appropriately changed by, for example, a user.

A simultaneous writing cluster group is formed for each cluster having the number j of simultaneous writing modules in order from the top in the order of the cluster serial number Cs. As illustrated in FIG. 6, when the number j of simultaneous writing modules is 3, a cluster having cluster serial numbers Cs = 1, 2, and 3 is formed as a simultaneous writing cluster group identified by the writing group number F = 1. Then, clusters having cluster serial numbers Cs = 4, 5, and 6 form a simultaneous write cluster group identified by the write group number F = 2, and so on. It is formed.

Blocks are cyclically allocated according to the order of the cluster serial number Cs in j clusters belonging to the same simultaneous writing cluster group.

As illustrated in FIG. 6, when the number of simultaneous writing modules j = 3, each of the blocks having block serial numbers Bs = 1, 2, 3, 4, 5, 6,. The cluster serial numbers Cs = 1 to 3 included in the number F = 1 are cyclically allocated, that is, the cluster serial numbers Cs = 1, 2, 3, 1, 2, 3,... It is. Similarly, each of the blocks having the block serial numbers Bs = 193, 194, 195, 196, 197, 198,..., 384 has the cluster serial numbers Cs = 4 to 6 included in the write group number F = 2. The clusters are allocated cyclically, that is, in the order of cluster serial numbers Cs = 4, 5, 6, 4, 5, 6,. Blocks after the block serial number Bs = 385 are also allocated to any cluster according to the same rule.

As a result of arranging the blocks as illustrated in FIG. 6, in the storage device 12, the data of the sectors corresponding to each of the two consecutive blocks is read / written in the memory modules 122 different from each other. In each memory module 122, data arranged in the same cluster is read and written at a time regardless of the block delimiter.

Reading and writing data according to the above-described rules is realized by address conversion processing of the control device 121 of the storage device 12. The address conversion process performed by the control device 121 is a data read / write target memory module 122 based on the top logical address of the read / write target data acquired from the host device 11 and the data size of the read / write target data. And a process of specifying a logical address of a storage destination of data to be read / written in the memory module 122.

FIG. 7 is a diagram showing a flow of processing performed when the storage device 12 receives a data write request from the host device 11. FIG. 8 is a diagram showing information used in the address conversion process of the control device 121 included in the process of the storage device 12 according to the flow shown in FIG. The write group number F, cluster serial number Cs, and block serial number Bs shown in FIG. 8 are the same as those illustrated in FIG. Cm shown in FIG. 8 is an in-module cluster number indicating the cluster position (order) in the memory module 122. Bc shown in FIG. 8 is an intra-cluster block number indicating the position (order) of blocks in the cluster. Bm shown in FIG. 8 is an in-module block number indicating the block position (order) in the memory module 122.

When the host device 11 makes a data write request to the storage device 12, the data to be written and the top logical address of the data to be written in the host device 11, that is, the sector serial number of the top sector (hereinafter referred to as sector serial number). Number Ss (S)) is output to the storage device 12. The acquisition unit 1211 of the control device 121 of the storage device 12 acquires the data to be written and the sector serial number Ss (S) output from the host device 11 (step S101). The data to be written acquired by the acquisition unit 1211 is temporarily stored in the storage unit 1212.

Based on the sector serial number Ss (S) acquired by the acquiring unit 1211 and the data size of the data to be written (hereinafter referred to as data size D), the instructing unit 1213 uses the sector serial number ( Hereinafter, the sector serial number Ss (E) is specified according to the following calculation formula. Here, s is the sector size.
Ss (E) = Ss (S) + D / s−1

Subsequently, the instructing unit 1213 sends the block serial number of the first block (hereinafter referred to as block serial number Bs (1)) and the block serial number of the end block (hereinafter referred to as block serial number Bs (z) )) Is specified according to the following calculation formula. Note that m is a block size, and RoundUp () is a function that rounds up the numerical value in ().
Bs (1) = RoundUp (Ss (S) / (m / s))
Bs (z) = RoundUp (Ss (E) / (m / s))

Subsequently, the instruction unit 1213 relates to the block corresponding to the data to be written, that is, for each of one or more blocks identified by the block serial numbers Bs (1) to Bs (z), the sector serial of the head sector of the block. The number is specified according to the following calculation formula. Bs (p) is the block serial number of the p-th block (p is a natural number satisfying 1 ≦ p ≦ z) of data to be written, and Ss (p) is the first sector serial number of the block.
Ss (p) = (m / s) × (Bs (p) −1) +1

Further, the instruction unit 1213 calculates the numbers in the blocks of the first sector and the last sector of the data to be written (hereinafter referred to as intra-block sector numbers Sb (S) and Sb (E)) according to the following calculation formula. Note that x% y indicates the remainder (remainder) obtained by dividing x by y.
Sb (S) = ((Ss (S) -1)% (m / s)) + 1
Sb (E) = ((Ss (E) -1)% (m / s)) + 1

Thus, the block corresponding to the data to be written, the position of the head sector in the head block, and the position of the tail sector in the tail block are specified (step S102).

Subsequently, the instruction unit 1213 assigns the write group number of the simultaneous write cluster group to which each block corresponding to the write target data is allocated, and the cluster number in the simultaneous write cluster group (hereinafter referred to as “group”). (Referred to as “internal cluster number”) according to the following calculation formula (step S103). F (p) is the write group number to which the p-th block is allocated, Cf (p) is the cluster number in the group to which the p-th block is allocated, and k is the number of blocks constituting one cluster. , J is the number of simultaneous writing modules.
F (p) = RoundUp (Bs (p) / (k × j))
Cf (p) = ((Bs (p) -1)% j) +1

Subsequently, the instruction unit 1213 identifies the cluster serial number of the cluster to which each block is allocated according to the following calculation formula (step S104). Cs (p) is the cluster serial number to which the p-th block is allocated.
Cs (p) = j × (F (p) −1) + Cf (p)

Subsequently, the instruction unit 1213 specifies the module serial number of the memory module 122 to which each block is allocated and the number (cluster number within the module) of the memory module 122 of the cluster to which each block is allocated according to the following calculation formula. (Step S105). Ms (p) is the module serial number of the p-th block, Cm (p) is the intra-module cluster number of the p-th block, and i is the number of memory modules 122 included in the storage device 12.
Ms (p) = ((Cs (p) -1)% i) +1
Cm (p) = RoundUp (Cs (p) / i)

Subsequently, the instructing unit 1213 specifies the block number (intra-cluster block number) in the cluster to which each block is allocated according to the following calculation formula (step S106). Bc (p) is the intra-cluster block number of the p-th block.
Bc (p) = RoundUp ((Bs (p) − (F (p) −1) × j × k) / j)

Subsequently, the instruction unit 1213 specifies the number (block number in the module) of each block in the memory module 122 according to the following calculation formula (step S107). Bm (p) is an in-module block number of the p-th block.
Bm (p) = (Cm (p) −1) × k + Bc (p)

Through the above processing, the correspondence and order of the memory module 122, the simultaneous writing cluster group, the cluster, and the block as illustrated in FIG. 8 are specified.

Subsequently, the instruction unit 1213 selects one simultaneous write cluster group in the order according to the write group number F from one or more simultaneous write cluster groups to which data to be written is allocated, and selects the selected simultaneous write For each of the j clusters belonging to the embedded cluster group, the in-module sector number Sm indicating the position in the memory module 122 of the first sector of the write target data included in the cluster is specified according to the following calculation formula (step S108). ). Bm is the block number in the module of the first block of the write target data included in the target cluster, and Sb is the sector number in the block of the first sector of the write target data included in the block.
Sm = (Bm−1) × (m / s) + Sb

Subsequently, the instruction unit 1213 issues a data write instruction in parallel to the j memory modules 122 to which the j clusters belonging to the simultaneous writing cluster group selected in step S108 are allocated (step S109). ). In step S109, the instruction unit 1213 delivers the in-module sector number Sm specified in step S108 to each of the memory modules 122 that are instructed to write data as the start address of the data writing destination. In addition, the instruction unit 1213 reads the portion of the write target data stored in the storage unit 1212 allocated to the cluster to be written in the order of the intra-cluster block number Bc, and stores it in the memory module 122 as the write target data. hand over.

Note that the start address of the write destination of the data handed over to the memory module 122 by the instruction means 1213 in step S109 is not limited to the intra-module sector number Sm as long as it is information indicating the data storage position in the memory module 122. For example, in the memory module 122, when data read / write is managed in a sector having a size different from the sector managed by the host device 11, the in-module sector number Sm is set to reflect the difference in the size of these sectors. A converted version may be used.

In step S109, the memory module 122 that has received the data write destination head address and data from the instruction unit 1213 writes the received data in the storage area starting from the received head address (step S110).

The control device 121 and the memory module 122 repeat the processing of the above-described steps S108 to S110 for each simultaneous write cluster group to which the write target data is allocated (step S111; No). When the processes in steps S108 to S110 are completed for all the simultaneous writing cluster groups to which the data to be written is allocated (step S111; Yes), the storage device 12 completes a series of data writing processes.

The above is the processing performed when the storage device 12 writes data in response to a request from the host device 11.

Subsequently, processing performed when the storage device 12 receives a data read request from the host device 11 will be described. FIG. 9 is a diagram illustrating a flow of processing performed when the storage device 12 receives a data read request from the host device 11. The processing of the storage device 12 in data reading is partly in common with the processing of the storage device 12 in data writing. In FIG. 9, the same step numbers as those used in the flow of FIG. 7 are used for the processes common to the processes in the flow shown in FIG.

When the host device 11 makes a data read request to the storage device 12, the head logical address of the data to be read in the host device 11, that is, the sector serial number Ss (S) of the head sector, and the data to be read Is output to the storage device 12. The acquisition unit 1215 of the control device 121 of the storage device 12 acquires the sector serial number Ss (S) and the data size D from the host device 11 (step S201).

Subsequently, the reading unit 1216 performs processing similar to steps S102 to S107 performed by the instruction unit 1213 in the data writing processing based on the sector serial number Ss (S) and the data size D acquired from the host device 11, and performs reading. For each block corresponding to the target data, the module serial number Ms of the memory module 122 storing the block, the intra-module cluster number Cm of the cluster including the block, the intra-cluster block number Bc of the block, the block The module serial number Ms for storing the cluster including the block serial number Bs of the block is specified.

Subsequently, the reading unit 1216 reads each of the memory modules 122 identified by the module serial number Ms specified by the reading unit 1216 from the cluster included in the cluster identified by the intra-module cluster number Cm specified by the reading unit 1216. An instruction to read the target data is issued, and data delivered from the memory module 122 is acquired in accordance with the read instruction (step S202). The reading unit 1216 temporarily stores the data acquired from the memory module 122 in the storage unit 1217. At that time, the reading unit 1216 stores the data acquired from the memory module 122 in the storage area of the storage unit 1217 corresponding to the block serial number Bs. As a result, the data temporarily stored in the storage unit 1217 is data rearranged so that the sector serial numbers are continuous.

In step S202, the reading unit 1216 reads data from each of the i memory modules 122 in parallel.

The reading unit 1216 repeats the process of step S202 for all clusters including the data to be read until reading of the data to be read included in the cluster is completed (step S203; No). When reading of all the data to be read is completed by the reading unit 1216 (step S203; Yes), the transfer unit 1218 transfers the data to be read stored in the storage unit 1217 to the host device 11 (step S204).

The processing described above is performed when the storage device 12 reads data in response to a request from the host device 11.

According to the data storage system 1, data reading / writing according to a request from the host device 11 is performed in parallel in the plurality of memory modules 122, so that data reading / writing speed by memory interleaving can be increased. At the same time, according to the data storage system 1, reading and writing of data in the memory module 122 is performed with a data size larger than that of a block that is a unit of data division in memory interleaving. Therefore, latency due to overhead associated with reading and writing data in the memory module 122 can be reduced. As a result, high-speed data reading / writing is realized as a whole.

[Second Embodiment]
A data storage system 2 according to another embodiment of the present invention will be described below. The data storage system 2 is common in many respects to the data storage system 1 according to the first embodiment. Accordingly, the following description will mainly focus on differences between the data storage system 2 and the data storage system 1, and description of points common to the data storage system 2 will be omitted as appropriate.

FIG. 10 is a diagram showing the configuration of the data storage system 2. In FIG. 10, among the components included in the data storage system 2, the same reference numerals as those used in the data storage system 1 are used for the components common to the components included in the data storage system 1. The data storage system 2 includes a host device 11 and a storage device 22.

The storage device 22 includes a control device 121, (h × n) memory modules 122, and data buses 123 (1) to 123 (h) for connecting the control device 121 and the memory modules 122. n is a natural number of 2 ≦ n. N memory modules 122 are connected to each of the data buses 123 (1) to 123 (h). As shown in FIG. 10, n memory modules 122 connected to the data bus 123 (q) are assumed to be memory modules 122 (q) (1) to 122 (q) (n).

While the control device 121 performs data read / write processing with any one of the n memory modules 122 connected to one data bus 123, the control device 121 uses the same data bus 123. Data read / write processing cannot be performed with another memory module 122 connected thereto. However, the control device 121 can perform data read / write processing in parallel with a plurality of memory modules 122 connected to different data buses 123.

11A and 11B (hereinafter, these diagrams are collectively referred to as FIG. 11), the positions of clusters arranged in (h × n) memory modules 122 in the storage device 22 are represented as h = 4, n = It is the figure illustrated regarding the case of 3. FIG. As shown in FIG. 11, the module serial number Ms is cyclically allocated to the (h × n) memory modules 122 between the data buses 123 (1) to (h). For example, when h = 4 and n = 3, as shown in FIG. 11, the memory modules 122 (1) (1), 122 (2) (1), 122 (3) (1), 122 (4) (1), 122 (2) (1), 122 (2) (2), 122 (3) (2), 122 (4) (2), 122 (1) (3),. A module serial number Ms is assigned.

In the storage device 22, clusters are cyclically allocated according to the order of module serial numbers. For example, when h = 4 and n = 3, as shown in FIG. 11, module serial numbers Ms = 1, 2, 3, 4,..., 11, 12, 1, 2,. The cluster serial number Cs is assigned to the memory module 122 in order from 1 so that the cluster serial number Cs = 1, 2, 3, 4,..., 11, 12, 13, 14,.

12A and 12B (hereinafter, these figures are collectively referred to as FIG. 12), the positions of blocks arranged in (h × n) memory modules 122 in the storage device 22 are represented as h = 4, n = 3 is a diagram illustrating a case where j = 3. Note that j is the number of simultaneous writing modules. As shown in FIG. 12, according to the order of the cluster serial number Cs, j clusters from the first cluster are made one simultaneous write cluster group, and the simultaneous write class tab loops are written sequentially. Group number F is assigned. Then, blocks are cyclically allocated to j clusters belonging to the same simultaneous writing cluster group. The rule of block allocation for this cluster is the same as the rule in the storage device 12.

13A and 13B show the write group number F, cluster serial number Cs, and block serial number Bs shown in FIG. 12, and the corresponding intra-module cluster number Cm, intra-cluster block number Bc, and intra-module block number. It is the figure which showed Bm.

In the data storage system 2, the processing in which the storage device 22 writes data in response to a request from the host device 11 is compared with the processing in the data storage system 1 shown in FIG. It is the same except that the equations are different. Further, in the data storage system 2, the processing in which the storage device 22 reads data in response to a request from the host device 11 is similar to the processing in the data storage system 1 shown in FIG. This is the same except that the calculation formula used in is different.

In the data storage system 2, the instruction unit 1213 (when writing data) or the reading unit 1216 (when reading data), in step S <b> 105, according to the following calculation formula, each block corresponding to the data to be written or read. The module serial number Ms (p) of the allocation destination memory module 122 and the intra-module cluster number Cm (p) of the allocation destination cluster of each block are specified.
Ms (p) = ((Cs (p) −1)% (h × n)) + 1
Cm (p) = RoundUp (Cs (p) / (h × n))

As with the data storage system 1 according to the first embodiment, the data storage system 2 having the above configuration also realizes high-speed data reading and writing as a whole. In the storage device 22 included in the data storage system 2, the ratio of the number of data buses to the number of memory modules is smaller than that of the storage device 12 included in the data storage system 1. Therefore, according to the configuration included in the storage device 22, the storage capacity can be increased at a lower cost than the configuration included in the storage device 12.

[Modification]
The above-described embodiments can be variously modified within the scope of the technical idea of the present invention. Examples of these modifications are shown below. Note that two or more of the above-described embodiments and the following modifications may be combined as appropriate.

(1) In the above-described embodiment, the memory module 122 includes the memory controller 1221, and the memory controller 1221 manages data reading / writing with respect to the memory chip 1222. Instead, a configuration in which the control device 121 directly manages data read / write in the memory module 122 may be employed. In this modification, the control device 121 converts a logical address indicating a data storage position in the memory module 122 into a physical address, and then writes data to the storage position specified by the physical address or specifies the physical address. The data is read from the storage position.

(2) In the description of the first embodiment described above, the case where the number j of the memory modules 122 into which the storage device 12 simultaneously writes data is smaller than the number i of the memory modules 122 included in the storage device 12 will be described as an example. However, j = i may be used. In the description of the second embodiment, the case where the number j of the memory modules 122 to which the storage device 12 simultaneously writes data is smaller than the number h of the data buses 123 included in the storage device 12 will be described as an example. Although done, j = h may be sufficient.

(3) In the description of the above-described embodiment, the physical arrangement of the memory module 122 is not particularly referred to. The physical arrangement of the memory modules 122 is not limited by the module serial number assigned to the memory modules.

(4) A configuration in which mirroring is performed when the storage device 12 (first embodiment) or the storage device 22 (second embodiment) writes data in response to a request from the host device 11 may be employed. FIG. 14 is a diagram illustrating, as an example, the correspondence relationship between the simultaneous writing cluster group, the cluster, and the block when i = 4 and j = 3 when the storage device 12 according to the first embodiment performs mirroring. It is.

(5) In the above-described embodiment, the allocation of clusters and blocks to the memory module 122 is performed cyclically. The cyclic allocation of clusters and blocks is an example of a method for allocating two consecutive blocks to different memory modules 122, and the present invention is not limited in this respect. That is, any other method may be adopted as long as a plurality of blocks are allocated between the plurality of memory modules 122 so that two consecutive blocks are not allocated to the same memory module 122.

(6) In the above-described embodiment, the control device 121 has a sector (address in the host device 11) managed by the host device 11, and the storage device 12 (first embodiment) or the storage device 22 (second embodiment). The correspondence relationship with the storage areas (addresses in the storage device 12) in the plurality of memory modules 122 managed in is determined by calculation based on the sector size, block size, cluster size, number of simultaneous writing modules, and the like. The method by which the control device 121 specifies the correspondence between addresses in each of the host device 11 and the storage device 12 or 22 is not limited to a calculation method. For example, there is a method in which the control device 121 stores a table showing the correspondence between the address in the host device 11 and the address in the storage device 12 or 22 and specifies the correspondence between these addresses by referring to the table. It may be adopted.

(7) In the second embodiment described above, the number of memory modules 122 connected to each of the plurality of data buses 123 included in the storage device 22 is the same (n). The number of memory modules 122 connected to each of the plurality of data buses 123 included in the storage device 22 may be different. In this case, the control device 121 stores, for example, a table indicating clusters belonging to the simultaneous writing cluster group, and identifies the memory module 122 that performs data reading / writing in parallel by referring to the table.

(8) In the above-described embodiment, the control device 121 instructs each memory module 122 to read / write data allocated to the same cluster at a time, and reads / writes data allocated to different clusters individually. Instruct. The upper limit value of the data that the control device 121 instructs the memory modules 122 to read / write at a time is not limited to the cluster size, and it is permitted to instruct the memory modules 122 to read / write data having a size exceeding the cluster size at a time. The structure to do may be employ | adopted.

(9) In the embodiment described above, the sector corresponding to the block is uniquely specified by the sector serial number. Instead of this, for example, a configuration may be adopted in which the control device 121 allocates a predetermined number of sectors to blocks in order from the first sector of data to be written acquired from the host device 11. In this case, for example, the control device 121 records the correspondence relationship between the sector and the block in accordance with the data write instruction, and identifies the block in which the data to be read is stored with reference to the table when reading the data. .

(10) In the embodiment described above, when the instruction unit 1213 instructs to write data in step S109 (FIG. 7), the instruction unit 1213 sends the data to be written to the memory module 122 to each of the designated memory modules 122. The data is read out in the order of the block number Bc in the cluster, and sequentially transferred to the memory module 122 that is the instruction destination. As a result, the rearrangement of the write target data in units of blocks is performed simultaneously with the data write instruction. The timing of the data rearrangement process in units of blocks in the data write may not be the same as the write instruction. For example, after the instruction unit 1213 rearranges the data in units of blocks in the storage unit 1212 prior to the data write instruction, the rearranged data is read from the storage unit 1212 and the instruction destination memory module 122 is read out. A configuration of handing over may be adopted.

(11) In the embodiment described above, when the reading unit 1216 reads data in step S202 (FIG. 9), the reading unit 1216 stores the data acquired from the reading source memory module 122 in the storage unit 1217 according to the block serial number Bs. Store in the storage area. As a result, rearrangement of data acquired from the memory module 122 in units of blocks is performed simultaneously with temporary storage of the data in the storage unit 1217. The timing of the data rearrangement process in units of blocks in the data reading may not be simultaneous with the temporary storage in the storage unit 1217. For example, when the reading unit 1216 stores the data acquired from the memory module 122 in the storage unit 1217 in the order of acquisition, the transfer unit 1218 delivers the read target data to the host device 11 in step S204 (FIG. 9). A configuration may be employed in which data is read from the storage unit 1217 in the order of the block serial number Bs and delivered to the host device 11. Further, the reading unit 1216 stores the data acquired from the memory module 122 in the storage unit 1217 in the order of acquisition, and before the transfer unit 1218 delivers the data to be read to the host device 11 in step S204 (FIG. 9), the reading unit 1217 A configuration may be employed in which the storage unit 1217 rearranges the data to be read in the order of the block serial number Bs in the storage unit 1217.

DESCRIPTION OF SYMBOLS 1 ... Data storage system, 2 ... Data storage system, 11 ... Host device, 12 ... Storage device, 22 ... Storage device, 121 ... Control device, 122 ... Memory module, 123 ... Data bus, 1211 ... Acquisition means, 1212 ... Storage Means, 1213 ... Instruction means, 1215 ... Acquisition means, 1216 ... Reading means, 1217 ... Storage means, 1218 ... Delivery means, 1221 ... Memory controller, 1222 ... Memory chip

Claims (8)

1. A control device capable of instructing reading / writing of data in parallel to a plurality of memory modules of i (i is a natural number satisfying 2 ≦ i),
   An acquisition means for acquiring data to be written;
   Storage means for temporarily storing the data to be written;
   When the data unit obtained by dividing the data into predetermined data sizes for each m is a block, the write target data temporarily stored in the storage means is a memory in which two consecutive blocks are different from each other Each of the i memory modules is allocated to j memory modules (j is a natural number satisfying 2 ≦ j ≦ i), and writing of the allocated data is assigned to each of the allocated memory modules. A control device comprising: instruction means for performing processing for instructing at a time on j memory modules in parallel.
2. The acquisition unit acquires a logical address of the data to be written,
   The instruction means includes a logical address acquired by the acquisition means, m which is the data size of the block, j which is the number of memory modules which the instruction means instructs to write data in parallel, and the total number of memory modules. Based on a certain i, according to a predetermined rule, the memory module to which the data to be written is allocated, the address to which the data to be written in the memory module to be allocated is specified, and the memory to which the data to be written is allocated The control device according to claim 1, wherein the controller instructs the module to write data at the specified write destination address.
3. When the instruction unit sets a cluster of k blocks (k is a natural number satisfying 2 ≦ k) as a cluster, the write target data temporarily stored in the storage unit is stored in the i memory modules. Allocation in cluster units and instruct to write data allocated to j memory modules (j is a natural number satisfying 2 ≦ j <i) selected according to a predetermined rule from the i memory modules in parallel The control device according to claim 1.
4. The acquisition unit acquires a logical address of the data to be written,
   The instruction means is included in the cluster, the logical address acquired by the acquisition means, m that is the data size of the block, j that is the number of memory modules that the instruction means instructs to write data in parallel. Based on k which is the number of blocks and i which is the total number of memory modules, the memory module to which the data to be written is allocated and the address to which the data is written in the memory module to which the data is to be written are specified according to a predetermined rule. The control device according to claim 3, wherein the controller instructs the memory module to which the write target data is allocated to write data at the specified write destination address.
5. Each of the i memory modules is connected to one of h data buses (h is a natural number satisfying 2 ≦ h <i),
   The instruction means assigns data to j memory modules (j is a natural number satisfying 2 ≦ j ≦ h) selected so as not to include two or more memory modules connected to the same data bus. The control device according to claim 1, wherein the writing is instructed in parallel.
6. Each of the h data buses is connected with n (n is a natural number satisfying 2 ≦) memory modules,
   The instruction means is based on j, which is the number of memory modules that the instruction means instructs to write data in parallel, and n, which is the number of memory modules connected to one data bus, according to a predetermined rule, The control device according to claim 5, wherein j memory modules instructing data writing are selected in parallel.
7. A processor capable of instructing reading / writing of data to a plurality of memory modules in i (i is a natural number satisfying 2 ≦ i) in parallel,
   Processing to get the data to write,
   A process of temporarily storing the data to be written in a storage means;
   When the data unit obtained by dividing the data into predetermined data sizes for each m is a block, the write target data temporarily stored in the storage means is a memory in which two consecutive blocks are different from each other Allocate to j memory modules (j is a natural number satisfying 2 ≦ j ≦ i) among the i memory modules, and write the allocated data to the allocation destination memory module so as to be allocated to the modules. A program that executes processing for instructing at a time on j memory modules in parallel.
8. i memory modules (i is a natural number satisfying 2 ≦ i);
   A control device capable of instructing reading / writing of data in parallel to a plurality of memory modules of the i memory modules,
   The controller is
   An acquisition means for acquiring data to be written;
   Storage means for temporarily storing the data to be written;
   When the data unit obtained by dividing the data into predetermined data sizes for each m is a block, the write target data temporarily stored in the storage means is a memory in which two consecutive blocks are different from each other Allocate to j memory modules (j is a natural number satisfying 2 ≦ j ≦ i) among the i memory modules, and write the allocated data to the allocation destination memory module so as to be allocated to the modules. Instructing means for performing processing instructed at a time for j memory modules in parallel.

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