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WO2016024180A1 - Alloy stud bump interconnects for semiconductor devices - Google Patents

Alloy stud bump interconnects for semiconductor devices Download PDF

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Publication number
WO2016024180A1
WO2016024180A1 PCT/IB2015/055706 IB2015055706W WO2016024180A1 WO 2016024180 A1 WO2016024180 A1 WO 2016024180A1 IB 2015055706 W IB2015055706 W IB 2015055706W WO 2016024180 A1 WO2016024180 A1 WO 2016024180A1
Authority
WO
WIPO (PCT)
Prior art keywords
bonding wire
alloy
wire
capillary
semiconductor device
Prior art date
Application number
PCT/IB2015/055706
Other languages
French (fr)
Inventor
Aik Hoe Sean NG
Cheng Hou LOH
Original Assignee
Koninklijke Philips N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips N.V. filed Critical Koninklijke Philips N.V.
Publication of WO2016024180A1 publication Critical patent/WO2016024180A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/742—Apparatus for manufacturing bump connectors
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/781—Means for controlling the bonding environment, e.g. valves, vacuum pumps
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H01L2224/81207—Thermosonic bonding
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls

Definitions

  • This invention relates to the field of semiconductor manufacture, and in particular to a method and system for creating alloyed stud bumps for attaching a semiconductor device to a substrate.
  • a thin wire (bonding wire) is fed through a capillary, and a high voltage electric charge is applied to the wire, which melts the wire at the capillary.
  • the tip of the wire forms into a ball shape because of the surface tension of the molten metal.
  • the capillary is lowered to the surface of the contact pad on the semiconductor device, which is typically heated to at least 125°C.
  • the bonding machine pushes the capillary down and applies ultrasonic energy. The combination of heat, pressure, and ultrasonic energy creates a weld between the ball at the tip of the wire and the contact pad on the semiconductor device.
  • the capillary, with the wire, is then placed above the contact pad on the leadframe or substrate, and lowered to crush the wire into the contact pad.
  • a combination of heat, pressure, and ultrasonic energy is applied to weld the wire to this second contact pad.
  • the wire at the capillary is cut, leaving the length of wire between the two contact pads.
  • a "stud bump” is formed on that contact pad.
  • a plurality of stud bumps may be arranged on conductive paths on a substrate, in a pattern that corresponds to the location of contact pads on the semiconductor device.
  • the contact pads of the semiconductor device may be placed upon these stud bumps and ultrasonically welded to the stud bumps.
  • Gold is commonly used as the bonding wire material due to its superior malleability and reliability. Copper, being less expensive, may also be used; but, because it is harder than gold, creating the welds often damages the contact pads.
  • a predominantly silver (Ag) alloy is used as a bonding wire or stud bump material.
  • This alloy may include gold (Au) and/or palladium (Pd).
  • Au gold
  • Pd palladium
  • an inert atmosphere is maintained at the vicinity of the capillary.
  • a continuous flow of nitrogen or a nitrogen compound may provide this inert atmosphere, and may assist in the formation of a "Free- Air- Ball” (FAB) when the high voltage is applied to the wire.
  • FAB Free- Air- Ball
  • FIGs. 1 A-ID illustrate an example semiconductor device and submount with stud bumps.
  • FIGs. 2A-2D illustrate example capillaries with an air-flow device.
  • FIGs. 3A-3B illustrate the example semiconductor device mounted on the example submount via the stud bumps.
  • FIGs. 1A-1D illustrate views of an example semiconductor device 100 and submount 150.
  • FIGs. 1A and IB illustrate a top-view and side-view of the example semiconductor device 100
  • FIGs. 1C and ID illustrate a top-view and side-view of the example submount, respectively.
  • the example semiconductor device 100 includes two contact pads 110, on one side, the 'bottom', of the semiconductor device 100.
  • the semiconductor device 100 may be, for example, a light emitting device, wherein light is emitted from the other side, opposite the bottom, i.e. the upper surface of the semiconductor device 100, when voltage is applied across these contact pads 110.
  • the device 100 may be an integrated circuit, with many contact pads 110.
  • the example submount 150 may be a ceramic base, or other substrate that provides structural support to the semiconductor device 100.
  • Conductive traces 160 are situated on the submount, and are intended to allow connectivity to the contact pads 110 of the semiconductor device 100.
  • the traces 160 provide a contact area 165 for external connection to the contact pads 110.
  • the term 'submount' is used herein in its general form, and includes any surface that provides support to conductive traces that are to be bonded to the semiconductor device 100.
  • the conductive traces may be self-supporting, in which case the self-supporting conductor forms the submount, and the surface layer of the conductor forms the conductive trace that is bonded to the semiconductor device.
  • the terms 'conductive traces' and 'contact pads' are used synonymously, each defining a conductive element on either the submount or the semiconductor device, the term 'conductive traces' being used herein for ease of illustration and understanding when specifically referring to the contact pad on the submount.
  • Stud bumps 170 are situated on the traces 160 to facilitate electrical connection to the contact pads 110 of the semiconductor device 100. These stud bumps 170 are formed using bond wire comprising an alloy having a substantial amount of silver (Ag), thereby reducing the amount of gold (Au) that would be used for conventional stud bumps. Silver may cost less than 1/50 the cost of gold; consequently, the material cost of providing the stud bumps 170 is substantially reduced.
  • the alloy may be a silver and palladium (Pd) combination, or a silver, palladium, and gold combination.
  • the alloy includes silver at least 50wt%, and may include as much as 95wt%.
  • the gold content of the alloy may be below 20wt%, preferably below 10%.
  • the palladium content of the alloy may be at least 3wt%. With an alloy formed within the above concentrations, the electrical performance of the alloy after being bonded to the contact pads 110 is comparable to gold.
  • FIG. 2A illustrates an example capillary 220 for creating the stud bumps 170 of
  • the silver alloy bonding wire 210 is fed through the capillary 220, with a short length 'tail' extending beyond the tip 225 of the capillary 220.
  • the length of the tail may be between 8 and 20 mil, although the length may be outside this range, depending upon the wire size.
  • a high-voltage electric charge is applied to the wire, above a ground plane, causing the tail to melt. Due to the surface tension of the melted wire, a ball 270 is formed.
  • the capillary 220 forces the ball 270 onto the conductive strip 160, which is preferably heated to at least 125°C.
  • the conductive strip 160 may be copper or gold, or a combination of both, or any suitable conductor.
  • a silver or silver alloy may be used to form or plate at least the portion of the conductive strip 160 that receives the ball 270. While pressing the ball 270 upon the conductive strip 160, ultrasonic energy is applied with an attached transducer (not illustrated). The combined pressure, heat, and ultrasonic energy causes the ball 270 to be securely bonded to the conductive strip 160.
  • a small amount of wire 210 is fed out of the capillary, and the wire 210 is cut at the ball 270, thereby forming the stud bump 170 of FIGs. 1C-1D.
  • the small amount of wire 210 that is fed out of the capillary 220 forms the wire tail to create the next ball 270.
  • the capillary 220 is then situated over the next intended location for a stud bump, and the process is repeated. This relocation may be accomplished by moving the capillary 220, or moving the base 250 upon which the submount 150 is situated.
  • the alloy is predominantly silver, the alloy will be more susceptible to oxidation and hydrolysis reactions than gold. To prevent the formation of defective stud bumps, an inert atmosphere is provided during the formation process.
  • an airflow device 230 is provided to provide a continuous flow 240 of inert gas, such as N 2 , or H2N2, or any other inert gas, as the stud bumps are being formed.
  • This airflow device 230 is attached to the capillary 220 at a given orientation, so that the flow 240 of inert gas is always toward the tip 225 of the capillary 220 and/or the trace 160.
  • the quantity of flow 240 should be sufficient to displace any other gases from the vicinity of the tip 225 and trace 160.
  • the flow may be, for example, about 1 liter per minute directed on the ball 270 at the tip of the capillary.
  • Capillary 220 and airflow device 230 are typically tubular devices with a circular cross section, other cross suitable cross sections such as elliptical are contemplated and included within the scope of the invention.
  • FIGs. 2B and 2C illustrate a different arrangement of the airflow device 230 and the capillary 220.
  • the capillary 220 is situated within the annulus of airflow device 230, and the flow 240 surrounds the capillary 220 in the space 235 between the airflow device 230 and the capillary 220.
  • the example capillary 220 projects out from the airflow device 230, other arrangements such a capillary 220 recessed within airflow device 230 are contemplated and are included within the scope of the invention.
  • the airflow device 230 may provide a flow 240 that is sufficient to provide an inert atmosphere over the entire submount 150, eliminating the need to move the airflow device 230 as the capillary 220 is moved over the surface of the submount 150.
  • FIGs. 3A-3B illustrate an example component comprising a semiconductor device 100 bonded to a submount 150 via a silver alloy stud bump 170 that bonds the contact pads 110 of the semiconductor device 100 to the conductive traces 160 on the submount 150 using the above described process.
  • the bonding of stud bump 170 onto the submount 150 may be performed by the capillary, whereby downward pressure of at least 0.5 newtons and ultrasonic energy is applied simultaneously.
  • the submount may be heated at a temperature above 125°C, and preferably above 150°C to improve the bond.
  • the bonding of semiconductor device 100 may be performed by heating the contacts 110 of the semiconductor device 100, heating the stud bump through the submount at a temperature above 175°C, applying downward pressure of at least 30 newtons on the semiconductor device 100 (and consequently the stud bump 170), and applying ultrasonic energy via a conventional bonding nozzle to create the bond.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A predominantly silver alloy is used as a bonding wire or stud bump material. This alloy may include gold and/or palladium. To avoid oxidation and hydrolysis reactions during the welding process, an inert atmosphere is maintained at the vicinity of the capillary that forms the stud bump. A continuous flow of nitrogen or a nitrogen compound may provide this inert atmosphere, and may assist in the formation of a "Free- Air-Ball" (FAB) when the high voltage is applied to the wire.

Description

ALLOY STUD BUMP INTERCONNECTS FOR SEMICONDUCTOR DEVICES
FIELD OF THE INVENTION
This invention relates to the field of semiconductor manufacture, and in particular to a method and system for creating alloyed stud bumps for attaching a semiconductor device to a substrate.
BACKGROUND OF THE INVENTION
Semiconductor devices are often electrically connected to a leadframe or substrate using "ball bonding" techniques. A thin wire (bonding wire) is fed through a capillary, and a high voltage electric charge is applied to the wire, which melts the wire at the capillary. The tip of the wire forms into a ball shape because of the surface tension of the molten metal. The capillary is lowered to the surface of the contact pad on the semiconductor device, which is typically heated to at least 125°C. The bonding machine pushes the capillary down and applies ultrasonic energy. The combination of heat, pressure, and ultrasonic energy creates a weld between the ball at the tip of the wire and the contact pad on the semiconductor device.
The capillary, with the wire, is then placed above the contact pad on the leadframe or substrate, and lowered to crush the wire into the contact pad. A combination of heat, pressure, and ultrasonic energy is applied to weld the wire to this second contact pad. The wire at the capillary is cut, leaving the length of wire between the two contact pads.
If the bonding wire is cut immediately after being placed on a single contact pad, a "stud bump" is formed on that contact pad. A plurality of stud bumps may be arranged on conductive paths on a substrate, in a pattern that corresponds to the location of contact pads on the semiconductor device. The contact pads of the semiconductor device may be placed upon these stud bumps and ultrasonically welded to the stud bumps.
Gold is commonly used as the bonding wire material due to its superior malleability and reliability. Copper, being less expensive, may also be used; but, because it is harder than gold, creating the welds often damages the contact pads. SUMMARY OF THE INVENTION
It would be advantageous to provide a less costly alternative to the use of gold bonding wire or gold stud bumps. It would also be advantageous if this alternative material exhibits similar electrical and mechanical properties to gold.
To better address one or more of these concerns, in an embodiment of this invention, a predominantly silver (Ag) alloy is used as a bonding wire or stud bump material. This alloy may include gold (Au) and/or palladium (Pd). To avoid oxidation and hydrolysis reactions during the welding process, an inert atmosphere is maintained at the vicinity of the capillary. A continuous flow of nitrogen or a nitrogen compound (N2 or H2N2) may provide this inert atmosphere, and may assist in the formation of a "Free- Air- Ball" (FAB) when the high voltage is applied to the wire.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein:
FIGs. 1 A-ID illustrate an example semiconductor device and submount with stud bumps. FIGs. 2A-2D illustrate example capillaries with an air-flow device.
FIGs. 3A-3B illustrate the example semiconductor device mounted on the example submount via the stud bumps.
Throughout the drawings, the same reference numerals indicate similar or corresponding features or functions. The drawings are included for illustrative purposes and are not intended to limit the scope of the invention.
DETAILED DESCRIPTION
In the following description, for purposes of explanation rather than limitation, specific details are set forth such as the particular architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the concepts of the invention.
However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments, which depart from these specific details. In like manner, the text of this description is directed to the example embodiments as illustrated in the Figures, and is not intended to limit the claimed invention beyond the limits expressly included in the claims. For purposes of simplicity and clarity, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
FIGs. 1A-1D illustrate views of an example semiconductor device 100 and submount 150. FIGs. 1A and IB illustrate a top-view and side-view of the example semiconductor device 100, and FIGs. 1C and ID illustrate a top-view and side-view of the example submount, respectively.
The example semiconductor device 100 includes two contact pads 110, on one side, the 'bottom', of the semiconductor device 100. The semiconductor device 100 may be, for example, a light emitting device, wherein light is emitted from the other side, opposite the bottom, i.e. the upper surface of the semiconductor device 100, when voltage is applied across these contact pads 110. Alternatively, the device 100 may be an integrated circuit, with many contact pads 110.
The example submount 150 may be a ceramic base, or other substrate that provides structural support to the semiconductor device 100. Conductive traces 160 are situated on the submount, and are intended to allow connectivity to the contact pads 110 of the semiconductor device 100. In this example, the traces 160 provide a contact area 165 for external connection to the contact pads 110. The term 'submount' is used herein in its general form, and includes any surface that provides support to conductive traces that are to be bonded to the semiconductor device 100. In some embodiments, such as a leadframe embodiment, the conductive traces may be self-supporting, in which case the self-supporting conductor forms the submount, and the surface layer of the conductor forms the conductive trace that is bonded to the semiconductor device. In like manner, the terms 'conductive traces' and 'contact pads' are used synonymously, each defining a conductive element on either the submount or the semiconductor device, the term 'conductive traces' being used herein for ease of illustration and understanding when specifically referring to the contact pad on the submount.
Stud bumps 170 are situated on the traces 160 to facilitate electrical connection to the contact pads 110 of the semiconductor device 100. These stud bumps 170 are formed using bond wire comprising an alloy having a substantial amount of silver (Ag), thereby reducing the amount of gold (Au) that would be used for conventional stud bumps. Silver may cost less than 1/50 the cost of gold; consequently, the material cost of providing the stud bumps 170 is substantially reduced.
The alloy may be a silver and palladium (Pd) combination, or a silver, palladium, and gold combination. Preferably, the alloy includes silver at least 50wt%, and may include as much as 95wt%. The gold content of the alloy may be below 20wt%, preferably below 10%. The palladium content of the alloy may be at least 3wt%. With an alloy formed within the above concentrations, the electrical performance of the alloy after being bonded to the contact pads 110 is comparable to gold. FIG. 2A illustrates an example capillary 220 for creating the stud bumps 170 of
FIGs. 1C-1D. The silver alloy bonding wire 210 is fed through the capillary 220, with a short length 'tail' extending beyond the tip 225 of the capillary 220. The length of the tail may be between 8 and 20 mil, although the length may be outside this range, depending upon the wire size. A high-voltage electric charge is applied to the wire, above a ground plane, causing the tail to melt. Due to the surface tension of the melted wire, a ball 270 is formed. The capillary 220 forces the ball 270 onto the conductive strip 160, which is preferably heated to at least 125°C. The conductive strip 160 may be copper or gold, or a combination of both, or any suitable conductor. To optimize the bonding of the silver alloy ball 270 to the conductive strip, a silver or silver alloy may be used to form or plate at least the portion of the conductive strip 160 that receives the ball 270. While pressing the ball 270 upon the conductive strip 160, ultrasonic energy is applied with an attached transducer (not illustrated). The combined pressure, heat, and ultrasonic energy causes the ball 270 to be securely bonded to the conductive strip 160. After bonding, a small amount of wire 210 is fed out of the capillary, and the wire 210 is cut at the ball 270, thereby forming the stud bump 170 of FIGs. 1C-1D. The small amount of wire 210 that is fed out of the capillary 220 forms the wire tail to create the next ball 270. The capillary 220 is then situated over the next intended location for a stud bump, and the process is repeated. This relocation may be accomplished by moving the capillary 220, or moving the base 250 upon which the submount 150 is situated.
Because the alloy is predominantly silver, the alloy will be more susceptible to oxidation and hydrolysis reactions than gold. To prevent the formation of defective stud bumps, an inert atmosphere is provided during the formation process.
As illustrated in FIG. 2A, an airflow device 230 is provided to provide a continuous flow 240 of inert gas, such as N2, or H2N2, or any other inert gas, as the stud bumps are being formed. This airflow device 230 is attached to the capillary 220 at a given orientation, so that the flow 240 of inert gas is always toward the tip 225 of the capillary 220 and/or the trace 160. The quantity of flow 240 should be sufficient to displace any other gases from the vicinity of the tip 225 and trace 160. The flow may be, for example, about 1 liter per minute directed on the ball 270 at the tip of the capillary. Capillary 220 and airflow device 230 are typically tubular devices with a circular cross section, other cross suitable cross sections such as elliptical are contemplated and included within the scope of the invention. FIGs. 2B and 2C illustrate a different arrangement of the airflow device 230 and the capillary 220. In this arrangement, the capillary 220 is situated within the annulus of airflow device 230, and the flow 240 surrounds the capillary 220 in the space 235 between the airflow device 230 and the capillary 220. Although the example capillary 220 projects out from the airflow device 230, other arrangements such a capillary 220 recessed within airflow device 230 are contemplated and are included within the scope of the invention.
Still other configurations of the airflow device 230 and the capillary 220 are also feasible. For example, as illustrated in FIG. 2D the airflow device 230 may provide a flow 240 that is sufficient to provide an inert atmosphere over the entire submount 150, eliminating the need to move the airflow device 230 as the capillary 220 is moved over the surface of the submount 150.
FIGs. 3A-3B illustrate an example component comprising a semiconductor device 100 bonded to a submount 150 via a silver alloy stud bump 170 that bonds the contact pads 110 of the semiconductor device 100 to the conductive traces 160 on the submount 150 using the above described process. The bonding of stud bump 170 onto the submount 150 may be performed by the capillary, whereby downward pressure of at least 0.5 newtons and ultrasonic energy is applied simultaneously. The submount may be heated at a temperature above 125°C, and preferably above 150°C to improve the bond.
The bonding of semiconductor device 100 may be performed by heating the contacts 110 of the semiconductor device 100, heating the stud bump through the submount at a temperature above 175°C, applying downward pressure of at least 30 newtons on the semiconductor device 100 (and consequently the stud bump 170), and applying ultrasonic energy via a conventional bonding nozzle to create the bond.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. For example, even though the above description discloses that the stud bumps are formed on the submount, it is possible to operate the invention in an embodiment wherein the stud bumps are formed on the semiconductor device. The term 'contact pad' as used in the claims include contact elements on either the semiconductor device or the submount.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:
1. A method of welding a bonding wire to a contact pad comprising:
feeding the bonding wire through a capillary;
applying a high voltage to the bonding wire, to melt a tip of the bonding wire at the capillary;
pressing the tip of the bonding wire upon the contact pad; and
applying ultrasonic energy to weld the bonding wire to the contact pad;
characterized in that:
the bonding wire comprises an alloy of at least 50% silver, and the method includes providing an inert atmosphere about the tip of the wire and the contact pad when the ultrasonic energy is applied.
2. The method of claim 1, wherein the inert atmosphere is provided about the tip of the wire when the high voltage is applied to the bonding wire.
3. The method of claim 1, wherein the inert atmosphere is provided by providing a continuous flow of an inert gas.
4. The method of claim 1, wherein the inert atmosphere comprises one of N2 and H2N2.
5. The method of claim 1, wherein the alloy includes at least one of gold and palladium.
6. The method of claim 1, wherein the alloy includes less than 90% silver and at least 10% of other metals, the other metals including at least one of gold and palladium.
7. The method of claim 1, including cutting the bonding wire after the bonding wire is welded to the contact pad, forming a stud bump.
8. The method of claim 7, including:
forming a plurality of stud bumps,
placing contacts of a semiconductor device upon the plurality of stud bumps, and welding the contacts to the plurality of stud bumps.
9. The method of claim 8, wherein welding the contacts includes applying pressure, heat, and ultrasonic energy.
10. The method of claim 8, wherein the semiconductor device includes a semiconductor light emitting device.
11. A semiconductor arrangement formed by the method of claim 6.
12. The semiconductor arrangement of claim 8, wherein the semiconductor arrangement includes a semiconductor light emitting device and a substrate upon which the stud bumps are formed.
13. A device comprising:
a submount; and
a semiconductor device having one or more contact pads that are bonded to one or more conductive traces on the submount via a stud bump;
wherein the stud bump comprises an alloy that includes at least 50wt% of silver
(Ag).
14. The device of claim 13, wherein the alloy includes at least 5wt% palladium (Pd).
15. The device of claim 13, wherein the alloy includes less than 10wt% gold (Au).
PCT/IB2015/055706 2014-08-11 2015-07-29 Alloy stud bump interconnects for semiconductor devices WO2016024180A1 (en)

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US62/035,535 2014-08-11

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Citations (5)

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Publication number Priority date Publication date Assignee Title
JP2000164636A (en) * 1998-11-27 2000-06-16 Matsushita Electronics Industry Corp Semiconductor light emitting device mounting method and bonding tool used therefor
JP2007142271A (en) * 2005-11-21 2007-06-07 Tanaka Electronics Ind Co Ltd Bump material and bonding structure
US20090039376A1 (en) * 2004-08-06 2009-02-12 Matsushita Electric Industrial Co., Ltd. Light source, manufacturing method of light source, lighting apparatus, and display apparatus
CN103409654A (en) * 2012-09-12 2013-11-27 田中电子工业株式会社 Silver-gold-palladium alloy bump manufacturing line
US20140124920A1 (en) * 2012-11-07 2014-05-08 Wire Technology Co., Ltd. Stud bump structure and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164636A (en) * 1998-11-27 2000-06-16 Matsushita Electronics Industry Corp Semiconductor light emitting device mounting method and bonding tool used therefor
US20090039376A1 (en) * 2004-08-06 2009-02-12 Matsushita Electric Industrial Co., Ltd. Light source, manufacturing method of light source, lighting apparatus, and display apparatus
JP2007142271A (en) * 2005-11-21 2007-06-07 Tanaka Electronics Ind Co Ltd Bump material and bonding structure
CN103409654A (en) * 2012-09-12 2013-11-27 田中电子工业株式会社 Silver-gold-palladium alloy bump manufacturing line
US20140124920A1 (en) * 2012-11-07 2014-05-08 Wire Technology Co., Ltd. Stud bump structure and method for manufacturing the same

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