WO2016019686A1

WO2016019686A1 - A method for scheduling transmitting timing of uplink channels and device

Info

Publication number: WO2016019686A1
Application number: PCT/CN2014/094814
Authority: WO
Inventors: 杨睿; 颜达
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2014-08-07
Filing date: 2014-12-24
Publication date: 2016-02-11
Also published as: CN106162835A; CN106162835B

Abstract

A method for scheduling transmitting timing of uplink channels is provided in the present invention. The method includes: determining the maximum time overhead during the processing of signals of each uplink channel; scheduling the transmitting timing of each uplink channel according to the maximum time overhead during the processing of signals of each uplink channel. A device for scheduling transmitting timing of uplink channels is also provided in the present invention.

Description

Scheduling method and device for uplink channel transmission timing

Technical field

The present invention relates to a channel transmission technology, and in particular, to a scheduling method and apparatus for uplink channel transmission timing in an evolved Long Term Evolution Advanced (LTE-A) system.

Background technique

In the 3GPP TS 36.211 protocol, the uplink channel includes a Physical Uplink Shared Channel (PUSCH), a Physical Uplink Control CHannel (PUCCH), and a Sounding Reference Signal (SRS). Channel type such as physical random access channel (PRACH); information processed by the uplink channel includes uplink service data, Hybrid Automatic Repeat Request Acknowledgement (HARQ-ACK), and rank indication (RI) , Rand Index), Channel Quality Indicator (CQI), Scheduling Request Signal (SR, Scheduling Request), Sounding Reference Signal, Preamble, Demodulation Reference Signal (DMRS) And other information.

The information and data to be processed by the above uplink channel need to go through different processing flows and occupy different time and resources respectively. For example, the data range sent by the PUSCH is 1 RB to 100 RB. In the case of a normal cyclic prefix (NCK), the location of the PUSCH DMRS is symbol 2 and symbol 9, and the extended cyclic prefix (ECK, Extended cyclic prefix) The location of the PUSCH DMRS is symbol 1 and symbol 7; the PUCCH transmission data is 1 RB; wherein the location of the PUCCH DMRS in the case of the Normal cyclic prefix and the Extended cyclic prefix is different according to different PUCCH format formats, such as As shown in 1 Table 1 shows the correspondence between the location of the PUCCH DMRS in the case of the Normal cyclic prefix and the Extended cyclic prefix and the PUCCH format format.

PUCCH formatPUCCH format	Normal cyclic prefixNormal cyclic prefix	Extended cyclic prefixExtended cyclic prefix
PUCCH formatPUCCH format	Normal cyclic prefixNormal cyclic prefix	Extended cyclic prefixExtended cyclic prefix	1,1a,1b1,1a,1b	33	22
2,32,3	22	11	1,1a,1b1,1a,1b	33	22
2,32,3	22	11	2a,2b2a, 2b	22	N/AN/A

Table 1

The SRS transmission data is a minimum of 2 RBs and a maximum of 48 RBs. The mapping position of the SRS is transmitted only in the last symbol, or only in the second last symbol, or in the last two symbols, depending on the situation.

Currently, when transmitting according to the communication protocol of the LTE-A system, data is transmitted in units of subframes, and each subframe is composed of 12 or 14 symbols in different CP modes. The transmission mechanism of the entire uplink is: latching the parameters of the high-level configuration at the time point of transmitting the 10th symbol of one subframe before the current subframe is processed; when processing the symbols of the current subframe, the time pair of the two symbols is advanced The data is subjected to corresponding symbol level calculation, and the data is subjected to Inverse Fast Fourier Transform (IFFT) and filter processing in advance of one symbol; finally, it is transmitted through the corresponding RF module.

However, due to the large number of channel types, the processing scenario is complicated, and various information such as CQI, ACK, SR, SRS, and DMRS may be included in the same subframe, and different data processing methods are required for different channel types; When processing large amounts of data, the reuse of resources and the processing time of read and write storage will be very long. If resources are not properly allocated, data loss will occur due to read and write conflicts. Therefore, if the channel is not properly arranged in time series, data loss occurs due to timing conflicts and the like in the process of uplink channel transmission, and waste of resources such as time, area, and power consumption may be caused.

Summary of the invention

In view of this, the embodiments of the present invention provide a scheduling method and apparatus for uplink channel transmission timing, which can at least solve the above problems in the prior art.

In order to achieve the above object, the technical solution of the present invention is achieved as follows:

The embodiment of the invention provides a scheduling method for uplink channel transmission timing, and the method includes:

Determining the maximum time overhead of the signal processing process of each uplink channel;

The timing of each uplink channel transmission is scheduled according to the maximum time overhead of the signal processing procedure of each uplink channel.

In the foregoing solution, the determining a maximum time overhead for a signal processing procedure of each uplink channel includes: determining a symbol level processing procedure of each uplink channel, an inverse fast Fourier transform IFFT data processing, and a one-half carrier frequency offset processing, respectively. The maximum time overhead for the process, input data to the buffer buffer process.

In the foregoing solution, the scheduling of the timings of sending the uplink channels according to the maximum time overhead of the signal processing procedure of each uplink channel includes:

Performing scheduling scheduling on the physical uplink shared channel PUSCH processing process and the physical uplink control channel PUCCH processing process according to the maximum time overhead of the symbol level processing procedure of each uplink channel;

According to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing and the PUCCH processing, the timing sequence scheduling is performed on the IFFT output process and the IFFT random access memory RAM reading process. cloth;

Maximum time overhead according to IFFT data processing and one-half carrier frequency offset processing, maximum time overhead of input data to buffer process, and PUSCH processing, PUCCH processing, IFFT output processing, IFFT random access memory RAM reading The timing of the process, the scheduling of the input data to the buffer and the IFFT sign bit clearing is scheduled.

In the above solution, the method further includes: performing timing on the demodulated reference signal DMRS processing procedure, the channel sounding reference signal SRS processing procedure, and the scheduling request signal SR processing process according to a maximum time overhead of a symbol level processing procedure of each uplink channel. The scheduling on the top.

In the above solution, the method further includes:

Determining a timing of the resource mapping process according to the timing of the PUSCH processing procedure and the PUCCH processing procedure;

The timing of the filter processing is determined based on the timing of the input data to the buffer process.

An embodiment of the present invention further provides a scheduling apparatus for uplink channel transmission timing, where the apparatus includes: a time determining module and a timing scheduling module, where

The time determining module is configured to determine a maximum time of a signal processing process of each uplink channel;

The timing scheduling module is configured to schedule the timing of each uplink channel transmission according to a maximum time overhead of the signal processing procedure of each uplink channel.

In the above solution, the time determining module determines the maximum time overhead of the signal processing process of each uplink channel, including: determining symbol level processing of each uplink channel, IFFT data processing, and one-half carrier frequency offset processing, and inputting data, respectively. The maximum time overhead to the buffer buffer process.

In the foregoing solution, the timing scheduling module includes a first scheduling unit, a second scheduling unit, and a third scheduling unit, where

The first scheduling unit is configured to perform scheduling scheduling on the PUSCH processing process and the PUCCH processing process according to a maximum time overhead of a symbol level processing procedure of each uplink channel;

The second scheduling unit is configured to: according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing procedure and the PUCCH processing procedure, the IFFT output process, the IFFT random access memory RAM The reading process performs scheduling scheduling on the timing;

The third scheduling unit is configured to process according to IFFT data and one-half carrier frequency offset processing Maximum time overhead of the process, maximum time overhead of input data to the buffer process, and timing of the PUSCH process, the PUCCH process, the IFFT output process, the IFFT random access memory RAM read process, the input data to the buffer, and the IFFT sign bit The clearing process is scheduled for scheduling.

In the foregoing solution, the timing scheduling module further includes a fourth scheduling unit, configured to perform a demodulated reference signal DMRS processing procedure, a channel sounding reference signal SRS processing process, according to a maximum time overhead of a symbol level processing procedure of each uplink channel, The scheduling request signal SR process performs scheduling scheduling on the timing.

In the above solution, the timing scheduling module includes a fifth scheduling unit, configured to determine a timing of the resource mapping process according to timings of the PUSCH processing procedure and the PUCCH processing procedure, and determine filtering according to timing of the input data to the buffer process. The timing of the process.

The method and device for scheduling the uplink channel transmission timing provided by the embodiment of the present invention determines the maximum time overhead of the signal processing process of each uplink channel; and sends the uplink channel according to the maximum time overhead of the signal processing procedure of each uplink channel. The timing is scheduled. In this way, resources can be reused to the maximum extent under the premise of function coverage, so as to save power consumption and area; and each channel is arranged reasonably in timing, thereby avoiding conflicts in timing.

DRAWINGS

1 is a schematic flowchart of a scheduling method for uplink channel transmission timing according to an embodiment of the present invention;

2 is a schematic diagram of a signal processing process of an uplink channel according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an arrangement of non-SRS uplink timings according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an SRS uplink timing arrangement according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a scheduling apparatus for uplink channel transmission timing according to an embodiment of the present invention.

detailed description

In the embodiment of the present invention, determining a maximum time overhead of a signal processing process of each uplink channel; The timing of each uplink channel transmission is scheduled according to the maximum time overhead of the signal processing procedure of each uplink channel.

The determining a maximum time overhead of the signal processing process of each uplink channel includes: determining a symbol level processing process, an IFFT data processing, and a half carrier frequency offset processing process of each uplink channel, and inputting data into a buffer (buffer) The maximum time overhead of the process.

The scheduling of the timing of sending each uplink channel according to the maximum time overhead of the signal processing procedure of each uplink channel includes:

According to the symbol level processing process of each uplink channel, IFFT data processing and one-half carrier frequency offset processing, and the maximum time overhead of input data to the buffer process, the PUSCH processing procedure, the PUCCH processing procedure, the IFFT output process, and the IFFT random storage Taking a memory (RAM, Ramdom Access Memory) reading process, inputting data to buffer, and IFFT sign bit clearing process, DMRS processing, SRS processing, and SR processing to perform timing scheduling; and according to the PUSCH The processing procedure and the timing of the PUCCH processing process determine the timing of the resource mapping process; and determine the timing of the filter processing process according to the timing of the input data to the buffer process.

The implementation of the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The flow of the scheduling method for the uplink channel transmission timing in the embodiment of the present invention is as shown in FIG. 1 , and includes the following steps:

Step 101: Determine a maximum time overhead of a signal processing process of each uplink channel.

Here, the determining the maximum time overhead of the signal processing procedure of each uplink channel includes: determining a symbol level processing procedure of each uplink channel, an IFFT data processing, a half carrier frequency offset processing, and inputting data to a buffer buffer process, respectively. The maximum time overhead.

The maximum time overhead for determining the signal processing procedure of each uplink channel is performed according to the signal processing procedure shown in FIG. 2, and FIG. 2 is a schematic diagram of a signal processing process of the uplink channel according to the embodiment of the present invention, as shown in FIG. The signal processing process in the embodiment of the present invention includes the following steps Step:

Step 101a: performing symbol level processing on each channel;

The so-called symbol level processing refers to modulation, scrambling and spread spectrum processing of data. The data is processed according to the protocol for easy transmission and reception. The symbol level processing for each channel includes the following procedure. The labels A1-C1 in the following process are only for distinguishing different processing procedures, and do not limit the execution order.

Step A1: performing symbol level processing on the PUSCH;

For the PUSCH in the symbol level processing process, first, the data stored in the interleaved memory unit needs to be read, the symbol level data processing is performed, and then the processed data is subjected to discrete Fourier transform (DFT, Discrete Fourier Transform) calculation;

Step B1: performing symbol level processing on the PUCCH;

The symbol level processing for PUCCH is mainly processing of symbol level data, but PUCCH format 3 (format 3 of an uplink control channel specified by the protocol) in the PUCCH needs to perform DFT operation after performing symbol level data processing;

Step C1: performing symbol level processing on the SRS, the PUSCH DMRS, and the PUCCH DMRS;

Among them, SRS, PUSCH DMRS, and PUCCH DMRS only need to process symbol data. However, since the PUSCH DMRS and SRS processing time is relatively long, it needs to be calculated in advance and then stored.

Step 101b: performing resource mapping processing on each channel;

For different data of each channel, the transmitted address protocol is required. Therefore, after performing symbol level processing on the channel, the corresponding data needs to be matched with the corresponding address through resource mapping processing, so that the next processing can be performed.

In the process of resource mapping processing, different channels need to be distinguished. Different channels correspond to different weighting coefficients. After different channels are weighted by corresponding coefficients, the results are stored in the IFFT RAM.

The weighting coefficient is related to the empirical value of the conventional transmitted data, and is determined according to the following calculation process:

IF LinearPowerRate>=1

Equivalent_RB=M_PUSCH_RB+1.0/LinearPowerRate;

K=sqrt(N/Equivalent_RB/12)

PUSCH_scale1=8

PUCCH_scale1=8/sqrt(LinearPowerRate)

PUSCH_scale3=0.9*K/8

PUCCH_scale3=0.9*K/8

ELSE

Equivalent_RB=1+M_PUSCH_RB*LinearPowerRate;

K=sqrt(N/Equivalent_RB/12)

PUSCH_scale1=8*sqrt(LinearPowerRate)

PUCCH_scale1=8

PUSCH_scale3=0.9*K/8

PUCCH_scale3=0.9*K/8

END

Among them, LinearPowerRate is linear power, M_PUSCH_RB is the bandwidth indicating uplink transmission, represented by the number of resource blocks, N is the number of points of the ifpt, scale1 and scale3 are two different weighting factors, and PUCCH scale and PUSCH scale respectively represent the weighting factors of different channels. .

Step 101c: performing IFFT processing;

After the resource mapping process, IFFT processing is performed. Here, the IFFT processing is to convert the data in the frequency domain and the time domain, and the purpose is to realize modulation of multiple carriers to ensure correct data transmission.

In the processing of the IFFT, it is first necessary to read data output by the resource mapping process in the IFFT RAM, where the data includes PUCCH, PUSCH, PRACH, and corresponding reference signals such as: SRS, PUCCH DMRS, PUSCH DMRS, SR, etc.; The data is subjected to IFFT processing.

Under different channel types, the IFFT process may contain some or all of the above data. After performing IFFT calculation on the data of each channel, the process proceeds to a half-carrier frequency offset processing;

Step 101d: one-half carrier frequency offset processing;

Specifically, in the one-half carrier frequency offset processing, the data needs to be weight-weighted according to the parameters of the upper layer, and then the data is written to the buffer according to different carrier modes.

Here, the parameters of the high-level configuration determine the working state of the one-half carrier frequency offset module. After the weighting is finished, there are two different processing modes: one is that the high-level configuration is a single-tone mode, and the data is directly written to the corresponding one. The address unit; the other is the non-monophonic mode, which causes the weighted data to be processed again for the carrier frequency offset; the two different processing methods are configured by the upper layer.

In the embodiment of the present invention, the carrier mode includes a single carrier and a dual carrier; when a single carrier is used, only two storage units are used for storage: the storage unit A and the storage unit B. The storage mode is ping-pong storage mode, that is, the first segment of data is stored in the storage unit A, the second segment of data is stored in the storage unit B, the third segment of data is stored in the storage unit A, and so on; in the dual-carrier mode Four storage units are used, and each two data storage for one carrier.

Step 101e: performing filter processing;

After one-half carrier frequency offset processing, filter processing is performed; in the processing of the filter, it is necessary to read data stored in one-half carrier frequency offset processing, and then perform internal calculation of the filter. For example, the multi-level multiplication and addition calculation is performed according to different orders of the filter, and the result of the calculation is a fixed-point number after the saturation truncation. For example, in the embodiment of the present invention, the real part of the imaginary part of the calculation result has a bit width of 18 bits. .

In the embodiment of the present invention, the maximum time overhead of the signal processing process of each uplink channel is determined separately. In the embodiment of the present invention, the maximum time overhead of the signal processing process of each uplink channel is determined by using the 245 MHz as an example, but is not limited to the following steps:

Step A2: determining a maximum time overhead of a symbol level process of each uplink channel;

In the case of the symbol level processing, in the case of a PUSCH of up to 100 RBs, the most time consuming is the process of performing DFT processing on the 96 hop (1152 points) PUSCH symbols, which is approximately 6920 clk;

Since PUCCH format3 needs to perform DFT operation after performing symbol level data processing, the maximum time overhead of PUCCH processing is also determined; the most occupied time in PUCCH processing is processing of PUCCH format3, which is approximately 205. Clk;

Step B2: determining the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing;

From the IFFT data input, to the buffer with the first data output to the half of the carrier frequency offset, the maximum time is 2048 points, which requires 3166 clk;

Step C2: determining the maximum time overhead of inputting data to the buffer process;

The maximum occupied time of the IFFT output data into the buffer is 2048 points, which requires 2048 clk, and the output data cannot exceed half of the symbol time;

In addition, the time for the symbol 0 is shorter than the normal symbol when the time adjustment (TA) is adjusted to the maximum, and separate calculation is required;

In the case of ECP, since the ECP time of the individual symbols is much longer than the NCP, the timing arrangement under the NCP is also applicable to the case of the ECP.

The method for determining the maximum time overhead of the signal processing procedure of each uplink channel in the embodiment of the present invention is merely exemplified by 245 MHz, but the 245 MHz clock range is not limited.

Step 102: Schedule the timing of each uplink channel transmission according to the maximum time overhead of the signal processing procedure of each uplink channel.

According to the symbol level processing process of each uplink channel, the IFFT data processing and the one-half carrier frequency offset processing, and the maximum time overhead of the input data to the buffer buffer process, at the PUSCH Process, PUCCH process, IFFT output process, IFFT RAM read process, input data to buffer and IFFT sign bit clearing process, DMRS process, SRS process, SR process, scheduling scheduling, and Determining a timing of the resource mapping process according to the timing of the PUSCH processing procedure and the PUCCH processing procedure; determining a timing of the filter processing procedure according to the timing of the input data to the buffer process.

Specifically, scheduling scheduling of the physical uplink shared channel PUSCH processing process and the physical uplink control channel PUCCH processing process according to the maximum time overhead of the symbol level processing procedure of each uplink channel;

According to the maximum time overhead of the symbol level processing of each uplink channel, the demodulated reference signal DMRS processing procedure, the channel sounding reference signal SRS processing procedure, and the scheduling request signal SR processing procedure are scheduled in time sequence.

The scheduling method of the uplink channel transmission timing in the embodiment of the present invention is analyzed in conjunction with FIG. 3, and FIG. 3 includes FIG. 3-0, FIG. 3-1, FIG. 3-2, and FIG. 3-3. In the embodiment of the present invention, the processing time of each symbol is 17536clk as an example. Under the current working clock, since the uplink supports dual-carrier processing, the time of each channel is allocated to a time of 8768clk of half symbol, at each time. Symbol start A counter counts each clock pulse and performs timing scheduling of the upstream channel based on the count.

Specifically, FIG. 3 - 0 is a schematic diagram of non-SRS uplink timing arrangement according to an embodiment of the present invention. In order to make the display of FIG. 3-0 clearer, FIG. 3-0 is divided into FIG. 3-1, FIG. 3-2, and FIG. 3, wherein, FIG. 3-1, FIG. 3-2, and FIG. 3-3 are respectively a part of FIG. 3-0; wherein 1200 and 12 represent PUSCH and

process,

For the PUSCH DMRS process,

For the PUCCH DMRS calculation process,

Output/write buffer process for IFFT,

For the SRS calculation process; the size of each process in Figure 3 on the timing diagram is only illustrative, and the duration of each process in the sequence is based on the data in Figure 3.

The scheduling method for non-SRS uplink channel transmission timing in the embodiment of the present invention includes the following steps:

Step A3: Determine the timing of the PUSCH processing process and the PUCCH processing process according to the maximum time overhead of the symbol level processing procedure of each uplink channel;

Specifically, when the PUSCH is processed by the DFT, the maximum is 6950clk, so the end point of the PUSCH is set to a point of 6950; since the PUCCH and the PUSCH are to be concurrently supported, and the PUCCHformat3 needs to use the DFT module, in order to avoid timing conflict, the PUCCH is used. After the processing is scheduled to be on the PUSCH, as shown in Figure 3-1.

During the symbol level processing of the channel, since the other channels only need to perform symbol level data processing, there is no timing conflict with the PUSCH processing process and the PUCCH processing process, and the time overhead of the process is smaller than the time of the PUSCH processing process and the PUCCH processing process. Overhead, therefore, symbol-level processing of other channels can be combined with PUSCH processing, PUCCH processing Execution.

Step B3: determining the timing of the IFFT output process according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing procedure and the PUCCH processing procedure;

Since IFFT is to support a maximum of 2048 points of calculation, the point at which output to the filter begins is at the end of 7165clk, so the point of the IFFT output is set at 5050clk in consideration of time overhead; as shown in Figure 3-2;

Step C3: determining the timing of the IFFT RAM reading process according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing, the PUCCH processing, and the IFFT output process;

The maximum time overhead required for the IFFT RAM from data input to the first data output is 3166clk, so the reading of the IFFT RAM is set at 1884;

Step D3: Maximum time overhead according to IFFT data processing and one-half carrier frequency offset processing, maximum time overhead of input data to buffer process, and PUSCH processing procedure, PUCCH processing procedure, IFFT output process, IFFT random access memory The timing of the RAM read process, determining the timing of the input data to the buffer and the clearing of the IFFT sign bit;

After the IFFT has data output, it starts to input data to the buffer. At this time, the IFFT input ram can be released. In order to avoid the influence of the data, the IFFT needs to be cleared. Therefore, when the IFFT has data output, it can be The corresponding sign bit is cleared to 0, so the input data is buffered and the IFFT sign bit is cleared to the point at 5050clk;

Step E3: determining a timing of the DMRS processing process according to a maximum time overhead of a symbol level processing process of each uplink channel;

Since the DMRS of the PUSCH takes up a lot of time in the maximum case, the DMRS of the PUSCH starts to be calculated at a time of 5 symbols in advance and is stored in the corresponding ram. When the PUSCH DMRS data processing is required, the DMRS is read. The corresponding ram is shown in Figure 3-0, 3-1, 3-2.

Step F3: determining a timing of the SRS processing process according to a maximum time overhead of a symbol level processing procedure of each uplink channel;

FIG. 4 is a schematic diagram of an SRS uplink timing arrangement according to an embodiment of the present invention. As shown in FIG. 4, in the case of SRS transmission, the current symbol is that there is no PUSCH or PUCCH channel data transmission, and the SRS processing also needs to be long. Time, the hardware will start the calculation of the SRS channel data and store it in the corresponding ram according to the symbol bit and the corresponding carrier condition that the SRS needs to transmit.

This is shown in Figure 4.

The processing of the SR is performed during the PUCCH processing;

In addition, according to the timing of the PUSCH processing procedure and the PUCCH processing procedure, the timing of the resource mapping process is determined; and the timing of the filter processing procedure is determined according to the timing of the input data to the buffer process.

Since the resource mapping process requires less clk, generally several clk, and generally does not cause timing conflicts, the timing of the resource mapping process can be determined according to the timing of the PUSCH processing process and the PUCCH processing procedure, that is, in the PUSCH. After the process and the PUCCH process, the resource mapping process is performed. After inputting the data to the buffer, the filter processing is entered. Therefore, the timing of the filter processing is determined according to the timing of the input data to the buffer process.

In the same situation, the processing of the second channel is the same as the processing of the first channel, except that the starting point is 7165clk;

In the case of TA, the symbol 0 of NCP is the shortest, which is 14320clk, as shown in Figure 3-3. In this case, channel 2 cannot be completed when the amount of processed data is relatively large, so it will be borrowed from symbol 1. Some time, after completing the processing of channel 1, the corresponding clearing operation is performed on the counter, and the data of symbol 1 is processed according to the normal situation, that is, the counter is accumulated from 0, and the corresponding data is processed at the corresponding node;

The method in the embodiment of the present invention is a scheduling method for the uplink channel transmission timing of the LTE-A system in the case of the 245 MHz clock, but the range is not limited. In the case of the working clock and bandwidth of other frequencies, the embodiment of the present invention is used. In the method, only the node of the counter needs to be moved correspondingly, and reasonable scheduling can be realized, thereby achieving the purpose of function coverage and saving area power consumption.

The embodiment of the present invention further provides a scheduling device for uplink channel transmission timing. As shown in FIG. 5, the device includes: a time determining module 51 and a timing scheduling module 52, where

The time determining module 51 is configured to determine a maximum time overhead of a signal processing process for each uplink channel;

Specifically, the time determining module 51 determines that the maximum time overhead of the signal processing process of each uplink channel includes: determining symbol level processing processes, IFFT data processing, and one-half carrier frequency offset processing, and input data of each uplink channel, respectively. The maximum time overhead to the buffer buffer process.

In the embodiment of the present invention, taking 245 MHz as an example, the time determining module 51 determines that the maximum time overhead of the symbol level processing procedure of each uplink channel includes: in the case of a PUSCH with a maximum of 100 RBs, the most time spent in the symbol level processing process Is the process of performing DFT processing on the 96RB (1152 point) PUSCH symbol, which is approximately 6920 clk;

Since the PUCCH format 3 needs to perform a DFT operation after performing symbol level data processing, the time determining module 51 also determines the maximum time overhead of the PUCCH processing process; the most occupied time in the PUCCH processing process is processing the PUCCH format 3 Process, about 205 clk;

The time determining module 51 determines that the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing process includes: from the IFFT data input to the buffer after the first data is output to the half of the carrier frequency offset. The maximum time is 2048 points, which requires 3166 clk;

The time determining module 51 calculates a maximum time overhead for determining the input data to the buffer process, including the maximum occupied time of the IFFT output data into the buffer is 2048 points, and 2048 clk is required. And the output data cannot exceed half of the symbol time;

In addition, the time for the symbol 0 is shorter than the normal symbol when the TA is adjusted to the maximum, and a separate calculation is required;

The timing scheduling module 52 is configured to schedule the timing of each uplink channel transmission according to the maximum time overhead of the signal processing procedure of each uplink channel.

The scheduling of the uplink channel transmission by the timing scheduling module 52 according to the maximum time overhead of the signal processing procedure of each uplink channel includes: the timing scheduling module 52 according to the symbol level processing procedure of each uplink channel, and the IFFT data. Processing and one-half carrier frequency offset processing, maximum time overhead of input data to buffer process; processing of PUSCH process, PUCCH process, IFFT output process, IFFT RAM read process, input data to buffer, and IFFT symbol bit clear The zero process, the DMRS process, the SRS process, and the SR process are scheduled for scheduling.

Specifically, the timing scheduling module 52 includes a first scheduling unit 521, a second scheduling unit 522, and a third scheduling unit 523;

The first scheduling unit 521 is configured to perform scheduling scheduling on the PUSCH processing process and the PUCCH processing process according to a maximum time overhead of a symbol level processing procedure of each uplink channel.

Specifically, the first scheduling unit 521 determines, according to the maximum time overhead of the symbol level processing procedure of each uplink channel, the timing of the PUSCH processing procedure and the PUCCH processing procedure, including: when the PUSCH is in the DFT processing, the maximum is 6950 clk, so the PUSCH is The end point is set at 6950; since the PUCCH and PUSCH are to be supported, and the PUCCH format 3 needs to use the DFT module, in order to avoid timing conflict, the first scheduling unit 521 sets the processing of the PUCCH after the PUSCH; In the symbol-level processing process, since the other channels only need to perform symbol-level data processing, there is no timing conflict with the PUSCH processing process and the PUCCH processing process, and the time overhead of the process is smaller than the time overhead of the PUSCH processing process and the PUCCH processing process. Therefore, the symbol level processing of other channels can be combined with PUSCH processing, PUCCH The process is executed concurrently.

The second scheduling unit 522 is configured to: according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing procedure and the PUCCH processing procedure, the IFFT output process, the IFFT random access memory The RAM reading process performs scheduling on the timing;

The second scheduling unit 522 determines the timing of the IFFT output process according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing procedure and the PUCCH processing procedure, including: The calculation of 2048 points, that is, the point at which the output is started to the filter ends at 7165clk at the latest, therefore, the timing scheduling module 52 sets the point of the IFFT output at a point of 5050clk in consideration of the time overhead;

The second scheduling unit 522 determines the timing of the IFFT RAM reading process according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing procedure and the PUCCH processing procedure, including: IFFT RAM from The data is input to the first data output, and the maximum time overhead required is 3166clk. Therefore, the reading of the IFFT RAM by the second scheduling unit 522 is set at the point of 1884;

The third scheduling unit 523 is configured to: according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, the maximum time overhead of the input data to the buffer process, and the PUSCH processing procedure, the PUCCH processing procedure, and the IFFT output. The timing of the process, the IFFT random access memory RAM read process, and the scheduling of the input data to the buffer and the IFFT sign bit clear are scheduled.

The third scheduling unit 523 is configured according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, the maximum time overhead of the input data to the buffer process, and the PUSCH processing procedure, the PUCCH processing procedure, the IFFT output process, and the IFFT. The timing of the random access memory RAM reading process determines the input data to the buffer and the timing of the IFFT sign bit clearing includes: after the IFFT has data output, the data input to the buffer is started, and the input ram of the IFFT at this time It can be released. In order to avoid the influence of data, it is necessary to clear the IFFT. When the IFFT has data output, it can be cleared to 0 by the corresponding sign bit. The third scheduling unit 523 will input the data to the buffer. And the IFFT sign bit is cleared to a point at 5050clk;

The timing scheduling module 52 further includes a fourth scheduling unit 524, configured to perform a demodulated reference signal DMRS processing procedure, a channel sounding reference signal SRS processing procedure, and a scheduling request according to a maximum time overhead of a symbol level processing procedure of each uplink channel. The signal SR process performs scheduling on the timing.

The timing of determining the DMRS processing procedure by the fourth scheduling unit 524 according to the maximum time overhead of the symbol level processing procedure of each uplink channel includes: since the DMRS of the PUSCH is in a maximum case, it takes more time, so the DMRS of the PUSCH will The calculation starts at the time of 5 symbols in advance and is stored in the corresponding ram. When the PUSCH DMRS data processing is required, the corresponding ram is read.

The fourth scheduling unit 524 determines the timing of the SRS processing procedure according to the maximum time overhead of the symbol level processing procedure of each uplink channel, including in the case of SRS transmission, the current symbol is data transmission without PUSCH or PUCCH channel, The processing of the SRS also takes a long time. The hardware starts the calculation of the SRS channel data and stores it in the corresponding ram according to the symbol bit and the corresponding carrier condition that the SRS needs to transmit.

In addition, the fourth scheduling unit 524 performs the processing procedure of the SR in the PUCCH processing process;

The timing scheduling module 52 further includes a fifth scheduling unit 525, configured to determine a timing of the resource mapping process according to timings of the PUSCH processing procedure and the PUCCH processing procedure; and determine a filter according to timing of the input data to the buffer process The timing of the process.

Since the resource mapping process requires less clk, generally several clk, and generally does not cause timing conflicts, the timing of the resource mapping process can be determined according to the timing of the PUSCH processing process and the PUCCH processing procedure, that is, in the PUSCH. Process and PUCCH process After that, resource mapping processing is performed. After inputting the data to the buffer, the filter processing is entered. Therefore, the timing of the filter processing is determined according to the timing of the input data to the buffer process.

In the case of TA, the symbol 0 of NCP is the shortest, which is 14320clk. In this case, channel 2 cannot be completed when the amount of processed data is relatively large, so some time in symbol 1 is borrowed, and channel 1 is completed. After the processing, the counter is cleared to the corresponding operation, and the data of the symbol 1 is processed according to the normal situation, that is, the counter is accumulated from 0, and the corresponding data is processed at the corresponding node;

The implementation function of each processing module in the scheduling apparatus of the uplink channel transmission timing shown in FIG. 5 can be understood by referring to the foregoing description of the scheduling method of the uplink channel transmission timing. It should be understood by those skilled in the art that the functions of the processing units in the scheduling apparatus of the uplink channel transmission timing shown in FIG. 5 may be implemented by a program running on the processor, or may be implemented by a specific logic circuit, such as : Can be implemented by a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

In the several embodiments provided by the present invention, it should be understood that the disclosed method, apparatus, and system may be implemented in other manners. The device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be another division manner, for example, multiple modules or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed. In addition, the communication connections between the various components shown or discussed may be indirect coupling or communication connections through some interfaces, devices or modules, and may be electrical, mechanical or otherwise.

The modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, may be located in one place. The party may also be distributed to multiple network units; some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may be separately used as one module, or two or more modules may be integrated into one module; The module can be implemented in the form of hardware or in the form of hardware plus software functional units.

It will be understood by those skilled in the art that all or part of the steps of implementing the foregoing method embodiments may be performed by hardware related to program instructions. The foregoing program may be stored in a computer readable storage medium, and when executed, the program includes The foregoing steps of the method embodiment; and the foregoing storage medium includes: a removable storage device, a read-only memory (ROM), a magnetic disk or an optical disk, and the like, which can store program codes.

Alternatively, the above-described integrated module of the embodiment of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a stand-alone product. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a magnetic disk, or an optical disk.

The present invention is an example of the scheduling method and apparatus for the uplink channel transmission timing described in the example. The foregoing embodiment is only used as an example, but is not limited thereto, and those skilled in the art should understand that it can still be described in the foregoing embodiments. The technical solutions are modified, or some or all of the technical features are equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Range of protection.

Industrial applicability

The present invention discloses a scheduling method and apparatus for uplink channel transmission timing, which can determine the maximum time overhead of the signal processing procedure of each uplink channel, and send to each uplink channel according to the maximum time overhead of the signal processing procedure of each uplink channel. The timing is scheduled. In this way, resources can be reused to the maximum extent under the premise of function coverage, so as to save power consumption and area; and each channel is arranged reasonably in timing, thereby avoiding conflicts in timing.

Claims

A scheduling method for uplink channel transmission timing, the method comprising:

Determining the maximum time overhead of the signal processing process of each uplink channel;

The timing of each uplink channel transmission is scheduled according to the maximum time overhead of the signal processing procedure of each uplink channel.
The method according to claim 1, wherein said determining a maximum time overhead for a signal processing procedure for each uplink channel comprises: respectively determining a symbol level processing procedure of each uplink channel, an inverse fast Fourier transform IFFT data processing, and a binary One of the carrier frequency offset processing, the maximum time overhead of input data to the buffer buffer process.
The method according to claim 1, wherein the scheduling of the timing of each uplink channel transmission according to the maximum time overhead of the signal processing procedure of each uplink channel comprises:

Performing scheduling scheduling on the physical uplink shared channel PUSCH processing process and the physical uplink control channel PUCCH processing process according to the maximum time overhead of the symbol level processing procedure of each uplink channel;

According to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing and the PUCCH processing, the timing sequence scheduling is performed on the IFFT output process and the IFFT random access memory RAM reading process. cloth;

Maximum time overhead according to IFFT data processing and one-half carrier frequency offset processing, maximum time overhead of input data to buffer process, and PUSCH processing, PUCCH processing, IFFT output processing, IFFT random access memory RAM reading The timing of the process, the scheduling of the input data to the buffer and the IFFT sign bit clearing is scheduled.
The method according to claim 3, wherein the method further comprises: a demodulated reference signal DMRS processing procedure, a channel sounding reference signal SRS processing procedure, a scheduling request according to a maximum time overhead of a symbol level processing procedure of each uplink channel The signal SR process performs scheduling on the timing.
The method of claim 3 or 4, wherein the method further comprises:

Determining a timing of the resource mapping process according to the timing of the PUSCH processing procedure and the PUCCH processing procedure;

The timing of the filter processing is determined based on the timing of the input data to the buffer process.
A scheduling device for uplink channel transmission timing, the device includes: a time determining module and a timing scheduling module, where

The time determining module is configured to determine a maximum time of a signal processing process of each uplink channel;

The timing scheduling module is configured to schedule the timing of each uplink channel transmission according to a maximum time overhead of the signal processing procedure of each uplink channel.
The apparatus according to claim 6, wherein the time determining module determines a maximum time overhead of a signal processing procedure of each uplink channel, comprising: determining a symbol level processing procedure, an IFFT data processing, and a half carrier frequency of each uplink channel, respectively. The maximum time overhead for the process of processing the input data to the buffer buffer.
The apparatus according to claim 6, wherein the timing scheduling module comprises: a first scheduling unit, a second scheduling unit, and a third scheduling unit; wherein

The first scheduling unit is configured to perform scheduling scheduling on the PUSCH processing process and the PUCCH processing process according to a maximum time overhead of a symbol level processing procedure of each uplink channel;

The second scheduling unit is configured to: according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, and the timing of the PUSCH processing procedure and the PUCCH processing procedure, the IFFT output process, the IFFT random access memory RAM The reading process performs scheduling scheduling on the timing;

The third scheduling unit is configured to: according to the maximum time overhead of the IFFT data processing and the one-half carrier frequency offset processing, the maximum time overhead of the input data to the buffer process, and the PUSCH processing procedure, the PUCCH processing procedure, and the IFFT output process. , IFFT random access memory The timing of the memory RAM read process, the scheduling of the input data to the buffer and the clearing of the IFFT sign bit is performed on a time-series basis.
The apparatus according to claim 8, wherein the timing scheduling module further comprises: a fourth scheduling unit configured to process the demodulated reference signal DMRS according to a maximum time overhead of a symbol level processing procedure of each uplink channel The sounding reference signal SRS processing process and the scheduling request signal SR processing process perform scheduling scheduling on the timing.
The apparatus according to claim 8 or 9, wherein the timing scheduling module comprises: a fifth scheduling unit configured to determine a timing of the resource mapping process according to timings of the PUSCH processing procedure and the PUCCH processing procedure; The timing of the data to the buffer process determines the timing of the filter processing.