WO2016004644A1 - Method and apparatus for monitoring ethernet clock synchronization - Google Patents

Abstract

The present application provides a method and apparatus for monitoring Ethernet clock synchronization. In the method, when a slave clock device returns a delay request packet to a master clock device, the delay request packet carries link delay information, determined by the slave clock device, between the master clock device and the slave clock device of a last time synchronization cycle, so that the master clock device can determine a time deviation between the master clock device and the slave clock device and determine, according to whether the time deviation is smaller than a set time deviation threshold, whether to send alarm information. Because in embodiments of the present application, the slave clock device returns the determined link delay information between the slave clock device and the master clock device to the master clock device, the master clock device can determine a time synchronization condition of the slave clock device so as to achieve the purpose of monitoring the slave clock device, and thus precision demands of time synchronization are ensured and loss caused by inaccuracy of time synchronization is reduced.

Description

 Method and device for monitoring Ethernet clock synchronization. The present application claims to be filed on July 9, 2014, the Chinese Patent Office, the application number is 201410325610.9, and the invention is a method and device for monitoring Ethernet clock synchronization. Priority is hereby incorporated by reference in its entirety.

Technical field

 The present invention relates to the field of Internet technologies, and in particular, to a method and apparatus for monitoring Ethernet clock synchronization.

Background technique

IEEE1588 is an accurate clock synchronization protocol based on packets. Based on the PTP protocol, message transmission between the master clock and the slave clock enables precise time synchronization and frequency synchronization in the packet transmission network. Frequency synchronization refers to a specific relationship in which the frequency or phase occurs at the same effective rate at the corresponding effective instant, thereby maintaining all devices in the communication network operating at the same rate. Clock synchronization means that the frequencies between the signals are the same and are consistent in phase.

 Industrial Ethernet requires high clock synchronization. If there is an error in the timing between the slave clock device and the master clock device, and when the error cannot be detected in time, the time deviation between the slave clock device and the master clock device may be more The bigger the time, the final time cannot be synchronized.

 In the existing 1588 clock synchronization protocol, the master clock device only periodically sends clock synchronization packets, or sends time synchronization packets according to the timing request from the clock device, but the master clock device cannot know the slave clock device and the master clock device. Whether the timing is correct, or whether the timing of the clock device from the master clock device is accurate. In addition, according to the PTP protocol, after receiving the clock synchronization sent by the master clock device from the clock device, the local clock is adjusted by calculating the phase compensation value OFFSET, thereby realizing time synchronization with the master clock device, but When there is a problem with the hardware configuration of the clock device itself, the phase compensation value OFFSET calculated by the hardware configuration is an error value, so that it is difficult for the slave clock device to adjust the local clock according to the erroneous phase compensation value OFFSET. The exact timing of the master clock, or when the link between the slave clock device and the master clock device is abnormal, the time synchronization will cause frequent packet loss, causing the slave clock device to perform punctuality for a long time, and thus cannot The master clock device remains synchronized.

Therefore, in the existing clock synchronization mechanism, the master clock device simply salifies the slave clock device, and the master clock device cannot detect the time synchronization accuracy of the slave clock device, and a large time occurs between the slave clock device and the master clock device. If the deviation is not processed in time, the time synchronization of the current network will not meet the accuracy requirements, which will result in very strict Heavy security risks; In addition, when the hardware configuration of a slave clock device fails or the network is abnormal, the time deviation between the master clock device and the slave clock device is gradually increased because the master clock device cannot detect the slave clock device. The synchronization is abnormal, so it can only be discovered after more serious consequences due to synchronization anomalies, but this has caused unnecessary losses. SUMMARY OF THE INVENTION In view of the above, the present invention has been made in order to provide a method and apparatus for monitoring Ethernet clock synchronization that overcomes the above problems or at least partially solves the above problems.

 The embodiment of the invention provides a method for monitoring Ethernet clock synchronization, the method comprising:

 The master clock device sends a clock synchronization Sync message to the slave clock device;

 Receiving a delay request message returned from the clock device, where the delay request message carries link delay information between the master clock device and the slave clock device determined by the slave device;

 The master clock device determines a time offset between the master clock device and the slave clock device according to the received link delay information;

 Determining whether the time deviation is less than a set time deviation threshold;

 When the time deviation is not less than the set time deviation threshold, a clock synchronization abnormality alarm signal is issued.

 In order to monitor each slave clock device, the implementation scope of the solution is expanded. When the slave clock device is a two-step clock, the method further includes:

 The master clock device receives the delay request that is sent by the slave clock device, wherein the delay request follows the time stamp Τ3, where Τ3 is the time for sending the delay request message from the clock device.

 In order to accurately determine the time offset, the determining the time offset between the master clock device and the slave clock device includes: the master clock device receiving the delay according to the time stamp Τ3 carried in the delay request message The time Τ4 of the request message and the link delay information carried in the delay request message determine the time offset between the master clock device and the slave clock device;

 When there is an end-to-end transparent clock device between the master clock device and the slave clock device, the delay request message further carries the resident time information of the end-to-end transparent clock device, where the master clock is determined. The time offset between the device and the slave clock device includes:

 The master clock device according to the timestamp Τ3 carried in the delay request message, the time 自身4 of the delay request message received by the master clock device, the link delay information, and the end-to-end transparent clock device The dwell time information determines the time offset between the master clock device and the slave clock device.

In order to accurately monitor each slave clock device, the delay request message returned by the slave clock device further includes: when the master clock device determines that the upper-level master clock device exists, the master clock device serves as the previous one. Master Returning, by the slave clock device of the clock device, a delay request message to the upper-level master clock device, where the delay request message carries the last pair of time periods determined by the master clock device as the slave clock device The link delay information between the upper-level master clock devices, and the determined time offset of each slave clock device belonging to itself, the clock identification information of each slave clock device, and the timing information for determining each time offset.

 In order to accurately monitor each slave clock device, the method further includes:

 When the master clock device does not have the upper-level master clock device, the master clock device records the clock identification information of each slave clock device in the networking, and records each slave clock device in each pair of time periods and itself. Time offset, wherein the time offset is determined based on the sum of the time offsets between the slave clock device and each stage master clock device.

 An embodiment of the present invention provides an apparatus for monitoring synchronization of an Ethernet clock, where the apparatus includes:

 a sending module, configured to send a clock synchronization Sync message to the slave clock device;

 a receiving module, configured to receive a delay request message returned from the clock device, where the delay request message carries link delay information between the master clock device and the slave clock device determined by the clock device;

 a determining module, configured to determine a time offset between the master clock device and the slave clock device according to the received link delay information;

 a determining module, configured to determine whether the time deviation is less than a set time deviation threshold;

 The alarm module is configured to issue a clock synchronization abnormality alarm signal when the determining module determines that the time deviation is not less than a set time deviation threshold.

 In order to monitor the implementation scope of the solution, the receiving module is further configured to: when the slave clock device is a two-step clock, receive a delay request sent by the slave clock device to follow For example, the delay request follows the time stamp Τ3, where Τ3 is the time for sending the delay request message from the clock device.

 In order to accurately determine the time deviation, the determining module is specifically configured to: according to the timestamp Τ3 carried in the delay request message, the time Τ4 of the delay request message and the delay request message The link delay information carried in the text determines the time deviation between the master clock device and the slave clock device;

 When there is an end-to-end transparent clock device between the master clock device and the slave clock device, the delay request message further carries the resident time information of the end-to-end transparent clock device, and the determining module, Specifically, the method is further configured to: timestamp Τ3 carried in the delay request packet, time 404 in which the delay request message is received by itself, the link delay information, and the station of the end-to-end transparent clock device. The time information is used to determine the time offset between the master clock device and the slave clock device.

In order to accurately monitor each of the slave clock devices, the sending module is further configured to: when it is determined that the upper-level master clock device exists, return a delay request message to the upper-level master clock device, where the delay The request message carries the link delay information between the last pair of time periods determined as the master clock device of the slave clock device and the upper master clock device, and the determined time of each slave clock device belonging to itself. Deviation, clock identification information for each slave clock device and timing information for determining each time offset. In order to accurately monitor each slave clock device, the device further includes:

 a storage module, configured to record, according to clock identification information of each slave clock device in the networking, when the upper-level master clock device does not exist, record a time deviation of each slave clock device from itself in each pair of time periods, where The time offset is determined based on the sum of the time offsets between the slave clock device and each stage master clock device.

 The embodiment of the present invention provides a method and a device for monitoring Ethernet clock synchronization. When the slave clock device returns a delay request message to the master clock device, the slave device carries the slave clock device in the delay request message. The link delay information between the master clock device and the slave clock device in the last pair of time periods, so that the master clock device can determine the time deviation between the master clock device and the slave clock device, according to whether the time deviation is less than the set time Deviation threshold to determine whether to send an alarm message. Because the link delay information between the slave clock device and the master clock device is returned to the master clock device in the embodiment of the present invention, the master clock device can determine the timing of the slave clock device to achieve monitoring. The purpose of the clock device is to ensure the accuracy of time synchronization and reduce the loss caused by inaccurate time.

 The above description is only an overview of the technical solutions of the present invention, and the technical means of the present invention can be more clearly understood, and can be implemented in accordance with the contents of the specification, and the above and other objects, features and advantages of the present invention can be more clearly understood. Specific embodiments of the invention are set forth below. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a process for monitoring Ethernet clock synchronization according to an embodiment of the present invention;

 2A is a clock synchronization monitoring list maintained by a master clock device of a higher-level master clock device according to Embodiment 1 of the present invention;

 2B is a clock synchronization monitoring list maintained by a master clock device of a higher-level master clock device according to Embodiment 2 of the present invention;

 3 is a schematic diagram of a detailed process of monitoring Ethernet clock synchronization according to an embodiment of the present invention;

 4A is a schematic structural diagram of a networking for performing clock synchronization monitoring on an Ethernet according to an embodiment of the present invention; FIG. 4B is a package format diagram of a delay request packet including a TIN field according to an embodiment of the present invention; FIG. 5 is a schematic structural diagram of a device for monitoring an Ethernet clock synchronization according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to effectively monitor the time-to-time situation of each slave clock device in the network, and discover the synchronization abnormality between the slave clock device and the master clock device in time, and improve the reliability of the network, the embodiment of the present invention provides a method for monitoring Ethernet. Method and device for clock synchronization.

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited by the embodiments set forth herein. System. Rather, these embodiments are provided so that this disclosure will be more fully understood, and the scope of the disclosure may be fully disclosed to those skilled in the art.

 The embodiments of the present invention will be described below with reference to the accompanying drawings.

 FIG. 1 is a schematic diagram of a process for monitoring Ethernet clock synchronization according to an embodiment of the present invention, where the process includes the following steps:

 S101: The master clock device sends a clock synchronization Sync message to the slave clock device.

 The master clock device sends a clock synchronization Sync message to the slave clock device according to the set time interval according to the IEEE1588 protocol, where the clock synchronization Sync message carries the time T1 and the time period SQ for transmitting the clock synchronization Sync message. ID and other information.

 S102: The master clock device receives the delay request message returned from the clock device, where the delay request message carries the link delay information between the master clock device and the slave clock device of the last pair of time periods determined by the slave clock device.

 The time T2 of the clock synchronization Sync message sent by the master clock device is recorded from the clock device, and the link delay Delay calculated according to the previous time period and the time T1 carried in the clock synchronization Sync message are calculated and calculated. The time offset of the master clock device is OFFSET, and the local clock is corrected according to the OFFSET value, and then the delay request message is returned to the master clock device, where the delay request message carries the delay request sent by the slave clock device. Information such as the time T3 of the packet, the clock ID information, the clock ID, and the SQ ID, and the TIN field of the delay request carries the last clock cycle between the master clock device and the slave clock device. The link delays the Delay.

 In addition, in order to monitor each slave clock, the implementation scope of the solution is expanded. When the slave clock device is a two-step clock, the method further includes: the master clock device receiving the delay request sent by the slave clock device Following the 艮 艮 text, where the delay request follows the time stamp Τ 3 , Τ 3 is the time for sending the delay request message from the clock device.

 Specifically, when the slave clock device is a two-step clock, the slave clock device calculates the time T2 of synchronizing the Sync message according to the clock sent by the master clock device, the timestamp T1 carried in the Sync message, and the previous time period. The link delay delay, calculate the time offset from the master clock device OFFSET and correct the local clock, and then return a delay request message carrying the SQ ID and delay information to the master clock device, and then send the delay request message. The time T3 of the text is carried to the delay request follow message and sent to the master clock device.

 S103: The master clock device determines a time offset between the master clock device and the slave clock device according to the received link delay information.

 The master clock device records the time T4 of receiving the delay request message sent from the clock device, and parses the delay request message to obtain the time when the slave clock device carries the delay request message carried in the delay request message. T3 and the link delay Delay between the master clock device and the slave clock device calculated in the last time period, and determine the time offset between the master clock device and the slave clock device based on the above information.

In the present invention, in order to be able to monitor the timing of each slave clock, it is necessary to determine whether there is a time deviation between each slave clock device and itself. The determining the time offset between the master clock device and the slave clock device includes: The master clock device determines, according to the timestamp T3 carried in the delay request message, the time T4 of the delay request message and the link delay information carried in the delay request message. Time offset between the master clock device and the slave clock device;

 When there is an end-to-end transparent clock device between the master clock device and the slave clock device, the delay request message further carries the resident time information of the end-to-end transparent clock device, where the master clock is determined. The time offset between the device and the slave clock device includes:

 The master clock device according to the timestamp T3 carried in the delay request message, the time T4 when the delay request message is received by itself, the link delay information, and the end-to-end transparent clock device The dwell time information determines the time offset between the master clock device and the slave clock device.

 Specifically, the master clock device records the time Τ4 of receiving the delay request message sent from the clock device, parses the delay request message, and extracts the time stamp Τ3, the time period SQ ID, and the slave clock carried in the message. The information such as the clock ID of the device, and the link delay Delay calculated by the last clock cycle of the slave clock device carried in the TIN field of the delay request message, according to the time deviation calculation formula : OF=T4-T3 -Delay, calculate the time deviation of the slave clock device from itself, and locally establish or update the mapping list of the clock ID, the time period SQ ID and the time offset of the slave clock device.

 When there is an end-to-end transparent clock device between the master clock device and the slave clock device, when the slave clock device returns a delay request message to the master clock device, the slave device carries the slave clock in the TIN field of the delay request message. The link delay Delay between the master clock device calculated by the device last time period and the dwell time information of the delay request message passing through each end-to-end transparent clock device, and the master clock device records the receive slave clock The time T4 of the delay request message sent by the device, parsing the delay request, extracting the time stamp Τ3 carried in the text, the SQ ID of the time period, and the clock ID of the slave clock device, Obtaining, in the TIN field of the delay request message, the link delay Delay between the primary clock device calculated by the slave clock device and the delay request message passing through each end The dwell time information of the transparent clock device, according to the time deviation calculation formula: OF=T4-T3-Delay-residence time, calculate the time deviation of the slave clock device and itself, and establish locally Or update the mapping list of the clock ID, the time period SQ ID, and the time offset of the slave clock device.

 S104: The master clock device determines whether the time deviation is less than a set time deviation threshold.

 In order to ensure accurate monitoring of whether the slave clock device has an error during the time synchronization with the master clock device, and when a large deviation occurs, the time-of-day exception can be detected in time, and each level of the master clock device is preset with time. Deviation threshold, wherein each primary clock device can set the same time deviation threshold, and different time deviation thresholds can be set for each primary clock device.

 S105: When the master clock device determines that the time deviation is not less than the set time deviation threshold, a clock synchronization abnormality alarm signal is issued.

After calculating the time deviation between each slave clock device and itself, the master clock device according to its own time offset The threshold value is used to determine whether the calculated time deviation is less than the time deviation threshold. When it is determined that the time deviation is not less than the set time deviation threshold, the master clock device determines that the slave clock device is in time synchronization with itself and issues a clock synchronization. Abnormal alarm signal. The clock synchronization abnormality alarm signal carries information such as a clock ID, a time period SQ ID, and the determined time offset of the slave clock device.

 In the embodiment of the present invention, when the slave clock device performs clock synchronization with the master clock device, the determined link delay information between the master clock device and the master clock device is returned to the master clock device, so that the master clock device Calculating the time deviation between the slave clock device and itself according to the link delay information and the sending and receiving time of the packet carrying the link delay information message, thereby determining the timing of the slave clock device and achieving the purpose of monitoring the slave clock device. In turn, the accuracy requirement of time synchronization is ensured, and the loss caused by inaccurate time is reduced.

 In the embodiment of the present invention, in order to accurately monitor the timing of all the slave clock devices, each primary clock device needs to monitor its own slave clock devices. When the master clock device determines that it has the upper-level master clock device, The delay request message returned by the master clock device as the slave clock device of the upper-level master clock device further includes:

 When the master clock device determines that the upper-level master clock device exists, the master clock device serves as a slave clock device of the upper-level master clock device, and returns a delay request message to the upper-level master clock device. The delay request message carries the link delay information between the last pair of time periods determined by the master clock device of the slave clock device and the upper-level master clock device, and each determined slave belongs to itself. Time offset of the clock device, clock identification information for each slave clock device, and timing information for determining each time offset.

 Specifically, when each level of the master clock device is based on the time T4 of receiving the delay request message returned from the clock device, the timestamp T3 carried in the delay request message, and a pair of time periods on the slave clock device. a link delay delay between the slave clock device and the master clock device, and after calculating the time offset of the slave clock device, updating a locally stored mapping list of the clock ID, the time period SQ ID, and the time offset of the slave clock device, where The master clock device determines whether it has the upper-level master clock device. When it is determined that the upper-level master clock device exists, the master clock device returns the delay request message to the upper-level master clock device. As the time T3 of transmitting the delay request message, the SQ ID and the clock ID of the slave clock device of the upper-level master clock device, and the link delay delay of the master clock with the upper-level master clock, It is necessary to save itself for the time offset of each slave clock device and its own time period, and the SQ ID and Clock I of each slave clock device corresponding to the time offset. The information such as D is carried in the delay request message. When the upper-level master clock device of the master clock device receives the delay request message, the upper-level master clock device calculates the formula according to the time deviation: OF= Determining the time deviation of the master clock device, and determining the master according to the determined time deviation of the master clock device and the time deviation of the slave clock device carrying the master clock device in the delay request message The time deviation between each slave clock device of the clock device and the upper master clock device.

In addition, in order to accurately monitor the timing of all slave clock devices in each pair of time periods, the master clock device that does not have the upper level master clock device needs to save the time offset of all slave clock devices in each pair of time periods, The master clock device with the upper-level master clock device only needs to save the time of each slave clock device and itself for the previous pair of clock cycles. For the purpose of saving the storage space of the master clock device of the upper-level master clock device, the method further includes:

 When the master clock device does not have the upper-level master clock device, the master clock device records the clock identification information of each slave clock device in the networking, and records each slave clock device in each pair of time periods and itself. Time offset, wherein the time offset is determined based on the sum of the time offsets between the slave clock device and each stage master clock device.

 Specifically, in the present invention, the master clock device of the upper-level master clock device does not need to monitor the timing of all the slave clock devices in the entire network, and the master clock device that does not exist in the upper-level master clock device establishes clock synchronization locally. a watch list, where the time synchronization deviation of each of the slave clock devices is saved in the clock synchronization monitoring list, where the clock synchronization monitoring list includes clock ID information of each of the slave clock devices, and a corresponding time period SQ ID. The time deviation from itself, through the clock synchronization monitoring list administrator or maintenance personnel can intuitively determine the timing deviation trend of each slave clock device and the master clock device without the upper-level master clock device, which is convenient for discovery The timing error of the slave clock device is processed in time, which solves the problem that the time deviation between the clock device and the master clock device is gradually increased, which ultimately leads to more serious consequences, improves the reliability of the network, and reduces unnecessary loss.

 In order to facilitate the time delay of the master clock device to send its slave clock device to its upper-level master clock device, the master clock device that does not exist in the upper-level master clock device monitors the timing of all slave clock devices. In different embodiments of the invention, different master clock devices can maintain their own saved clock synchronization monitoring list in different ways. As shown in FIG. 2A, when there is a clock synchronization monitoring list maintained by the master clock device of the upper-level master clock device, the master clock device determines the information according to the information carried in the delay request message returned by each of the slave clock devices. a time offset OF of each slave clock device, and a mapping list is established according to the time offset OF and the identification information Clock ID and the time period SQ ID of the slave clock device corresponding to the time offset, wherein, in order to save the storage of the master clock Resources, the master clock device only needs to save the time deviation of each slave clock device calculated in a pair of time periods; FIG. 2B is a clock synchronization monitoring list maintained when the upper-level master clock device does not exist, as shown in the figure, and exists Compared with the master clock device of the upper-level master clock device, the master clock device that does not exist in the upper-level master clock device needs to save the time offset of each slave clock device with each time period, thereby monitoring the whole The timing of each slave clock device.

 FIG. 3 is a schematic diagram of a detailed process of monitoring Ethernet clock synchronization according to an embodiment of the present invention, where the process includes the following steps:

 S301: The master clock device sends a clock synchronization Sync message to the slave clock device.

 S302: The master clock device receives the delay request message returned from the clock device, where the delay request message carries the link delay information between the master clock device and the slave clock device of the last pair of time periods determined by the slave clock device.

 S303: The master clock device determines a time offset between the master clock device and the slave clock device according to the received link delay information.

S304: The master clock device determines whether the time deviation is less than a set time deviation threshold. If the determination result is yes, proceed to step S306; otherwise, proceed to step S305. S305: When the master clock device determines that the time deviation is not less than a set time deviation threshold, a clock synchronization abnormality alarm signal is issued.

 S306: The master clock device updates its own clock synchronization monitoring list according to the clock ID of the slave clock device, the time period SQ ID, and the time offset.

 S307: The master clock device determines whether there is a higher-level master clock device. If the determination result is YES, then step S308 is performed; otherwise, step S309 is performed.

 S308: The master clock device returns a delay request message to the upper-level master clock device, where the delay request message carries the link between the last pair of time periods determined by the master clock device and the upper-level master clock device. The delay information, and the determined time offset of each slave clock device belonging to itself, the clock identification information of each slave clock device, and the time period information determining each time offset.

 S309: The master clock device records, for the clock identification information of each slave clock device in the networking, a time offset of each slave clock device with each time period, wherein the time offset is according to the slave clock device and each The sum of the time offsets between the primary clock devices.

 In the embodiment of the present invention, when the slave clock device performs clock synchronization with the master clock device, the link delay information between the determined master clock device and the master clock device and the associated slave clock device and its own The time offset is returned to the master clock device, so that the master clock device updates its own clock synchronization monitoring list, and reports the time offset of each slave clock device to which it belongs to the upper-level master clock device through the delay request message. The master clock device of the upper-level master clock device does not monitor the timing of all slave clock devices, thereby ensuring the accuracy requirement of time synchronization and reducing the loss caused by inaccurate timing.

 The following description will be made in conjunction with a specific embodiment.

 FIG. 4A is a schematic diagram of a network structure for performing clock synchronization monitoring on an Ethernet according to an embodiment of the present invention. As shown in the figure, M is a master clock device having no upper-level master clock device, and switching devices S1-S8 For the slave clock devices of M, both are Boundary Clocks (BC), and SI is the upper-level master clock device of S3. Similarly, S2 is the upper-level master clock device of S4~S6, and S4 is S7 and The upper-level master clock device of S8, the slave clock device of S2 includes S4~S8, wherein the synchronization period of the slave clock devices S1-S8 and the master clock device M is the same.

 When the master clock device performs clock synchronization on the slave clock device in the first timing cycle, M sends a Sync message to S1 and S2 according to the IEEE1588 protocol, where the Sync 4 message carries the transmission time t1 of the message. S1 records the time t2 when the Sync message is received, and returns a delay request message to the M. The delay request message carries the time t3 at which the delay request message is sent, and the M record receives the delay request message. The time t4 of the text, and t4 is carried into the Delay_resp message and sent to the SI, and the S1 calculates the average link delay delayMl of itself and M according to the four timestamps tl, t2, t3, t4, and the same S2 determines and M The average link delay delayM2, S3 determines the average link delay delayl3 with S1, and so on, and analogously, the average link delay delay calculated by each slave clock device with the upper-level master clock device.

When the master clock device M clocks the slave clock in the second timing cycle, the slave clock device S1, according to Sync The timestamp tl in the message and the link delay delayMl calculated in the first pair of time periods, calculate the time offset from the master clock device OFFSET and adjust the local clock, and then return the delay request to M. And adding a TIN field at the end of the delay request message, and the delay request message is sent from the timestamp t3 of the clock device to the origintimestamp field of the • 艮 ,, where the TIN field Type is set to DELAY, the length is 8 bytes, and the value is the link delay delayMl calculated in the previous pair of time periods.

 M records the time t4 of receiving the delay request············································ If the time difference OFM1 is less than the set time deviation threshold, the M will issue a clock synchronization abnormality alarm message, where The clock synchronization abnormality alarm message includes information such as the clock ID of the S1, the current SQ ID, and the time offset OFM1.

 The M updates the locally saved clock synchronization monitoring list according to the determined time deviation OFM1 of the slave clock device S1 and the clock ID of the S1 carried in the delay request message and the current time period SQ ID. Similarly, in the second During the next-time period, the time synchronization OFM2 of S2 is also stored in the clock synchronization monitoring list of M. The time synchronization OF13 of S3 is stored in the clock synchronization monitoring list of S1, and the time of S4 S6 is saved in the clock synchronization monitoring list of S2. The time deviations OF47 and OF48 of S7 and S8 are stored in the clock synchronization monitoring list of the deviations OF24, OF25 and OF26, S4.

 When the master clock device M clocks the slave clock in the third timing cycle, the slave clock device S1 calculates the time according to the timestamp t1 in the Sync message and the link delay delayMl calculated in the second pair of time periods. The offset OFFSET adjusts the local clock, and returns the delay request message to the M. In addition to the link delay delayM1 of the second pair of time periods and the time t3 of sending the delay request message, the delay is still Adding a new TIN field at the end of the request message, carrying the time offset of the S3 in the second pair of time periods, the clock ID of the S3, the clock ID of the S3, and the second time period SQ ID, where the new increase is made in the TIN field. In the TIN field, Type can be set to SLAVE, the length is 24 bytes, the Value content part can store the Block ID of S3 with 8 bytes, and the 8 bytes store the time deviation of the second timing period of S3 and S1 OF13, 8 The byte holds the second time period SQID.

 M records the time t4 of receiving the delay request, extracts the delay request, obtains the delay M1 of the second time period, calculates the time deviation OFM1 of the third time period SI, and according to The time offset OFM of the second time interval S3 of the S3 carried in the delay request message and the time offset OF13 of the S1 and the second time period S1 saved in the self clock synchronization monitoring list, by the formula OFM3=OFM1+ OF13 Determining whether S3 is within the second time period of time and its own time deviation OFM3, and determining whether the time deviation OFM1 of the determined third timing period S1 or the time deviation OFM3 of the second timing period S3 is less than the set time. Deviation threshold, when it is determined that any one of the above time deviations is not less than the set time deviation threshold, M will issue a clock synchronization abnormality alarm message.

M increases the time offset of the third timing period of S 1 in its own clock synchronization monitoring list according to the determined time offset OFM1 of the clock device S1 according to the determined third timing period, and according to the determined S3 in the second pair Time period The inter-vehicle OFM3 and the clock ID of the S3 carried in the delay request message store the mapping relationship between the clock identification information, the time period and the time offset value of the S3 in the clock synchronization monitoring list. Similarly, M can save the time offset of the slave clock device S4 S8 in the local clock synchronization monitoring list through the delay request message returned by S2, thereby realizing the monitoring of the timing of all the slave clock devices.

 When an abnormality occurs in the slave clock device in the network, for example, the clock device S4 is inaccurate with the S2 due to a hardware failure or a network abnormality, and the time deviation from the previous master clock S2 is large, but does not exceed S2. The time deviation threshold is set, and the time deviation threshold of the main clock M is not exceeded after the time deviation of S2 is added. At this time, the clock synchronization abnormality signal is not issued by the previous main clock S2 and the main clock device M. The member will not be able to find the problem in time. However, the slave clock devices S7 and S8 of S4 also have a time deviation when synchronizing with S4. When the master clock device M determines that the time offset value of S7 or S8 exceeds the set threshold, it will also trigger.艮 艮 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , .

 FIG. 4 is a package format diagram of a delay request packet including a TIN field according to an embodiment of the present invention. As shown in the figure, taking a one-clock clock as an example, a conventional delay request message carries a slave clock device in a DATA. Clock ID, SQ ID, and source timestamp t3. In the invention, in order to realize that the master clock of the upper-level master clock device cannot monitor the synchronization of all slave clock devices with their own clocks, the end of the delay request message is added. The TIN field, in which the Value part is used to carry the link delay of the slave clock device and the master clock device in the last pair of time periods, when the slave clock device still has the next-level slave clock device, The new TLV1 field is added after the TIN field, and the value of the next-level slave clock device calculated by the Clock ID, the SQ ID of the next-level slave clock device, and the last-stage time period is carried in the Value portion of the new TIN field. Deviation, wherein the length of the newly added TIN field is determined by the number of slave clock devices of the next level included in the slave clock device.

 FIG. 5 is a schematic structural diagram of a device for monitoring an Ethernet clock synchronization according to an embodiment of the present invention. The device includes: a sending module 51, configured to send a clock synchronization Sync message to a slave clock device;

 The receiving module 52 is configured to receive a delay request message returned from the clock device, where the delay request message carries the link delay information between the master clock device and the slave clock device determined by the clock device. ;

 a determining module 53 , configured to determine a time offset between the master clock device and the slave clock device according to the received link delay information;

 The determining module 54 is configured to determine whether the time deviation is less than a set time deviation threshold;

 The alarm module 55 is configured to send a clock synchronization abnormality alarm signal when the determining module determines that the time deviation is not less than a set time deviation threshold.

The receiving module 52 is further configured to: when the slave clock device is a two-step clock, receive a delay request follow message sent by the slave clock device, where the delay request follows a time stamp T3, and T3 is The time from when the clock device sends a delay request. The determining module 53 is configured to: according to the timestamp Τ3 carried in the delay request message, the time Τ4 of the delay request message and the link carried in the delay request message Delay information to determine the time offset between the master clock device and the slave clock device.

 When the end-to-end transparent clock device exists between the master clock device and the slave clock device, the delay request message further carries the resident time information of the end-to-end transparent clock device, and the determining module 53 Specifically, the method is further configured to: timestamp Τ3 carried in the delay request message, time 自身4 of receiving the delay request message by itself, the link delay information, and the end-to-end transparent clock device The dwell time information determines the time offset between the master clock device and the slave clock device.

 The sending module 51 is further configured to: when it is determined that the upper-level master clock device exists, return a delay request message to the upper-level master clock device, where the delay request packet carries the slave request The link delay information between the last pair of time periods determined by the master clock device of the clock device and the master clock device of the upper level, and the determined time deviation of each slave clock device belonging to itself, the clock of each slave clock device Identification information and timing information for determining each time offset.

 The device also includes:

 The storage module 56 is configured to record, for the clock identification information of each slave clock device in the networking, when the upper-level master clock device does not exist, record the time deviation of each slave clock device from itself in each pair of time periods, The time offset is determined based on a sum of time deviations between the slave clock device and each stage master clock device.

 The embodiment of the present invention provides a method and a device for monitoring Ethernet clock synchronization. When the slave clock device returns a delay request message to the master clock device, the slave device carries the slave clock device in the delay request message. The link delay information between the master clock device and the slave clock device in the last pair of time periods, so that the master clock device can determine the time deviation between the master clock device and the slave clock device, according to whether the time deviation is less than the set time Deviation threshold to determine whether to send an alarm message. Because the link delay information between the slave clock device and the master clock device is returned to the master clock device in the embodiment of the present invention, the master clock device can determine the timing of the slave clock device to achieve monitoring. The purpose of the clock device is to ensure the accuracy of time synchronization and reduce the loss caused by inaccurate time.

 The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general purpose systems can also be used with the teaching based on the teachings herein. From the above description, the structure required to construct such a system is obvious. Moreover, the invention is not directed to any particular programming language. It is to be understood that the description of the present invention may be embodied in a variety of programming language, and the description of the specific language is set forth herein.

 Numerous specific details are set forth in the description provided herein. However, it is understood that the embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the description.

Similarly, it should be understood that in order to refine the disclosure and to assist in understanding one or more of the various inventive aspects, In the description of the exemplary embodiments of the present invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description. However, the method disclosed is not to be interpreted as reflecting the intention that the claimed invention requires more features than those recited in the claims. Rather, as the following claims reflect, inventive aspects reside in less than all features of the single embodiments disclosed herein. Therefore, the claims following the specific embodiments are hereby explicitly incorporated into the specific embodiments, and each of the claims as a separate embodiment of the invention.

 Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively changed and placed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and further they may be divided into a plurality of sub-modules or sub-units or sub-assemblies. In addition to such features and/or at least some of the processes or units being mutually exclusive, any combination of the features disclosed in the specification, including the accompanying claims, the abstract and the drawings, and any methods so disclosed may be employed. Or combine all the processes or units of the device. Each feature disclosed in the specification (including the accompanying claims, the abstract, and the drawings) may be replaced by alternative features that provide the same, equivalent or similar purpose.

 In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features that are not included in other embodiments, and other features, combinations of features of different embodiments are intended to be within the scope of the present invention. Different embodiments are formed and formed. For example, in the following claims, any one of the claimed embodiments can be used in any combination.

 The various component embodiments of the present invention may be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the devices, terminals, and systems that monitor Ethernet clock synchronization in accordance with embodiments of the present invention. Some or all of the features of the part. The invention may also be embodied as a device or device program (e.g., a computer program and a computer program product) for performing some or all of the methods described herein. Such a program implementing the present invention may be stored on a computer readable shield or may have the form of one or more signals. Such signals may be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

It is to be noted that the above-described embodiments are illustrative of the invention and are not intended to limit the scope of the invention, and those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as a limitation. The word "comprising" does not exclude the presence of the elements or steps that are not in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising thousands of different elements and by means of a suitably programmed computer. In the unit claims enumerating the thousands of devices, thousands of these devices may be embodied by the same hardware item. The use of the words first, second, and third does not indicate any order. These words can be interpreted as Name.

 It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

Rights request

A method for monitoring synchronization of an Ethernet clock, the method comprising:

 The master clock device sends a clock synchronization Sync message to the slave clock device;

 Receiving a delay request message returned from the clock device, where the delay request message carries link delay information between the master clock device and the slave clock device determined by the slave device;

 The master clock device determines a time offset between the master clock device and the slave clock device according to the received link delay information;

 Determining whether the time deviation is less than a set time deviation threshold;

 When the time deviation is not less than the set time deviation threshold, a clock synchronization abnormality alarm signal is issued.

 2. The method according to claim 1, wherein when the slave clock device is a two-step clock, the method further includes:

 The master clock device receives the delay request that is sent by the slave clock device, wherein the delay request follows the time stamp Τ3, where Τ3 is the time for sending the delay request message from the clock device.

 The method according to claim 1 or 2, wherein the determining a time offset between the master clock device and the slave clock device comprises:

 The master clock device determines, according to the timestamp Τ3 carried in the delay request message, the time Τ4 of the delay request message and the link delay information carried in the delay request message, Time offset between the master clock device and the slave clock device;

 When there is an end-to-end transparent clock device between the master clock device and the slave clock device, the delay request message further carries the resident time information of the end-to-end transparent clock device, where the master clock is determined. The time offset between the device and the slave clock device includes:

 The master clock device according to the timestamp Τ3 carried in the delay request message, the time 自身4 of the delay request message received by the master clock device, the link delay information, and the end-to-end transparent clock device The dwell time information determines the time offset between the master clock device and the slave clock device.

 The method of claim 1 or 2, wherein the delay request message returned from the clock device further includes:

 When the master clock device determines that the upper-level master clock device exists, the master clock device serves as a slave clock device of the upper-level master clock device, and returns a delay request message to the upper-level master clock device. The delay request message carries the link delay information between the last pair of time periods determined by the master clock device of the slave clock device and the upper-level master clock device, and each determined slave belongs to itself. Time offset of the clock device, clock identification information for each slave clock device, and timing information for determining each time offset.

5. The method of claim 4, wherein the method further comprises: When the master clock device does not have the upper-level master clock device, the master clock device records the clock identification information of each slave clock device in the networking, and records each slave clock device in each pair of time periods and itself. Time offset, wherein the time offset is determined based on the sum of the time offsets between the slave clock device and each stage master clock device.

 6. A device for monitoring Ethernet clock synchronization, wherein the device comprises:

 a sending module, configured to send a clock synchronization Sync message to the slave clock device;

 a receiving module, configured to receive a delay request message returned from the clock device, where the delay request message carries link delay information between the master clock device and the slave clock device determined by the clock device;

 a determining module, configured to determine a time offset between the master clock device and the slave clock device according to the received link delay information;

 a determining module, configured to determine whether the time deviation is less than a set time deviation threshold;

 The alarm module is configured to issue a clock synchronization abnormality alarm signal when the determining module determines that the time deviation is not less than a set time deviation threshold.

 The device according to claim 6, wherein the receiving module is further configured to: when the slave clock device is a two-step clock, receive a delay request following message sent by the slave clock device, The delay request carries the timestamp T3, and T3 is the time for sending the delay request message from the clock device.

 The device according to claim 6 or 7, wherein the determining module is configured to receive the delay request message according to the timestamp T3 carried in the delay request message. Time T4 and link delay information carried in the delay request message, determining a time offset between the master clock device and the slave clock device;

 When there is an end-to-end transparent clock device between the master clock device and the slave clock device, the delay request message further carries the resident time information of the end-to-end transparent clock device, and the determining module, The method is further configured to: timestamp T3 carried in the delay request message, time 自身4 in which the delay request message is received by itself, the link delay information, and the station of the end-to-end transparent clock device. The time information is used to determine the time offset between the master clock device and the slave clock device.

 The device according to claim 6 or 7, wherein the sending module is further configured to: when it is determined that the upper-level master clock device exists, return a delay request to the upper-level master clock device. a message, wherein the delay request message carries the link delay information between the last pair of time periods determined by the master clock device of the slave clock device and the upper-level master clock device, and the determined attribution to itself The time offset of each slave clock device, the clock identification information of each slave clock device, and the timing information for each time offset.

 The device of claim 9, wherein the device further comprises:

 a storage module, configured to record, according to clock identification information of each slave clock device in the networking, when the upper-level master clock device does not exist, record a time deviation of each slave clock device from itself in each pair of time periods, where The time offset is determined based on the sum of the time offsets between the slave clock device and each stage master clock device.