WO2015062663A1

WO2015062663A1 - Driven dual phase lock loop

Info

Publication number: WO2015062663A1
Application number: PCT/EP2013/072847
Authority: WO
Inventors: Steve Tanner; Yazhou Zhao; Pierre-André Farine
Original assignee: Ecole Polytechnique Federale De Lausanne (Epfl)
Priority date: 2013-10-31
Filing date: 2013-10-31
Publication date: 2015-05-07
Also published as: EP3063873A1

Abstract

The invention relates to a phase lock loop (100) comprising: - a loop filter (140), - a voltage controlled oscillator (150), - a frequency divider (160), - a frequency lock detector (113), able to emit a frequency lock indication signal (LOCK), - a digital phase and frequency comparator (110), - a charge pump (111), and - an analogue phase comparator (120). The loop is essentially characterized in that it further comprises a switch (130) equipped with an output connected to the loop filter (140), and with two inputs, this switch being able to selectively connect the first input, originating from the analogue phase comparator, to its output in response to the lock indication signal; and its second input, originating from the digital phase and frequency comparator, to its output, in the absence of the lock indication signal.

Description

DUAL PHASE LOCKED AND PILOTED BUCKLE

Technical area

The present invention relates to the field of phase locked loops or phase locked loops more generally called PLL (for "Phase-Locked Loop" in English).

[0002] PLLs are electronic circuits that make it possible to slave the phase of the output signal to the phase of the input signal, and which also make it possible to slave a frequency of the output signal to a multiple of the frequency of the signal. input.

State of the art

A conventional phase-locked loop comprises:

a phase comparator,

a charge pump,

a loop filter,

a voltage controlled oscillator (or VCO for Voltage Controlled Oscillator in English), and

- a frequency divider.

[0004] PLLs are mainly used as frequency synthesizers (generation of a high frequency from a reference frequency) in very wide application domains covering telecommunications, radio frequency, computers, etc.

PLL performance is affected in particular by intrinsic interference related to the electronic circuit and components or by extrinsic parasites related to the conditions of use.

In particular, PLLs have a phase noise that is generally desirable to reduce as much as possible.

[0007] It is known from US2002 / 0158621 a dual mode PLL which comprises a digital branch and an analog branch, both connected to the charge pump.

[0008] I ntroducing an analog branch in a PLL is an interesting solution that makes it possible to reduce the phase noise. Indeed, an analog circuit chosen with high linearity introduces less noise from phase that a digital circuit whose limited linearity is obtained by averaging.

Disclosure of the invention

A main object of the present invention is to improve the solution of the prior art.

More specifically, according to a first of its objects, the invention relates to a phase-locked loop capable of locking the frequency and the phase of an output signal on the frequency and the phase of an input signal. , this loop comprising:

a loop filter equipped with an input,

a voltage controlled oscillator comprising an output on which it generates the output signal and an input of which is electrically connected to an output of the loop filter,

a digital phase and frequency comparator having an input electrically connected to an output of the frequency divider and having another input connected to the input signal,

a frequency divider whose input is electrically connected to the output of the voltage controlled oscillator and whose output supplies the digital phase and frequency comparator,

a phase and frequency lock detector, which emits a phase lock indication signal only when the two inputs of the digital phase and frequency comparator have the same phase,

a charge pump whose input is electrically connected to an output of the digital phase and frequency comparator, and

an analog phase comparator having an input electrically connected to an output of the frequency divider and having another input electrically connected to the input signal.

[001 1] It is essentially characterized by the fact that it further comprises:

a switch comprising an output electrically connected to the input of the loop filter, a first input and a second input, this switch being able to selectively connect the first input, coming from the analog phase comparator, to its output in response the lock indication signal; and its second input, from the digital phase and frequency comparator, at its output in the absence of the lock indication signal.

Preferably, the frequency lock detector is electrically connected to the switch, so that the frequency lock indication signal is able to control the switching of said switch.

[0013] Preferably, the analog phase comparator is a passive multiplier.

It is possible to provide an analog branch amplifier whose inputs are electrically connected to the outputs of the analog phase comparator and whose outputs are electrically connected to the switch. In this case, this amplifier has the function of increasing the gain and transforming a voltage signal into a current signal.

It can further provide an analog branch filter whose inputs are electrically connected to the outputs of the analog phase comparator and whose outputs are electrically connected to the inputs of the analog branch amplifier.

[0016] Preferably, the analog branch amplifier is a transconductance operational amplifier.

According to another of its objects, the invention relates to an atomic clock comprising a phase-locked loop according to the invention.

Finally, according to another of its objects, the invention relates to a timepiece comprising an atomic clock according to the invention.

According to the invention, and contrary to the aforementioned document US2002 / 0158621, the charge pump is only connected to the digital phase and frequency comparator of the digital branch, and not to the phase comparator of the analog branch. , which improves the signal-to-noise ratio, the charge pump generally suffering from non-linearities.

Brief description of the drawings

Other features and advantages of the present invention will appear more clearly on reading the following description given by way of illustrative and nonlimiting example and with reference to the appended figures in which:

[0021] FIG. 1 illustrates an embodiment of a PLL according to the invention,

[0022] FIG. 2 illustrates an embodiment of an analog phase-passive comparator according to the invention,

[0023] FIG. 3 illustrates an embodiment of an analog branch amplifier according to the invention,

[0024] FIG. 4 illustrates another embodiment of a passive phase analog comparator according to the invention,

[0025] FIG. 5 illustrates an atomic clock equipped with a phase-locked loop according to the invention, and

[0026] - Figure 6 illustrates a timepiece equipped with an atomic clock according to the invention.

Mode (s) of realization of the invention

As illustrated in FIG. 1, the phase-locked loop 100 according to the invention, hereinafter PLL, comprises a digital phase and frequency comparator 1 10.

An input signal IN, also called a reference signal, enters the PLL at the frequency f_in and leaves it in the form of an output signal OUT at the frequency f_out.

The PLL comprises a digital branch DIGIT (dashed figure 1) and a feedback loop FBL (for FEEDBACK LOOP in English, dotted Figure 1). By "branch" is meant all the electronic components arranged in series between the input of the PLL and a loop filter 140.

The DIGIT digital branch comprises a digital phase and frequency comparator 1 10, and a charge pump 1 1 1.

The input signal IN is input to the digital phase and frequency comparator 1 10.

The digital phase and frequency comparator 1 10 is a digital (non-linear) circuit. Without locking, it outputs a correction signal COR in the form of high or low pulses whose number allows to drive a controlled voltage oscillator 150, the high pulses for increasing the frequency of the voltage controlled oscillator 150 and the low pulses for decreasing the frequency of the voltage controlled oscillator 150. In latching, it emits at the output a correction signal COR equal to 0 V.

There is provided a charge pump 1 1 1 which makes it possible to transform the pulses of the correction signal COR into current pulses, and which can be connected to a loop filter 140. The charge pump 1 1 1 is an intrinsically nonlinear electronic component.

Preferably, the PLL comprises the loop filter 140 which makes it possible to filter, that is to say to limit the bandwidth of the correction signal COR. The loop filter 140 also makes it possible to limit the regulation speed of the PLL. For this, the filter 140 is typically a passive low pass filter.

At the input of the loop filter 140, the correction signal COR is a current signal; and at the output of the loop filter 140, the correction signal COR is a voltage signal.

For simplification the signal COR is illustrated as a single signal, in fact it may be a differential signal, in this case between the input signal IN and DIV split signal described later.

The correction signal COR filtered by the loop filter 140 is input to a voltage controlled oscillator 150 (or VCO for Voltage Controlled Oscillator English).

The voltage controlled oscillator 150 is an oscillating circuit whose oscillation frequency is controlled by the input voltage of this circuit, in this case by the corrected COR correction signal.

At the output of the voltage controlled oscillator 150, the output signal OUT is fed to the output of the PLL. Beforehand, it can be amplified by an amplifier, in this case a power amplifier (not shown).

The output signal OUT is also fed to the input of the feedback loop FBL. Feedback loop

The feedback loop FBL comprises a frequency divider 160.

Preferably, the frequency divider 160 is programmable.

In this case, the output signal OUT, a feedback signal, is inputted to the frequency divider 160 which outputs an output signal DIV, hereinafter referred to as a divided signal. The frequency of the divided signal DIV is equal to the frequency f_out of the output signal OUT divided by a number N which depends on the type of frequency divider 160 implemented. In this case N can be any and not be a natural number.

It can be provided that the feedback loop FBL further comprises a duty cycle controller 170, either in the form of an autonomous block or integrated, for example integrated in the frequency divider 160.

Preferably, the duty cycle controller 170 is configured to transform the input signal into an output signal whose duty ratio is at most 50%, for example 50% +/- 10%, which improves the performance of the analog branch. Indeed, the digital phase and frequency comparator 1 10 of the digital branch is triggered on the rising edges of its input signals, and is insensitive to the duty cycle. On the other hand, in an analog branch, a phase-analog comparator 120 exposed later is sensitive to the average value of the input signal. A 50% duty cycle ensures that the analog comparator operates at an optimal point, ie in the middle of its dynamics.

After the eventual duty cycle controller 170, the divided signal DIV is fed into the input of the digital branch DIGIT of the PLL.

In this case, the divided signal DIV is input to the digital phase and frequency comparator 1 10, so that it measures the difference between the phase of the divided signal DIV and the phase of the signal d input IN, as well as the difference between the frequency of the divided signal DIV and the frequency f_in of the input signal IN. The high or low pulses emitted by the digital phase and frequency comparator 1 10, converted into current pulses by the charge pump 1 1 1, and converted into voltage by the loop filter 140, make it possible to increase or decrease the value of the frequency of the voltage-controlled oscillator 150 as a function of the value of the difference measured in phase and in frequency by the phase comparator. The value of the frequency of the output signal f_out can thus be corrected so that it respects the equation f_out = f_in / N. In this case, it is said that the frequency is locked.

Advantageously, the feedback loop further comprises a phase shifter 180, in this case 90 °. The divided signal DIV is fed to the input of the phase-shifter 180, in this case downstream of the duty cycle controller 170. At the output of the phase-shifter 180, the output signal DIV90 of the phase-shifter 180 is the input signal DIV whose phase is rotated 90 °.

At the initialization of the analog branch, the digital branch is locked. However, if the phase comparator of the analog branch detects an error, it introduces a disturbance in the PLL which may then lose the lock. To limit this risk, it is expected that the analog phase comparator 120 generates at the initialization of the analog branch a zero error signal (in this case a voltage of 0 volts). Thanks to the phase-shifter 180, the signal DIV90 is phase-shifted by 90 ° with respect to the input signal IN. As these two signals IN and DIV90 are brought to the input of the analog phase comparator 120, it does generate a signal equal to 0V at the initialization of the analog branch. Indeed, the operating point of the digital phase and frequency comparator 1 10 of the digital branch (correction signal equal to 0 when its inputs are in phase) is different from the operating point of the phase comparator of the analog branch ( output signal PHA equal to 0 when its inputs are 90 ° out of phase).

Analog branch [0049] The PLL also includes an analog ANALOG branch (in dotted lines in FIG. 1). In this case, the phase noise generated by the analog branch is less than that generated by the digital branch, in particular because of its greater linearity compared to the blocks of the branch digital, the digital phase and frequency comparator 1 10 and the charge pump 1 1 1, which are essentially non-linear blocks.

The ANALOG analog branch comprises the phase comparator 120.

Preferably, the analog phase comparator 120 is an analog multiplier, preferably passive, an embodiment of which is illustrated in FIG. 2. The multiplier is more commonly called a mixer by anglicism. In Figure 2, RFp and RFn are the differential inputs for the signal FIN, while LOp and LOn are the differential inputs for the signal DIV90. Ifp and I Fn are the outputs. The advantage of this embodiment lies in the fact that the transistors are used in switching and add very little thermal noise to the signal. The alternating switching current is transposed at high frequencies and can be easily filtered.

An evolution of the analog multiplier of FIG. 2 is illustrated in FIG. 4. In FIG. 2, a transconductor g _m is arranged at the inputs RFp and RFn; in FIG. 4, this transconductor is suppressed, which is possible thanks to the sufficient amplitude of the signal DIV90 on one of the RFp or RFn inputs. In addition, a resistor R1, R2 is added in series with the capacitance C1 and C2 respectively, so as to improve the equivalent input impedance and to form a low-pass filter, in this case first-order.

A passive analog multiplier has the advantage of having a very linear output and very little noise flicker (noise flicker anglicism) and thermal noise. It can be used as a phase comparator, but not as a frequency comparator. It can therefore be used only with a blocked frequency, ie when the PLL is already locked. In this case, its good linearity and low noise level make it possible to reduce the phase noise in comparison with a digital comparator or even an active multiplier.

As the output of the analogue phase comparator 120 is a voltage, at least one electronic component is preferably provided for transforming this voltage into a current, which makes it possible to feed the input of the loop filter 140. For this purpose, the analogue branch ANALOG may further comprise an analog branch amplifier.

An embodiment of an analog branch amplifier 122 is illustrated in FIG. 3. In this example, the circuit is symmetrical and allows, for reasons partially explained here, to obtain a reduced gain, as well as a band. satisfactory pass-through and stability without degrading the noise.

The analog branch amplifier 122 makes it possible to transform an input voltage into an output current. The function is therefore the same as that of the charge pump 1 1 1. When the analog branch is activated, the loop filter 140 is powered only by the output load of the analog branch amplifier 122.

In this case, there is provided an operational transconductance amplifier or OTA for "operational transconductance amplifier" in English, which is an intrinsically linear electronic circuit, that is to say whose output current is a linear function of the differential input voltage.

With this feature, a single loop filter 140 can be used for both the digital branch and the analog branch.

In Figure 3, the OTA is based on a fully differential symmetrical amplifier. Differential input transistors M5 and M6 are PMOS, which generate less noise than NMOS. Equipped with a Vbias bias current, the PMOS transistor M4 copies the current from a BIAS polarization block according to a certain ratio. A supply voltage Vcmfb comes from a block CMFB and drives the PMOS transistors M1 1, M12 to adjust and stabilize the output level of the analog branch when the PLL is locked. A first stage of the OTA consists of the NMOS transistors M7 and M8 connected to the nodes Vb1 and Vb2. Two NMOS transistors M9 and M10 form two current mirrors to copy the output current of the first stage to a second stage in a certain ratio. Then, the current bridges M13 and M14 (NMOS transistors) are connected in a cross-coupling manner to increase the bandwidth and the phase margin of ΓΟΤΑ with the loop filter load, so as to guarantee the stability of the locked loop system.

As ΓΟΤΑ is activated once the PLL is locked, the gain, which intrinsically represents the sensitivity of the response of the detected error, becomes relatively low. In addition, the trade-off between noise and phase margin is facilitated.

In replacement, an operational amplifier can be provided as an analog branch amplifier 122, but the response thereof being in voltage, an OTA is preferred, which remains coherent with the digital branch which generates a current signal at the same time. output of the charge pump.

It is also possible to provide an analog branch filter 121, in particular interposed between the analog phase comparator 120 and the analog branch amplifier, as shown in FIG. 1, and which smooths the voltage output of the analog comparator of FIG. phase 120.

The analog branch filter 121 and the analog branch amplifier 122 may be autonomous blocks as shown in Figure 1, or integrated, for example the phase comparator.

The input signal IN is fed to the input of the analog branch, in this case to the input of the phase comparator 120. Another input of the phase comparator is connected to the output signal DIV90 of the phase shifter 180.

At the output of the phase comparator, a PHA phase signal is emitted, in this case a voltage signal. This voltage is filtered by the analog branch filter 121 and then amplified by the analog branch amplifier 122 whose output is a current signal, which can be connected to the input of the loop filter 140.

It is advantageous to selectively connect the loop filter 140:

the COR correction signal from the charge pump 1 1 1, or

phase signal PHA of the phase comparator, in this case filtered and amplified. The selection of one of these inputs of the loop filter 140 is performed by a switch, in this case by a multiplexer 130 which selectively enables the activation of the analog branch or the activation of the digital branch.

Multiplexer 130

The multiplexer 130 is connected at the output to the loop filter 140, and connected at the input:

the COR correction signal from the charge pump 1 1 1, or

phase signal PHA of the phase comparator, in this case filtered and amplified.

The selection of the input of the multiplexer 130 is preferably carried out by means of a control signal, in particular the LOCK signal described hereinafter.

Operation

At the initialization of the PLL, the digital branch is activated by default: the input of the loop filter 140 is connected to the COR correction signal from the charge pump 1 1 1.

The digital phase and frequency comparator 1 10 operates first in frequency detection mode.

The digital phase and frequency comparator 1 10 and the charge pump 1 1 1 make it possible to control the frequency f_out of the output signal OUT of the voltage-controlled oscillator, via the input voltage thereof. to change said frequency f_out until the difference between the frequency of the divided signal DIV and the frequency f_in of the input signal IN is zero, i.e. f_out = f_in / N.

When the difference between the frequencies is zero, the digital phase and frequency comparator 1 10 of the digital branch automatically switches to phase comparator mode. Where the difference between the phases is in addition zero, ie in the linear regime of digital phase and frequency comparator 1 10 of the digital branch, the PLL is said to be locked.

The digital phase and frequency comparator 1 10 comprises a phase and frequency lock detector 1 13, which emits a phase lock indication signal LOCK, only when the two inputs of the phase digital comparator and frequency have the same phase.

The detection of the lock indication signal LOCK can control the switch 130, so the activation of the analog branch or the digital branch.

In this case, the multiplexer 130 is controlled by the LOCK lock indication signal which, upon detection of the lock, selects the input of the analog branch so that the input of the loop filter 140 is then connected to the phase PHA phase signal of the phase comparator, in this case filtered and amplified.

The charge pump 1 1 1 is a component whose impulse response is nonlinear. As the charge pump 1 1 1 is present only in the digital branch and the analog branch is free, the behavior of the analog branch is linear, which reduces the phase noise and improves the performance of the PLL.

The analog branch has a linear behavior and allows, by the phase comparator, to compare the phase of the input signal IN to the phase of the divided signal, in this case to the phase of the DIV90 output signal of the phase-shifter. 180.

In the event of a disturbance such that the PLL loses the lock, the LOCK lock indication signal of the digital phase and frequency comparator 1 10 goes to 0, which for example drives the multiplexer 130 to reactivate the digital branch. instead of the analog branch. When the digital branch has been used to lock the PLL again, the LOCK signal becomes active and again allows the analogue comparator to be selected in stable operation mode.

The digital branch performs well in locking but has a high phase noise. The analog branch performs poorly in locking but powerful in phase noise, once locked. The invention advantageously uses the complementarity of these two branches and the automatic switching from one to the other to obtain a PLL with overall better performance.

The phase locked loop 100 can be integrated in an atomic clock 200. The atomic clock 200 can be integrated into a timepiece 300.

Nomenclature

100 PLL

1 10 digital phase and frequency comparator

1 charge pump

1 12 digital branch amplifier

1 13 phase and frequency lock detector

120 analog phase comparator

121 analog branch filter

122 analog branch amplifier

130 multiplexer

140 loop filter

150 voltage controlled oscillator (VCO)

160 frequency divider

170 duty cycle controller

180 phase shifter

200 atomic clock

300 timepieces

FBL feedback loop

ANALOG analog branch

DIGIT digital branch

Claims

A phase locked loop (100) adapted to lock the frequency and phase of an output signal (OUT) on the frequency and phase of an input signal (IN), said loop comprising:

a loop filter (140) equipped with an input,

a voltage controlled oscillator (150) comprising an output on which it generates the output signal and an input of which is electrically connected to an output of the loop filter (140),

a digital phase and frequency comparator (1 10) whose input is electrically connected to an output of the frequency divider (160) and of which another input is connected to the input signal (IN),

a frequency divider (160) whose input is electrically connected to the output of the voltage controlled oscillator (150), the output of which supplies the digital phase and frequency comparator,

a phase and frequency lock detector (1 13), which emits a phase lock indication signal (LOCK) only when the two inputs of said digital phase and frequency comparator (1 10) have the same phase ,

a charge pump (1 1 1) whose input is electrically connected to an output of the digital phase and frequency comparator (1 10), and

a phase analog comparator (1 20) having an input electrically connected to an output of the frequency divider (160) and having another input electrically connected to the input signal (IN),

characterized in that it further comprises

a switch (130) comprising an output electrically connected to the input of the loop filter (140), a first input and a second input; said switch being adapted to selectively connect the first input from the analog phase comparator (120) to its output in response to the lock indication signal; and its second input, from the digital phase and frequency comparator (1 10), at its output, in the absence of the lock indication signal.

The phase locked loop (100) according to claim 1, wherein the phase and frequency lock detector (1 13) is electrically connected to the switch (130), so that the latching indication signal of frequency (LOCK) is able to control the switching of said switch (130).

The phase locked loop (100) according to any one of the preceding claims, wherein the analog phase comparator (120) is a passive multiplier.

The phase locked loop (100) according to any one of the preceding claims, wherein an output of the charge pump

(1 1 1) is electrically connected to the second input of the switch (130).

The phase locked loop (100) according to any one of the preceding claims, further comprising an analog branch amplifier (122) whose inputs are electrically connected to the outputs of the phase comparator (1 20) and whose outputs are electrically connected to the switch (130).

The phase locked loop (100) according to claim 5, further comprising an analog branch filter (121) whose inputs are electrically connected to the outputs of the analog phase comparator (120) and whose outputs are electrically connected to the inputs of the analog branch amplifier (122).

The phase locked loop (100) according to any one of claims 5 or 6, wherein the analog branch amplifier (122) is a transconductance operational amplifier.

An atomic clock comprising a phase locked loop (100) according to any one of the preceding claims.

9. Timepiece comprising an atomic clock according to claim 8.