WO2015025041A1

WO2015025041A1 - Optimisation of envelope tracked power amplifier

Info

Publication number: WO2015025041A1
Application number: PCT/EP2014/067926
Authority: WO
Inventors: Gerard Wimpenny; Martin Wilson
Original assignee: Nujira Ltd
Current assignee: Nujira Ltd
Priority date: 2013-08-23
Filing date: 2014-08-22
Publication date: 2015-02-26
Anticipated expiration: 2016-02-23
Also published as: GB2517496A; GB201315120D0

Abstract

The invention relates to an amplifier arrangement comprising an envelope tracked power supply providing a modulated supply voltage and a modulated bias voltage; a power amplifier stage having a supply voltage input and at least two bias voltage inputs, wherein the supply voltage input is connected to receive the modulated supply voltage and one of the bias voltage inputs is connected to receive the modulated bias voltage and further adapted to receive the modulated supply voltage and the modulated bias voltage.

Description

OPTIMISATION OF ENVELOPE TRACKED POWER AMPLIFIER

Field of the Invention:

The present invention relates to power amplifier architectures, and in particular power amplifier architectures employing an envelope tracked modulated power supply, and in which a modulated supply voltage and a modulated bias voltage are provided to the power amplifier . Background to the Invention :

Traditionally power amplifiers have operated with a fixed supply voltage and a fixed bias voltage, and are optimised to provide for best trade-off between efficiency and linearity under these conditions . The instantaneous RF (radio frequency) output voltage is dependent on only the instantaneous RF input voltage in such an arrangement.

In an improved arrangement envelope tracking is used to provide a supply voltage for a power amplifier which is modulated and derived from the instantaneous RF input voltage . The instantaneous RF output voltage of the power ampli fier is thus dependent on both the instantaneous supply voltage and the instantaneous RF input voltage. Typically a non-linear mapping function or shaping table is utilised in the envelope path to define the relationship between the powe ampl i fier' s RF input voltage and a supply voltage .

Figure 1 illustrates an example implementation of a known envelope tracking power amplifier architecture. As illustrated in Figure 1, the envelope tracked power amplifier architecture 10 comprises a modulator 2 which generates a modulated signal .

The modulated signal is provided by the modulator 2 to a delay adjust block 11, which in turn provides an input to an upconvert block 12. The upconvert block 12 converts the modulated signal into an RF signal and then provides this as an input to an RF power amplifier 8. The delay adjust block 11 is provided to compensate for delays in the envelope path as is known to one skilled in the art. It should be noted that in general a delay could also or alternatively be provided in the envelope path. The purpose of any delay is to align the s ignals in the envelope and RF paths at the power amplifier . The RF power amplifier 8 generates an RF output which is an amplified version of the RF signal at its input.

The modulator 2 also generates a signal to an envelope detect block 4 , which generates at its output an envelope signal which represents the envelope of the instantaneous input signal.

The envelope signal is provided as an input to a voltage generation block 6, which provides a supply voltage V_suppi_y on line 22 and a bias voltage V_bias on line 20 to the RF power amplifier 8. The illustrated voltage generation block 6 includes first and second non-linear mapping means and an envelope amplifier comprising the supply modulator .

A trade-off between ef ficiency and linearity may be controlled by the choice of non-linear mapping functions.

I he example of Figure 1» there is illustrated a first non-linear mapping function block 14 provided for generation of a modulated voltage supply, and a second non-linear mapping function block 16 provided for generation of a modulated bias voltage . In the arrangement of Figure 1 the non-linear mapping function block 14 p ovides a input to an envelope amplifier 18, which generates a modulated supply V_suppi_y 22. The non-linear mapping function block 16 directly generates the modulated bias voltage V_bias o line 20.

The arrangement as illustrated in Figure 1 is described in more detail in WO 2007/000959. The linearity and efficiency trade-off may be optimised through use of the two non-linear mapping function blocks 14 and 16, to provide both a modulated supply voltage and a modulated bias voltage .

I has long been a goal to implement handset power amplifiers in CMOS (complimentary metal oxide semiconductor) technology rather than GaAs (gallium arsenide) technology, due to CMOS cost and integration advantages.

Howe e , one problem with fixed supply CMOS power amplifiers is that it is difficult to achieve an acceptable trade-off between efficiency and linearity due to the inherent "soft compression" characteristics of CMOS power amplifiers and strong AM- ?M modulation.

Furthermore, in a second problem the low breakdown voltage of small geometry CMOS processes have made it di fficult to implement watt level handset power amplifiers without suffering excessive output match losses due to the high impedance transformation ratio required at this power level .

The use of envelope tracking power supplies has overcome the first problem of fixed power supplies, such that the use of envelope tracking in conjunction with CMOS power amplifiers largely overcomes the soft compression problem, as the shaping table ra her than the intrinsic device characteris ics define the envelope tracking power amplifiers compression characteristic .

However in order to provide a practical implementation, it is additionally necessary to address the second problem, namely the low breakdown voltage problem.

It is an aim of the present invention to provide a power amplifier architecture which can be implemented in CMOS technology in conjunction with an envelope tracking power supply, and which address one or more of the above-stated problems .

Summary of the Invention :

In one aspect the invention provides an amplifier arrangement comprising an envelope tracked power supply providing a modulated supply voltage and a modulated bias voltage ; a powe amplifier stage having a supply voltage input and two or more bias voltage inputs , wherein the supply voltage input is connected to the modulated supply voltage and a least one of the bias vol age inputs is connected to the modulated bias voltage .

One of the bias voltage inputs may be connected to receive a fixed bias voltage . The power amplifier may comprise stacked transistors, wherein the stacked transistor connected to receive the amplifier input signal is connected to receive a fixed bias voltage, and wherein one or more further stacked transistors are connected to receive the modulated bias voltage.

The power amplifier may comprise at least three stacked transistors, each transistor other than the one connected to receive the amplified input signal being connected to receive a different scaled modulated bias vol tage .

The e may be provided a first non-linear mapping circuit for providing the modulated supply voltage based on an e velope of an input signal to be amplified.

There may be provided a second non-linear mapping circuit for providing the modulated bias voltage based on the envelope of the input signal to be amplified. There may be provided scaling circuitry for providing the modulated bias voltage derived from the output of the first non-linear mapping circuit. There may be provided a plurality of scaling circuits for providing a plurality of modulated bias voltages derived from the output of the first non-linear mapping circuit .

The transistors of the power amplifier may be CMOS devices, or GaAs HBT devices, or SiGe devices, or Ga devices.

The power amplifier comprises a cascode topology comprising at least two stacked transistors.

An upper cascode transistor may rece ive the modulated supply voltage and the modulated bias voltage, and the lower cascode transistor receives a fixed bias voltage. The envelope tracked power supply may include a first non-linear mapping circuit for providing the modulated supply voltage and a second non-linear mapping circuit for providing the modulated bias voltage .

The envelope tracked power supply may include a single non-linear mapping circuit for providing the modulated supply voltage and the modulated bias vol age .

The modulated bias voltage may be a scaled and offset version of the output of the non-linear mapping circuit .

The power amplifier may comprise a stacked field effect transistor, FET, amplifier topology. The envelope tracked power supply may include a single non-linear rr.app ing circuit for providing the modulated supply voltage and the modulated bias voltage. There may be provided scaling and offsetting circuitry for providing modulated bias voltage. The power amplifier may comprise two or more stacked transistors, and there is provided one or more scaling circuits for providing one or more modulated bias voltages to one or more of the two or more transistors.

The power amplifier may comprise a stacked cascode topology. The envelope tracked power supply may include a single non-linear mapping circuit for providing the modulated supply voltage and the modulated bias voltage. The power amplifier may comprise four stacked transistors , and there is provided three scaling and offsetting circuits for providing three modulated bias voltages to the three transistors.

There is also provided a method of providing voltages to a power amplifier having a supply voltage input and two or more bias voltage inputs , comprising connecting the supply voltage input to a modulated supply voltage and connecting one of the two or more bias voltage inputs to a modulated bias voltage .

The method may further comprise connecting a first bias voltage input to a modulated bias voltage and connecting a second bias voltage input to a fixed supply.

The method may further comprise stacked transistors, the method comp i s ing connecting one of the stacked transistors to receive the input signal to be amplified and the fixed bias voltage .

The method may further comprise connecting each other of the stacked transistors to receive a modulated bias voltage.

The method may provide a modified version of a modulated bias voltage to each of a plurality of the stacked transistors .

The method may comprise modifying a shaping function output generated for the modulated supply voltage.

Description of the Figures :

The present invention is now described by way of reference to the following Figures, in which :

Figure 1 illustrates an envelope tracking power amplifier architecture in accordance with the prior art;

Figure 2 illustrates a prior art arrangement of a cascode power amplifier;

Figure 3 illustrates the implementation of a cascode envelope tracked power amplifier architecture in accordance with an improved arrangement;

Figure 4 is illustrates the implementation of a modulated cascode envelope tracking power amplifier architecture in accordance with an improved arrangement;

Figures 5(a) to 5(c) illustrate improved cascode envelope tracking power amplifier performance in accordance with an improved arrangement;

Figure 6 illustrates a stacked FET power amplifier architecture in accordance with the prior art;

Figure 7 illustrates a stacked FET envelope tracked power amplifier architecture in accordance with an improvement;

Figures 8(a) to 8(c) illustrate performance of a stacked FET envelope tracked power amplifier resui t in accordance with an improve ent ;

Figure 9 illustrates a stacked cascode power amplifier in accordance with the prior art;

Figure 10 illustrates a stacked cascode envelope tracking power amplifier architecture in accordance with an improvement; and

Figures 11(a) to 11(c) illustrate performance of a stacked cascode envelope tracking power amplifier result in accordance with an improvement.

Description of the Preferred Embodiments:

The invention is now described by way of reference to a particular example and embodiment. In particular the invention is described by way of reference to the implementation of an envelope tracking power supply for a radio frequency power amplifier, which may be utilised in applications such as mobile cellular handsets. However the invention is not limited to such an application, and in general the invention is applicable to the implementation of any power amplifier incorporating an envelope tracked modulated power supply.

The advantageous arrangements described herein are applicable to single stage amplifier arrangements in which the single stage of the amplifier requires at least one supply voltage and two or more bias voltages. The advantageous arrangements may be applicable in multistage amplifier arrangements, in which a single stage of the multistage arrangement requires two or more bias voltages.

An example is an amplifier stage comprising stacked transistor devices. In general an amplifier comprising stacked transistor devices includes two or more transistor devices. Two transistor devices are stacked when the source of one transistor device is connected to the drain of another transistor device. In general, multiple transistor devices are stacked when the source of each device is connected to the drain of another device, the transistor devices thus forming a stacked chain. The aim of the stacking is to distribute voltages across the stacked devices, thereby allowing the stacked assembly to operate at a higher voltage than a single device .

In a stacked arrangement, a lower transistor receives the signal to be amplified at its gate, and an upper transistor provides the amplified output signal at its drain. Each transistor has a gate bias voltage, and thus two gate bias voltages are required. Alternative stacked architectures require additional transistors connected between the lower and upper transistors, and additional gate bias voltages are required for each of the additional transistors. In an arrangement where an amplifier is provided with a modulated supply voltage and a modulated gate bias voltage, then for an amplifier requiring two or more gate bias voltages consideration must be given as to which gates to modulate.

In the following there are described arrangements in which a power amplifier stage includes stacked transistor devices , but in general the advantages discussed can be obtained in any amplifier stage having a power supply input and at least two bias inputs.

Advantageously, in accordance with the preferred arrangements described herein a modulated voltage is connected to one or more bias inputs and a fixed voltage is connected to another bias input . More specifically, the fixed voltage is provided as a bias voltage for the transistor havi g its gate connected to receive the input signal to be amplified, and one or more modulated voltages are provided as bias voltages for one or more upper transistors in the stack. The modulated voltage for each transistor may be generated independently, or may be generated from a common source but scaled and offset, as discussed in further detail below.

In a first arrangement , the low breakdown voltage problem can be addressed by providing a stacked arrangement using the well-known cascode topology for a power amplifier. In this arrangement two devices are provided. A lower device of the stack operates in common source mode and an upper de ice of the stack operates in common gate mode. This technique may be used in conjunction with specialised high voltage devices to furthe extend the operating voltage .

An example cascode topology is illustrated in Figure 2. Reference numeral 30 illustrates a power amplifier stage. As illustrated in Figure 2, the power amplifier 30 receives a DC supply voltage V_DCsupply, and two DC bias voltages, V_{DC b}ias i and V_DC bias 2. An input RF signal is received on line 4 8 , and an amplified RF output signal is provided on an output line

5 0 .

The power amplifier is preferably constituted of an upper CMOS transistor 32 and a lower CMOS transistor 3 4 .

An input match circuit 3 8 provides a matching input for the input signal on line 48, and is further connected to the gate of the lower CMOS device 34 . The gate of the lower CMOS device 3 4 is also connected to the first fixed bias voltage V_DC bias 1 via resistor 44. The gate of the upper CMOS device 32 is connected to the second ixed bias voltage V_DC bias 2 via the resistor 4 0 .

The gate of the transistor 3 2 is also connected to electrical ground via capaci tor 46, which presents an RF short circuit. The output signal on line 50 is provided through an output match circuit 36, which is connected to the drain of the upper CMOS device 32. The drain of the upper CMOS device

32 is connected to receive the fixed supply voltage V_DCsup i through the inductor 4 2 .

The source of the upper CMOS device 32 is connected to the drain of the lower CMOS device 3 4 consistent with a stacked topology .

With reference to Figure 3 , there is illustrated the cascode power amplifier topology arrangement of Figure 2 in combination with an exemplary envelope tracking path including two non-linear mapping functions for generating both a supply voltage and a bias voltage .

I the arrangement of Figure 3, it must be determined which of the two bias i puts of the Figure 2 arrangement the modulated bias voltage is to be applied.

The characteristics, including efficiency characte istics, of the lowest transistor in the stack can be maintained if the RF duty cycle can be he I d constant with respect to changes in the RF envelope . This can be achieved by applying envelope modulation to the gate bias of the upper device in the stack (i.e the cascode transistor), as this indirectly controls the drain bias voltage of the lower device in the stack. The duty cycle of this transistor can be controlled by controlling the voltage on its drain.

Thus it is advantageous to modulate the bias voltage of the upper transistor and maintain fixed DC bias for the lower transistor . There is little advantage in modulating the bias of the lower transistor.

Thus the arrangement of Figure 2 is modi ied such that the bias voltage applied to the gate of the upper transistor 32 is provided through a gate driver 68, which receives its input from a non-linear mapping function block or circuit 64. The gate of the upper CMOS transistor 32 is additionally connected to electrical ground by RF shorting capacitor 46. The modulated supply voltage is provided to a terminal of inductor 42 via the envelope amplifier 66 , which receives its input from a non-linear mapping function block or circuit 62. Each of the non-linear mapping function circuits 62 and 64 receive an input on line 16 from the envelope path. In the exemplary arrangement of Figure 3 first and second independent shaping tables are used to generate a modulated supply voltage and a modulated bias voltage for the cascode power amplifier arrangement, the gate bias input of the lower device of the cascode power amplifier being fixed .

The architecture of Figure 3 is well-suited to a system on a chip implementation, in which the entire RF transceiver and envelope amplifier and power amplifier are monolithically integrated .

With reference to Figure 4 there is shown an alternative implementation to Figure 3. Like reference numerals are used in Figure 4 to refer to elements which are equivalent to those elements referred to in Figure 3.

In the simplified arrangement of Figure 4 a single non- linear mapping function block or circuit 70 is provided in place of the two distinct non-linear mapping function blocks 62 and 64. The output of the non-linear mapping function block 70 is provided at an inpu to the envelope amplifier 66, and also provided as an input to an amplifier 72 having a gain K . The output of the amplifier 72 is connected to a first input of a combiner 74, which as a second input receives an output of a block 76. The block 76 provides an offset voltage having value C. The output of the combiner 74 is connected to the gate driver 68.

The overall f nction of blocks 72, 74, 76 is to provide a linear scaled and offset version of the envelope amplifier reference signal (i.e. the signal at the input to the envelope amplifier ) to the gate driver 68.

Hence, in the ar angement of Figure 4 the modulated bias voltage for the upper CMOS device 32 is linearly derived from the output of the shaping table 70, which is used to determine the modulated power amplifier supply voltage . This architecture is particularly well-suited to a power amplifier module in which the power amplifier and envelope amplifier are monolithically integrated.

It can be rioted that in the arrangement of Figure 4 the scaling circuitry for generating the modulated bias voltage may take its input from either the input or the output of the envelope amplifier 66.

A slight improvement in efficiency, gain and phase plots may be obtained with the architecture of Figure 3 compared with that of Figure 4 as a result of the additional degrees of freedom allowed by a completely independent shaping table, but nevertheless Figure 4 illustrates a useful arrangement.

Figures 5(a) to 5(c) respectively show gain, phase and efficiency contour plots for the cascode envelope tracking power amplifier of Figure 4. The benefit to efficiency and linearity of co-modulating the gate bias voltage can be clearly seen.

The solid lines 49 show the trajectory across the surfaces if gate bias modulation is used, whereas the dotted lines 51 show the trajectory across the surfaces if fixed DC gate bias is used.

The use of cascode bias modulation simultaneously improves efficiency and gain and phase flatness, which in turn are key to achieving good linearity metrics such as adjacent channel power ratio (ACPR) and error vector magnitude ( EVM ) .

In particular, the phase characteristics of the power amplifier are markedly improved. For example, there is 5 degrees phase shift with cascode bias modulation, versus 50 degrees phase shift without bias modulation.

In a second arrangement, the low breakdown voltage problem can be addressed by providing a stacked arrangement using a stacked FET topology. A stacked FET topology is shown in Figure 6, and is also disclosed in US 6,137,367 and US 2012/0299658.

In subsequent arrangements described hereafter, for simplicity only a single non-linear mapping block or circuit is used. However specific non-linear mapping functions may be used to generate the modulated supply voltage and the modulated bias voltage, and where applicable a plurality of specific non-linear mapping functions may be used to generate a plurality of modulated bias voltages.

With reference to Figure 6, the stacked FET power amplifier topology includes a plurality n of stacked CMOS transistors denoted by reference numerals 80_x to 80_n. Each of the CMOS transistors 80χ to 80_n receives on its gate a gate voltage signal V_gate i to V_{gate n}, via a resistor 98i to 98_n respectively. The gate of each transistor 80i to 80_n is also connected to electrical ground via a respective capacitor Ι Ο Ο χ to 100_n, having values C_tUnei to Ctunen e which provides a tuning of the gate voltage.

The drain of the transistor 80i at the top of the block is connected to one terminal of inductor 88 , the other terminal of the inductor 88 being connected to a modulated supply voltage . The drain of the transistor 8 0 i is also connected to one end of an output match circuit 84, the RF output signal 86 being generated by the other end of the output match circuit 84.

The source of the transistor 80_n is connected to the drain of a transistor 96, which has its source connected to electrical ground . The gate of the transistor 96 is connected to one end of the input match circuit 92, the RF input signal being received on signal line 90 at the other end of the input match circuit 92. The gate of transistor 96 is also connected to the fixed DC bias voltage V_Dc bias vi resistor 94.

The number of stacked transistors n is implementation dependent. With the exception of the transistors at the top and bottom of the stack, each transistor in the stack has its source connected to the drain of the next lowest transistor, and its drain connected to the source of the next highest transistor consistent with a stack topology .

With reference to Figure 7 there is illustrated the arrangement of Figure 6 advantageously modi ied to provide for gate bias modulation for the upper devices in the stack . The arrangement of Figure 7 identifies elements by reference numerals which are common to Figure 6, when the elements of Figure 7 correspond to those of Figure 6.

In the arrangement of Figure 7, it is determined to indirectly provide control of the drain voltage of transistor 96 by controlling the gate bias of transistor 80n for the same reasons as discussed above with reference to Figure 3. In the stacked arrangement of Figure 7, the voltage at the drains of each of stacked transistors 802 to 80n may be indirectly controlled by applying modulation to the gates of next higher device in the stack 801 to 80n-l . Thus the gate bias voltage for each of the transistors 80i to 80_n is modulated, and the gate bias voltage for the lower transistor 96 is fixed.

In Figure 7 the arrangement of Figure 6 is modified such that each of the stacked transistors S0i to 80_n receives a gate voltage from a gate driver 104i to 104_n. Each of the gate drivers 104χ to 104_n receives an input from the output of a combiner 106χ to 106_n. A first input of each combiner 106_x to 106_n is provided by a respective amplifier 110χ to 110_n aving a respective gain K_x to K_n, and a second input to each combiner 106i to 106_n is provided by a block 108i to 108_n providing DC offset voltages C_% to C_n. The output of the amplifier blocks Huh to 110_n are thus offset by DC voltages Ci to C_n. Each amplifier 110χ to 110_n is connected to receive the envelope signal in the envelope path at its input, or in the alternative the output of the envelope amplifier as shown by the dotted line .

Thus the gate of each stacked transistor receives a different scaled and offset version of the amplifier reference signal provided by a single non-linear mapping block or circuit .

Thus in the arrangement of Figure 7 the transistor having its gate connected to receive the input signal to be amplified is connected to a fixed gate bias voltage, and all other transistors are connected to receive modulated gate bias voltages. In the described arrangement the scaling/offset for generating the gate voltage for each transistor is chosen to optimise the bias for each transistor.

The envelope signal in the envelope path also provides the input to the envelope amplifier 1 12 , which provides the modulated supply signal to one te minal of the inductor 8 8 in accordance with the arrangement of Figure 6 .

Thus in the arrangement of Figure 7 the gate bias voltages for each of the transistors 8 0 χ to 8 0_n are scaled by the respective amplifier 110i to 1 1 0_n and offset (by the respective blocks 1 0 8 χ to 1 0 8_n ) by addition of DC voltages Ci to C_n and applied to the gates of the upper stacked transistor devices (device 80χ to 8 0_n ) .

The capacitor values C_tUnei to C_tUnen ( 1 0 0 i to 10 0_n ) are small value capacitors chosen to ensure even distribution of R? voltages across the devices in the stack.

The gate driver amplifiers 1 04 χ to 104_n are designed to have low output impedance at the envelope modulation frequency and high impedance at the RF carrier frequency. The low impedance at envelope frequencies ensures tight control of the gate bias voltages , which in turn prevents the power amplifier from exhibiting so-ca 1 led memory effects , in which the power amplifier instantaneous output power depends not only on the instantaneous input power but also on its history.

If envelope tracking is applied to only the supply voltage of a stacked FET power amplifier a d the bias voltages of the stacked devices is not tightly controlled, strong memory effects may be observed, particularly at high modulation bandwidths .

The gate driver amplifiers 110i to 110_n can be designed to have low power consumption as they only have to drive small value capacitors at the relatively low envelope rate.

It can be seen from Figure 8 that the performance of the stacked FET configuration can be considerably improved by co- modulating the supply voltage and the gate voltages of the stacked devices. The improvement in gain flatness for the stacked FET configuration through use of co-modulation is particularly notable.

Figures 8 (a) to 8(c) respectively show gain, phase and efficiency contour plots for the stacked FET envelope tracking power amplifier of Figure 7, The beneficial effect on efficiency and linearity of co-modulating the gate bias voltage can be clearly seen.

The solid lines 91 show the trajectory across the surfaces if gate bias modulation is used, whereas the dotted lines 87 show the trajectory if fixed DC gate bias is used.

The use of a stacked FET envelope tracking power amplifier with simultaneous bias modulation improves efficiency, gain and phase flatness, which in turn are key to achieving good linearity metrics such as adjacent channel power ratio (ACPR) and error vector magnitude (EVM) . In particular, the phase characteristics of the power amplifier are markedly improved.

In a third arrangement, the low breakdown voltage problem can be addressed by providing a stacked arrangement using a stacked cascode topology. Such a topology is illustrated in Figure 9, and disclosed in US 2011/0018625 and US 2013/0082782.

With reference to Figure 9 the prior art stacked cascode topology for a power amplifier is denoted by reference numeral 150. An RF input signal is received on line 156 as an input to an input match circuit 158, and an RF output signal is generated on line 154 from an output match circuit 152.

The output of the input match circuit 158 is connected to the gate of a transistor 17 0 . The gate of the transistor 17 0 is also connected to a fixed DC bias voltage V_{dc b}ias i via resistor 1 60 . The drain of a transistor 174 is connected to a fixed supply voltage V_supply, and also connected to an input terminal of the output match circuit 152. A bias voltage V_bias is connected to a biasing block 1 62 .

The biasing block 1 62 generates three outputs in the example of Figure 9, a first output to one terminal of a resistor 1 64 , a second output to a first terminal of a resistor 180 , and a third output to a first terminal of resistor 1 7 8 . The second terminal of resistor 1 64 is connected to the gate of transistor 168, the second terminal of resistor 1 8 0 is connected to the gate of transistor 17 6 , and the second terminal of resistor 17 8 is connected to the gate of transistor 17 4 .

An RF short capacitor 1 6 6 is connected between the gate of transistor 1 68 and electrical ground. A small val e RF capacitor 182 having value C_tUne is connected between the gate of trans istor 1 7 6 and electrical ground . An RF short capacitor 17 2 is connected between the gate of transistor 17 4 and the source of transistor 176.

The source of transistor 174 is connected to the drain of transistor 17 6 , the source of transistor 17 6 is connected to the drain of transistor 168, and the source of transistor 168 is connected to the drain of transistor 17 0 . The source of trans istor 17 0 is connected to electrical ground .

Figure 1 0 shows a modification to the arrangement of Figure 3, in which a modulated gate bias voltage is used for a stacked cascode envelope tracking power amplifier . Reference numerals are used in Figure 10 to refer to elements which are equivalent to elements of Figure 9.

In the arrangement of Figure 10, it is determined to provide control of the drain voltage of transistor 170 for the same reasons as discussed above with reference to Figure 3. In the stacked arrangement of Figure 10, the voltage at the dra ins of stacked transistors 168 and 176 may be indirectly controlled by applying modulation to the gates of devices 176 and 174 respectively . Thus the gate bias voltage for transistors 168, 176 and 174 are modulated, and the gate bias voltage of transistor 170 is fixed.

In the arrangement of Figure 10 each transistor 174 , 176, 168 receives a gate voltage from a respective gate driver 200, 202, 206. Each gate driver 200, 202, 206 receives an output of a respective combiner 208, 210, 212. Each combiner receives a first input from a respective amplifier 214, 216, 218 having a respective gain Ki, K₂, K₃, and a second input from a respective block 220, 222, 224 having a respective DC offset voltage Ci, C₂, C₃ , The amplifiers 214, 216, 218 are connected to receive inputs from the envelope signal , which provides an input to an envelope amplifier 226 which generates a modulated supply voltage for the transistor 174 through inductor 228. The amplifiers 214, 216, 218 could receive inputs from the output of the envelope amplifier 226 as denoted by the dashed line.

In the arrangement of Figure 10 the value of the capacitor 182 is a small value, chosen to ensure even distribution of RF voltages across the devices in the stacked cascode .

The value of the capacitors 166 and 172 are larger value capacitors than the value of capacitor 182, and provide an RF short-circuit .

As with the stacked FET architecture, tight control of the gate bias voltages minimises power amplifier memory effects .

Figures 11(a) to 11(c) respectively show gain, phase and efficiency contour plots for the stacked cascode envelope tracking power amplifier architecture of Figure 10. The effect of co-modulating the gate bias voltage can be clearly seen .

The solid lines 157 shows the trajectory across the surfaces if gate bias modulation is used, whereas the dotted lines 155 shows the trajectory if fixed DC gate bias is used.

The use of a stacked cascode envelope tracking power amplifier architecture with bias modulation simultaneously imp oves efficiency and gain and phase flatness, which in turn are key to achieving good linearity metrics such as adjacent channel power ratio (ACPR) and error vector magnitude (EVM) . The improvement in phase flatness for the stacked cascode configuration through use of co-modulation is particularly notable .

Thus the described techniques for increasing operating voltage can also be used in conjunction with envelope tracking. There are substantial advantages , as discussed hereinabove, associated with modulating the gate bias voltage of the stacked devices.

The examples refer to the application of the disclosed techniques to CMOS technologies, but the techniques described may be applied to other technologies, such as GaAs HBT and SiGe for example.

The examples refer to appi icat ion of advantageous techniques to particular implementations of stacked transistor powe amplifiers. The principle used in applying the improvement is the same, and may be applied to other arrangements in accordance with the inven ion as defined by the claims.

The invention has been described with reference to particular examples, and three example implementations of an exemplary CMOS power amplifier have been described herein above. The invention is limited in its scope to the definition as given in the appended claims. The invention is not limited to application in any described embodiment or example .

Claims

CLAIMS :

1. An amplifier arrangement comprising:

an envelope tracked power supply configured to provide a modulated supply voltage based on an envelope of an input signal to be amplified and including offset and sea 1 ing circuitry for providing a modulated bias voltage based o the envelope of an input signal to be amplified;

a power amplifier stage having a supply voltage input and two or more bias voltage inputs, wherein the supply voltage input is conr.ecr.ed to the modulated supply voltage and at least one of the bias voltage i nputs is connected to the modulated bias voltage .

2. The amplifier arrangement of claim 1 wherein one of the bias voltage inputs is connected to receive a fixed bias voltage .

3. The amplifier arrangement of claim 2 wherein the power amplifier comprises stacked transisto s , wherein the stacked transistor connected to receive the amplifier input s ignal is connected to receive a fixed bias voltage, and wherein one or more further stacked transistors are connected to receive the modulated bias voltage .

4. The amplifier arrangement of claim 3 wherein the powe amplifier comprises at least three stacked transistors, each transistor other than the one connected to receive the amplified input signal being connected to receive a different scaled modulated bias voltage .

5. The amplifier arrangement of any one of claims 1 to 4 wherein there is provided a first non-linear mapping circuit for providing the modulated supply voltage based on an envelope of an input signal to be amplified.

6. The amplifier arrangement of claim 5 wherein there is provided a second non-linear mapping circuit for providing the modulated bias voltage based on the envelope of the input signal to be amplified .

7. The amplifier arrangement of claim 5 wherein there is provided scaling and offsetting circuitry to derive the modulated bias voltage from the output of the first non-linear mapping circuit .

8. The amplifier arrangement of claim 7 wherein there is provided a plurality of scaling and offsetting circuits to derive a plurality of modulated bias voltages from the output of the non-linear mapping circuit.

9. The amplifier arrangement of any one of claims 1 to 8 wherein the transistors of the power amplifier are CMOS devices, or GaAs HBT devices, or SiGe devices, or GaN devices.

10. The amplifier arrangement of any one of claims 1 to 9 wherein the power amplifier comprises a cascode topology comprising at least two stacked transistors.

11. The amplifier arrangement o claim 10 wherein an upper cascode transistor receives the modulated supply voltage and the modulated bias voltage, and the lower cascode transistor receives a fixed bias voltage.

12. The ampli ier arrangement of claim 11 wherein the envelope tracked powe supply includes a first non-linear mapping circuit for providing the modulated supply voltage and a second non-linear mapping circuit for p oviding the modulated bias voltage.

13. The amplifier arrangement of claim 10 wherein the envelope tracked power supply includes a single non-linear mapping circuit for providing the modulated supply voltage and the modulated bias voltage.

14. The amplifier arrangement of claim 13 wherein the modulated bias voltage is a scaled and offset version of the output of the non- linear mapping circuit .

15. The amplifier arrangement of any one of claims 1 to 9 wherein the power ampli fier comprises a stacked field effect transistor, FET, amplifier topology .

16. The amplifier arrangement of claim 15 wherein the envelope tracked power suppl includes a single non-linear mapping circuit for providing the modulated supply voltage and the modulated bias voltage .

17. The amplifier arrangement of claim 16 wherein there is provided scaling and offsetting circuitry for providing modulated bias voltage .

18. The amplifier arrangement of claim 17 wherein the power amplifier comprises three or more stacked transistors, and there is provided two or more scaling circuits for providing two or more modulated bias voltages to two or more of the three or more transistors.

19. The amplifier arrangement of any one of claims 1 to 9 wherein the power amplifier comprises a stacked cascode topology .

20. The amplifier arrangement of claim 19 wherein the envelope tracked power supply includes a single non- linear mapping circuit for providing the modulated supply voltage and the modulated bias voltage.

21. The amplifier arrangement of claim 19 or claim 20 whe ein the powe amplifier comprises four stacked transistors, and there is provided three scaling and offsetting circuits for providing three modulated bias voltages to three of the transistors .

22. A method of providing voltages to a power amplifier having a supply voltage input and two or more bias voltage inputs , comprising: connecting the supply voltage input to a supply voltage modulated based on an envelope of an input signal to be amplified; and connecting one of the two bias voltage inputs to a bias voltage modulated based o an envelope of an input signal to be amplified, the genera ion of the modulated bias voltage comprising offsetting a d scaling .

23. The method of claim 22 further comprising connecting a first bias vol age input to a modulated bias voltage and connecting a second bias voltage input to a fixed sup ly.

24. The method of claim 23 wherein the power amplifier comprises stacked transistors, the method comprising connecting one of the stacked transistors to receive the input signal to be amplified and the fixed bias voltage.

25. The method of claim 24 comprising connecting each other of the stacked transistors to receive a modulated bias voltage .

26. The method of claim 25 comprising providing a modified version of a modulated bias voltage to each of a plurality of the stacked transistors.

27. The method of claim 26 comprising modifying a shaping function output generated for the modulated supply voltage.