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WO2015009249A1 - Transistor à enrichissement au iii-n à polarité n et son procédé de fabrication - Google Patents

Transistor à enrichissement au iii-n à polarité n et son procédé de fabrication Download PDF

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Publication number
WO2015009249A1
WO2015009249A1 PCT/SK2014/000011 SK2014000011W WO2015009249A1 WO 2015009249 A1 WO2015009249 A1 WO 2015009249A1 SK 2014000011 W SK2014000011 W SK 2014000011W WO 2015009249 A1 WO2015009249 A1 WO 2015009249A1
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Prior art keywords
transistor
enhancement
layer
polarity
barrier layer
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PCT/SK2014/000011
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WO2015009249A9 (fr
Inventor
Ján KUZMIK
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Elektrotechnicky Ustav Sav
Centrum Vedecko-Technickych Informacii Sr (Cvti Sr)
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Publication of WO2015009249A1 publication Critical patent/WO2015009249A1/fr
Publication of WO2015009249A9 publication Critical patent/WO2015009249A9/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/84—Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment

Definitions

  • InN is a semiconductor material where the drift electron velocity is about 4 times higher than the electron velocity in Si.
  • III-N semiconductors are materials showing high level of spontaneous polarization P D .
  • a piezoelectric polarization P piao is generated for a strained epitaxial layer along c axis .
  • Total polarization defines a polarization-induced charge density p, ola i according to equation - ⁇ , 0 ⁇ ⁇ - ' (Ppiezo + Po)-
  • a hetero-junction of two materials exhibits the charge density of the polarization-induced charge as a consequence of difference in spontaneous polarizations APo of materials and in a case of strained materials with different lattice constants, also as a consequence of a gradient of the piezoelectric polarization APpiezo-
  • a change in the polarization therefore generates the charge density which can act as donors or as acceptors.
  • Table 1 shows values of polarizations and of some other physical parameters for A1N, GaN and InN, respectively, and also of some dielectric materials which are used for the transistor gate insulation (see J. Appl. Phys. 85, p.7727, 1999, J. Appl. Phys. 87, p.334, 2000, Semicond. Sci. Technol. 17, p. 540, 2002, J. Appl. Phys. 100, p. 01411 1, 2006, Appl. Phys. Express 5, p.015502, 2002). ⁇ ,.
  • Orientation of the polarization depends on a crystal polarity, e.g. if the crystal surface is terminated by bonds from a cation (Ga, Al, In) or from an anion (N). Negative value of all polarization parameters in Table 1 corresponds to the cation polarity (growth along (0001)), positive value corresponds to the anion polarity (growth along (000-1)).
  • Po(A X B,. X C) Po(BC) + X(PQ(AQ- PO(BQ).
  • Ve ard's equation may be analogously used for any other parameter of Table 1.
  • Polarization of III-N semiconductors is applied in the channel of high electron mobility transistors (HEMTs) without using dopants.
  • Conductance of the channel is provided by a 2- dimensional electron gas in a quantum well at the junction of two semiconductors having different polarization or with a different value of AE G .
  • layers show cation (Ga, Al, In) polarity
  • creation of the 2-dimensional electron gas of transistors requires placing of the channel layer, having typically smaller AE G (e.g. GaN), below the material of the barrier layer, having typically larger AE G (e.g. AlGaN).
  • AE G e.g. GaN
  • AlGaN anion polarity of the HEMT
  • sequence of layers is mirror-like, i.e.
  • Threshold voltage (V T ) of transistors is a value of the voltage bias applied on the gate when the conductance of the channel is flipped (opened/closed channel) as a consequence of an electrostatic effect of the gate. If Vr> 0 V, than we deal with an enhancement-mode transistor, which is closed without applying the gate bias. In the opposite case we deal with a depletion-mode transistor. Construction and integration of both types of transistors is important for e.g. preparation of logic circuits. It is desirable that the enhancement-mode transistor VT value is sufficiently high in order to prevent undesired switching of the transistor.
  • VT of the enhancement-mode transistor can be changed with the thickness of the top AlGaN layer.
  • WO2011008531 (A2) follows a method of fabricating enhancement- mode HEMT having the particular AIN/GaN configuration.
  • the enhancement-mode HEMT can be fabricated by using oxygen plasma.
  • a masking layer to protect an area of the depletion-mode HEMT, both transistors can be fabricated on the same chip.
  • Enhancement-mode III-N transistor with N polarity contains from the bottom following layers: the bottom barrier layer, the channel layer, the upper barrier layer having chemical composition different from the composition of the bottom barrier layer, and the dielectric insulator of the gate while the upper barrier layer/channel layer interface shows a negative polarization charge with an absolute value greater than the positive polarization charge at the channel layer/bottom barrier layer interface.
  • Described transistor contains the channel layer based on InN which enhances the speed performance.
  • Fig. 1 Structure of the novel enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and having a free adjustment of V T .
  • Fig. 2 Simulated output characteristics of the novel enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and 5 nm thick Hf0 2 dielectric insulating layer.
  • Fig. 3 Simulated dependences of V T on the thickness of the Hf0 2 dielectric gate insulator of the novel enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and of the depletion-mode transistor prepared on the same substrate.
  • Fig. 12 Simulated transfer characteristics of the novel enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and of the depletion-mode transistor prepared on the same substrate.
  • Fig. 1 shows the enhancement-mode III-N transistor with N-polarity which from the bottom contains the bottom relaxed InAlN barrier layer 1, strained InN channel layer 2, the upper GaN barrier layer 3 and the Hf0 2 -based dielectric gate insulator 4.
  • VT ⁇ - ⁇ E - d E oTox ij£cH- (dwrox+dwrr) ⁇ cn /S H- (dEoiOX+d EO TT+dcn) PCWB/ECH (1)
  • S C HI ' S permittivity of the channel layer ⁇ , d EO n are equivalent thicknesses of the dielectric insulating layer and of the barrier layer in relation to S CJ H
  • d CH is the thickness of the channel layer, the charge at the insulator/semiconductor interface which can be eliminated by annealing (see Applied Phys. Lett.
  • p TC H and p C H, B are total polarization charges at the upper barrier layer/channel layer interface and at the channel layer/bottom layer interface, and layers are undoped. Simultaneously it is valid that where p R /B is the total polarization charge which would be created on a hypothetical interface upper barrier layer/bottom barrier layer. Consequently:
  • VT ⁇ - ⁇ AEc - d E omxN ne ec - ⁇ ⁇ ⁇ + ⁇ ⁇ ⁇ ) pm / CH - dctipcHi scH (3)
  • the GaN interlayer between the bottom barrier layer and the channel layer.
  • the thickness of this layer is chosen to be less than 1 nm in order to prevent relaxation of its lattice.
  • Polarization dipole of such a thin interlayer can be neglected by calculating V T , if the interlayer is used.
  • Fig. 2 shows a simulation of output characteristics of the enhancement-mode transistor, schematic structure of which is shown in Fig. I .
  • Calculation assumes relaxed Ino.9Alo . 1N bottom barrier layer, 5 nm thick strained InN channel layer, 1 nm thick GaN upper barrier layer, 5 nm thick HfC>2 dielectric insulator and 100 nm long gate which is located between the source and the drain having 1 ⁇ pitch.
  • Contact resistance of the source and of the drain is assumed to be 0.1 ⁇ , the upper barrier layer in access regions of the transistor is removed in order to minimalize source-gate and gate- drain parasitic resistances.
  • N m , 1 x 10 13 cm "2 is the maximal value corresponding to the non-optimized interface (see Applied Phys. Lett. 102, 072105, 2013).
  • the transistor channel is opened only for gate bias larger than 3.1 V, which facilitates sufficient protection against the undesired switching. Maximal currents are above 4 A/mm.
  • Fig. 3 shows a simulation of the V T dependence of the described enhancement-mode transistor on the thickness of the dielectric insulation layer.
  • Arbitral combination of InGaN is also possible to use in the place of the channel layer while in this case x in the bottom barrier layer can be decreased closer to 0.4.
  • the bottom barrier layer it is also possible to use an arbitral combination of InAlGaN providing p m ⁇ 0.
  • the dielectric insulating layer it is also possible to use other alternative materials and its combinations, such as A1 2 0 3 , Zr0 2 , Ti0 2 or similar providing the gate leakage current is eliminated.
  • Polarity of the grown layers may be set by the polarity of the substrate or by the growth of the bottom barrier layer on the N-polar GaN buffer layer.
  • the advantage of the described concept of the enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity is also given by a particular chemical composition of the upper barrier layer and of the channel layer. Used composition facilitates a selective plasma etching of the upper barrier layer over InN-containing channel layer. This provides a reproducible and homogeneous fabrication of the depletion-mode transistor together with the enhancement-mode transistor across the wafer while the enhancement-mode transistor is covered with a mask, such as with a photoresist, during the etching. Removal of the upper barrier layer is possible to be performed by using a fluoride-containing plasma which will form InF-based etch-stop layer on the surface of the channel layer.
  • Fig. 3 shows variability of V T of the depletion-mode InN/InAIN transistor which is fabricated by removing the GaN upper barrier layer and by subsequent formation of the Hf0 2 dielectric insulating layer of variable thickness, while the channel layer thickness remains constant for both types of transistors. Moreover, before fabricating the gate metallization systems of both of transistors, it is additionally possible to deposit a second dielectric layer.
  • Epitaxial growth of III-N layers is done by using techniques like molecular-beam epitaxy (MBE) or by a metal-oxide chemical vapor deposition (MOCVD), or by a technique of sputtering on a properly chosen substrate.
  • MBE molecular-beam epitaxy
  • MOCVD metal-oxide chemical vapor deposition
  • a substrate 11 see Fig. 4, it can be used e.g. bulk GaN, SiC, Si, sapphire, diamond, or any other material which provides epitaxial growth of the GaN buffer layer 12 or InAlN layer 1 with the anion orientation.
  • Anion (N) orientation of layers can be provided by e.g. growth on SiC with C orientation of the surface, on GaN with N orientation, by growth on an off-axis sapphire or by a proper preparation of the substrate surface.
  • GaN GaN is N plasma assisted.
  • MOCVD Metal Organic Chemical Vapor deposition
  • Trimethylindium, trimethylaluminium, trimethylgalium and ammonia are used as precursors.
  • Growth of about 100 nm to 3 ⁇ thick GaN buffer layer 12 is followed by the growth of the In x Ali -x N bottom barrier layer 1.
  • the InAIN layer 1 fulfills simultaneously the role of the buffer layer as well as of the bottom barrier layer.
  • Thickness of the In x Ali -x N layer 1 is chosen between 100 nm to 3 ⁇ so that when the growth is finished the layer is relaxed.
  • the growth is performed with fixed x ⁇ 0.7 ⁇ 0.9 or with a graded x.
  • Content of In is chosen in a way to provide the growth of the strained InN-based channel layer 2 and of the upper GaN barrier layer 3_ in later steps. Residual donors in the bottom barrier layer 1 are compensated by e.g. Mg or Fe doping, or by an increased content of C in the layer.
  • After growing the bottom barrier layer 1 follows the growth of about 5 nm thick InN channel layer 2 and finally the growth of about 1 nm thick GaN upper barrier layer 3.
  • InAlGaN InAlGaN
  • InGaN InGaN
  • Isolation of transistors on the future integrated circuit is done by either proton implantation, or by definition of mesa areas using plasma etching in reactive ions, see Fig. 4. Masking of areas can be done by using the resist mask 13 prepared by photolithography.
  • the area of transistors working in the depletion-mode is defined by e.g. photolithography and the upper GaN barrier layer 3 is selectively etched away, see Fig. 5.
  • Selectivity of etching can be provided by plasma etching in fluoride-containing gasses, e.g. in the mixture of SiCl 4 /SF 6 or in CCI 2 F 2 .
  • the upper barrier layer 3 does not contain elements like In or Al and can be easily etched away.
  • the InF-based etch stop is created and etching will be terminated.
  • Plasma etching in this and also in the below described processing steps is always performed with the absolute value of the self-induced bias less than 100 V so that the damage of the semiconductor surface is minimal.
  • the etching on the whole area of the structure of integrated transistors follows the growth of about 5 to 10 nm thick dielectric insulating layer 4 with high permittivity, such as Zr0 2 or Hf0 2 , see Fig. 6.
  • the growth can be performed by using a technique of atomic layer deposition (ALD) at about 100 to 200 °C by using precursors or by using any other proper technique.
  • Figs. 7, 8 show preparation of the source and the drain ohmic contacts 14 which is done on both types of transistors simultaneously.
  • plasma etching in reactive ions through the particular resist mask 13.
  • Ni/Au may be used as gates 15 and the system is evaporated directly on the dielectric insulating layer 4.
  • Fig. 10 shows removal of the dielectric layer 4 and subsequently also of the GaN barrier layer 3 from the areas between contacts 14 and 15, which is performed only on the enhancement-mode transistor, i.e. depletion-mode transistor during this technological step is covered by using e.g. the resist mask 13.
  • Dielectric insulating layer 4 is removed by using e.g. SF & - based etching which stops at the surface of GaN 3 and then the upper GaN barrier layer 3 is removed by using e.g. SiCVSFe or CCI2F2 plasma.
  • Ohmic contacts 14 and the gate 15. of the enhancement-mode transistor may serve as a mask in the process of etching and consequently the usage of the resist mask is not necessary, see Fig. 10.
  • Passivation of the whole structure is the last technological step, see Fig. 11.
  • Different materials and their combinations such as SiN, AI 2 0 3 , Zr0 2 , Hf0 2 and similar ones can be used as the passivation layer 16.
  • the upper GaN barrier layer 3 is present only in areas below the gate of the enhancement-mode transistor (eventually below the source and the drain contacts, see Fig. 7), which is important for the minimization of the parasitic source-to-gate and gate-to-drain resistances of both types of transistors.
  • a unified thickness of the insulating layer 4 e.g. 5 nm thickness on the whole area of the structure, using this method it is possible to prepare simultaneously extremely high transconductance (more than 2 S/mm) transistors operating in both modes with a high span of V T , which is shown on simulations in Fig. 12.
  • transistors with different thicknesses of the dielectric insulating layer providing the evaporation process of gates 15 shown in the Fig. 9 is performed separately for each type of the transistor using a separate mask for each.
  • the thickness of the dielectric insulating layer 4 can be changed before evaporating the gate 15 of the particular transistor by using the same mask also for the evaporation of the additional insulating layer from e.g. an electron gun or by using the ALD technique at 100 °C. In this way a full variability of V T values according to calculations shown in Fig. 3 is secured.
  • Various materials and their combinations can be used for the preparation of the first and of the second dielectric insulating layers providing elimination of the leakage current through the gate is obtained.
  • the invention will be used in the semiconductor industry. Simple integration of the depletion-mode and of the enhancement-mode transistors with the InN channel layer and with the free adjustment of threshold voltage values will facilitate fabrication of a new generation of extremely fast digital or analogue integrated circuits.

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Abstract

La présente invention concerne un transistor à enrichissement au III-N à polarité N constitué des couches suivantes, à partir de la surface inférieure : d'une couche de transition inférieure (1); d'une couche de canal (2); d'une couche de transition supérieure (3), dont la composition chimique est différente de la composition de la couche de transition inférieure; et d'une couche d'isolation diélectrique (4), l'interface couche de transition supérieure/couche de canal présentant une charge de polarisation négative de valeur absolue supérieure à celle de la charge de polarisation positive au niveau de l'interface couche de canal/couche de transition inférieure, et la tension de seuil de transistor pouvant être réglée librement.
PCT/SK2014/000011 2013-07-17 2014-04-30 Transistor à enrichissement au iii-n à polarité n et son procédé de fabrication WO2015009249A1 (fr)

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JP2016134612A (ja) * 2015-01-22 2016-07-25 国立大学法人名古屋大学 Ｉｉｉ族窒化物半導体素子とその製造方法
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