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WO2014196223A1 - Semiconductor chip and semiconductor device - Google Patents

Semiconductor chip and semiconductor device Download PDF

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Publication number
WO2014196223A1
WO2014196223A1 PCT/JP2014/053038 JP2014053038W WO2014196223A1 WO 2014196223 A1 WO2014196223 A1 WO 2014196223A1 JP 2014053038 W JP2014053038 W JP 2014053038W WO 2014196223 A1 WO2014196223 A1 WO 2014196223A1
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Prior art keywords
semiconductor chip
mosfet
protection element
terminal
electrostatic protection
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PCT/JP2014/053038
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French (fr)
Japanese (ja)
Inventor
栄治 荻野
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シャープ株式会社
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Publication of WO2014196223A1 publication Critical patent/WO2014196223A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/20—Breakdown diodes, e.g. avalanche diodes
    • H10D8/25—Zener diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the electrostatic protection element 12 connected between the gate electrode and the source electrode can be disposed by effectively utilizing the space in the normal direction of the substrate surface in the semiconductor chip 1. Therefore, while preventing electrostatic breakdown of the gate oxide film, a gate electrode and a source electrode are provided on one surface side of the substrate as described in Patent Document 1 described above, and a bidirectional Zener diode consisting of a single layer of these electrodes is provided. Compared with the case of using and connecting, the size of the semiconductor chip in the direction parallel to the substrate surface can be reduced, and the semiconductor chip can be downsized.
  • the semiconductor device according to aspect 4 of the present invention is the structure according to any one of the aspects 1 to 3, wherein the MOSFET has a lateral diffusion MOS structure.

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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The present invention provides a MOSFET gate terminal (G1) and drain terminal (D1) on one surface of a semiconductor chip (1), provides a source terminal (S1) on the other surface thereof, and is equipped with an electrostatic-discharge protection element (12) having one end thereof connected to the gate terminal (G1) and the other end thereof connected to the source terminal (S1). As a result, it is possible to reduce chip size and improve electrostatic-discharge properties in a semiconductor chip having a MOSFET.

Description

半導体チップおよび半導体装置Semiconductor chip and semiconductor device

　本発明は、ＭＯＳＦＥＴ（酸化金属半導体電界効果トランジスタ）を有する半導体チップおよび半導体装置に関するものである。 The present invention relates to a semiconductor chip having a MOSFET (metal oxide semiconductor field effect transistor) and a semiconductor device.

　従来、ゲート酸化膜を静電破壊から保護するための静電気保護素子（ＥＳＤ（Electro-Static Discharge）保護素子）を備えたＭＯＳＦＥＴが知られている。 Conventionally, a MOSFET having an electrostatic protection element (ESD (Electro-Static Discharge) protection element) for protecting a gate oxide film from electrostatic breakdown is known.

　例えば、特許文献１には、ゲート電極とソース電極との間に双方向ツェナーダイオードを接続し、さらに、ゲート電極に抵抗を接続したＭＯＳＦＥＴが開示されている。 For example, Patent Document 1 discloses a MOSFET in which a bidirectional Zener diode is connected between a gate electrode and a source electrode, and a resistor is connected to the gate electrode.

日本国公開特許公報「特開２００８－７８５７９号公報（２００８年４月３日公開）」Japanese Patent Publication “Japanese Unexamined Patent Application Publication No. 2008-78579 (published April 3, 2008)”

　しかしながら、上記特許文献１の技術では、ゲート電極およびソース電極が半導体チップの上面側に設けられており、静電気保護素子としての双方向ツェナーダイオードが単一層のポリシリコン膜で形成されているので、半導体チップのチップ面積が増大してしまうという問題がある。 However, in the technique of Patent Document 1, the gate electrode and the source electrode are provided on the upper surface side of the semiconductor chip, and the bidirectional Zener diode as the electrostatic protection element is formed of a single layer polysilicon film. There is a problem that the chip area of the semiconductor chip increases.

　本発明は、上記の問題点に鑑みてなされたものであり、その目的は、ＭＯＳＦＥＴを有する半導体チップにおいて、静電耐圧特性を向上させるとともにチップサイズを低減することにある。 The present invention has been made in view of the above problems, and an object thereof is to improve the electrostatic withstand voltage characteristics and reduce the chip size in a semiconductor chip having a MOSFET.

　本発明の一態様にかかる半導体チップは、ＭＯＳＦＥＴを有する半導体チップであって、上記ＭＯＳＦＥＴのゲート端子およびドレイン端子が当該半導体チップの一方の面側に設けられ、上記ＭＯＳＦＥＴのソース端子が当該半導体チップの他方の面側に設けられており、一端側が上記ゲート端子に接続され、他端側が上記ソース端子に接続された静電気保護素子を備えていることを特徴としている。 A semiconductor chip according to an aspect of the present invention is a semiconductor chip having a MOSFET, wherein a gate terminal and a drain terminal of the MOSFET are provided on one surface side of the semiconductor chip, and a source terminal of the MOSFET is the semiconductor chip. And an electrostatic protection element having one end connected to the gate terminal and the other end connected to the source terminal.

　上記の構成によれば、静電気保護素子を設けることにより、静電耐圧特性を向上させ、ゲート絶縁膜の静電気（ESD（Electro-Static Discharge））による劣化を効果的に防止することができる。また、ＭＯＳＦＥＴのゲート電極を半導体チップの一方の面側に設け、ソース電極を他方の面側に設けることにより、これら両電極を接続する静電気保護素子を当該半導体チップにおける厚さ方向のスペースを有効に用いて配置することができる。これにより、半導体チップの面内方向のサイズを低減し、半導体チップの小型化を図ることができる。 According to the above configuration, by providing the electrostatic protection element, it is possible to improve the electrostatic withstand voltage characteristics and effectively prevent deterioration of the gate insulating film due to static electricity (ESD (Electro-Static Discharge)). In addition, by providing the gate electrode of the MOSFET on one surface side of the semiconductor chip and the source electrode on the other surface side, the electrostatic protection element that connects these two electrodes can effectively make space in the thickness direction of the semiconductor chip. Can be used. Thereby, the size of the semiconductor chip in the in-plane direction can be reduced, and the semiconductor chip can be downsized.

本発明の一実施形態にかかる半導体チップの構成を示す回路図である。It is a circuit diagram which shows the structure of the semiconductor chip concerning one Embodiment of this invention. 図１に示した半導体チップの構成を示す説明図である。FIG. 2 is an explanatory diagram illustrating a configuration of the semiconductor chip illustrated in FIG. 1. 図１に示した半導体チップに備えられるＭＯＳＦＥＴの構成を示す説明図である。FIG. 2 is an explanatory diagram illustrating a configuration of a MOSFET provided in the semiconductor chip illustrated in FIG. 1. 図１に示した半導体チップに備えられる静電気保護素子の構成を示す説明図である。It is explanatory drawing which shows the structure of the electrostatic protection element with which the semiconductor chip shown in FIG. 1 is equipped. 図１に示した半導体チップの変形例を示す回路図である。FIG. 8 is a circuit diagram showing a modification of the semiconductor chip shown in FIG. 1. 本発明の他の実施形態にかかる半導体装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the semiconductor device concerning other embodiment of this invention. 図６に示した半導体装置に備えられる半導体チップの構成を示す説明図である。FIG. 7 is an explanatory diagram illustrating a configuration of a semiconductor chip provided in the semiconductor device illustrated in FIG. 6. 図６に示した半導体装置に備えられる半導体チップの構成を示す説明図である。FIG. 7 is an explanatory diagram illustrating a configuration of a semiconductor chip provided in the semiconductor device illustrated in FIG. 6. 図６に示した半導体装置の変形例を示す回路図である。FIG. 7 is a circuit diagram showing a modification of the semiconductor device shown in FIG. 6. 図６に示した半導体装置の変形例を示す回路図である。FIG. 7 is a circuit diagram showing a modification of the semiconductor device shown in FIG. 6. 図１に示した半導体チップに備えられる静電気保護素子の変形例を示す説明図である。It is explanatory drawing which shows the modification of the electrostatic protection element with which the semiconductor chip shown in FIG. 1 is equipped.

　　〔実施形態１〕
　本発明の一実施形態について説明する。 [Embodiment 1]
An embodiment of the present invention will be described.

　図１は本実施形態にかかる半導体チップ１の回路図であり、図２は半導体チップ１の概略構成を示す説明図である。 FIG. 1 is a circuit diagram of a semiconductor chip 1 according to the present embodiment, and FIG. 2 is an explanatory diagram showing a schematic configuration of the semiconductor chip 1.

　図１に示したように、半導体チップ１は、互いに並列に接続された多数のＭＯＳＦＥＴ１１からなるＭＯＳＦＥＴ群１０を備えており、ＭＯＳＦＥＴ群１０のソース端子（各ＭＯＳＦＥＴ１１のソース電極）は半導体チップ１のソース端子Ｓ１に接続され、ドレイン端子（各ＭＯＳＦＥＴ１１のドレイン電極）は半導体チップ１のドレイン端子Ｄ１に接続され、ゲート端子（各ＭＯＳＦＥＴ１１のゲート電極）は半導体チップ１のゲート端子Ｇ１に接続されている。また、半導体チップ１のゲート端子Ｇ１とソース端子Ｓ１との間には、静電気保護素子１２が接続されている。 As shown in FIG. 1, the semiconductor chip 1 includes a MOSFET group 10 composed of a large number of MOSFETs 11 connected in parallel to each other, and the source terminal (source electrode of each MOSFET 11) of the MOSFET group 10 is the same as that of the semiconductor chip 1. Connected to the source terminal S1, the drain terminal (drain electrode of each MOSFET 11) is connected to the drain terminal D1 of the semiconductor chip 1, and the gate terminal (gate electrode of each MOSFET 11) is connected to the gate terminal G1 of the semiconductor chip 1. . An electrostatic protection element 12 is connected between the gate terminal G1 and the source terminal S1 of the semiconductor chip 1.

　なお、各ＭＯＳＦＥＴ１１は、図２の（ａ）に示すように、半導体チップ１の面内方向に沿ってマトリクス状に配置され、互いに並列に接続されている。また、図２の（ｂ）に示したように、ゲート端子Ｇ１およびドレイン端子Ｄ１は半導体チップ１の一方の面に設けられており、ソース端子Ｓ１は半導体チップ１の他方の面に設けられている。 The MOSFETs 11 are arranged in a matrix along the in-plane direction of the semiconductor chip 1 and are connected in parallel to each other as shown in FIG. Also, as shown in FIG. 2B, the gate terminal G1 and the drain terminal D1 are provided on one surface of the semiconductor chip 1, and the source terminal S1 is provided on the other surface of the semiconductor chip 1. Yes.

　図３は、ＭＯＳＦＥＴ１１の構成を示す説明図である。この図に示すように、ＭＯＳＦＥＴ１１は、Ｐ型シリコン基板１３、Ｐ型シリコン基板１３上に形成されたＰ型半導体層１４、Ｐ型半導体層１４の一部に不純物イオンを注入することにより形成されたＮ＋領域（Ｎ型拡散領域、ドレイン領域）１５およびＮ＋領域（Ｎ型拡散領域、ソース領域）１６、Ｐ型半導体層１４上に形成されたゲート絶縁膜１７、ゲート絶縁膜１７上に形成されたゲート電極１９、Ｎ＋領域１５に接続されたドレイン電極１８、およびＮ＋領域１６に接続されたソース電極２０を備えた横方向拡散ＭＯＳ（ＬＤＭＯＳ（Laterally diffused MOS））構造のＮチャネル型ＭＯＳＦＥＴである。 FIG. 3 is an explanatory diagram showing the configuration of the MOSFET 11. As shown in this figure, the MOSFET 11 is formed by implanting impurity ions into a P-type silicon substrate 13, a P-type semiconductor layer 14 formed on the P-type silicon substrate 13, and a part of the P-type semiconductor layer 14. N + region (N-type diffusion region, drain region) 15 and N + region (N-type diffusion region, source region) 16, gate insulating film 17 formed on P-type semiconductor layer 14, and gate insulating film 17 N channel of lateral diffusion MOS (LDMOS (Laterally diffused MOS)) structure having formed gate electrode 19, drain electrode 18 connected to N + region 15, and source electrode 20 connected to N + region 16 Type MOSFET.

　なお、ドレイン電極１８およびゲート電極１９は半導体チップ１の一方の面側に形成されており、ソース電極２０はＰ型シリコン基板１３およびＰ型半導体層１４に設けられたトレンチ部２１を介して半導体チップ１の一方の面側から他方の面側に例えば金属等の導電部材によって接続されている。 The drain electrode 18 and the gate electrode 19 are formed on one surface side of the semiconductor chip 1, and the source electrode 20 is a semiconductor through a trench portion 21 provided in the P-type silicon substrate 13 and the P-type semiconductor layer 14. The chip 1 is connected from one surface side to the other surface side by a conductive member such as metal.

　静電気保護素子１２としては、図１に示したように、１対のツェナーダイオードのカソード電極同士を接続することにより形成した双方向ツェナーダイオードからなり、一端側がゲート端子Ｇ１に接続され、他端側がソース端子Ｓ１に接続されている。 As shown in FIG. 1, the electrostatic protection element 12 is a bidirectional Zener diode formed by connecting the cathode electrodes of a pair of Zener diodes, one end side being connected to the gate terminal G1, and the other end side being It is connected to the source terminal S1.

　図４は、静電気保護素子１２の構成例を示す説明図である。この図に示すように、静電気保護素子１２は、Ｐ型シリコン基板１３上にＮ型拡散領域（ＤＮ領域）４３およびＰ型半導体領域４４が形成されており、Ｐ型半導体領域４４内にＰ＋領域（Ｐ型拡散領域）４５、ＮＨＶ領域（ドリフト形成用のＮ型拡散領域）４６、Ｐ＋（Ｐ型拡散領域）領域４７が基板面内方向に沿って所定の間隔を隔てて形成され、Ｐ型半導体領域４４を覆うように酸化物層（ＯＸＩＤＥ層）４８が形成されている。また、酸化物層４８に設けられたコンタクトホールを介してＰ＋領域４５およびＰ＋領域４７に金属配線層（Ｍ１層）４９および金属配線層（Ｍ２層）５０がそれぞれ接続されている。なお、金属配線層４９は半導体チップ１のゲート端子Ｇ１（各ＭＯＳＦＥＴ１１のゲート端子）に接続され、金属配線層５０は半導体チップ１のソース端子Ｓ１（各ＭＯＳＦＥＴ１１のソース端子）に接続されている。 FIG. 4 is an explanatory diagram illustrating a configuration example of the electrostatic protection element 12. As shown in this figure, in the electrostatic protection element 12, an N-type diffusion region (DN region) 43 and a P-type semiconductor region 44 are formed on a P-type silicon substrate 13, and P + in the P-type semiconductor region 44. A region (P-type diffusion region) 45, an NHV region (N-type diffusion region for drift formation) 46, and a P + (P-type diffusion region) region 47 are formed at predetermined intervals along the in-plane direction of the substrate. An oxide layer (OXIDE layer) 48 is formed so as to cover the P-type semiconductor region 44. A metal wiring layer (M1 layer) 49 and a metal wiring layer (M2 layer) 50 are connected to the P + region 45 and the P + region 47 through contact holes provided in the oxide layer 48, respectively. The metal wiring layer 49 is connected to the gate terminal G1 (gate terminal of each MOSFET 11) of the semiconductor chip 1, and the metal wiring layer 50 is connected to the source terminal S1 of the semiconductor chip 1 (source terminal of each MOSFET 11).

　なお、静電気保護素子１２の耐圧特性は、ＭＯＳＦＥＴ１１のゲート端子Ｇ１に印加される電圧に応じて適宜設定すればよい。例えば、ＭＯＳＦＥＴ１１のゲート端子Ｇ１に対する印加電圧の仕様が±２０Ｖである場合、耐圧電圧が±２０Ｖよりも大きくなるように静電気保護素子１２を形成すればよい。静電気保護素子１２の耐圧特性は、例えば、（ｉ）Ｐ＋領域４５，４７とＮＨＶ領域４６との間隔、あるいは（ｉｉ）Ｎ型拡散領域（ＤＮ領域）４３の濃度を制御することにより調整できる。具体的には、Ｐ＋領域４５，４７とＮＨＶ領域４６との間隔を広くするほど静電気保護素子１２のブレークダウン電圧が増大し、Ｎ型拡散領域４３の濃度を低くするほど静電気保護素子１２のブレークダウン電圧が増大する。 The withstand voltage characteristic of the electrostatic protection element 12 may be set as appropriate according to the voltage applied to the gate terminal G1 of the MOSFET 11. For example, when the specification of the applied voltage to the gate terminal G1 of the MOSFET 11 is ± 20V, the electrostatic protection element 12 may be formed so that the withstand voltage is larger than ± 20V. The withstand voltage characteristic of the electrostatic protection element 12 can be adjusted by controlling, for example, (i) the interval between the P + regions 45 and 47 and the NHV region 46 or (ii) the concentration of the N-type diffusion region (DN region) 43. . Specifically, the breakdown voltage of the electrostatic protection element 12 increases as the distance between the P + regions 45 and 47 and the NHV region 46 increases, and the concentration of the N-type diffusion region 43 decreases as the concentration of the electrostatic protection element 12 decreases. The breakdown voltage increases.

　また、静電気保護素子１２の構成は、双方向ツェナーダイオードを実現できる構成であればよく、図４に示した構成に限るものではない。 The configuration of the electrostatic protection element 12 may be any configuration that can realize a bidirectional Zener diode, and is not limited to the configuration shown in FIG.

　例えば、図１１の（ａ）に示すように、Ｐ型シリコン基板１３上に形成されたＰ型半導体層１４内に、Ｐ型シリコン基板１３側から順にＤＰ領域（Ｐ型拡散領域）２２、ＮＷ領域（Ｎ型ウェル領域）２３、ＮＨＶ領域（Ｎ型拡散領域）２４、およびＰ＋領域（Ｐ型拡散領域）２５が積層された構成の静電気保護素子１２を用いてもよい。このように、図１１の（ａ）の例では、半導体チップ１の基板面法線方向に積層された複数の半導体領域からなる複数段のＰＮ接合を備えた双方向ツェナーダイオードが形成されている。 For example, as shown in FIG. 11A, in the P-type semiconductor layer 14 formed on the P-type silicon substrate 13, a DP region (P-type diffusion region) 22, NW in order from the P-type silicon substrate 13 side. The electrostatic protection element 12 having a configuration in which the region (N-type well region) 23, the NHV region (N-type diffusion region) 24, and the P + region (P-type diffusion region) 25 are stacked may be used. Thus, in the example of FIG. 11A, a bidirectional Zener diode having a plurality of stages of PN junctions composed of a plurality of semiconductor regions stacked in the direction normal to the substrate surface of the semiconductor chip 1 is formed. .

　また、図１１の（ｂ）に示すように、Ｐ型シリコン基板１３上に形成されたＰ型半導体層１４に第１ＮＨＶ領域（Ｎ型拡散領域）２６および第２ＮＨＶ領域（Ｎ型拡散領域）２７を形成し、第１ＮＨＶ領域２６にＮ＋領域２８を形成し、第２ＮＨＶ領域２７にＮ＋領域２９およびＰ＋領域３０を形成した構成の双方向ツェナーダイオードを用いてもよい。 Also, as shown in FIG. 11B, a first NHV region (N-type diffusion region) 26 and a second NHV region (N-type diffusion region) 27 are formed on the P-type semiconductor layer 14 formed on the P-type silicon substrate 13. , A N + region 28 may be formed in the first NHV region 26, and a N + region 29 and a P + region 30 may be formed in the second NHV region 27.

　また、図１１の（ｃ）に示すように、Ｐ型シリコン基板１３上に形成されたＰ型半導体層１４に第１ＮＨＶ領域（Ｎ型拡散領域）３１および第２ＮＨＶ領域（Ｎ型拡散領域）３２を形成し、第１ＮＨＶ領域３１にＮ＋領域３３およびＰ＋領域３４を形成し、第２ＮＨＶ領域３２にＮ＋領域３５およびＰ＋領域３６を形成した構成の双方向ツェナーダイオードを用いてもよい。 Further, as shown in FIG. 11C, a first NHV region (N-type diffusion region) 31 and a second NHV region (N-type diffusion region) 32 are formed on the P-type semiconductor layer 14 formed on the P-type silicon substrate 13. A bidirectional Zener diode having a configuration in which the N + region 33 and the P + region 34 are formed in the first NHV region 31 and the N + region 35 and the P + region 36 are formed in the second NHV region 32 may be used. .

　また、本実施形態では、１対のツェナーダイオードのカソード電極同士を接続することにより形成した双方向ツェナーダイオードを用いているが、これに限るものではない。例えば、図５に示すように、１対のツェナーダイオードのアノード電極同士を接続した双方向ツェナーダイオードを用いてもよい。 In this embodiment, a bidirectional Zener diode formed by connecting the cathode electrodes of a pair of Zener diodes is used, but the present invention is not limited to this. For example, as shown in FIG. 5, a bidirectional Zener diode in which the anode electrodes of a pair of Zener diodes are connected may be used.

　以上のように、本実施形態にかかる半導体チップ１は、基板１３の一方の面側に形成されたＭＯＳＦＥＴ１１を有する半導体チップであって、ＭＯＳＦＥＴ１１のゲート端子Ｇ１（ゲート電極１９）およびドレイン端子Ｄ１（ドレイン電極１８）が基板１３の一方の面側に設けられ、ＭＯＳＦＥＴ１１のソース端子Ｓ１（ソース電極２０）が基板１３の他方の面側に設けられており、一端側がゲート端子Ｇ１（ゲート電極１９）に接続され、他端側がソース端子Ｓ１（ソース電極２０）に接続された静電気保護素子１２を備えている。 As described above, the semiconductor chip 1 according to the present embodiment is a semiconductor chip having the MOSFET 11 formed on one surface side of the substrate 13, and includes the gate terminal G <b> 1 (gate electrode 19) and the drain terminal D <b> 1 ( The drain electrode 18) is provided on one surface side of the substrate 13, the source terminal S1 (source electrode 20) of the MOSFET 11 is provided on the other surface side of the substrate 13, and one end side is the gate terminal G1 (gate electrode 19). The other end side is provided with the electrostatic protection element 12 connected to the source terminal S1 (source electrode 20).

　これにより、ゲート電極とソース電極との間に接続される静電気保護素子１２を、当該半導体チップ１における基板面法線方向のスペースを有効に利用して配置することができる。したがって、ゲート酸化膜の静電破壊を防止するとともに、上述した特許文献１のようにゲート電極およびソース電極を基板の一方の面側に設け、これら両電極を単一層からなる双方向ツェナーダイオードを用いて接続する場合に比べて、半導体チップの基板面平行方向のサイズを低減し、半導体チップの小型化を図ることができる。 Thereby, the electrostatic protection element 12 connected between the gate electrode and the source electrode can be disposed by effectively utilizing the space in the normal direction of the substrate surface in the semiconductor chip 1. Therefore, while preventing electrostatic breakdown of the gate oxide film, a gate electrode and a source electrode are provided on one surface side of the substrate as described in Patent Document 1 described above, and a bidirectional Zener diode consisting of a single layer of these electrodes is provided. Compared with the case of using and connecting, the size of the semiconductor chip in the direction parallel to the substrate surface can be reduced, and the semiconductor chip can be downsized.

　なお、本実施形態では、本発明をＮチャネル型ＭＯＳＦＥＴに適用する場合について説明したが、本発明の適用対象はこれに限るものではなく、Ｐチャネル型ＭＯＳＦＥＴにも適用できる。この場合、Ｐチャネル型ＭＯＳＦＥＴの各半導体層の構成は特に限定されるものではなく、従来から公知のＰチャネル型ＭＯＳＦＥＴを用いることができる。 In the present embodiment, the case where the present invention is applied to an N-channel MOSFET has been described. However, the application target of the present invention is not limited to this, and the present invention can also be applied to a P-channel MOSFET. In this case, the configuration of each semiconductor layer of the P-channel MOSFET is not particularly limited, and a conventionally known P-channel MOSFET can be used.

　　〔実施形態２〕
　本発明の他の実施形態について説明する。なお、説明の便宜上、実施形態１と同様の機能を有する部材については実施形態１と同じ符号を付し、その説明を省略する。 [Embodiment 2]
Another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

　図６は本実施形態にかかる半導体装置１００の回路図であり、図７は半導体装置１００に備えられる半導体チップ１ｂの概略構成を示す説明図である。また、図８は、半導体装置１００を上方から見た平面図である。 FIG. 6 is a circuit diagram of the semiconductor device 100 according to the present embodiment, and FIG. 7 is an explanatory diagram showing a schematic configuration of the semiconductor chip 1b provided in the semiconductor device 100. FIG. 8 is a plan view of the semiconductor device 100 as viewed from above.

　図６に示すように、半導体装置１００は、半導体チップ１ｂ、半導体チップ２、ゲート端子Ｇ３、ソース端子Ｓ３、およびドレイン端子Ｄ３を備えている。 As shown in FIG. 6, the semiconductor device 100 includes a semiconductor chip 1b, a semiconductor chip 2, a gate terminal G3, a source terminal S3, and a drain terminal D3.

　半導体チップ１ｂは、実施形態１に示した半導体チップ１に加えて、基板の一方の面側（ゲート端子Ｇ１（ゲート電極１９）およびドレイン端子Ｄ１（ドレイン電極１８）が形成されている側）に設けられた第２ソース端子Ｓ１ｂと、ソース端子Ｓ１と第２ソース端子Ｓ１ｂとを接続するように設けられた、双方向ツェナーダイオードからなる第２静電気保護素子４２とを備えている。また、半導体チップ１ｂのソース端子Ｓ１は半導体装置１００のソース端子Ｓ３に接続され、半導体チップ１ｂのゲート端子Ｇ１は半導体装置１００のゲート端子Ｇ３に接続され、半導体チップ１ｂのドレイン端子Ｄ１は半導体チップ２のソース端子Ｓ２に接続され、第２ソース端子Ｓ１ｂは半導体チップ２のゲート端子Ｇ２に接続されている。半導体チップ１ｂにおけるその他の構成は実施形態１で示した半導体チップ１と略同様である。なお、第２静電気保護素子４２の構成は特に限定されるものではなく、例えば、静電気保護素子１２と同様のものを用いることができる。 In addition to the semiconductor chip 1 shown in the first embodiment, the semiconductor chip 1b is provided on one surface side of the substrate (the side on which the gate terminal G1 (gate electrode 19) and the drain terminal D1 (drain electrode 18) are formed). A second source terminal S1b is provided, and a second electrostatic protection element 42 made of a bidirectional Zener diode is provided so as to connect the source terminal S1 and the second source terminal S1b. The source terminal S1 of the semiconductor chip 1b is connected to the source terminal S3 of the semiconductor device 100, the gate terminal G1 of the semiconductor chip 1b is connected to the gate terminal G3 of the semiconductor device 100, and the drain terminal D1 of the semiconductor chip 1b is the semiconductor chip. The second source terminal S <b> 1 b is connected to the gate terminal G <b> 2 of the semiconductor chip 2. Other configurations of the semiconductor chip 1b are substantially the same as those of the semiconductor chip 1 shown in the first embodiment. The configuration of the second electrostatic protection element 42 is not particularly limited, and for example, the same structure as that of the electrostatic protection element 12 can be used.

　半導体チップ２は、ＭＯＳＦＥＴ４１を備えており、このＭＯＳＦＥＴ４１のゲート端子Ｇ２は半導体チップ１ｂの第２ソース端子Ｓ１ｂに接続され、ソース端子Ｓ２は半導体チップ１ｂのドレイン端子Ｄ１に接続され、ドレイン端子Ｄ２は半導体装置１００のドレイン端子Ｄ３に接続されている。すなわち、半導体チップ２のＭＯＳＦＥＴ４１は、半導体チップ１ｂの各ＭＯＳＦＥＴ１１に対してカスコード接続されている。なお、ＭＯＳＦＥＴ４１の構成は特に限定されるものではなく、従来から公知の構成からなるＭＯＳＦＥＴを用いることができる。 The semiconductor chip 2 includes a MOSFET 41. The gate terminal G2 of the MOSFET 41 is connected to the second source terminal S1b of the semiconductor chip 1b, the source terminal S2 is connected to the drain terminal D1 of the semiconductor chip 1b, and the drain terminal D2 is The drain terminal D3 of the semiconductor device 100 is connected. That is, the MOSFET 41 of the semiconductor chip 2 is cascode-connected to each MOSFET 11 of the semiconductor chip 1b. The configuration of the MOSFET 41 is not particularly limited, and a MOSFET having a conventionally known configuration can be used.

　以上のように、本実施形態にかかる半導体装置１００は、実施形態１で示した半導体チップ１に加えて、半導体チップ１のＭＯＳＦＥＴ群１０（各ＭＯＳＦＥＴ１１）に対してカスコード接続されたＭＯＳＦＥＴ４１を備えている。これにより、ＭＯＳＦＥＴ１１のドレイン電圧の変化を低減し、ミラー効果による帰還容量の影響を小さくすることができる。 As described above, the semiconductor device 100 according to the present embodiment includes the MOSFET 41 that is cascode-connected to the MOSFET group 10 (each MOSFET 11) of the semiconductor chip 1 in addition to the semiconductor chip 1 described in the first embodiment. Yes. Thereby, the change in the drain voltage of the MOSFET 11 can be reduced, and the influence of the feedback capacitance due to the mirror effect can be reduced.

　また、本実施形態にかかる半導体装置１００は、半導体チップ１ｂのソース端子Ｓ１とＭＯＳＦＥＴ４１のゲート端子Ｇ２との間に双方向ツェナーダイオードからなる第２静電気保護素子４２を備えている。これにより、静電気によってＭＯＳＦＥＴ４１のゲート酸化膜が破壊されることを防止できる。 Further, the semiconductor device 100 according to the present embodiment includes the second electrostatic protection element 42 formed of a bidirectional Zener diode between the source terminal S1 of the semiconductor chip 1b and the gate terminal G2 of the MOSFET 41. Thereby, it is possible to prevent the gate oxide film of the MOSFET 41 from being destroyed by static electricity.

　また、本実施形態では、上記の第２静電気保護素子４２を半導体チップ１ｂにおける基板１３の一方の面に設けている。これにより、第２静電気保護素子４２を、半導体チップ１ｂにおける基板面法線方向のスペースを有効に利用して配置することができる、半導体チップ１ｂのチップサイズを低減して半導体装置１００の小型化を図ることができる。 In the present embodiment, the second electrostatic protection element 42 is provided on one surface of the substrate 13 in the semiconductor chip 1b. Thereby, the second electrostatic protection element 42 can be disposed by effectively using the space in the normal direction of the substrate surface in the semiconductor chip 1b, and the semiconductor device 100 can be reduced in size by reducing the chip size of the semiconductor chip 1b. Can be achieved.

　なお、本実施形態では、第２静電気保護素子４２が半導体チップ１ｂに備えられている構成について説明したが、これに限るものではない。例えば、図９に示すように第２静電気保護素子４２を半導体チップ１ｂおよび半導体チップ２の外部に配置してもよく、図１０に示すように第２静電気保護素子４２を半導体チップ２に配置してもよい。なお、第２静電気保護素子４２を半導体チップ１ｂに設けない場合、半導体チップ１ｂに代えて、実施形態１と同様の半導体チップ１を用いればよい。 In addition, although this embodiment demonstrated the structure with which the 2nd electrostatic protection element 42 was equipped in the semiconductor chip 1b, it is not restricted to this. For example, the second electrostatic protection element 42 may be arranged outside the semiconductor chip 1b and the semiconductor chip 2 as shown in FIG. 9, and the second electrostatic protection element 42 is arranged in the semiconductor chip 2 as shown in FIG. May be. When the second electrostatic protection element 42 is not provided in the semiconductor chip 1b, the semiconductor chip 1 similar to that of the first embodiment may be used instead of the semiconductor chip 1b.

　　〔まとめ〕
　本発明の態様１にかかる半導体チップは、ＭＯＳＦＥＴを有する半導体チップであって、上記ＭＯＳＦＥＴのゲート端子およびドレイン端子が当該半導体チップの一方の面側に設けられ、上記ＭＯＳＦＥＴのソース端子が当該半導体チップの他方の面側に設けられており、一端側が上記ゲート端子に接続され、他端側が上記ソース端子に接続された静電気保護素子を備えていることを特徴としている。 [Summary]
The semiconductor chip according to the first aspect of the present invention is a semiconductor chip having a MOSFET, wherein the gate terminal and drain terminal of the MOSFET are provided on one surface side of the semiconductor chip, and the source terminal of the MOSFET is the semiconductor chip. And an electrostatic protection element having one end connected to the gate terminal and the other end connected to the source terminal.

　上記の構成によれば、静電気保護素子を設けることにより、静電耐圧特性を向上させ、ゲート絶縁膜の静電気（ESD（Electro-Static Discharge））による劣化を効果的に防止することができる。また、ＭＯＳＦＥＴのゲート電極を半導体チップの一方の面側に設け、ソース電極を他方の面側に設けることにより、これら両電極を接続する静電気保護素子を、当該半導体チップにおける厚さ方向のスペースを有効に用いて配置することができる。これにより、上述した特許文献１のようにゲート電極およびソース電極を半導体チップの一方の面側に設け、これら両電極を単一層からなる双方向ツェナーダイオードを用いて接続する場合に比べて、半導体チップの面内方向のサイズを低減し、半導体チップの小型化を図ることができる。 According to the above configuration, by providing the electrostatic protection element, it is possible to improve the electrostatic withstand voltage characteristics and effectively prevent deterioration of the gate insulating film due to static electricity (ESD (Electro-Static Discharge)). In addition, by providing the gate electrode of the MOSFET on one surface side of the semiconductor chip and the source electrode on the other surface side, the electrostatic protection element that connects these electrodes can be provided with a space in the thickness direction of the semiconductor chip. It can be used and arranged effectively. As a result, as compared with the case where the gate electrode and the source electrode are provided on one surface side of the semiconductor chip as in Patent Document 1 described above, and both electrodes are connected using a bidirectional Zener diode consisting of a single layer, the semiconductor The size in the in-plane direction of the chip can be reduced, and the semiconductor chip can be miniaturized.

　本発明の態様２にかかる半導体装置は、上記態様１において、上記ソース端子は、当該半導体チップに設けられたトレンチ部を介して上記ＭＯＳＦＥＴのソース領域に接続されている構成である。 The semiconductor device according to aspect 2 of the present invention is the structure according to aspect 1, in which the source terminal is connected to the source region of the MOSFET via a trench portion provided in the semiconductor chip.

　上記の構成によれば、半導体チップの一方の面側に設けられたＭＯＳＦＥＴのソース領域と、他方の面側に設けられたソース端子とを接続するための配線の長さを短くし、半導体チップをさらに小型化することができる。 According to the above configuration, the length of the wiring for connecting the source region of the MOSFET provided on one surface side of the semiconductor chip and the source terminal provided on the other surface side is shortened, and the semiconductor chip Can be further reduced in size.

　本発明の態様３にかかる半導体装置は、上記態様１または２において、上記静電気保護素子は、複数段のＰＮ接合を有する双方向ツェナーダイオードである構成としてもよい。 The semiconductor device according to aspect 3 of the present invention may be configured such that in the aspect 1 or 2, the electrostatic protection element is a bidirectional Zener diode having a plurality of stages of PN junctions.

　上記の構成によれば、静電気保護素子を容易に形成することができる。なお、上記双方向ツェナーダイオードは、半導体チップの厚さ方向に沿って配置された複数の半導体層からなるＰＮ接合を有する構成であってもよい。この場合、半導体チップの厚さ方向のスペースを有効に利用して双方向ツェナーダイオードを配置することができるので、半導体チップのサイズをより小さくすることができる。 According to the above configuration, the electrostatic protection element can be easily formed. The bidirectional Zener diode may have a PN junction composed of a plurality of semiconductor layers arranged along the thickness direction of the semiconductor chip. In this case, since the bidirectional Zener diode can be arranged by effectively using the space in the thickness direction of the semiconductor chip, the size of the semiconductor chip can be further reduced.

　本発明の態様４にかかる半導体装置は、上記態様１から３のいずれかにおいて、上記ＭＯＳＦＥＴは、横方向拡散ＭＯＳ構造を有している構成である。 The semiconductor device according to aspect 4 of the present invention is the structure according to any one of the aspects 1 to 3, wherein the MOSFET has a lateral diffusion MOS structure.

　上記の構成によれば、ゲート電極が基板の一方の面側に形成され、ソース電極が基板の他方の面側に形成された半導体装置を容易に製造することができる。 According to the above configuration, it is possible to easily manufacture a semiconductor device in which the gate electrode is formed on one surface side of the substrate and the source electrode is formed on the other surface side of the substrate.

　本発明の態様５にかかる半導体装置は、上記態様１から４のいずれかにおいて、上記双方向ツェナーダイオードは、一対のツェナーダイオードにおける互いのカソード電極同士またはアノード電極同士が接続された構成である。 In the semiconductor device according to Aspect 5 of the present invention, in any one of Aspects 1 to 4, the bidirectional Zener diode is configured such that the cathode electrodes or the anode electrodes of a pair of Zener diodes are connected to each other.

　上記の構成によれば、静電気保護素子としての双方向ツェナーダイオードを容易に形成することができる。 According to the above configuration, a bidirectional Zener diode as an electrostatic protection element can be easily formed.

　本発明の一態様にかかる半導体装置は、上記したいずれかの半導体チップと、上記ＭＯＳＦＥＴに接続された第２ＭＯＳＦＥＴを有する第２半導体チップと、第２静電気保護素子とを備え、上記第２ＭＯＳＦＥＴのゲート端子は上記第２静電気保護素子を介して上記ＭＯＳＦＥＴのソース端子に接続され、上記第２ＭＯＳＦＥＴのソース端子は上記各ＭＯＳＦＥＴのドレイン端子に接続されていることを特徴としている。 A semiconductor device according to an aspect of the present invention includes any one of the semiconductor chips described above, a second semiconductor chip having a second MOSFET connected to the MOSFET, and a second electrostatic protection element, and a gate of the second MOSFET. The terminal is connected to the source terminal of the MOSFET via the second electrostatic protection element, and the source terminal of the second MOSFET is connected to the drain terminal of each MOSFET.

　上記の構成によれば、上記半導体チップのＭＯＳＦＥＴと上記第２半導体チップの第２ＭＯＳＦＥＴとがカスコード接続された半導体装置を形成することができる。また、半導体チップのサイズを低減できるので、半導体装置のサイズを低減できる。 According to the above configuration, a semiconductor device in which the MOSFET of the semiconductor chip and the second MOSFET of the second semiconductor chip are cascode-connected can be formed. In addition, since the size of the semiconductor chip can be reduced, the size of the semiconductor device can be reduced.

　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。さらに、各実施形態にそれぞれ開示された技術的手段を組み合わせることにより、新しい技術的特徴を形成することができる。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

　本発明は、ＭＯＳＦＥＴを有する半導体装置およびその製造方法に適用できる。 The present invention can be applied to a semiconductor device having a MOSFET and a manufacturing method thereof.

１，１ｂ　半導体チップ
２　半導体チップ（第２半導体チップ）
１０　ＭＯＳＦＥＴ群
１１　ＭＯＳＦＥＴ
１２　静電気保護素子
１３　Ｐ型シリコン基板（基板）
１７　ゲート絶縁膜
１８　ドレイン電極
１９　ゲート電極
２０　ソース電極
２１　トレンチ部
４１　ＭＯＳＦＥＴ
４２　第２静電気保護素子
１００　半導体装置
Ｄ１～Ｄ３　ドレイン端子
Ｇ１～Ｇ３　ゲート端子
Ｓ１～Ｓ３　ソース端子
Ｓ１ｂ　第２ソース端子
  1, 1b Semiconductor chip 2 Semiconductor chip (second semiconductor chip)
10 MOSFET group 11 MOSFET
12 Electrostatic protection element 13 P-type silicon substrate (substrate)
17 Gate insulating film 18 Drain electrode 19 Gate electrode 20 Source electrode 21 Trench portion 41 MOSFET
42 Second electrostatic protection element 100 Semiconductor devices D1 to D3 Drain terminals G1 to G3 Gate terminals S1 to S3 Source terminal S1b Second source terminal

Claims (5)

　ＭＯＳＦＥＴを有する半導体チップであって、
　上記ＭＯＳＦＥＴのゲート端子およびドレイン端子が当該半導体チップの一方の面側に設けられ、
　上記ＭＯＳＦＥＴのソース端子が当該半導体チップの他方の面側に設けられており、
　一端側が上記ゲート端子に接続され、他端側が上記ソース端子に接続された静電気保護素子を備えていることを特徴とする半導体チップ。 A semiconductor chip having a MOSFET,
A gate terminal and a drain terminal of the MOSFET are provided on one surface side of the semiconductor chip;
The source terminal of the MOSFET is provided on the other surface side of the semiconductor chip,
A semiconductor chip comprising an electrostatic protection element having one end connected to the gate terminal and the other end connected to the source terminal. 　上記ソース端子は、当該半導体チップに設けられたトレンチ部を介して上記ＭＯＳＦＥＴのソース領域に接続されていることを特徴とする請求項１に記載の半導体チップ。 2. The semiconductor chip according to claim 1, wherein the source terminal is connected to a source region of the MOSFET through a trench provided in the semiconductor chip. 　上記静電気保護素子は、複数段のＰＮ接合を有する双方向ツェナーダイオードであることを特徴とする請求項１または２に記載の半導体チップ。 3. The semiconductor chip according to claim 1, wherein the electrostatic protection element is a bidirectional Zener diode having a plurality of stages of PN junctions. 　上記ＭＯＳＦＥＴは、横方向拡散ＭＯＳ構造を有していることを特徴とする請求項１から３のいずれか１項に記載の半導体チップ。 4. The semiconductor chip according to claim 1, wherein the MOSFET has a lateral diffusion MOS structure. 　請求項１から４のいずれか１項に記載の半導体チップと、
　上記ＭＯＳＦＥＴに接続された第２ＭＯＳＦＥＴを有する第２半導体チップと、
　第２静電気保護素子とを備え、
　上記第２ＭＯＳＦＥＴのゲート端子は上記第２静電気保護素子を介して上記ＭＯＳＦＥＴのソース端子に接続され、上記第２ＭＯＳＦＥＴのソース端子は上記各ＭＯＳＦＥＴのドレイン端子に接続されていることを特徴とする半導体装置。
  The semiconductor chip according to any one of claims 1 to 4,
A second semiconductor chip having a second MOSFET connected to the MOSFET;
A second electrostatic protection element,
The gate terminal of the second MOSFET is connected to the source terminal of the MOSFET via the second electrostatic protection element, and the source terminal of the second MOSFET is connected to the drain terminal of each MOSFET. .
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