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WO2014036725A1 - Method, device and equipment for pcie port configuration - Google Patents

Method, device and equipment for pcie port configuration Download PDF

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Publication number
WO2014036725A1
WO2014036725A1 PCT/CN2012/081144 CN2012081144W WO2014036725A1 WO 2014036725 A1 WO2014036725 A1 WO 2014036725A1 CN 2012081144 W CN2012081144 W CN 2012081144W WO 2014036725 A1 WO2014036725 A1 WO 2014036725A1
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WO
WIPO (PCT)
Prior art keywords
cpu
pcie
pcie port
channels
strobed
Prior art date
Application number
PCT/CN2012/081144
Other languages
French (fr)
Chinese (zh)
Inventor
罗雁云
刘华伟
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2012/081144 priority Critical patent/WO2014036725A1/en
Priority to CN201280001711.XA priority patent/CN103003806B/en
Publication of WO2014036725A1 publication Critical patent/WO2014036725A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

Definitions

  • the present invention belongs to the field of bus interfaces, and in particular, to a method, device and device for configuring a PCIE port. Background technique
  • PCIE Peripheral Component Interconnect Express
  • the CPU Central Processing Unit
  • the CPU is a PCIE port and an endpoint such as a graphics card and memory.
  • the device is connected.
  • Different CPUs may provide different PCIE port resources, that is, there may be different numbers of PCIE ports, and channels supporting different PCIE port types (lane in English).
  • PCIE model A only supports PCIe 1.0 type channels, which can support The 81ane has only one PCIe controller; the CPU model B can support PCIe 2.0 type channels, can support 41ane, and has two PCIe controllers.
  • the EP device of the graphics card and the memory should be adapted to the CPU of different PCIE port resources, that is, it needs to adapt to different numbers of PCIE ports and PCIE ports of the CPU.
  • the prior art can only complete the configuration of the PCIE port in the hardware setting, and cannot Flexible configuration of PCIE ports, to achieve good implementation of graphics cards, memory and other EP devices to adapt to different CPUs.
  • the purpose of the embodiments of the present invention is to provide a method, a device, and a device for configuring a PCIE port, so as to solve the problem that the PCIE port cannot be flexibly configured in the prior art, so as to be well adapted to the CPU of different PCIE ports.
  • a method for configuring a PCIE port includes the following steps: Receiving an identification signal sent by the central processing unit CPU, where the identification signal includes information indicating a model number of the CPU;
  • PCIE port information of the CPU includes one or more of a number of PCIE ports, a PCIE port type, and a number of PCIE port channels;
  • the MUX chip performs CPU strobing according to the PCIE port information
  • a device for configuring a PCIE port includes: a receiving unit, configured to receive an identification signal sent by a CPU of the central processing unit, where the identification signal includes information indicating a model of the CPU;
  • a PCIE port information acquiring unit configured to acquire PCIE port information of the CPU according to the identifier signal received by the receiving unit, where the PCIE port information includes one of a PCIE port number, a PCIE port type, and a PCIE port channel number.
  • a strobe unit configured to control the multiplexer, and the MUX chip performs CPU strobing according to the PCIE port information acquired by the PCIE port information acquiring unit;
  • a connecting unit configured to control the MUX chip to perform a PCIE port connection according to the result of the gating unit gating.
  • a device for configuring a PCIE port comprising an input device, a processor, and an output device, the processor performing the following steps:
  • PCIE port information of the CPU includes one or more of a number of PCIE ports, a PCIE port type, and a PCIE port channel number; Controlling the multiplexer MUX chip to perform CPU strobe according to the PCIE port information;
  • the MUX chip is controlled to perform a PCIE port connection according to the result of the gating.
  • the type identification signal of the CPU is used to identify the model of the CPU, thereby obtaining the PCIE port information provided by the CPU, and controlling the multiplexer (the multiplexer, the cartridge is called the MUX) chip for CPU strobe and the strobed CPU.
  • the PCIE port is connected, so that the EP device can be adaptively connected with the PCIE port of different CPUs, that is, the flexible configuration of the PCIE port is realized.
  • FIG. 1 is a flowchart of a method for configuring a PCIE port according to an embodiment of the present invention
  • FIG. 2 is a structural diagram of a device for configuring a PCIE port according to another embodiment of the present invention
  • FIG. 3 is a configuration of a PCIE according to another embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for configuring a PCIE port according to an embodiment of the present invention, where the method includes the following steps:
  • step S101 an identification signal transmitted by the CPU is received.
  • the EP device and the CPU are both connected to the backplane, and the data interaction between the EP device and the CPU can be implemented through the backplane.
  • the EP device receives the identification signal sent by the CPU.
  • the identification signal is used to indicate the model of the CPU, which may be a standard hardware signal or a software signal implemented using software such as I2C.
  • step S102 according to the received identification signal, acquiring the CPU provided PCIE port information.
  • the EP device after receiving the identification signal sent by the CPU, the EP device analyzes and identifies the identification signal, identifies the CPU model corresponding to the identification signal, and further obtains the PCIE port information corresponding to the CPU model.
  • the PCIE port information includes: the number of ports provided, the type of each port (PCIE1.0, PCIE2.0, etc.), the number of channel lanes provided by each port, and the like.
  • step S103 the control multiplexer MUX chip performs CPU strobe according to the acquired PCIE port information.
  • a plurality of CPUs may be connected to a backplane.
  • the EP device controls the MUX chip to select a suitable CPU according to the PCIE port information, that is, performs CPU strobe.
  • the CPU strobe is specifically: The CPU corresponding to the PCIE port with the matching number of channels is preferentially selected. When the number of channels provided is matched, the number of CPUs with a large number of PCIE ports is selected. When the number of channels provided is smaller than the number of channels required, the CPU with a large number of channels is preferentially selected. When the number of channels provided is greater than the number of channels required, the number of CPUs with a small number of channels is preferred.
  • step S104 the control MUX chip performs a PCIE port connection according to the result of the gating.
  • the EP device controls the MUX chip to perform connection with the PCIE port of the CPU. Specifically: if the CPU only provides one PCIE port, The EP device controls the MUX chip to connect to the PCIE port. If the CPU provides multiple PCIE ports, the EP device controls the MUX chip to connect to one of the PCIE ports, and disconnects from other PCIE ports.
  • the specific connection method uses the existing MUX. Chip technology, no longer detailed here.
  • CPU A can provide one 8-channel (X8) PCIE port
  • CPU B can provide two 4-channel (X4) PCIE ports.
  • CPU A and CPU B simultaneously send an identification signal to the EP device, where the type signal may be a type signal, and the type signal includes information of a CPU model, which may be a hardware signal or a software signal implemented by software;
  • the EP device receives the type signal sent by the CPU, analyzes the type signal to obtain the CPU model, and obtains the detailed information of the PCIE port provided by the CPU, that is, the CPU A can provide an 8-channel (X8) PCIE port, CPU B. Two 4-channel (X4) PCIE ports are available;
  • EP device control multiplexer The MUX chip selects the appropriate CPU.
  • the EP device controls the MUX chip to connect with the PCIE port of the selected CPU. Specifically: a. If CPU A is selected, CPU A can only provide one PCIE port, and then connect with all PCIE ports of CPU A, the specific connection. The method is the same as the connection technology of the existing MUX chip. b. If CPU B is selected, CPU B can provide two PCIE ports, then connect with one PCIE port of CPU B, and disconnect another PCIE port. The specific connection method is The connection technology of the existing MUX chip is the same.
  • the identification signal of the CPU by acquiring the identification signal of the CPU, identifying the model of the CPU, obtaining the PCIE port information provided by the CPU, controlling the MUX chip to perform CPU strobe and connecting with the PCIE port of the strobed CPU, thereby implementing the EP device. It can be adaptively connected with PCIE ports of different CPUs, that is, flexible configuration of PCIE ports.
  • FIG. 2 is a structural diagram of a device for configuring a PCIE port according to an embodiment of the present invention. For ease of description, only parts related to the embodiment of the present invention are shown, including:
  • the receiving unit 21 is configured to receive an identification signal sent by the central processing unit CPU.
  • the receiving unit 21 and the CPU are both connected to the backboard, and
  • the backplane can implement data interaction between the EP device and the CPU.
  • the EP device receives the identification signal sent by the CPU.
  • the identification signal includes information of a CPU model, which may be a standard hardware signal, or may be a software signal implemented by using software such as I2C.
  • the PCIE port information obtaining unit 22 is configured to obtain PCIE port information provided by the CPU according to the identification signal received by the receiving unit 21.
  • the PCIE port information acquiring unit 22 analyzes and identifies the identification signal, identifies the CPU model corresponding to the identification signal, and acquires the CPU.
  • the PCIE port information corresponding to the model, the PCIE port information includes: the number of ports that can be provided, the type of each port (PCIE1.0, PCIE2.0, etc.), and the number of channels provided by each port.
  • the strobe unit 23 is configured to control the multiplexer.
  • the MUX chip performs CPU strobe according to the PCIE port information acquired by the PCIE port information acquiring unit 22.
  • a backplane may be connected to a plurality of CPUs.
  • the gate unit 23 controls the MUX chip to select a suitable CPU according to the PCIE port information, that is, performs CPU strobe, and the CPU strobe is specifically :
  • the CPU corresponding to the port with the matching number of channels is preferentially selected; when the number of channels provided is matched, the number of CPUs with a large number of PCIE ports is selected; when the number of channels provided is less than the number of channels required, the CPU with a large number of channels is preferentially selected; When the number of channels provided is greater than the number of channels required, the number of CPUs with a small number of channels is preferred.
  • the connecting unit 24 is configured to control the MUX chip to perform a PCIE port connection according to the result of the gating of the gating unit 23.
  • connection unit 24 controls the MUX chip to perform a PCIE port connection according to the result of the gating unit 23 gating.
  • the connection unit 24 specifically includes: a single port connection subunit 241, configured to be provided only when the CPU provides a PCIE port, the control MUX chip is connected to the PCIE port; and the plurality of port connection sub-units 242 are used When the CPU provides multiple PCIE ports, the MUX chip is connected to one of the PCIE ports, and the other PCIE ports are disconnected.
  • the specific connection method uses the existing MUX chip technology, and details are not described herein.
  • the identification signal of the CPU by acquiring the identification signal of the CPU, identifying the model of the CPU, obtaining the PCIE port information provided by the CPU, controlling the MUX chip to perform CPU strobe and connecting with the PCIE port of the strobed CPU, thereby implementing the EP device. It can be adaptively connected with PCIE ports of different CPUs, that is, flexible configuration of PCIE ports.
  • FIG. 3 is a structural diagram of a device for configuring a PCIE port according to an embodiment of the present invention.
  • the device includes an input unit 31, a processor 32, and an output unit 33, and the processor 32 performs the following steps:
  • the EP device and the CPU are both connected to the backplane, and the data interaction between the EP device and the CPU can be implemented through the backplane.
  • the EP device receives the identification signal sent by the CPU.
  • the identification signal includes information indicating a CPU model, and may be a standard hardware signal or a software signal implemented by using software such as I2C.
  • the PCIE port device After receiving the identification signal sent by the CPU, the PCIE port device analyzes and identifies the identification signal, identifies the CPU model corresponding to the identification signal, and obtains the PCIE port corresponding to the CPU model. Information, the PCIE port information includes: the number of ports that can be provided, the type of each port (PCIE1.0, PCIE2.0, etc.), the number of channels provided by each port, and so on.
  • the MUX chip performs CPU strobe according to the obtained PCIE port information.
  • the device control MUX chip selects a suitable CPU according to the PCIE port information, that is, performs CPU strobe, and the CPU strobe is specifically: preferentially selecting a CPU corresponding to a port whose number of channels matches; selecting a port when the number of channels provided is matched A large number of CPUs; when the number of channels provided is less than the number of channels required, the number of channels is preferred.
  • the control MUX chip performs a PCIE port connection according to the result of the gating.
  • the EP device controls the MUX chip to perform connection with the PCIE port. Specifically: if the CPU only provides one PCIE port, the EP device controls The MUX chip is connected to the PCIE port. If the CPU provides multiple PCIE ports, the EP device controls the MUX chip to connect to one of the PCIE ports, and disconnects from the other PCIE ports.
  • the specific connection method uses the existing MUX chip technology. I will not repeat them here.
  • the identification signal of the CPU by acquiring the identification signal of the CPU, identifying the model of the CPU, obtaining the PCIE port information provided by the CPU, controlling the MUX chip to perform CPU strobe and connecting with the PCIE port of the strobed CPU, thereby implementing the EP device. It can be adaptively connected with PCIE ports of different CPUs, that is, flexible configuration of PCIE ports.
  • each unit included is only divided according to functional logic, but is not limited to the foregoing division, as long as the corresponding function can be implemented;
  • the specific names are also for convenience of distinguishing from each other and are not intended to limit the scope of the present invention.
  • all or part of the steps in implementing the foregoing method embodiments may be performed by a program to instruct related hardware, and the corresponding program may be stored in a computer readable storage medium.
  • the storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

The invention, which is applicable to the field of bus interfaces, provides a method, a device and equipment for PCIE port configuration. The method comprises: receiving an identification signal from a CPU; obtaining the PCIE port information of the CPU according to the received identification signal; controlling the multiplexer MUX chip to gate the CPU according to the PCIE port information; controlling the MUX chip to connect the PCIE port according to the gating result. By obtaining the CPU type identification signal, the embodiment of the invention recognizes the type of the CPU, thereby obtains the PCIE interface information provided by the CPU, controls the MUX chip to gate the CPU and connect the gated CPU, so as to enable the EP device to be self-adapted to and connected to the PCIE ports of different CPUs, i.e., flexible configuration of the PCIE port is realized.

Description

一种配置 PCIE端口的方法、 装置和设备 技术领域  Method, device and device for configuring PCIE port
本发明属于总线接口领域，尤其涉及一种配置 PCIE端口的方法、 装置和设备。 背景技术  The present invention belongs to the field of bus interfaces, and in particular, to a method, device and device for configuring a PCIE port. Background technique
高速夕卜设组件互连 ( Peripheral Component Interconnect Express , 筒称 PCIE )是最新的总线与接口标准， CPU ( Central Processing Unit , 筒称 CPU )通过 PCIE端口与显卡、 内存等端点（ endpoint, 筒称 EP ) 设备进行连接。不同的 CPU可能会提供不同的 PCIE端口资源， 即可 能会有不同的 PCIE端口数量， 以及支持不同 PCIE端口类型的通道 (英文为 lane ) , 例如 CPU型号 A只支持 PCIe 1.0类型的通道， 可 以支持 81ane,只有一个 PCIe控制器； 而 CPU型号 B,可以支持 PCIe 2.0类型的通道， 能支持 41ane, 有两个 PCIe控制器。  Peripheral Component Interconnect Express (PCIE) is the latest bus and interface standard. The CPU (Central Processing Unit) is a PCIE port and an endpoint such as a graphics card and memory. The device is connected. Different CPUs may provide different PCIE port resources, that is, there may be different numbers of PCIE ports, and channels supporting different PCIE port types (lane in English). For example, CPU model A only supports PCIe 1.0 type channels, which can support The 81ane has only one PCIe controller; the CPU model B can support PCIe 2.0 type channels, can support 41ane, and has two PCIe controllers.
显卡、 内存等 EP设备要适应不同 PCIE端口资源的 CPU, 即需 要适应 CPU不同数量的 PCIE端口和 PCIE端口不同类型的通道， 而 现有技术只能在硬件设置时完成 PCIE端口的配置， 并不能灵活配置 PCIE端口， 以很好的实现显卡、 内存等 EP设备适应不同的 CPU。  The EP device of the graphics card and the memory should be adapted to the CPU of different PCIE port resources, that is, it needs to adapt to different numbers of PCIE ports and PCIE ports of the CPU. However, the prior art can only complete the configuration of the PCIE port in the hardware setting, and cannot Flexible configuration of PCIE ports, to achieve good implementation of graphics cards, memory and other EP devices to adapt to different CPUs.
发明内容 Summary of the invention
本发明实施例的目的在于提供一种配置 PCIE端口的方法、 装置 和设备， 以解决现有技术不能灵活配置 PCIE端口， 以很好的适应不 同 PCIE端口的 CPU的问题。  The purpose of the embodiments of the present invention is to provide a method, a device, and a device for configuring a PCIE port, so as to solve the problem that the PCIE port cannot be flexibly configured in the prior art, so as to be well adapted to the CPU of different PCIE ports.
一方面， 提供了一种配置 PCIE端口的方法， 所述方法包括以下 步骤： 接收中央处理器 CPU发送的标识信号， 所述标识信号包含用来 指明所述 CPU的型号的信息； In one aspect, a method for configuring a PCIE port is provided, and the method includes the following steps: Receiving an identification signal sent by the central processing unit CPU, where the identification signal includes information indicating a model number of the CPU;
根据接收的所述标识信号，获取所述 CPU的 PCIE端口信息，所 述 PCIE端口信息包括 PCIE端口数量、 PCIE端口类型、 PCIE端口 通道数中的一种或几种；  Obtaining PCIE port information of the CPU according to the received identification signal, where the PCIE port information includes one or more of a number of PCIE ports, a PCIE port type, and a number of PCIE port channels;
控制多路选择器 MUX芯片根据所述 PCIE端口信息进行 CPU选 通；  Controlling the multiplexer The MUX chip performs CPU strobing according to the PCIE port information;
控制所述 MUX芯片根据所述选通的结果进行 PCIE端口连接。 另一方面， 提供了一种配置 PCIE端口的装置， 所述装置包括： 接收单元， 用于接收中央处理器 CPU发送的标识信号， 所述标 识信号包含用来指明所述 CPU的型号的信息；  The MUX chip is controlled to perform a PCIE port connection according to the result of the gating. In another aspect, a device for configuring a PCIE port is provided, the device includes: a receiving unit, configured to receive an identification signal sent by a CPU of the central processing unit, where the identification signal includes information indicating a model of the CPU;
PCIE端口信息获取单元， 用于根据所述接收单元接收的标识信 号，获取所述 CPU的 PCIE端口信息，所述 PCIE端口信息包括 PCIE 端口数量、 PCIE端口类型、 PCIE端口通道数中的一种或几种；  a PCIE port information acquiring unit, configured to acquire PCIE port information of the CPU according to the identifier signal received by the receiving unit, where the PCIE port information includes one of a PCIE port number, a PCIE port type, and a PCIE port channel number. Several
选通单元， 用于控制多路选择器 MUX芯片根据所述 PCIE端口 信息获取单元获取的 PCIE端口信息进行 CPU选通；  a strobe unit, configured to control the multiplexer, and the MUX chip performs CPU strobing according to the PCIE port information acquired by the PCIE port information acquiring unit;
连接单元， 用于控制所述 MUX芯片根据所述选通单元选通的结 果进行 PCIE端口连接。  And a connecting unit, configured to control the MUX chip to perform a PCIE port connection according to the result of the gating unit gating.
再一方面， 提供了一种配置 PCIE端口的设备， 所述设备包括输 入装置、 处理器、 输出装置， 所述处理器执行以下步骤：  In a further aspect, a device for configuring a PCIE port is provided, the device comprising an input device, a processor, and an output device, the processor performing the following steps:
接收中央处理器 CPU发送的标识信号， 所述标识信息包含用来 指明所述 CPU的型号的信息；  Receiving an identification signal sent by the central processing unit CPU, where the identification information includes information indicating a model number of the CPU;
根据接收的所述标识信号，获取所述 CPU的 PCIE端口信息，所 述 PCIE端口信息包括 PCIE端口数量、 PCIE端口类型、 PCIE端口 通道数中的一种或几种； 控制多路选择器 MUX芯片根据所述 PCIE端口信息进行 CPU选 通； Obtaining PCIE port information of the CPU according to the received identifier signal, where the PCIE port information includes one or more of a number of PCIE ports, a PCIE port type, and a PCIE port channel number; Controlling the multiplexer MUX chip to perform CPU strobe according to the PCIE port information;
控制所述 MUX芯片根据所述选通的结果进行 PCIE端口连接。 本发明实施例，通过获取 CPU的类型标识信号来识别 CPU的型 号， 进而获取 CPU 提供的 PCIE 端口信息， 控制多路选择器 ( multiplexer, 筒称 MUX ) 芯片进行 CPU选通并与选通的 CPU的 PCIE端口进行连接， 从而 EP设备可以与不同 CPU的 PCIE端口的 自适应和连接， 即实现了 PCIE端口的灵活配置。  The MUX chip is controlled to perform a PCIE port connection according to the result of the gating. In the embodiment of the present invention, the type identification signal of the CPU is used to identify the model of the CPU, thereby obtaining the PCIE port information provided by the CPU, and controlling the multiplexer (the multiplexer, the cartridge is called the MUX) chip for CPU strobe and the strobed CPU. The PCIE port is connected, so that the EP device can be adaptively connected with the PCIE port of different CPUs, that is, the flexible configuration of the PCIE port is realized.
附图说明 DRAWINGS
图 1是本发明一个实施例提供的配置 PCIE端口方法的流程图； 图 2是本发明另一实施例提供的配置 PCIE端口装置的结构图； 图 3是本发明再一实施例提供的配置 PCIE端口设备的结构图。  1 is a flowchart of a method for configuring a PCIE port according to an embodiment of the present invention; FIG. 2 is a structural diagram of a device for configuring a PCIE port according to another embodiment of the present invention; FIG. 3 is a configuration of a PCIE according to another embodiment of the present invention. A block diagram of the port device.
具体实施方式 detailed description
为了使本发明的目的、技术方案及优点更加清楚明白， 以下结合 附图及实施例， 对本发明进行进一步详细说明。 应当理解， 此处所描 述的具体实施例仅仅用以解释本发明， 并不用于限定本发明。 如图 1 所示为本发明实施例提供的配置 PCIE端口方法的流程 图， 所述方法包括以下步骤：  In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. FIG. 1 is a flowchart of a method for configuring a PCIE port according to an embodiment of the present invention, where the method includes the following steps:
在步骤 S101中， 接收 CPU发送的标识信号。  In step S101, an identification signal transmitted by the CPU is received.
在本发明实施例中， EP设备与 CPU都连接在背板上， 通过背板 可以实现 EP设备与 CPU的数据交互。 通过背板， EP设备接收 CPU 发送的标识信号。 所述标识信号用来指明 CPU的型号， 可以是标准 的硬件信号， 也可以是使用 I2C等软件实现的软件信号。  In the embodiment of the present invention, the EP device and the CPU are both connected to the backplane, and the data interaction between the EP device and the CPU can be implemented through the backplane. Through the backplane, the EP device receives the identification signal sent by the CPU. The identification signal is used to indicate the model of the CPU, which may be a standard hardware signal or a software signal implemented using software such as I2C.
在步骤 S102 中， 根据所述接收的标识信号， 获取 CPU提供的 PCIE端口信息。 In step S102, according to the received identification signal, acquiring the CPU provided PCIE port information.
在本发明实施例中， EP设备在接收到 CPU发送的标识信号之后， 对所述标识信号进行分析识别，识别出该标识信号对应的 CPU型号， 进而获取所述 CPU型号对应的 PCIE端口信息， 所述 PCIE端口信息 包括： 提供的端口数量、 每个端口的类型 （PCIE1.0、 PCIE2.0等） 、 每个端口提供的通道 lane数量等。  In the embodiment of the present invention, after receiving the identification signal sent by the CPU, the EP device analyzes and identifies the identification signal, identifies the CPU model corresponding to the identification signal, and further obtains the PCIE port information corresponding to the CPU model. The PCIE port information includes: the number of ports provided, the type of each port (PCIE1.0, PCIE2.0, etc.), the number of channel lanes provided by each port, and the like.
在步骤 S103 中， 控制多路选择器 MUX 芯片根据所述获取的 PCIE端口信息进行 CPU选通。  In step S103, the control multiplexer MUX chip performs CPU strobe according to the acquired PCIE port information.
在本发明实施例中， 一个背板上有可能连接多个 CPU, 此时 EP 设备控制 MUX芯片根据所述 PCIE端口信息选择合适的 CPU, 即进 行 CPU选通，所述 CPU选通具体为：优先选择通道数量匹配的 PCIE 端口对应的 CPU; 当提供的通道数量都匹配时选择提供 PCIE端口数 量多的 CPU; 当提供的通道数量都小于需要的通道数量时， 优先选 择通道数量多的 CPU; 当提供的通道数量都大于需要的通道数量时， 优先选择通道数量少的 CPU。  In the embodiment of the present invention, a plurality of CPUs may be connected to a backplane. In this case, the EP device controls the MUX chip to select a suitable CPU according to the PCIE port information, that is, performs CPU strobe. The CPU strobe is specifically: The CPU corresponding to the PCIE port with the matching number of channels is preferentially selected. When the number of channels provided is matched, the number of CPUs with a large number of PCIE ports is selected. When the number of channels provided is smaller than the number of channels required, the CPU with a large number of channels is preferentially selected. When the number of channels provided is greater than the number of channels required, the number of CPUs with a small number of channels is preferred.
在步骤 S104中， 控制 MUX芯片根据所述选通的结果进行 PCIE 端口连接。  In step S104, the control MUX chip performs a PCIE port connection according to the result of the gating.
在本发明实施例中， EP设备在选择到合适的 CPU后 （即 CPU 选通有结果后 ) , 控制 MUX芯片进行与 CPU的 PCIE端口的连接， 具体的： 如果 CPU只提供一个 PCIE端口， 则 EP设备控制 MUX芯 片连通所述 PCIE端口； 如果 CPU提供了多个 PCIE端口， 则 EP设 备控制 MUX芯片连通其中一个 PCIE端口， 断开与其他 PCIE端口 的连通，具体的连通方法使用现有的 MUX芯片技术，此处不再赘述。  In the embodiment of the present invention, after selecting the appropriate CPU (that is, after the CPU strobe has a result), the EP device controls the MUX chip to perform connection with the PCIE port of the CPU. Specifically: if the CPU only provides one PCIE port, The EP device controls the MUX chip to connect to the PCIE port. If the CPU provides multiple PCIE ports, the EP device controls the MUX chip to connect to one of the PCIE ports, and disconnects from other PCIE ports. The specific connection method uses the existing MUX. Chip technology, no longer detailed here.
举例说明：  for example:
假设在一个系统中同时有两个 CPU: CPU A和 CPU B, 与背板 连接的有 EP设备 C。 CPU A可以提供 1个 8通道（ X8 ) 的 PCIE端 口， CPU B可以提供 2个 4通道（ X4 ) 的 PCIE端口。 具体的： Assume that there are two CPUs in a system at the same time: CPU A and CPU B, with the backplane The EP device C is connected. CPU A can provide one 8-channel (X8) PCIE port, and CPU B can provide two 4-channel (X4) PCIE ports. specific:
1、 CPU A、 CPU B同时向 EP设备发送标识信号， 此处可以为 type信号，所述 type信号中包含 CPU型号的信息，可以是硬件信号， 也可以是通过软件实现的软件信号；  1. CPU A and CPU B simultaneously send an identification signal to the EP device, where the type signal may be a type signal, and the type signal includes information of a CPU model, which may be a hardware signal or a software signal implemented by software;
2、 EP设备接收 CPU发送的 type信号， 分析所述 type信号获取 CPU型号， 进而获取 CPU提供的 PCIE端口的详细信息， 即： CPU A 可以提供 1个 8通道（ X8 )的 PCIE端口， CPU B可以提供 2个 4通 道（ X4 ) 的 PCIE端口；  2. The EP device receives the type signal sent by the CPU, analyzes the type signal to obtain the CPU model, and obtains the detailed information of the PCIE port provided by the CPU, that is, the CPU A can provide an 8-channel (X8) PCIE port, CPU B. Two 4-channel (X4) PCIE ports are available;
3、 EP设备控制多路选择器 MUX芯片选择合适 CPU。  3. EP device control multiplexer The MUX chip selects the appropriate CPU.
4、 EP设备控制 MUX芯片与选择的 CPU的 PCIE端口进行连接， 具体： a、 如果选择 CPU A, CPU A只能提供 1个 PCIE端口， 则与 CPU A的所有 PCIE端口进行连接， 具体的连接方法与现有 MUX芯 片的连接技术相同； b、如果选择 CPU B, CPU B可以提供 2个 PCIE 端口，那么与 CPU B的一个 PCIE端口进行连接，断开另外一个 PCIE 端口， 具体的连接方法与现有 MUX芯片的连接技术相同。  4. The EP device controls the MUX chip to connect with the PCIE port of the selected CPU. Specifically: a. If CPU A is selected, CPU A can only provide one PCIE port, and then connect with all PCIE ports of CPU A, the specific connection. The method is the same as the connection technology of the existing MUX chip. b. If CPU B is selected, CPU B can provide two PCIE ports, then connect with one PCIE port of CPU B, and disconnect another PCIE port. The specific connection method is The connection technology of the existing MUX chip is the same.
本发明实施例， 通过获取 CPU的标识信号， 识别 CPU的型号， 进而获取 CPU提供的 PCIE端口信息， 控制 MUX芯片进行 CPU选 通并与选通的 CPU的 PCIE端口进行连接， 从而实现了 EP设备可以 与不同 CPU的 PCIE端口的自适应和连接， 即实现了 PCIE端口的灵 活配置。  In the embodiment of the present invention, by acquiring the identification signal of the CPU, identifying the model of the CPU, obtaining the PCIE port information provided by the CPU, controlling the MUX chip to perform CPU strobe and connecting with the PCIE port of the strobed CPU, thereby implementing the EP device. It can be adaptively connected with PCIE ports of different CPUs, that is, flexible configuration of PCIE ports.
如图 2所示为本发明实施例提供的配置 PCIE端口装置的结构图， 为了便于说明， 仅示出与本发明实施例相关的部分， 包括：  FIG. 2 is a structural diagram of a device for configuring a PCIE port according to an embodiment of the present invention. For ease of description, only parts related to the embodiment of the present invention are shown, including:
接收单元 21 , 用于接收中央处理器 CPU发送的标识信号。  The receiving unit 21 is configured to receive an identification signal sent by the central processing unit CPU.
在本发明实施例中， 接收单元 21与 CPU都连接在背板上， 通过 背板可以实现 EP设备与 CPU的数据交互。 通过背板， EP设备接收 CPU发送的标识信号。 所述标识信号中包含 CPU型号的信息， 可以 是标准的硬件信号， 也可以是使用 I2C等软件实现的软件信号。 In the embodiment of the present invention, the receiving unit 21 and the CPU are both connected to the backboard, and The backplane can implement data interaction between the EP device and the CPU. Through the backplane, the EP device receives the identification signal sent by the CPU. The identification signal includes information of a CPU model, which may be a standard hardware signal, or may be a software signal implemented by using software such as I2C.
PCIE端口信息获取单元 22,用于根据所述接收单元 21接收的标 识信号， 获取 CPU提供的 PCIE端口信息。  The PCIE port information obtaining unit 22 is configured to obtain PCIE port information provided by the CPU according to the identification signal received by the receiving unit 21.
在本发明实施例中， PCIE端口信息获取单元 22在接收单元 21 接收到 CPU发送的标识信号之后， 对所述标识信号进行分析识别， 识别出该标识信号对应的 CPU型号，进而获取所述 CPU型号对应的 PCIE端口信息， 所述 PCIE端口信息包括： 可以提供的端口数量、每 个端口的类型（ PCIE1.0、 PCIE2.0等 )、每个端口提供的通道数量等。  In the embodiment of the present invention, after the receiving unit 21 receives the identification signal sent by the CPU, the PCIE port information acquiring unit 22 analyzes and identifies the identification signal, identifies the CPU model corresponding to the identification signal, and acquires the CPU. The PCIE port information corresponding to the model, the PCIE port information includes: the number of ports that can be provided, the type of each port (PCIE1.0, PCIE2.0, etc.), and the number of channels provided by each port.
选通单元 23 , 用于控制多路选择器 MUX芯片根据所述 PCIE端 口信息获取单元 22获取的 PCIE端口信息进行 CPU选通。  The strobe unit 23 is configured to control the multiplexer. The MUX chip performs CPU strobe according to the PCIE port information acquired by the PCIE port information acquiring unit 22.
在本发明实施例中， 一个背板有可能连接多个 CPU, 此时选通单 元 23控制 MUX芯片根据所述 PCIE端口信息选择合适的 CPU, 即 进行 CPU选通， 所述 CPU选通具体为： 优先选择通道数量匹配的端 口对应的 CPU; 当提供的通道数量都匹配时选择提供 PCIE端口数量 多的 CPU; 当提供的通道数量都小于需要的通道数量时， 优先选择 通道数量多的 CPU; 当提供的通道数量都大于需要的通道数量时， 优先选择通道数量少的 CPU。  In the embodiment of the present invention, a backplane may be connected to a plurality of CPUs. In this case, the gate unit 23 controls the MUX chip to select a suitable CPU according to the PCIE port information, that is, performs CPU strobe, and the CPU strobe is specifically : The CPU corresponding to the port with the matching number of channels is preferentially selected; when the number of channels provided is matched, the number of CPUs with a large number of PCIE ports is selected; when the number of channels provided is less than the number of channels required, the CPU with a large number of channels is preferentially selected; When the number of channels provided is greater than the number of channels required, the number of CPUs with a small number of channels is preferred.
连接单元 24, 用于控制 MUX芯片根据所述选通单元 23选通的 结果进行 PCIE端口连接。  The connecting unit 24 is configured to control the MUX chip to perform a PCIE port connection according to the result of the gating of the gating unit 23.
在本发明实施例中， 连接单元 24控制 MUX芯片根据所述选通 单元 23选通的结果进行 PCIE端口连接，所述连接单元 24具体包括： 单个端口连接子单元 241 , 用于当 CPU只提供一个 PCIE端口时， 控 制 MUX芯片连通所述 PCIE端口； 多个端口连接子单元 242, 用于 当 CPU提供了多个 PCIE端口时，控制 MUX芯片连通其中一个 PCIE 端口， 断开与其他 PCIE 端口的连通， 具体的连通方法使用现有的 MUX芯片技术， 此处不再赘述。 In the embodiment of the present invention, the connection unit 24 controls the MUX chip to perform a PCIE port connection according to the result of the gating unit 23 gating. The connection unit 24 specifically includes: a single port connection subunit 241, configured to be provided only when the CPU provides a PCIE port, the control MUX chip is connected to the PCIE port; and the plurality of port connection sub-units 242 are used When the CPU provides multiple PCIE ports, the MUX chip is connected to one of the PCIE ports, and the other PCIE ports are disconnected. The specific connection method uses the existing MUX chip technology, and details are not described herein.
本发明实施例， 通过获取 CPU的标识信号， 识别 CPU的型号， 进而获取 CPU提供的 PCIE端口信息， 控制 MUX芯片进行 CPU选 通并与选通的 CPU的 PCIE端口进行连接， 从而实现了 EP设备可以 与不同 CPU的 PCIE端口的自适应和连接， 即实现了 PCIE端口的灵 活配置。  In the embodiment of the present invention, by acquiring the identification signal of the CPU, identifying the model of the CPU, obtaining the PCIE port information provided by the CPU, controlling the MUX chip to perform CPU strobe and connecting with the PCIE port of the strobed CPU, thereby implementing the EP device. It can be adaptively connected with PCIE ports of different CPUs, that is, flexible configuration of PCIE ports.
如图 3所示为本发明实施例提供的配置 PCIE端口设备的结构图， 所述设备包括输入单元 31、 处理器 32、 输出单元 33, 所述处理器 32 执行以下步骤：  FIG. 3 is a structural diagram of a device for configuring a PCIE port according to an embodiment of the present invention. The device includes an input unit 31, a processor 32, and an output unit 33, and the processor 32 performs the following steps:
接收中央处理器 CPU发送的标识信号。  Receives an identification signal sent by the CPU of the central processing unit.
在本发明实施例中， EP设备与 CPU都连接在背板上， 通过背板 可以实现 EP设备与 CPU的数据交互。 通过背板， EP设备接收 CPU 发送的标识信号。 所述标识信号中包含指示 CPU型号的信息， 可以 是标准的硬件信号， 也可以是使用 I2C等软件实现的软件信号。  In the embodiment of the present invention, the EP device and the CPU are both connected to the backplane, and the data interaction between the EP device and the CPU can be implemented through the backplane. Through the backplane, the EP device receives the identification signal sent by the CPU. The identification signal includes information indicating a CPU model, and may be a standard hardware signal or a software signal implemented by using software such as I2C.
根据所述接收的标识信号， 获取 CPU提供的 PCIE端口信息。 在本发明实施例中，配置 PCIE端口设备在接收到 CPU发送的标 识信号之后， 对所述标识信号进行分析识别， 识别出该标识信号对应 的 CPU型号， 进而获取所述 CPU型号对应的 PCIE端口信息， 所述 PCIE 端口信息包括： 可以提供的端口数量、 每个端口的类型 ( PCIE1.0, PCIE2.0等） 、 每个端口提供的通道数量等。  Obtaining PCIE port information provided by the CPU according to the received identification signal. In the embodiment of the present invention, after receiving the identification signal sent by the CPU, the PCIE port device analyzes and identifies the identification signal, identifies the CPU model corresponding to the identification signal, and obtains the PCIE port corresponding to the CPU model. Information, the PCIE port information includes: the number of ports that can be provided, the type of each port (PCIE1.0, PCIE2.0, etc.), the number of channels provided by each port, and so on.
控制多路选择器 MUX芯片根据所述获取的 PCIE端口信息进行 CPU选通。  Controlling the multiplexer The MUX chip performs CPU strobe according to the obtained PCIE port information.
在本发明实施例中， 一个背板上有可能连接多个 CPU, 此时 EP 设备控制 MUX芯片根据所述 PCIE端口信息选择合适的 CPU, 即进 行 CPU选通， 所述 CPU选通具体为： 优先选择通道数量匹配的端口 对应的 CPU; 当提供的通道数量都匹配时选择端口数量多的 CPU; 当提供的通道数量都小于需要的通道数量时，优先选择通道数量多的In the embodiment of the present invention, it is possible to connect multiple CPUs on one backplane, and EP at this time The device control MUX chip selects a suitable CPU according to the PCIE port information, that is, performs CPU strobe, and the CPU strobe is specifically: preferentially selecting a CPU corresponding to a port whose number of channels matches; selecting a port when the number of channels provided is matched A large number of CPUs; when the number of channels provided is less than the number of channels required, the number of channels is preferred.
CPU; 当提供的通道数量都大于需要的通道数量时， 优先选择通道数 量少的 CPU。 CPU; When the number of channels provided is greater than the number of channels required, the CPU with a small number of channels is preferred.
控制 MUX芯片根据所述选通的结果进行 PCIE端口连接。  The control MUX chip performs a PCIE port connection according to the result of the gating.
在本发明实施例中， EP设备在选择到合适的 CPU后 （即选通有 结果后） ， 控制 MUX芯片进行与 PCIE端口的连接， 具体的： 如果 CPU只提供一个 PCIE端口，则 EP设备控制 MUX芯片连通所述 PCIE 端口； 如果 CPU提供了多个 PCIE端口， 则 EP设备控制 MUX芯片 连通其中一个 PCIE端口， 断开与其他 PCIE端口的连通， 具体的连 通方法使用现有的 MUX芯片技术， 此处不再赘述。  In the embodiment of the present invention, after selecting the appropriate CPU (that is, after the strobe has a result), the EP device controls the MUX chip to perform connection with the PCIE port. Specifically: if the CPU only provides one PCIE port, the EP device controls The MUX chip is connected to the PCIE port. If the CPU provides multiple PCIE ports, the EP device controls the MUX chip to connect to one of the PCIE ports, and disconnects from the other PCIE ports. The specific connection method uses the existing MUX chip technology. I will not repeat them here.
本发明实施例， 通过获取 CPU的标识信号， 识别 CPU的型号， 进而获取 CPU提供的 PCIE端口信息， 控制 MUX芯片进行 CPU选 通并与选通的 CPU的 PCIE端口进行连接， 从而实现了 EP设备可以 与不同 CPU的 PCIE端口的自适应和连接， 即实现了 PCIE端口的灵 活配置。  In the embodiment of the present invention, by acquiring the identification signal of the CPU, identifying the model of the CPU, obtaining the PCIE port information provided by the CPU, controlling the MUX chip to perform CPU strobe and connecting with the PCIE port of the strobed CPU, thereby implementing the EP device. It can be adaptively connected with PCIE ports of different CPUs, that is, flexible configuration of PCIE ports.
以上所述仅为本发明的较佳实施例而已， 并不用以限制本发明， 凡在本发明的精神和原则之内所作的任何修改、 等同替换和改进等， 均应包含在本发明的保护范围之内。  The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.
值得注意的是， 上述用户设备和基站实施例中， 所包括的各个单 元只是按照功能逻辑进行划分的，但并不局限于上述的划分， 只要能 够实现相应的功能即可； 另外， 各功能单元的具体名称也只是为了便 于相互区分， 并不用于限制本发明的保护范围。 另外，本领域普通技术人员可以理解实现上述各方法实施例中的 全部或部分步骤是可以通过程序来指令相关的硬件完成，相应的程序 可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是 只读存储器， 磁盘或光盘等。 It should be noted that, in the foregoing user equipment and base station embodiments, each unit included is only divided according to functional logic, but is not limited to the foregoing division, as long as the corresponding function can be implemented; The specific names are also for convenience of distinguishing from each other and are not intended to limit the scope of the present invention. In addition, those skilled in the art can understand that all or part of the steps in implementing the foregoing method embodiments may be performed by a program to instruct related hardware, and the corresponding program may be stored in a computer readable storage medium. The storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
以上所述，仅为本发明较佳的具体实施方式， 但本发明的保护范 围并不局限于此，任何熟悉本技术领域的技术人员在本发明实施例揭 露的技术范围内， 可轻易想到的变化或替换， 都应涵盖在本发明的保 护范围之内。 因此， 本发明的保护范围应该以权利要求的保护范围为  The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of it within the technical scope disclosed by the embodiments of the present invention. Variations or substitutions are intended to be covered by the scope of the invention. Therefore, the scope of protection of the present invention should be protected by the scope of the claims.

Claims

权 利 要 求 Rights request
1、 一种配置高速外设组件互连 PCIE端口的方法， 其特征在于， 所述方法包括以下步骤： A method for configuring a high-speed peripheral component to interconnect a PCIE port, the method comprising the steps of:
接收中央处理器 CPU发送的标识信号， 所述标识信号包含用来 指明所述 CPU的型号的信息；  Receiving an identification signal sent by the central processing unit CPU, where the identification signal includes information indicating a model number of the CPU;
根据接收的所述标识信号，获取所述 CPU的 PCIE端口信息，所 述 PCIE端口信息包括 PCIE端口数量、 PCIE端口类型、 PCIE端口 通道数中的一种或几种；  Obtaining PCIE port information of the CPU according to the received identification signal, where the PCIE port information includes one or more of a number of PCIE ports, a PCIE port type, and a number of PCIE port channels;
控制多路选择器 MUX芯片根据所述 PCIE端口信息进行 CPU选 通；  Controlling the multiplexer The MUX chip performs CPU strobing according to the PCIE port information;
2、 如权利要求 1所述的方法， 其特征在于， 所述根据接收的所 述标识信号， 获取所述 CPU的 PCIE端口信息， 具体为： The method according to claim 1, wherein the acquiring the PCIE port information of the CPU according to the received identification signal is specifically:
对所述标识信号进行分析， 获取所述 CPU的型号， 根据获取的 所述 CPU的型号获取所述 CPU的 PCIE端口信息。  The identification signal is analyzed, the model of the CPU is obtained, and the PCIE port information of the CPU is obtained according to the acquired model of the CPU.
3、 如权利要求 1所述的方法， 其特征在于， 所述控制多路选择 器 MUX芯片根据所述 PCIE端口信息进行 CPU选通， 具体为：  The method of claim 1, wherein the control multiplexer MUX chip performs CPU strobe according to the PCIE port information, specifically:
优先选择提供的通道数量匹配的 CPU;  Prefer the number of channels provided by the matching CPU;
当 CPU提供的通道数量都匹配时选择提供 PCIE端口数量多的 When the number of channels provided by the CPU matches, choose to provide a large number of PCIE ports.
CPU; CPU;
当 CPU提供的通道数量都小于需要的通道数量时， 优先选通通 道数量多的 CPU;  When the number of channels provided by the CPU is less than the required number of channels, the CPU with a larger number of gates is preferentially strobed;
当 CPU提供的通道数量都大于需要的通道数量时， 优先选通通 道数量少的 CPU。 When the number of channels provided by the CPU is greater than the number of channels required, the number of CPUs with a small number of channels is preferentially gated.
4、 如权利要求 1所述的方法， 其特征在于， 所述控制 MUX芯 片根据所述选通的结果进行 PCIE端口连接的步骤具体为： The method according to claim 1, wherein the step of controlling the MUX chip to perform PCIE port connection according to the result of the gating is specifically:
如果所述选通的 CPU只提供一个 PCIE端口， 则控制所述 MUX 芯片连通所述选通的 CPU的所述 PCIE端口； 或者，  If the strobed CPU only provides one PCIE port, controlling the MUX chip to connect to the PCIE port of the strobed CPU; or
如果所述选通的 CPU提供了多个 PCIE端口， 则控制所述 MUX 芯片连通所述选通的 CPU的所述多个 PCIE端中的一个 PCIE端口， 断开与其他 PCIE端口的连通。  If the strobed CPU provides a plurality of PCIE ports, controlling the MUX chip to communicate with one of the plurality of PCIE ports of the strobed CPU, and disconnecting from the other PCIE ports.
5、 一种配置高速外设组件互连 PCIE端口的装置， 其特征在于， 所述装置包括：  5. A device for configuring a high speed peripheral component to interconnect a PCIE port, the device comprising:
接收单元， 用于接收中央处理器 CPU发送的标识信号， 所述标 识信号包含用来指明所述 CPU的型号的信息；  a receiving unit, configured to receive an identification signal sent by a central processing unit CPU, where the identification signal includes information indicating a model number of the CPU;
PCIE端口信息获取单元， 用于根据所述接收单元接收的标识信 号，获取所述 CPU的 PCIE端口信息，所述 PCIE端口信息包括 PCIE 端口数量、 PCIE端口类型、 PCIE端口通道数中的一种或几种；  a PCIE port information acquiring unit, configured to acquire PCIE port information of the CPU according to the identifier signal received by the receiving unit, where the PCIE port information includes one of a PCIE port number, a PCIE port type, and a PCIE port channel number. Several
选通单元， 用于控制多路选择器 MUX芯片根据所述 PCIE端口 信息获取单元获取的 PCIE端口信息进行 CPU选通；  a strobe unit, configured to control the multiplexer, and the MUX chip performs CPU strobing according to the PCIE port information acquired by the PCIE port information acquiring unit;
连接单元，用于控制所述 MUX芯片根据所述选通单元选通的结 果进行 PCIE端口连接。  And a connecting unit, configured to control the MUX chip to perform a PCIE port connection according to the result of the gating unit gating.
6、 如权利要求 5所述的装置， 其特征在于， 通过对所述标识信 号进行分析， 获取所述 CPU的型号， 根据获取的所述 CPU的型号获 取所述 CPU的 PCIE端口信息。  The device according to claim 5, wherein the model number of the CPU is obtained by analyzing the identification signal, and the PCIE port information of the CPU is obtained according to the obtained model of the CPU.
7、 如权利要求 5所述的装置， 其特征在于， 所述选通具体为： 优先选择提供的通道数量匹配的 CPU;  The device according to claim 5, wherein the gating is specifically: preferentially selecting a CPU that provides a matching number of channels;
当 CPU提供的通道数量都匹配时选择提供 PCIE端口数量多的 When the number of channels provided by the CPU matches, choose to provide a large number of PCIE ports.
CPU; 当 CPU提供的通道数量都小于需要的通道数量时， 优先选通通 道数量多的 CPU; CPU; When the number of channels provided by the CPU is less than the required number of channels, the number of CPUs with a large number of channels is preferentially gated;
当 CPU提供的通道数量都大于需要的通道数量时， 优先选通通 道数量少的 CPU。  When the number of channels provided by the CPU is greater than the number of channels required, the CPU with a small number of gates is preferentially strobed.
8、 如权利要求 5所述的装置， 其特征在于， 所述连接单元具体 包括：  The device according to claim 5, wherein the connecting unit specifically includes:
单个端口连接子单元，用于当所述选通的 CPU只提供一个 PCIE 端口时，控制所述 MUX芯片连通所述选通的 CPU的所述 PCIE端口； 多个端口连接子单元，用于当所述选通的 CPU提供了多个 PCIE 端口时， 控制所述 MUX芯片连通所述选通的 CPU的所述多个 PCIE 端中的一个 PCIE端口， 断开与其他 PCIE端口的连通。  a single port connection subunit, configured to control the MUX chip to communicate with the PCIE port of the strobed CPU when the strobed CPU only provides one PCIE port; and multiple port connection subunits for when When the strobed CPU provides a plurality of PCIE ports, the MUX chip is controlled to communicate with one of the plurality of PCIE ports of the strobed CPU, and the communication with other PCIE ports is disconnected.
9、 一种配置高速外设组件互连 PCIE端口的设备， 其特征在于， 所述设备包括输入装置、 处理器、 输出装置， 所述处理器执行以下步 骤：  9. An apparatus for configuring a high speed peripheral component to interconnect a PCIE port, the device comprising an input device, a processor, and an output device, the processor performing the following steps:
接收中央处理器 CPU发送的标识信号， 所述标识信息包含用来 指明所述 CPU的型号的信息；  Receiving an identification signal sent by the central processing unit CPU, where the identification information includes information indicating a model number of the CPU;
根据接收的所述标识信号，获取所述 CPU的 PCIE端口信息，所 述 PCIE端口信息包括 PCIE端口数量、 PCIE端口类型、 PCIE端口 通道数中的一种或几种；  Obtaining PCIE port information of the CPU according to the received identification signal, where the PCIE port information includes one or more of a number of PCIE ports, a PCIE port type, and a number of PCIE port channels;
控制多路选择器 MUX芯片根据所述 PCIE端口信息进行 CPU选 通；  Controlling the multiplexer The MUX chip performs CPU strobing according to the PCIE port information;
10、 如权利要求 9所述的设备， 其特征在于， 所述根据接收的所 述标识信号， 获取所述 CPU的 PCIE端口信息， 具体为： The device according to claim 9, wherein the acquiring the PCIE port information of the CPU according to the received identification signal is specifically:
对所述标识信号进行分析， 获取所述 CPU的型号， 根据获取的 所述 CPU的型号获取所述 CPU的 PCIE端口信息。 Performing analysis on the identification signal to obtain a model number of the CPU, according to the acquired The model of the CPU acquires PCIE port information of the CPU.
11、 如权利要求 9所述的设备， 其特征在于， 所述控制多路选择 MUX芯片根据所述获取的 PCIE端口信息进行 CPU选通的步骤， 具 体为：  The device according to claim 9, wherein the controlling the multi-channel selection MUX chip performs a CPU strobe according to the acquired PCIE port information, which is specifically:
优先选择提供的通道数量匹配的 CPU;  Prefer the number of channels provided by the matching CPU;
当 CPU提供的通道数量都匹配时选择提供 PCIE端口数量多的 When the number of channels provided by the CPU matches, choose to provide a large number of PCIE ports.
CPU; CPU;
当 CPU提供的通道数量都小于需要的通道数量时， 优先选通通 道数量多的 CPU;  When the number of channels provided by the CPU is less than the required number of channels, the CPU with a larger number of gates is preferentially strobed;
当 CPU提供的通道数量都大于需要的通道数量时， 优先选通通 道数量少的 CPU。  When the number of channels provided by the CPU is greater than the number of channels required, the CPU with a small number of gates is preferentially strobed.
12、 如权利要求 9所述的设备， 其特征在于， 所述控制 MUX芯 片根据所述选通的结果进行 PCIE端口连接的步骤具体为：  The device according to claim 9, wherein the step of controlling the MUX chip to perform PCIE port connection according to the result of the gating is specifically:
如果所述选通的 CPU只提供一个 PCIE端口， 则控制所述 MUX 芯片连通所述选通的 CPU的所述 PCIE端口； 或者，  If the strobed CPU only provides one PCIE port, controlling the MUX chip to connect to the PCIE port of the strobed CPU; or
如果所述选通的 CPU提供了多个 PCIE端口， 则控制所述 MUX 芯片连通所述选通的 CPU的所述多个 PCIE端中的一个 PCIE端口， 断开与其他 PCIE端口的连通。  If the strobed CPU provides a plurality of PCIE ports, controlling the MUX chip to communicate with one of the plurality of PCIE ports of the strobed CPU, and disconnecting from the other PCIE ports.
PCT/CN2012/081144 2012-09-07 2012-09-07 Method, device and equipment for pcie port configuration WO2014036725A1 (en)

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