WO2013159464A1

WO2013159464A1 - Multiple core processor clock control device and control method

Info

Publication number: WO2013159464A1
Application number: PCT/CN2012/078946
Authority: WO
Inventors: 毕敏
Original assignee: 中兴通讯股份有限公司
Priority date: 2012-04-26
Filing date: 2012-07-20
Publication date: 2013-10-31
Also published as: CN103376877B; CN103376877A

Abstract

A multi-core processor clock control device and control method. The device comprises an N-number of core processors. The device also comprises a clock management and control module. The clock management and control module comprises an N-number of core clock control units, where the ith core clock control unit is connected to the ith core processor, and where i is an integer greater than zero. The clock management and control module also comprises a clock monitoring unit connected to all of the N-number of core clock control units. The core clock control units are set to receive from the core processor connected thereto a core clock shutdown request and to notify same to the clock monitoring unit. The clock monitoring unit is set to receive from the core clock control units the core clock shutdown request, and to shut down a high-frequency crystal oscillator clock when the core clock shutdown request is determined to have come from the last core processor that is in a working state among the N-number of core processors. The present solution is capable of conserving the power consumption of a terminal by means of controlling core processor-related clocks.

Description

Multi-core processor clock control device and control method

Technical field

The present invention relates to the field of mobile communication technologies, and in particular, to a multi-core processor clock control device and a control method.

Background technique

With the continuous development of terminal hardware technology and the continuous improvement of chip integration, many high-end mobile phone baseband processing chips are implemented by multiple core processor architectures, such as two ARM (Advanced RISC Machines) and two numbers. The architecture of the Signal Processor (Digital Signal Processer, DSP). One of the ARM and one DSP is used to process the signaling and data related to mobile communications, while the other ARM and DSP are used to implement software and audio and video codecs.

The multi-core architecture solves the problem of insufficient resources on a single-core processor, but it also increases the power consumption of the chip. It is well known that the core processor in the entire terminal chip is the largest power consuming component. When the power consumption of the core processor is poorly controlled, the terminal battery life will be affected, and the user experience will become poor.

For multi-core systems, each core processor has different tasks and different working hours. You can use this difference for power control management. One of the most direct ways is to use a power supply that does not work. Broken, so the power consumption of the core will be zero, but in practical applications, if the nuclear power is cut off, all information on the core processor will be lost if it is not specially processed, and it needs to be initialized or used again. It is to restore this information and also need to reload the software running on the core, so it is necessary to weigh the power-off operation and restore the power consumption relationship of the operation, otherwise it may not be worth the loss. Therefore, in multi-core processors, the most common method is to break the clock that does not use the core processor. In this way, although the power consumption of the non-working core does not drop directly to zero, most of the dynamic power consumption is no longer There is no clock drive signal flipping and only the chip's leakage power is left. This part of the power consumption is guaranteed in the chip design to meet the minimum power consumption of the process design.

It should be noted that for a multi-core chip system, the working basic clock is provided by an external crystal oscillator; when multiple cores are not working, the crystal oscillator that provides the clock for the working state of the chip can be turned off to achieve further power saving of the terminal; For the opening of the crystal, only one core needs to work. To turn on the clock of the external crystal and the working core, the clocks of other cores should still be off. The following takes a dual-core system as an example to illustrate how to implement chip core clock management in an existing software solution. As shown in Figure 1, the basic terminal communication function is implemented in a dual-core (ARM+DSP) system. When the core processor X is not working, the state of the core processor X is notified to the core processor Y, and the core processor Y operates to close the clock of the core processor X, and when the core processor Y needs to be turned into an inactive state When the SPI port is written to the register, the external crystal is turned off. This mode of operation adds extra power consumption. With the increase of the number of core processors, the operation mode of the software makes the inter-core communication mechanism complicated, and the chip bus design is complicated. Summary of the invention

Embodiments of the present invention provide a multi-core processor clock control apparatus and method, which solves the problem of large power consumption caused by inaccurate clock control methods.

In order to solve the above technical problem, an embodiment of the present invention provides a multi-core processor clock control apparatus, including N core processors, where N is an integer greater than 1, the device further includes a clock management and control module; And the control module includes N core clock control units, the i-th core clock control unit is connected to the i-th core processor, i is an integer greater than zero; the clock management and control module further includes the N core clocks a clock monitoring unit to which the control units are connected;

The core clock control unit is configured to receive a core clock shutdown request of a core processor connected thereto and notify the clock monitoring unit;

The clock monitoring unit is configured to: receive a core clock shutdown request from the core clock control unit, and determine that the received core clock shutdown request is from a core processor of the last one of the N core processors that is in a working state, Turn off the high frequency crystal clock.

The core clock control unit is further configured to: after receiving a core clock shutdown request of the core processor connected thereto and notifying the clock monitoring unit, shutting down the core processor of the core processor after two clock cycles delay clock.

The clock management and control module further includes an interrupt monitoring unit connected to the clock monitoring unit;

The interrupt monitoring unit is configured to detect a core processor wake-up interrupt signal and detect the core Notifying the clock monitoring unit after the processor wakes up the interrupt signal;

The clock monitoring unit is further configured to: after receiving the core processor wake-up interrupt signal, determine that the high-frequency crystal oscillator is in a closed state, turn on the high-frequency crystal oscillator, and determine a target core processor of the core processor wake-up interrupt signal, Transmitting the core processor wake-up interrupt signal to a core clock control unit of the target core processor;

The core clock control unit is further configured to, after receiving the core processor wake-up interrupt signal, turn on the core-gated clock of the core processor connected to the core clock control unit.

The clock monitoring unit is further configured to: after receiving the core processor wake-up interrupt signal, determine that the high-frequency crystal oscillator is in an on state, determine the target processor of the core processor wake-up interrupt signal, and wake up the core processor A signal is sent to the core clock control unit of the target core processor.

The clock monitoring unit is further configured to turn on the low frequency crystal oscillator clock after turning off the high frequency crystal oscillator clock. The core processor is configured to: upon no task processing, or to determine a request to close the task of the pending task.

An embodiment of the present invention further provides a multi-core processor clock control method, including: a core clock control unit receives a core clock shutdown request of a core processor connected thereto and notifies a clock monitoring unit, wherein the clock monitoring unit is from the core The clock control unit receives the core clock shutdown request, and determines that the core clock shutdown request is from the last core processor of the N core processors, and turns off the high frequency crystal oscillator clock.

The method further includes: after receiving the core clock shutdown request of the core processor connected thereto and notifying the clock monitoring unit, the core clock control unit turns off the core processor gate of the core processor after two clock cycles delay Control the clock.

The method further includes: the interrupt monitoring unit detecting the core processor wake-up interrupt signal, and notifying the clock monitoring unit after detecting the core processor wake-up interrupt signal;

After receiving the core processor wake-up interrupt signal, the clock monitoring unit determines that the high-frequency crystal oscillator is in an off state, turns on the high-frequency crystal oscillator, and determines a target core processor that wakes up the interrupt signal of the core processor, and the core is a processor wake-up interrupt signal is sent to a core clock control unit of the target core processor; After receiving the core processor wake-up interrupt signal, the core clock control unit of the target core processor turns on the core-gated clock of the target core processor.

The method further includes: after the clock monitoring unit receives the core processor wake-up interrupt signal, determining that the high-frequency crystal oscillator is in an on state, determining a target core processor of the core processor wake-up interrupt signal, and the core processor The wake-up interrupt signal is sent to the core clock control unit of the target core processor.

This solution can save power consumption of the terminal by controlling the clock related to the core processor. BRIEF abstract

1 is a clock management structure diagram of a dual core system in the related art;

2 is a structural diagram of a multi-core processor clock control apparatus in an embodiment of the present invention;

3 is a schematic diagram of clock management failure caused by high frequency clock to low frequency clock conversion; FIG. 4 is a timing diagram of a crystal clock when the clock is off in the embodiment of the present invention;

Fig. 5 is a timing chart showing the state of the crystal oscillator when the clock is turned on in the embodiment of the present invention. Preferred embodiment of the invention

As shown in FIG. 2, the multi-core processor clock control apparatus includes N core processors, N is an integer greater than 1, and further includes a clock management and control module, and the clock management and control module includes N core clock control units, the ith The core clock control unit is connected to the i-th core processor, i is an integer greater than zero, that is, each core processor is provided with a set of independent nuclear clock control units, and the independent nuclear clock control units can receive the corresponding core processor. The transmitted signal is controlled by an independent core clock according to the signal, for example: receiving a core clock off request of the core processor connected thereto and notifying the clock monitoring unit.

The core clock monitoring unit and the core processor can be connected to each other through a hard wire, and only a simple signal flip is required to indicate the clock off signal. When the preset time threshold is greater than the preset time threshold, a nuclear clock shutdown request is sent to the nuclear clock control unit connected thereto.

The clock management and control module further includes a clock monitor connected to the N core clock control units a measurement unit, the clock monitoring unit is configured to receive a core clock shutdown request from the core clock control unit, and determine that the core clock shutdown request is from a last core processor in the working state , Turn off the high-frequency crystal clock. That is, when the core processor is in a non-operating state, the high frequency crystal oscillator clock is turned off. The clock monitoring unit can save the state of each core processor.

The apparatus also includes an interrupt monitoring unit coupled to the clock monitoring unit.

The interrupt monitoring unit is configured to detect a core processor wake-up interrupt signal, and notify the clock monitoring unit after detecting the core processor wake-up interrupt signal; the clock monitoring unit is further configured to receive a core processor wake-up interrupt After the signal is determined, when the high-frequency crystal oscillator is in the off state, the high-frequency crystal oscillator is turned on, the target core processor that determines the core processor wake-up interrupt signal is sent, and the core processor wake-up interrupt signal is sent to the target core processing. The core clock control unit. Of course, after receiving the core processor wake-up interrupt signal, the interrupt monitoring unit determines that the high-frequency crystal oscillator is in an on state, directly determines the target core processor of the core processor wake-up interrupt signal, and wakes up the core processor. A signal is sent to the core clock control unit of the target core processor.

Interrupt signals can be keyboard interrupts, timer interrupts, plug-in interrupts for some peripheral devices, USB interrupts, and more.

The core clock control unit is further configured to, upon receiving the core processor wake-up interrupt signal, turn on the core-gated clock of the core processor connected thereto.

The wake-up interrupts of the clock management and control module and the multi-core processor are hooked. When the wake-up interrupt arrives, the external high-frequency crystal oscillator is opened by the interrupt flip logic, and the interrupt core logic is used to identify the interrupted home core information. Turn on the clock for the corresponding core processor. These processes are implemented by flip logic on the hardware signal line and do not require an additional clock.

The core clock control unit is further configured to receive a core clock off request of the core processor connected thereto and notify the clock monitoring unit, and then turn off the core processor gate clock of the core processor after two clock cycles delay .

The reasons for setting this function are detailed below:

The control between the clock management and control module and the external crystal oscillator is implemented by hardware logic and is physically connected by hard wires, making the clock off control more precise and fast. Clock management and control module connection The external crystal oscillator has a low-frequency crystal oscillator (for example, 32khz) in addition to the high-frequency crystal oscillator. The high-frequency crystal oscillator clock and the low-frequency crystal oscillator clock work differently. When the high-frequency crystal oscillator clock is turned on, the module always uses the high-frequency clock to work. The clock monitoring unit turns off the high-frequency crystal oscillator clock and turns on the low-frequency crystal oscillator clock. The clock switching is to meet the design. demand. If only the high-frequency crystal oscillator clock is used, when the last-closed core processor of the multi-core system sends a clock-off signal to the clock monitoring unit through the core clock control unit, the clock monitoring unit judges that the condition of turning off the high-frequency crystal oscillator clock is turned off and immediately turns off the external The crystal oscillator, as shown in Figure 3, the closing gate of the core clock of the last closed core processor (such as the core processor X) is actually ineffective. When the subsequent high-frequency crystal oscillator is turned on, the above-mentioned core processor The clock must be turned on, resulting in an increase in overall processor power consumption. Therefore, in this solution, after setting the core clock control unit to receive the core clock shutdown request of the core processor connected thereto and notifying the clock monitoring unit, the core processor gated clock of the core processor is turned off after two clock cycles delay. In order to enable the signal to be transmitted.

As shown in FIG. 4, the clock control circuit and the device clock off timing diagram, the core processor X requests to turn off the core clock, and the send request signal is captured by the clock monitoring unit and judges that the multi-core processor does not need the high-frequency crystal clock, and immediately closes The high-frequency crystal clock is broken, and the core clock needs to be delayed for two clock cycles after the request signal is issued, so that the shutdown clock of the core clock is switched from bus clock 1 to bus clock 2 (32k low-frequency clock). Thus, the gated clock signal of the core processor X is finally turned off. As shown in FIG. 5, the interrupt signal belonging to the core processor Y is captured by the interrupt monitoring unit in the clock control circuit, and it is determined that the external high-frequency clock crystal needs to be turned on, and the clock gating signal of the core processor Y is turned on. The core processor X is still inactive and the clock gating is off. Thereby, the above-mentioned defects caused only by the high-frequency crystal oscillator are solved.

The multi-core processor clock control method in the present solution includes: the core clock control unit receives a core clock shutdown request of the core processor connected thereto and notifies the clock monitoring unit, and the clock monitoring unit receives the core clock off from the core clock control unit. The request is made to close the high frequency crystal oscillator clock when the core clock shutdown request is from the last core processor of the N core processors.

After receiving the core clock shutdown request of the core processor connected thereto and notifying the clock monitoring unit, the core clock control unit executes two branches, the first branch: sends the core clock shutdown request to The clock monitoring unit, the trigger clock monitoring unit determines whether the core clock shutdown request is a nuclear clock shutdown request issued by the last core processor in operation, thereby triggering the operation of turning off the high frequency crystal oscillator; the second branch delays two clock cycles The core processor gated clock of the core processor is then turned off. If the external crystal oscillator is turned off, the clock sample signal is replaced with a low frequency clock signal to ensure that the clock gating of the last core processor in operation is valid.

The flow of the core processor clock is: the interrupt monitoring unit detects the core processor wake-up interrupt signal, and notifies the clock monitoring unit after detecting the core processor wake-up interrupt signal; the clock monitoring unit receives the core processor wake-up After the signal is interrupted, when the high-frequency crystal oscillator is turned off, the high-frequency crystal oscillator is turned on (if the high-frequency crystal oscillator is turned on, the following process is directly executed), and the target core processor that determines the core processor wake-up interrupt signal is determined. And sending the core processor wake-up interrupt signal to the core clock control unit of the target core processor; after receiving the core processor wake-up interrupt signal, the target core clock control unit turns on the core-gated clock of the target core processor.

It should be noted that the features in the embodiments and the embodiments of the present application may be arbitrarily combined with each other without conflict.

There are a variety of other embodiments that can be made by those skilled in the art without departing from the spirit and scope of the invention. And modifications are intended to fall within the scope of the appended claims.

One of ordinary skill in the art will appreciate that all or a portion of the above steps may be accomplished by a program instructing the associated hardware, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps of the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the above embodiment may be implemented in the form of hardware or in the form of a software function module. This application is not limited to any specific form of combination of hardware and software.

Industrial Applicability The embodiments of the present invention save power consumption of the terminal by controlling the clock associated with the core processor.

Claims

Claim

A multi-core processor clock control device, comprising N core processors, wherein N is an integer greater than 1, wherein the device further comprises a clock management and control module;

The clock management and control module includes N core clock control units, and the i-th core clock control unit is connected to the i-th core processor, where i is an integer greater than zero;

The clock management and control module further includes a clock monitoring unit connected to the N core clock control units;

2. The apparatus according to claim 1, wherein

3. The apparatus according to claim 1, wherein

The interrupt monitoring unit is configured to detect a core processor wake-up interrupt signal, and notify the clock monitoring unit after detecting the core processor wake-up interrupt signal;

The core clock control unit is further configured to, after receiving the core processor wake-up interrupt signal, turn on a core-gated clock of the core processor connected to the core clock control unit.

4. The apparatus according to claim 3, wherein

5. The apparatus according to claim 1, wherein

The clock monitoring unit is further configured to turn on the low frequency crystal oscillator clock after turning off the high frequency crystal oscillator clock.

6. The apparatus according to claim 1, wherein

The core processor is configured to: upon no task processing, or to determine a request to close the task of the pending task.

7. A multi-core processor clock control method, comprising:

The core clock control unit receives a core clock shutdown request of the core processor connected thereto and notifies the clock monitoring unit, the clock monitoring unit receives a core clock shutdown request from the core clock control unit, and determines that the core clock shutdown request is from When the last of the N core processors is in the working core processor, the high frequency crystal clock is turned off.

8. The method of claim 7 further comprising:

After receiving the core clock off request of the core processor connected thereto and notifying the clock monitoring unit, the core clock control unit turns off the core processor gate clock of the core processor after two clock cycles.

9. The method of claim 7 further comprising:

The interrupt monitoring unit detects the core processor wake-up interrupt signal, and notifies the clock monitoring unit after detecting the core processor wake-up interrupt signal;

After receiving the core processor wake-up interrupt signal, the clock monitoring unit determines that the high-frequency crystal oscillator is in an off state, turns on the high-frequency crystal oscillator, and determines a target core processor that wakes up the interrupt signal of the core processor, and the core is a processor wake-up interrupt signal is sent to a core clock control unit of the target core processor;

After the core clock control unit of the target core processor receives the core processor wake-up interrupt signal, The core-gated clock of the target core processor is started.

10. The method of claim 9 further comprising:

After receiving the core processor wake-up interrupt signal, the clock monitoring unit determines that the high-frequency crystal oscillator is in an on state, determines a target core processor that wakes up the interrupt signal of the core processor, and sends the core processor wake-up interrupt signal to A core clock control unit of the target core processor.