WO2013100086A1

WO2013100086A1 - Liquid crystal display device

Info

Publication number: WO2013100086A1
Application number: PCT/JP2012/083959
Authority: WO
Inventors: 耕平田中
Original assignee: シャープ株式会社
Priority date: 2011-12-28
Filing date: 2012-12-27
Publication date: 2013-07-04

Abstract

A liquid crystal display device (100) has: a plurality of pixels arranged in a matrix form having rows and columns; a plurality of TFTs; a plurality of gate bus lines; and a plurality of source bus lines. Each of the plurality of pixels has: a first sub-pixel having a first sub-pixel electrode; a second sub-pixel having a second sub-pixel electrode; and a first transfer capacitor having a first electrode and second electrode facing each other across a dielectric layer. The first electrode (14C) of the first transfer capacitor (Ctr(n)) of a certain pixel (Pix(n,m) is connected to a second sub-pixel electrode (10B(n)) of the certain pixel, and the second electrode (12C) of the first transfer capacitor of the certain pixel is connected to the next electrode after the certain pixel to be supplied with a display signal voltage.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device excellent in viewing angle characteristics.

Currently, liquid crystal display devices in vertical alignment mode (VA mode) and lateral electric field mode (including IPS mode and FFS mode) are mainly used as liquid crystal display devices for TV applications and the like. Note that the transverse electric field mode is sometimes referred to as an IPS mode.

Of these, the VA mode liquid crystal display device has a larger viewing angle dependency of the γ characteristic than the IPS mode liquid crystal display device. The γ characteristic is a gradation-luminance characteristic. In general, the observation direction is represented by an angle (polar angle) from the normal to the display surface and an azimuth indicating the azimuth in the display surface. The γ characteristics of the VA mode liquid crystal display device are particularly highly dependent on the polar angle in the observation direction. That is, since the γ characteristic when observed from the front (normal direction of the display surface) and the γ characteristic when observed from the oblique direction are different from each other, the gradation display state differs depending on the observation direction (polar angle).

Therefore, in order to reduce the viewing angle dependency of the γ characteristic in the VA mode liquid crystal display device, for example, a liquid crystal display device having a multi-pixel structure as described in Patent Document 1 by the present applicant is put into practical use. Has been. A multi-pixel structure refers to a structure in which one pixel has a plurality of sub-pixels having different brightness. In the present specification, “pixel” refers to a minimum unit for display by a liquid crystal display device, and in the case of a color liquid crystal display device, a minimum for displaying individual primary colors (typically R, G, or B). It is a unit and is sometimes called “dot”.

A pixel of a liquid crystal display device having a multi-pixel structure has a plurality of sub-pixels that can apply different voltages to the liquid crystal layer. The multi-pixel structure is also called a pixel division structure, and various types are known. For example, in the liquid crystal display device described in Patent Document 1, an auxiliary capacitor is provided for each of a plurality of subpixels in one pixel, and is connected to an auxiliary capacitor electrode (CS bus line) constituting the auxiliary capacitor. ) Is electrically independent for each sub-pixel, and is applied to the liquid crystal layers of a plurality of sub-pixels using capacitive division by changing the voltage supplied to the auxiliary capacitor counter electrode (referred to as the auxiliary capacitor counter voltage). The effective voltages are different from each other.

Note that the display quality of the VA mode liquid crystal display device also depends on the viewing direction. In order to suppress and prevent the display quality of the VA mode liquid crystal display device from being different depending on the observing direction, there is a method of forming liquid crystal domains having different alignment directions (director directions) of liquid crystal molecules in one pixel. It has been adopted. Typically, four types of domains are formed in one pixel, and the four types of domains have four orientations that bisect the angle formed by the polarization axes of a pair of polarizing plates arranged in a crossed Nicol state. It is arranged to face. For example, assuming that the azimuth angle of the clock face at 3 o'clock is 0 ° and the counterclockwise direction is positive, the two polarization axes are set at 3 o'clock -9 o'clock and 6 o'clock -12 o'clock. The directors of the four types of liquid crystal domains are set to face 45 °, 135 °, 225 °, and 315 °. In this way, a structure having a plurality of domains with different director directions in one pixel is called an orientation division structure or a multi-domain structure.

For TV applications, a vertical mode liquid crystal display device having a multi-pixel structure and an alignment division structure is widely used. For example, Patent Document 1 discloses a liquid crystal display device in which each of a plurality of subpixels in a pixel has four types of liquid crystal domains.

However, when an alignment division structure or a pixel division structure is introduced, there is a problem that the aperture ratio decreases. As the resolution of liquid crystal display devices increases and the size of individual pixels decreases, countermeasures against this problem are strongly desired. Further, when the aperture ratio decreases, it is necessary to increase the light emission intensity of the backlight, which causes a problem of increasing power consumption. In particular, low power consumption is an important issue for liquid crystal display devices for mobile use.

JP 2004-62146 A (US Pat. No. 6,958,791)

The conventional multi-pixel structure is not necessarily suitable for a liquid crystal display device for mobile use. For example, the multi-pixel structure described in Patent Document 1 has a problem that the circuit becomes complicated because it is necessary to supply different auxiliary capacitor counter voltages to the auxiliary capacitors provided for each sub-pixel. Also. Since it is necessary to provide CS bus lines that are electrically independent from each other in order to supply the auxiliary capacitor counter voltage, there is a problem that the number of CS bus lines increases and the aperture ratio decreases. In addition, since a voltage having a waveform oscillating at a constant cycle is used as the auxiliary capacitor counter voltage, there is a problem that power consumption increases.

An object of the present invention is to provide a liquid crystal display device more suitable for mobile use than a liquid crystal display device having a conventional multi-pixel structure by solving at least one of the above problems. Of course, the liquid crystal display device of the present invention is not limited to mobile use, but can be used for other purposes.

A liquid crystal display device according to an embodiment of the present invention includes a plurality of pixels arranged in a matrix having rows and columns, a plurality of TFTs, a plurality of gate bus lines, and a plurality of source bus lines. Each of the plurality of pixels includes a first subpixel having a first subpixel electrode, a second subpixel having a second subpixel electrode, and a first electrode and a second electrode facing each other through a dielectric layer. The first transition capacitor of the certain pixel, the first electrode of the first transition capacitor of the certain pixel is connected to the second subpixel electrode of the certain pixel, and the first transition capacitor of the certain pixel. The second electrode is connected to an electrode to which a display signal voltage is supplied next to the certain pixel.

In one embodiment, the second electrode of the first transition capacitor of the certain pixel is connected to the first subpixel electrode of a pixel adjacent to the certain pixel in the column direction.

In one embodiment, the display signal voltage supplied to the certain pixel and the display signal voltage supplied next to the certain pixel have opposite polarities.

In one embodiment, the display signal voltage supplied to the certain pixel and the display signal voltage supplied next to the certain pixel have the same polarity.

In one embodiment, the first subpixel electrode and the second subpixel electrode of the certain pixel, and the first subpixel electrode and the second subpixel electrode of a pixel adjacent to the certain pixel in the column direction are Are connected to the same source bus line.

In one embodiment, the first subpixel electrode and the second subpixel electrode of a plurality of pixels constituting a certain column are connected to different source bus lines for every k consecutive rows (k is an integer of 2 or more). Yes.

In one embodiment, display signal voltages having different polarities are simultaneously supplied to two pixels adjacent in the column direction from different source bus lines, and the second electrode of the first transition capacitor of the certain pixel is supplied to the second pixel. Is supplied with a display signal voltage that is supplied to two pixels separated in the column direction of the certain pixel.

In one embodiment, the plurality of pixels arranged in the column direction are divided into an even number of groups, and each of the even number of groups has pixels arranged in a row, and from one end in the column direction. When assigning numbers to the groups in order, display signal voltages having different polarities are supplied from different source bus lines to the pixels belonging to the odd numbered group and the pixels belonging to the even numbered group, The display signal voltages having different polarities are simultaneously supplied to one pixel belonging to the group and one pixel belonging to the even-numbered group.

In one embodiment, each of the plurality of pixels includes a third subpixel having a third subpixel electrode, and a second transition capacitor having a third electrode and a fourth electrode facing each other through a dielectric layer. Further, the third electrode of the second transition capacitor of the certain pixel is connected to the third sub-pixel electrode of the certain pixel, and the fourth electrode of the second transition capacitor of the certain pixel Is connected to the first electrode or the second subpixel electrode of the first transition capacitor.

In one embodiment, the liquid crystal display device is connected to a first auxiliary capacitor connected to the first subpixel electrode and the first auxiliary capacitance line, and to the second subpixel electrode and the second auxiliary capacitance line. And a second auxiliary capacitor.

In one embodiment, the first auxiliary capacitor and the second auxiliary capacitor have different capacitance values.

In one embodiment, the first auxiliary capacitance line and the second auxiliary capacitance line are electrically independent from each other.

In one embodiment, the liquid crystal display device includes: a first GD capacitor connected to the first subpixel electrode; and a gate bus line connected to a TFT to which the first subpixel electrode is connected; A second subpixel electrode; and a second GD capacitor connected to the gate bus line connected to the TFT to which the second subpixel electrode is connected.

In one embodiment, the TFT includes a first TFT connected to the first subpixel electrode and a second TFT connected to the second subpixel electrode, and the first TFT and the second TFT have a common gate bus line. It is connected to the.

In one embodiment, a first TFT connected to the first subpixel electrode and a second TFT connected to the second subpixel electrode, wherein the first TFT and the second TFT are a common source bus line. It is connected to the.

In one embodiment, one of the first TFT and the second TFT is connected to the common source bus line via the other.

In one embodiment, the plurality of TFTs include an oxide semiconductor layer.

In one embodiment, the liquid crystal display device further includes a drive circuit, the drive circuit receiving an input video signal and generating a display signal based on the input video signal, wherein the display signal is The display signal voltage supplied to the certain pixel including the display signal voltage corresponding to each pixel is obtained as a function of the display signal voltage supplied next to the certain pixel.

According to the embodiment of the present invention, a liquid crystal display device more suitable for mobile use is provided than a liquid crystal display device having a conventional multi-pixel structure. Of course, the liquid crystal display device according to the embodiment of the present invention is not limited to the mobile use but is also used for other uses, and provides the advantage of high aperture ratio or low power consumption.

It is a figure which shows the equivalent circuit corresponding to 1 pixel of the liquid crystal display device 100 by embodiment of this invention. It is a figure which shows the equivalent circuit of 100 A of liquid crystal display devices by embodiment of this invention. It is a figure which shows typically the scanning signal voltage in liquid crystal display device 100A, a display signal voltage, and the voltage applied to a subpixel. It is a figure which shows the equivalent circuit of the liquid crystal display device 100B by other embodiment of this invention. It is a figure which shows typically the scanning signal voltage in liquid crystal display device 100B, a display signal voltage, and the voltage applied to a subpixel. It is a figure which shows the equivalent circuit of 100 C of liquid crystal display devices by further another embodiment of this invention. It is a figure which shows typically the connection relation of the source bus line and pixel in liquid crystal display device 100C. It is a figure which shows typically the scanning signal voltage in the liquid crystal display device 100C, a display signal voltage, and the voltage applied to a subpixel. It is a figure which shows typically the connection relation of the source bus line and pixel in liquid crystal display device 100D by further another embodiment of this invention. It is a figure which shows typically the scanning signal voltage in liquid crystal display device 100D, a display signal voltage, and the voltage applied to a subpixel. (A) And (b) is a figure which shows typically the structure of liquid crystal display device 100 A1, (a) is a typical top view of the TFT substrate which liquid crystal display device 100 A1 has, (b) is ( It is a typical sectional view of liquid crystal display device 100A1 along the AA 'line in a). (A) And (b) is a figure which shows typically the structure of liquid crystal display device 100A2, (a) is a typical top view of the TFT substrate which liquid crystal display device 100A2 has, (b) is ( It is a typical sectional view of liquid crystal display device 100A2 along the BB 'line in a). It is a figure which shows the equivalent circuit of the liquid crystal display device 100E by other embodiment of this invention. It is a figure which shows typically the scanning signal voltage in the liquid crystal display device 100E, a display signal voltage, and the voltage applied to a subpixel. It is a figure which shows typically the connection relation of the source bus line and pixel in the liquid crystal display device 100E. It is a figure which shows typically the connection relation of the source bus line and pixel in the liquid crystal display device 100F by further another embodiment of this invention. It is a typical top view of the TFT substrate which liquid crystal display device 100E1 has. It is a typical top view of the TFT substrate which liquid crystal display device 100E2 has. It is a figure which shows the equivalent circuit of the liquid crystal display device 100G by further another embodiment of this invention. It is a figure which shows typically the scanning signal voltage in the liquid crystal display device 100G, a display signal voltage, and the voltage applied to a subpixel. It is a typical top view of the TFT substrate which liquid crystal display device 100G1 has. It is a typical top view of the TFT substrate which liquid crystal display device 100G2 has. (A) is a figure which shows the equivalent circuit corresponding to 1 pixel of 200 A of liquid crystal display devices by further another embodiment of this invention, (b) is the liquid crystal display device by further another embodiment of this invention. It is a figure which shows the equivalent circuit corresponding to 1 pixel of 200B. (A) is a typical top view of the TFT substrate which liquid crystal display device 200A1 has, (b) is a typical top view of the TFT substrate which liquid crystal display device 200B1 has. (A) is a figure which shows the equivalent circuit of the liquid crystal display device 300 by further another embodiment of this invention, (b) is the source bus line SL and TFT (T1, T2) in the liquid crystal display device 300a. It is a schematic diagram which shows a connection relationship (series), (c) is a schematic diagram which shows the connection relationship (parallel) of source bus line SL and TFT (T1, T2) in all the previous embodiment. (A) And (b) is a schematic diagram for demonstrating the example of the method of calculating | requiring a display signal voltage based on an input video signal in the liquid crystal display device by embodiment of this invention.

Hereinafter, a liquid crystal display device and an operation thereof according to an embodiment of the present invention will be described with reference to the drawings, but the embodiment of the present invention is not limited to the illustrated embodiment. Moreover, although the case where each pixel has two subpixels is mainly described, each pixel may have three or more subpixels as will be exemplified later. However, since the aperture ratio decreases as the number of subpixels included in one pixel increases, the number of subpixels included in each pixel is preferably 2 from the viewpoint of the aperture ratio.

FIG. 1 shows an equivalent circuit corresponding to one pixel of the liquid crystal display device 100 according to the embodiment of the present invention. In the following drawings, equivalent components are denoted by common reference numerals, and description thereof may be omitted.

The liquid crystal display device 100 includes a plurality of pixels arranged in a matrix having rows and columns, a plurality of TFTs, a plurality of gate bus lines, and a plurality of source bus lines. Each of the plurality of pixels includes a first subpixel having a first subpixel electrode and a second subpixel having a second subpixel electrode.

Here, the pixel of n rows and m columns is expressed as Pix (n, m). The pixel Pix (n, m) includes a first subpixel pix (n) A and a second subpixel pix (n) B. In the equivalent circuit, the first subpixel pix (n) A is represented by a first liquid crystal capacitor CLC (n) A, and the second subpixel pix (n) B is represented by a second liquid crystal capacitor CLC (n) B. Is done. One of the pair of electrodes of the first liquid crystal capacitor CLC (n) A is the first subpixel electrode, and one of the pair of electrodes of the second liquid crystal capacitor CLC (n) B is the second subpixel. Electrode.

The first subpixel electrode of the first liquid crystal capacitor CLC (n) A is connected to the drain electrode of the TFT (n) A, and the second subpixel electrode of the second liquid crystal capacitor CLC (n) B is connected to the TFT ( n) Connected to the B drain electrode. The other electrode of the first liquid crystal capacitor CLC (n) A and the second liquid crystal capacitor CLC (n) B is a common counter electrode. That is, the first liquid crystal capacitor CLC (n) A includes a first subpixel electrode, a liquid crystal layer, and a counter electrode. The first liquid crystal capacitor CLC (n) A includes the first subpixel electrode. And a liquid crystal layer and a counter electrode.

A display signal voltage is supplied to the first subpixel of the first subpixel pix (n) A from the source bus line SL (m) via the TFT (n) A, and the second subpixel pix (n) B A display signal voltage is supplied to the second subpixel from the source bus line SL (m) via the TFT (n) B. Note that the display signal voltage supplied to the pixel from the source bus line is “voltage applied to the liquid crystal layer” when the voltage (Vcom) of the counter electrode com is used as a reference.

The gates of TFT (n) A and TFT (n) B are connected to the gate bus line GL (n), and are turned on / off according to the scanning signal voltage supplied from the gate bus line GL (n). The Although an example in which two TFT (n) A and TFT (n) B are connected to a common source bus line SL (m) and a common gate bus line GL (n) is shown, the present invention is not limited to this. As long as a desired display signal voltage and a desired scanning signal voltage can be supplied, there is no need to provide a common bus line. That is, a plurality of gate bus lines or a plurality of source bus lines may be provided as long as the same scanning signal voltage or the same display signal voltage can be supplied. Of course, the advantage of improving the aperture ratio can be obtained by sharing the bus line. Here, an example is shown in which two TFT (n) A and TFT (n) B are connected in parallel to a common source bus line SL (m), which will be described later with reference to FIG. As described above, either one of the TFT (n) A and the TFT (n) B may be connected to a common source bus line through the other. That is, TFT (n) A and TFT (n) B may be connected in series to one source bus line SL (m).

The above configuration of the pixel Pix (n, m) having the first subpixel pix (n) A and the second subpixel pix (n) B is described in, for example, Patent Document 1, and various modifications are made. Is possible.

The liquid crystal display device 100 is different from a conventional liquid crystal display device having a multi-pixel structure (for example, Patent Document 1) in that it has a first transition capacitance Ctr (n). The first transition capacitor Ctr (n) has a first electrode and a second electrode that face each other with the dielectric layer and the dielectric layer interposed therebetween. The dielectric layer of the first transition capacitor Ctr (n) can be formed using various insulating layers formed on the TFT substrate. Further, the first electrode and the second electrode of the first transition capacitance Ctr (n) can be formed using the same conductive layer as various electrodes and bus lines formed on the TFT substrate. As the TFT, a well-known TFT can be widely used. However, a TFT having an oxide semiconductor layer is preferably used because the liquid crystal capacitance and the transition capacitance can be charged in a short time.

The oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor (hereinafter abbreviated as “IGZO-based semiconductor”). Here, the IGZO-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited. In: Ga: Zn = 2: 2: 1, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 1: 1: 2, and the like. The IGZO semiconductor may be amorphous or crystalline. As the crystalline IGZO-based semiconductor, a crystalline IGZO-based semiconductor having a c-axis oriented substantially perpendicular to the layer surface is preferable. Such a crystal structure of an IGZO-based semiconductor is disclosed in, for example, Japanese Patent Application Laid-Open No. 2012-134475. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference.

A first electrode of a first transition capacitor (eg, Ctr (n)) of a pixel (eg, Pix (n, m)) is connected to a second subpixel electrode of the pixel (eg, Pix (n, m)). The second electrode of the first transition capacitor (eg, Ctr (n)) of the pixel (eg, Pix (n, m)) is supplied with the display signal voltage next to the pixel (eg, Pix (n, m)). Connected to the electrode. All the liquid crystal display devices of the embodiments exemplified below have this connection relationship.

Next, the electrode to which the display signal voltage is supplied is, for example, the first subpixel electrode (first pixel) of the pixel (for example, Pix (n + 1, m)) in the next row as in the liquid crystal display device 100 illustrated in FIG. Sub-pixel pix (n + 1) A). That is, the second electrode of the first transition capacitor (for example, Ctr (n)) of a certain pixel (for example, Pix (n, m)) is adjacent to the pixel (for example, Pix (n, m)) in the column direction (for example, Pix (n, m)). For example, Pix (n + 1, m)) is connected to the first subpixel electrode (refer to the following liquid

crystal display devices

100, 100A, 100B, 100C and 100D, 100A1, 100A2).

Further, as will be exemplified later, depending on the driving method, the electrode to which the display signal voltage is supplied next is a pixel (Pix (n + 2,..., Pix (n + 2,. The first subpixel electrode of m)) may be used. That is, the second electrode of the first transition capacitor (eg, Ctr (n)) of a certain pixel (eg, Pix (n, m)) is separated by two in the column direction of the pixel (eg, Pix (n, m)). It may be connected to the first subpixel electrode of the pixel (Pix (n + 2, m)) (see the following liquid crystal display devices 100E, 100E1, and 100E2).

In a liquid crystal display device, the polarity (direction of electric field) of a voltage applied to a liquid crystal layer of a pixel (hereinafter, sometimes referred to as “voltage applied to a pixel” for the sake of simplicity) is constant every time. (So-called AC drive). The polarity of the voltage applied to the pixel is typically “1 V” in one frame period (vertical scanning period: a period from when a gate bus line is selected to when the gate bus line is selected again. Is inverted every time (frame inversion drive). Note that the period from the selection of the first row of pixels arranged in a matrix to the selection of the first row is sometimes referred to as “one frame”. One frame is a period for writing a display signal voltage for forming one image to all pixels (including strictly vertical blanking), and one frame period has the same length as one frame. In contrast, one frame has a fixed starting point.

Further, the driving is performed so that the polarity of the voltage applied to the liquid crystal layer of the adjacent pixel is different in one frame period. For example, row inversion drive (gate bus line inversion drive) drives with different voltages applied to pixels adjacent in the column direction, and drives with different voltages applied to pixels adjacent in the row direction. Column inversion driving (source bus line inversion driving) and driving in which the polarities of voltages applied to adjacent pixels in the column and row directions are different (dot inversion driving) are known.

As described above, in the liquid crystal display device according to the embodiment of the present invention, the first electrode of the first transition capacitor Ctr (n) of the pixel Pix (n, m) is the second subpixel of the pixel Pix (n, m). The second electrode of the first transition capacitor Ctr (n) of Pix (n, m) is connected to the electrode to which the display signal voltage is supplied next to the pixel Pix (n, m), for example. ing. Therefore, depending on the polarity relationship between the display signal voltage supplied to the pixel Pix (n, m) and the display signal voltage supplied next, the liquid crystal layer of the second subpixel of the pixel Pix (n, m) The applied voltage Vpix (n) B may be smaller or larger than the voltage Vpix (n) A applied to the liquid crystal layer of the first subpixel. Therefore, the liquid crystal display device according to the embodiment of the present invention can form a bright sub-pixel and a dark sub-pixel in one pixel. Note that the voltage applied to the liquid crystal layer of each subpixel may be referred to as “voltage applied to the subpixel” for the sake of simplicity.

2 and 3, the configuration and operation of the liquid crystal display device 100A according to the embodiment of the present invention will be described. FIG. 2 is a diagram showing an equivalent circuit of the liquid crystal display device 100A according to the embodiment of the present invention. FIG. 3 schematically shows the scanning signal voltage, the display signal voltage, and the voltage applied to the subpixel in the liquid crystal display device 100A. FIG.

As shown in FIG. 2, the pixel Pix (n, m) of the liquid crystal display device 100A includes a first subpixel pix (n) A (= first liquid crystal capacitance CLC (n) A) and a second subpixel pix (n ) B (second liquid crystal capacitance CLC (n) B). The first subpixel electrode of the first subpixel pix (n) A and the second subpixel electrode of the second subpixel pix (n) B are respectively connected to the corresponding TFTs (TFT (n) A and TFT (n ) Corresponding to B) to the source bus line SL (m).

The first electrode of the first transition capacitor Ctr (n) of the pixel Pix (n, m) is connected to the second subpixel electrode of the pixel Pix (n, m), and the first electrode of the pixel Pix (n, m). The second electrode of the one transfer capacitor Ctr (n) is connected to the first subpixel electrode of the pixel Pix (n + 1, m) adjacent to the pixel Pix (n, m) in the column direction. The first subpixel electrode and the second subpixel electrode of the pixel Pix (n, m), and the first subpixel electrode and the second subpixel electrode of the pixel Pix (n + 1, m) adjacent to the pixel Pix (n, m) in the column direction The sub-pixel electrode is connected to the same source bus line. The equivalent circuit of the liquid crystal display device 100A is the same as the equivalent circuit of the liquid crystal display device 100 shown in FIG.

The liquid crystal display device 100A is driven by dot inversion. With reference to FIG. 3, the scanning signal voltage, the display signal voltage, and the voltage applied to the sub-pixel in the liquid crystal display device 100A will be described. VGL (n) and VGL (n + 1) indicate scanning signal voltages supplied from the gate bus lines GL (n) and GL (n + 1), respectively, and VSL (m) is supplied from the source bus line SL (m). Display signal voltage. Vpix (n) A and Vpix (n) B and Vpix (n + 1) A are respectively referred to as the first subpixel pix (n) and the second subpixel pix (n) B of the pixel Pix (n, m). The voltage applied and the voltage applied to the first sub-pixel pix (n + 1) A of the pixel Pix (n + 1, m) are shown. The display signal voltage and the voltage applied to the subpixel are based on the voltage of the counter electrode (common voltage Vcom). Therefore, the voltage applied to each subpixel is synonymous with the voltage of the subpixel electrode of each subpixel with respect to the common voltage Vcom.

FIG. 3 shows each voltage in two consecutive frames of the liquid crystal display device 100A. The polarities of the display signal voltage VSL (m) (Vcom is set to 0V) are opposite to each other in two consecutive frames (frame inversion driving). The polarity of the display signal voltage VSL (m) may be expressed as “1H” in one horizontal scanning period (a period from selection of a certain gate bus line to selection of the next gate bus line). )), The time changes so as to be reversed between adjacent pixel rows (n and n + 1 rows). That is, the polarity of the display signal voltage supplied to a certain pixel and the display signal voltage supplied next to that pixel (that is, in the horizontal scanning period next to the horizontal scanning period in which the pixel is selected) are reversed. It is. Although not shown in FIG. 3, the polarity of the display signal voltage VSL (m + 1) is opposite to that of the display signal voltage VSL (m). That is, the liquid crystal display device 100A is driven by dot inversion.

The display signal voltage VSL (m) is applied to the first and second subpixels of the pixel Pix (n, m) while the scanning signal voltage VGL (n) is high (the TFT is on). The voltage Vpix (n) A of one subpixel and the voltage Vpix (n) B of the second subpixel are increased (because the display signal voltage VSL (m) in the above period is positive).

When the scanning signal voltage VGL (n) switches from high to low, the TFT is turned off, and the first subpixel and the second subpixel of the pixel Pix (n, m) are electrically connected from the source bus line SL (m). Insulated. Accordingly, the voltage Vpix (n) A of the first subpixel of the pixel Pix (n, m) is maintained.

On the other hand, the second subpixel of the pixel Pix (n, m) is connected to the first subpixel electrode of the pixel Pix (n + 1, m) via the first transfer capacitor Ctr (n) (scanning). After the signal voltage VGL (n) is switched from high to low), the scanning signal voltage VGL (n + 1) becomes high, thereby affecting the influence of the voltage change of the first subpixel electrode of the pixel Pix (n + 1, m). receive. Here, since the voltage corresponding to the (n + 1) th row of the display signal voltage VSL (m) supplied to the pixel Pix (n + 1, m) is negative, the voltage of Vpix (n + 1) A becomes negative as shown in FIG. . This voltage affects the voltage Vpix (n) B of the second subpixel of the pixel Pix (n, m) via the first transition capacitor Ctr (n), and Vpix (n) B decreases.

As a result, a voltage difference of ΔV is generated between the voltage Vpix (n) A of the first subpixel of the pixel Pix (n, m) and the voltage Vpix (n) B of the second subpixel (ΔV = Vpix ( n) A-Vpix (n) B> 0).

The display signal voltage supplied from the source bus line is VSL (m), the capacitance of the liquid crystal capacitance of the second subpixel is CLCB, the capacitance of the first transition capacitance is Ctr, and other capacitance (for example, an auxiliary capacitance provided optionally) When the total capacitance of CS and gate-drain capacitance CGD) and parasitic capacitance is Cp, Vpix (n) A and Vpix (n) B are respectively expressed by the following equations. The following formula is established when a still image is displayed.

Vpix (n) A = VSL (m) (1)
Vpix (n) B = VSL (m) + α · 2 · Vpix (n + 1) A (2)
α = Ctr / (CLCB + Ctr + Cp) (3)

Here, since Vpix (n) A is positive and Vpix (n + 1) A is negative, | Vpix (n) A |> | Vpix (n) B |, and the second subpixel pix (n + 1) B The luminance is lower than the luminance of the first subpixel pix (n) A. That is, the luminance to be displayed by the pixel Pix (n, m) is the first subpixel pix (n) A having a higher luminance than the luminance to be displayed and the second subpixel pix having a lower luminance than the luminance to be displayed. (N) Expressed as B. As a result, the viewing angle dependency of the γ characteristic is reduced as in the case of a liquid crystal display device having a conventional multi-pixel structure.

In the liquid crystal display device according to the embodiment of the present invention, the difference in luminance between two subpixels (the difference in the magnitude (absolute value) of the voltage applied to the two subpixels is supplied next to the pixel. Accordingly, the driving circuit (not shown) included in the liquid crystal display device according to the embodiment of the present invention receives the input video signal and receives the input video signal. When the display signal is generated based on the signal, the display signal voltage supplied to a certain pixel can be obtained as a function of the display signal voltage supplied next to the certain pixel. According to the signal gradation data (gradation data of the current horizontal scanning period and the next horizontal scanning period), a lookup table storing data of a preset display signal voltage may be provided, or the input video signal The display signal voltage may be obtained by calculation based on the gradation data, a specific example will be described later with reference to Fig. 26. Note that the liquid crystal according to the embodiment of the present invention includes the liquid crystal display device exemplified below. All the driving circuits of the display device have this function.

Next, the configuration and operation of a liquid crystal display device 100B according to another embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a diagram showing an equivalent circuit of a liquid crystal display device 100B according to another embodiment of the present invention. FIG. 5 shows scanning signal voltages, display signal voltages, and voltages applied to sub-pixels in the liquid crystal display device 100B. It is a figure shown typically. The liquid crystal display device 100B is so-called pseudo-dot inversion driven, and the polarity of the voltage applied to the adjacent pixels in the column direction and the row direction is different in each frame period as in the liquid crystal display device 100A.

Transistors in a pixel column of the liquid crystal display device 100B are alternately connected to different ones of two source bus lines arranged on both sides of the pixel column for each pixel row. For example, in FIG. 4, attention is focused on m pixel columns. A source bus line SL (m) and a source bus line SL (m + 1) are arranged on both sides of the m pixel columns. The TFT of the pixel Pix (n, m) is connected to the source bus line SL (m), and the TFT of the pixel Pix (n + 1, m) in the next row is connected to the source bus line SL (m + 1). . In the liquid crystal display device 100B, the connection relationship between the TFT (that is, the sub-pixel electrode) and the source bus line is different from that in the liquid crystal display device 100A.

As shown in FIG. 5, in the liquid crystal display device 100B, adjacent source bus lines, for example, the source bus line SL (m) and the source bus line SL (m + 1) are displayed with opposite polarities over one frame period. Signal voltages (VSL (m), VSL (m + 1)) are supplied, and the polarity of each display signal voltage does not change during one frame period. This is different from the fact that the polarity of the display signal voltage VSL (m) in the liquid crystal display device 100A shown in FIG. 3 is reversed every horizontal scanning period. That is, in the liquid crystal display device 100B, the TFTs of each pixel column are connected to different source bus lines alternately (zigzag) for each row with respect to two source bus lines within one frame period. Inversion of the polarity of the display signal voltage can be eliminated. As a result, the liquid crystal display device 100B has an advantage that it can be driven with lower power consumption than the liquid crystal display device 100A.

In the liquid crystal display device 100B, between the voltage Vpix (n) A applied to the first subpixel pix (n) A and Vpix (n) B applied to the second subpixel pix (n) B. The mechanism for generating the voltage difference ΔV is the same as that of the liquid crystal display device 100A. That is, since Vpix (n) A (= VSL (m)) is positive and Vpix (n + 1) A (= VSL (m + 1)) is negative, | Vpix (n) A |> | Vpix (n) B The luminance of the second subpixel pix (n + 1) B is lower than the luminance of the first subpixel pix (n) A.

Next, the structure and operation of a liquid crystal display device 100C according to still another embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a diagram showing an equivalent circuit of a liquid crystal display device 100C according to still another embodiment of the present invention, and FIG. 7 is a diagram schematically showing a connection relationship between source bus lines and pixels in the liquid crystal display device 100C. It is. FIG. 8 is a diagram schematically illustrating a scanning signal voltage, a display signal voltage, and a voltage applied to the sub-pixel in the liquid crystal display device 100C.

The equivalent circuit of the liquid crystal display device 100C shown in FIG. 6 is substantially the same as the equivalent circuit of the liquid crystal display device 100A shown in FIG. However, the liquid crystal display device 100A is driven by dot inversion, whereas the liquid crystal display device 100C is different in that it is driven by column inversion (source bus line inversion driving). That is, in the liquid crystal display device 100A of FIG. 1, “+” is added to each subpixel of the pixel Pix (n, m), and “−” is added to each subpixel of the pixel Pix (n + 1, m). On the other hand, in the liquid crystal display device 100C of FIG. 6, “+” is added to both subpixels of the pixel Pix (n, m) and the pixel Pix (n + 1, m). That is, as shown in FIG. 7, in a certain pixel column, voltages having the same polarity are applied to all the pixels from the first row to the Nth row. In FIG. 6, a positive (+) voltage is applied to all the pixels in the m column, and a negative (−) voltage is applied to all the pixels in the m + 1 column adjacent thereto.

That is, in the liquid crystal display device 100C, the display signal voltage supplied to a certain pixel and the display signal voltage supplied next to the pixel have the same polarity. Therefore, as shown in FIG. 8, for example, the second subpixel pix (1) B of the pixel Pix (1, m) is affected by VSL (m) applied to the pixel Pix (2, m). The voltage is boosted to | Vpix (n) A | <| Vpix (n) B |, and the luminance of the second subpixel pix (n + 1) B is higher than the luminance of the first subpixel pix (n) A. Therefore, compared with the liquid

crystal display device

100A or 100B, since the magnitude of the display signal voltage with respect to the gradation to be displayed can be reduced, there is an advantage that power consumption can be reduced.

However, the liquid crystal display device 100C has a problem that display luminance varies depending on pixel rows. This problem will be described with reference to FIGS.

As shown in FIG. 7, an arbitrary pixel has a parasitic capacitance Csd1 between the pixel and a source bus line (for example, SL (m)) to which the pixel (two subpixel electrodes) is connected. A parasitic capacitance Csd2 is provided between the pixel and a source bus line (for example, SL (m + 1)) to which a pixel adjacent in the row direction of the pixel is connected. Each pixel is affected by the voltage variation of the source bus line via these parasitic capacitances Csd. In the liquid crystal display device 100C, the polarities of the voltages of the adjacent source bus lines are opposite to each other, and the polarities of the voltages of the source bus lines are inverted every frame.

In the liquid crystal display device 100C, the pixels in a certain pixel column are all connected to the same source bus line (for example, SL (m)). At this time, as shown in FIG. 8, the voltages of the first subpixel pix (1) A and the second subpixel pix (1) B included in the pixel Pix (1, m) in the first row, Vpix (1) A And Vpix (1) B are affected by the polarity inversion of the voltage of the source bus line at the end of one frame period. The voltage fluctuation at this time is assumed to be ΔV (Csd). On the other hand, the voltages of the first subpixel pix (n) A and the second subpixel pix (n) B included in the pixel Pix (n, m) of the nth row selected near the end of one frame, Vpix (N) A and Vpix (n) B are affected by the polarity inversion of the voltage of the source bus line at the beginning of one frame period (here, n is an integer close to N).

As described above, the timing at which the pixel Pix (1, m) in the first row and the pixel Pix (n, m) in the n-th row are affected by the polarity inversion of the voltage of the source bus line (ΔV (Csd)). Are different from each other in the effective value of one frame period of the pixel Pix (1, m) in the first row and the effective value of one frame period of the pixel Pix (n, m) in the nth row. Since it appears as a difference in luminance, the display quality is lowered.

Next, the structure and operation of a liquid crystal display device 100D according to another embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a diagram schematically showing a connection relationship between source bus lines and pixels in the liquid crystal display device 100D, and FIG. 10 is applied to the scanning signal voltage, the display signal voltage, and the sub-pixels in the liquid crystal display device 100D. It is a figure which shows a voltage typically.

As shown in FIG. 9, in the liquid crystal display device 100 </ b> D, the first subpixel electrode and the second subpixel electrode of a plurality of pixels constituting a column are different for each successive k rows (k is an integer of 2 or more). Connected to the source bus line. Specifically, the pixels in a certain pixel column are connected to different source bus lines SL (m) or SL (m + 1) of two adjacent source bus lines for every k rows. The liquid crystal display device 100D has the same configuration as the liquid crystal display device 100C except for the connection relationship between the source bus lines and the pixels.

Here, as shown in FIG. 10, the polarity of the display signal voltage VSL (m) supplied to the source bus line SL (m) is inverted for every k rows of pixels. That is, the display signal voltage VSL (m) is inverted every 1H (horizontal scanning period) × k hours. Then, every time the polarity of the display signal voltage VSL (m) is inverted, the voltage variation (ΔV (Csd)) due to the parasitic capacitance described above occurs. The fluctuation of the voltage is not only the pixel in the first row (first subpixel pix (1) A and second subpixel pix (1) B), but also the pixel in the nth row (first subpixel pix (n)). This also occurs for A and the second subpixel pix (n) B), and the number of fluctuations is the same for every row. Therefore, in the liquid crystal display device 100D, occurrence of variations in display luminance in the liquid crystal display device 100C is suppressed.

In FIG. 9, as shown by adding “+” or “−” to each pixel, display signal voltages having opposite polarities are supplied to adjacent pixel columns. In other words, in the 1H × k period in which the display signal voltage supplied to the source bus line SL (m) is positive, the display signal voltage supplied to the source bus line SL (m + 1) is negative and conversely In the 1H × k period in which the display signal voltage supplied to the source bus line SL (m) is negative, the display signal voltage supplied to the source bus line SL (m + 1) is positive.

k may be an integer greater than or equal to 2, but if k is small, the polarity inversion period is short, so the effect of reducing power consumption is small. If k is large, the effect of suppressing variations in display luminance is effective. Get smaller.

Next, an example of a specific structure of the liquid crystal display devices 100A1 and 100A2 according to the embodiment of the present invention will be described with reference to FIGS. The liquid crystal display devices 100A1 and 100A2 exemplified here are used for the previous liquid

crystal display devices

100A, 100C, and 100D. Further, if the connection relationship between the TFT and the source bus line is changed, it can be used for the liquid crystal display device 100B.

11A and 11B schematically show the structure of the liquid crystal display device 100A1. FIG. 11A is a schematic plan view of a TFT substrate included in the liquid crystal display device 100A1, and FIG. 11B is a schematic view of the liquid crystal display device 100A1 taken along the line AA ′ in FIG. FIG.

The basic structure of the liquid crystal display device 100A1 is the same as that of a known TFT type liquid crystal display device, and can be manufactured by a known manufacturing method. Below, it demonstrates centering around a difference with a well-known TFT type liquid crystal display device.

As shown in FIG. 11A, the TFT substrate of the liquid crystal display device 100A1 includes a gate bus line 12, a source bus line 14,

TFTs

16A and 16B formed on a substrate (for example, a glass substrate), sub-pixel electrodes. 10A (n) and 10B (n). The gate bus line 12 is disposed between the subpixel electrodes 10A (n) and 10B (n). The source electrode 14SA of the TFT 16A and the source electrode 14SB of the TFT 16B are connected to the source bus line 14 (typically formed integrally). The drain electrode 14DA of the TFT 16A and the drain electrode 14DB of the TFT 16B are led out to substantially the center of the first subpixel pix (n) A and the second subpixel pix (n) B, respectively. The first subpixel electrode 10A (n) and the second subpixel electrode 10B (n) are connected.

The first transition capacitor Ctr (n) is formed at a position overlapping the boundary between the second subpixel electrode 10B (n) and the first subpixel electrode 10A (n + 1). The first transition capacitor Ctr (n) has a first electrode 14C and a second electrode 12C. The first electrode 14C of the first transition capacitance Ctr (n) is formed integrally with the drain electrode 14DB and is connected to the second subpixel electrode 10B (n). The second electrode 12C of the first transition capacitance Ctr (n) is formed by patterning the same conductive layer as the gate bus line 12, and is connected to the first subpixel electrode 10A (n + 1) in the contact hole 13VA. ing.

As shown in FIG. 11B, the first electrode 14C and the second electrode 12C of the first transition capacitance Ctr (n) are formed on a substantially entire surface of the substrate so as to cover the second electrode 12C. 13 are formed so as to face each other with 13 therebetween. That is, the gate insulating layer 13 is a dielectric layer of the first transition capacitance Ctr (n). The first electrode 14C and the drain electrode 14DB of the first transition capacitance Ctr (n) are formed by patterning the same conductive layer as the source bus line 14, and these are covered with the interlayer insulating layer 15. A first subpixel electrode 10A and a second subpixel electrode 10B are formed on the interlayer insulating layer 15. A counter electrode (also referred to as “common electrode”) 30 is disposed so as to face the first subpixel electrode 10 </ b> A and the second subpixel electrode 10 </ b> B via the liquid crystal layer 20.

The counter electrode 30 is typically formed on a substrate (for example, a glass substrate: not shown), and the substrate having the counter electrode 30 is called a counter substrate. The liquid crystal layer 20 is provided between the TFT substrate and the counter substrate. Typically, the first subpixel electrode 10A, the second subpixel electrode 10B, and the surface of the counter electrode 30 on the liquid crystal layer 20 side are covered with an alignment film (not shown). Here, a VA mode liquid crystal display device in which the liquid crystal layer 20 includes a nematic liquid crystal material having negative dielectric anisotropy, has a vertical alignment film as an alignment film, and performs display in a normally black mode is illustrated. Yes. In addition, a color filter layer having a color filter of three primary colors or more and a black matrix (light shielding layer) is generally formed on the counter substrate.

12A and 12B schematically show the structure of the liquid crystal display device 100A2. 12A is a schematic plan view of a TFT substrate included in the liquid crystal display device 100A2, and FIG. 12B is a schematic view of the liquid crystal display device 100A2 along the line BB ′ in FIG. FIG.

The liquid crystal display device 100A2 is different from the liquid crystal display device 100A1 in that the first subpixel electrode 10A (n) and the second subpixel electrode 10B (n) are formed of different transparent conductive layers. The first transition capacitor Ctr (n) is formed in a region where the second subpixel electrode 10B (n) and the first subpixel electrode 10A (n + 1) overlap with each other via the interlayer insulating layer 17. That is, the first electrode of the first transition capacitor Ctr (n) is a part of the second subpixel electrode 10B (n), and the second electrode of the first transition capacitor Ctr (n) is the first subpixel electrode 10A. Part of (n + 1).

As can be seen by comparing FIG. 12A and FIG. 11B, the liquid crystal display device 100A2 has the advantage of a higher aperture ratio than the liquid crystal display device 100A1. In the liquid crystal display device 100A2, since the first and second electrodes of the first transition capacitance Ctr (n) are formed of a transparent conductive layer (subpixel electrode), the liquid crystal layer 20 has the first transition capacitance Ctr (n). A region overlapping with can also contribute to display. Further, like the liquid crystal display device 100A1, the extension of the electrode for connecting the second electrode 12C of the first transition capacitance Ctr (n) to the first subpixel electrode 10A (n + 1) or the contact hole 13VA (FIG. 11A )) Is not required to be formed, and there is no decrease in the aperture ratio due to these.

Next, the structure and operation of a liquid crystal display device 100E having a so-called double source structure according to another embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a diagram illustrating an equivalent circuit of the liquid crystal display device 100E, and FIG. 14 is a diagram schematically illustrating a scanning signal voltage, a display signal voltage, and a voltage applied to the sub-pixel in the liquid crystal display device 100E. FIG. 15 is a diagram schematically showing the connection relationship between the source bus lines and the pixels in the liquid crystal display device 100E.

As shown in FIG. 13, the liquid crystal display device 100E has source bus lines SL (m) 1 and SL (m) 2 arranged on both sides of a pixel column (for example, m columns). Here, this structure is called a double source structure. In the liquid crystal display device 100E, two different source bus lines SL (m) 1 and SL (m) are simultaneously applied to two pixels (for example, a pixel Pix (n, m) and a pixel Pix (n + 1, m)) adjacent to each other in the column direction. The display signal voltages having different polarities are supplied from 2. The gate bus line to which the gate electrodes of the two TFTs of the pixel Pix (n, m) are connected and the pixel Pix (n + 1, m). The gate bus lines to which the gate electrodes of the two TFTs are connected are GL (n), and the same scanning signal voltage VGL (n) is supplied to the two TFTs of the pixel Pix (n, m). Are connected to the source bus line SL (m) 1, and the source electrodes of the two TFTs of the pixel Pix (n + 1, m) are connected to the source bus line SL (m) 2.

Accordingly, in the liquid crystal display device 100E, as in the liquid crystal display device of the previous embodiment, the voltage of the second subpixel pix (n) B is set using the display signal voltage supplied to the pixels adjacent in the column direction. It cannot be changed.

Therefore, in the liquid crystal display device 100E, the pixel Pix (n, m) is provided with a third TFT whose gate electrode is connected to the gate bus line GL (n + 1). The drain electrodes of the first TFT and the second TFT are connected to the first subpixel electrode and the second subpixel electrode, respectively, while the drain electrode of the third TFT is connected to the first transition capacitor Ctr ( n) connected to the second electrode. Similar to the source electrodes of the first TFT and the second TFT, the source electrode of the third TFT is connected to the source bus line SL (m) 1, and the second TFT of the first transfer capacitor Ctr (n) is connected. A display signal voltage supplied to the pixel Pix (n + 2, m) selected next to the pixel Pix (n, m) is supplied to the electrode.

As shown in FIG. 14, in the liquid crystal display device 100E, adjacent source bus lines, for example, the source bus line SL (m) 1 and the source bus line SL (m) 2, have opposite polarities over one frame period. Display signal voltages (VSL (m) 1, VSL (m) 2) are supplied, and the polarity of each display signal voltage does not change during one frame period. The display signal voltage Vpix (n + 2) is first applied to the pixel Pix (n + 2, m) that is two columns away from the pixel Pix (n, m) in the period when the scanning signal voltage VGL (n + 1) is high. The voltage Vpix (n) B of the second subpixel pix (n) B of the pixel Pix (n, m) is supplied through the transfer capacitor Ctr (n). As a result, a voltage difference of ΔV is generated between the voltage Vpix (n) A of the first subpixel of the pixel Pix (n, m) and the voltage Vpix (n) B of the second subpixel (ΔV = Vpix ( n) A-Vpix (n) B <0).

As shown in FIG. 15, in the liquid crystal display device 100E, the pixel rows to be selected simultaneously are two rows adjacent to each other in the column direction. For example, the scanning signal voltage of the gate bus line GL (1) becomes high at the same time, and the display signal voltage is simultaneously supplied to the uppermost row and the two pixel rows immediately below it in FIG. Next, the scanning signal voltage of the gate bus line GL (2) simultaneously becomes high, and the display signal voltage is simultaneously supplied to the third and fourth pixel rows from the top in FIG. Note that the gate bus line connected to the lower side of each pixel (for example, GL (2) for the pixel in the uppermost row) is connected to the second sub-pixel electrode through the third TFT. A gate bus line is shown.

When two pixel rows adjacent in the column direction are selected simultaneously (display signal voltage is supplied), the display signal voltage supplied to the pixel in the next row is used to change the voltage of the second subpixel. Therefore, it is necessary to use a display signal voltage supplied to pixels separated by two in the column direction. Here, the display signal voltages supplied to each pixel have relatively small variations corresponding to adjacent pixels, and the correlation decreases as the pixels move away. Therefore, it is preferable to change the voltage supplied to the second sub-pixel using the display signal voltage supplied to the adjacent pixel.

Therefore, in the liquid crystal display device 100F shown in FIG. 16, the display area (consisting of a plurality of pixels arranged in a matrix) is divided into, for example, an upper half (upper area) and a lower half (lower area), and at the same time. By using one of the two selected pixel rows as an upper region and the other as a lower region, the display signal voltage supplied to the pixels in the next row adjacent to each other in the column direction is used. The voltage supplied to the pixel is changed.

Specifically, the gate bus line GL (1) is connected to the pixels in the uppermost row in the upper half and the uppermost row in the lower half, and the pixel row to which the display signal voltage is supplied next is A line immediately below the uppermost line in the upper half of the display area and a line immediately below the uppermost line in the lower half of the display area. In this way, the liquid crystal display device 100F can perform display with higher quality than the liquid crystal display device 100E. At this time, in one frame period, the polarity (all the same, for example, negative) of the display signal voltage written to the pixels included in the upper half of each pixel column and the display signal voltage written to the pixels included in the lower half The polarities (all the same, eg positive) are opposite to each other.

Here, an example is shown in which the display area is divided into two upper and lower areas, but the display area may be divided into an even number of areas of 4 or more. However, in one frame period, for example, it is preferable to alternately arrange a region to which a positive display signal voltage is supplied and a region to which a negative display signal voltage is supplied along the column direction. That is, the plurality of pixels arranged in the column direction are divided into an even number of groups, and each of the even number of groups has pixels arranged in succession, and the groups are sequentially numbered from one end in the column direction. Is preferably configured such that display signal voltages having different polarities are supplied from different source bus lines to pixels belonging to the odd-numbered group and pixels belonging to the even-numbered group. . Of course, display signal voltages having different polarities are simultaneously supplied to one pixel belonging to the odd-numbered group and one pixel belonging to the even-numbered group.

Next, an example of a specific structure of the liquid crystal display devices 100E1 and 100E2 according to the embodiment of the present invention will be described with reference to FIGS. The liquid crystal display devices 100E1 and 100E2 exemplified here are used in the previous liquid crystal display device 100E. Further, if the connection relation between the TFT and the source bus line is changed, it can be used for the liquid crystal display device 100F.

FIG. 17 is a schematic plan view of a TFT substrate included in the liquid crystal display device 100E1. Since the basic structure of the liquid crystal display device 100E1 is the same as that of the above-described liquid crystal display device 100A1, the following description will focus on differences from the liquid crystal display device 100A1.

As shown in FIG. 17A, the TFT substrate of the liquid crystal display device 100E1 includes gate bus lines 12 (GL (n), GL (n + 1)) formed on a substrate (for example, a glass substrate), and source bus lines. 14 (SL (m−1) 1, SL (m−1) 2),

TFTs

16A, 16B, and 16C, and subpixel electrodes 10A (n) and 10B (n). The gate bus line GL (n) is disposed between the subpixel electrodes 10A (n) and 10B (n), and is connected to the gate electrodes of the TFT 16A and the TFT 16B. The gate bus line GL (n + 1) is disposed between the subpixel electrodes 10B (n) and 10A (n + 1), and is connected to the gate electrode of the TFT 16C.

The drain electrode of the TFT 16A and the drain electrode of the TFT 16B are led out to substantially the center of the first sub-pixel pix (n) A and the second sub-pixel pix (n) B, respectively, and in the contact holes 15VA and 15VB, the first It is connected to the subpixel electrode 10A (n) and the second subpixel electrode 10B (n). The drain electrode of the TFT 16C is connected to the second electrode 12C of the first transition capacitor Ctr (n) in the contact hole 13VB. The first electrode of the first transition capacitor Ctr (n) is formed by the extended portion 14C of the drain electrode of the TFT 16B. The second electrode 12C of the first transition capacitance Ctr (n) is formed by patterning the same conductive layer as the gate bus line 12, and is covered with the gate insulating layer 13 (see FIG. 11 and FIG. 17). Not shown). Accordingly, the first transition capacitance Ctr (n) is formed at a portion where the second electrode 12C, the gate insulating layer 13, and the extended portion 14C of the drain electrode of the TFT 16B overlap.

FIG. 18 is a schematic plan view of a TFT substrate included in the liquid crystal display device 100E2. The liquid crystal display device 100E2 is different from the liquid crystal display device 100E1 in the configuration of the first transition capacitance Ctr (n).

In the liquid crystal display device 100E2, the second electrode of the first transition capacitance Ctr (n) is formed of the transparent conductive layer 10C (n). The transparent conductive layer 10C (n) is connected to the drain electrode of the TFT 16C through the contact hole 17VB. The first electrode of the first transition capacitor Ctr (n) is formed by the second subpixel electrode 10B (n). The cross-sectional structure of the first transition capacitor Ctr (n) of the liquid crystal display device 100E2 is similar to the cross-sectional structure of the first transition capacitor Ctr (n) of the liquid crystal display device 100A2 shown in FIG. The first transition capacitance Ctr (n) of the liquid crystal display device 100E2 is formed in a region where the transparent conductive layer 10C (n) and the second subpixel electrode 10B (n) overlap with the interlayer insulating layer 17 interposed therebetween.

In the liquid crystal display device 100E2, since the first and second electrodes of the first transition capacitor Ctr (n) are formed of a transparent conductive layer, the region where the liquid crystal layer 20 overlaps the first transition capacitor Ctr (n) It can contribute to the display. Therefore, the liquid crystal display device 100E2 has an advantage that the aperture ratio is higher than that of the liquid crystal display device 100E1.

Next, with reference to FIGS. 19 and 20, the structure and operation of a liquid crystal display device 100G according to still another embodiment of the present invention in which the pixel has three sub-pixels will be described. FIG. 19 is a diagram showing an equivalent circuit of the liquid crystal display device 100G, and FIG. 20 is a diagram schematically showing a scanning signal voltage, a display signal voltage, and a voltage applied to the sub-pixel in the liquid crystal display device 100G.

The pixel Pix (n, m) of the liquid crystal display device 100G includes a third subpixel in addition to the first subpixel pix (n) A, the second subpixel pix (n) B, and the first transfer capacitor Ctr (n) 1. pix (n) C and a second transition capacitor Ctr (n) 2 having a third electrode and a fourth electrode facing each other with a dielectric layer interposed therebetween. The third electrode of the second transition capacitor Ctr (n) 2 is connected to the third subpixel electrode of the pixel, and the fourth electrode of the second transition capacitor of the pixel is the first electrode of the first transition capacitor. Alternatively, it is connected to the second subpixel electrode. Here, the names of the second and third subpixels, the second and third subpixel electrodes, and the first and second transfer capacitors are connected to an electrode to which a display signal voltage is supplied next to the pixel. The second subpixel electrode is the second subpixel electrode, and the transition capacitor connected to the second subpixel electrode is the first transition capacitor. Therefore, the second subpixel, the second subpixel electrode, and the first transition capacitor The position in the pixel is different from the liquid crystal display device 100A shown in FIG.

The liquid crystal display device 100G corresponds to a liquid crystal display device 100A having one TFT, one subpixel electrode, and one transition capacitor added to the liquid crystal display device 100A. The voltage Vpix (n) C applied to the third subpixel pix (n) C is connected in series to the first subpixel electrode of the pixel Pix (n + 1, m), and the first transfer capacitor Ctr (n) 1 and the second transition capacitor Ctr (n) 2, as shown in FIG. 20, the voltage Vpix (n) A of the first subpixel and the voltage Vpix (n) B of the second subpixel are It becomes an intermediate voltage. As a result, a first sub-pixel pix (n) A having a high luminance, a second sub-pixel pix (n) B having a low luminance, and a third sub-pixel pix (n) C having intermediate luminance between them are obtained. .

Next, an example of a specific structure of the liquid crystal display devices 100G1 and 100G2 according to the embodiment of the present invention will be described with reference to FIGS. The liquid crystal display devices 100G1 and 100G2 exemplified here are used in the previous liquid crystal display device 100G.

FIG. 21 is a schematic plan view of a TFT substrate included in the liquid crystal display device 100G1. Since the basic structure of the liquid crystal display device 100G1 is the same as that of the above-described liquid crystal display device 100A1, the following description will focus on differences from the liquid crystal display device 100A1.

As shown in FIG. 21, the TFT substrate of the liquid crystal display device 100G1 includes a gate bus line 12, a source bus line 14,

TFTs

16A, 16B, and 16C formed on a substrate (for example, a glass substrate), first to first. 3 sub-pixel electrodes 10A (n), 10B (n), and 10C (n). The gate bus line GL (n) is provided between the first subpixel electrode 10A (n) and the third subpixel electrode 10C (n), and between the third subpixel electrode 10C (n) and the second subpixel electrode 10B ( n) in two places.

The gate bus line GL (n) between the first subpixel electrode 10A (n) and the third subpixel electrode 10C (n) is connected to the gate electrodes of the

TFTs

16A and 16C. The drain electrodes of the TFT 16A and the TFT 16C are led out to substantially the center of the first subpixel pix (n) A and the third subpixel pix (n) C, respectively. In the contact holes 15VA and 15VC, the first subpixel electrode 10A (n) and the third subpixel electrode 10C (n).

The gate bus line GL (n) between the third subpixel electrode 10C (n) and the second subpixel electrode 10B (n) is connected to the gate electrode of the TFT 16B. The drain electrode of the TFT 16B is drawn to almost the center of the second subpixel pix (n) B, and is connected to the second subpixel electrode 10B (n) in the contact hole 15VB. The drain electrode of the TFT 16B extends to a position overlapping the boundary between the second subpixel electrode 10B (n) and the first subpixel electrode 10A (n + 1), and the first electrode of the first transition capacitor Ctr (n) 1. It is used as 14C1. The second electrode 12C1 of the first transition capacitor Ctr (n) 1 is formed by patterning the same conductive layer as the gate bus line 12, and is covered with the gate insulating layer 13 (see FIG. 11, FIG. 21). (Not shown). The second electrode 12C1 of the first transition capacitor Ctr (n) 1 is connected to the first subpixel electrode 10A (n + 1) in the contact hole 13VA.

The drain electrode of the TFT 16B extends to the lower part of the third subpixel electrode 10C (n), and is connected to the fourth electrode 12C2 of the second transition capacitor Ctr (n) 2 in the contact hole 13VC. The third electrode 14C2 of the second transition capacitor Ctr (n) 2 is an extended portion of the drain electrode of the TFT 16C.

FIG. 22 is a schematic plan view of a TFT substrate included in the liquid crystal display device 100G2. In the liquid crystal display device 100G2, the first subpixel electrode 10A (n), the third subpixel electrode 10C (n), and the second subpixel electrode 10B (n) are formed of different transparent conductive layers. This is different from the liquid crystal display device 100G1. Further, in the liquid crystal display device 100G2, the second subpixel electrode 10B (n) and the first subpixel electrode 10A (n + 1) are interposed via the interlayer insulating layer 17 (see FIG. 12B, not shown in FIG. 22). The first transition capacitor Ctr (n) 1 is formed in the overlapping region, and the second subpixel electrode 10B (n) and the third subpixel electrode 10C (n) overlap with the interlayer insulating layer 17 therebetween. The second transition capacitor Ctr (n) 2 is also different from the liquid crystal display device 100G1 in that the second transition capacitor Ctr (n) 2 is formed.

As can be seen from a comparison between FIG. 22 and FIG. 21, the liquid crystal display device 100G2 has an advantage of a higher aperture ratio than the liquid crystal display device 100G1. In the liquid crystal display device 100G2, the first and second electrodes of the first transition capacitor Ctr (n) 1 and the third and fourth electrodes of the second transition capacitor Ctr (n) 2 are both transparent conductive layers (subpixels). Therefore, the region where the liquid crystal layer 20 overlaps the first transition capacitor Ctr (n) 1 and the first transition capacitor Ctr (n) 2 can also contribute to display. Further, like the liquid crystal display device 100G1, the extension of the electrode for connecting the second electrode 12C1 of the first transition capacitor Ctr (n) 1 to the first subpixel electrode 10A (n + 1) or the contact hole 13VA (see FIG. 21). ), The extension of the electrode for connecting the fourth electrode 12C2 of the second transition capacitance Ctr (n) 2 to the third subpixel electrode 10C (n), and the contact hole 13VC (see FIG. 21). ) Does not need to be formed, and there is no decrease in the aperture ratio.

Next, the structure of the liquid

crystal display devices

200A and 200B according to still another embodiment of the present invention will be described with reference to FIGS. This embodiment can be combined with the liquid crystal display devices of all the embodiments described above.

FIG. 23A is a diagram illustrating an equivalent circuit corresponding to one pixel of the liquid crystal display device 200A, and FIG. 23B is a diagram illustrating an equivalent circuit corresponding to one pixel of the liquid crystal display device 200B. is there.

In the TFT type liquid crystal display device, the potential of the subpixel electrode is drawn by the parasitic capacitance between the gate bus line and the subpixel electrode (generally, the pixel electrode) immediately after the TFT is switched from the on state to the off state. Phenomenon occurs. The change in potential of the sub-pixel electrode due to this pull-in is called “feedthrough voltage”. The magnitude of the feedthrough voltage depends on the magnitude of the capacitance (subpixel capacitance, parasitic capacitance, transfer capacitance, etc.) electrically connected to the TFT. Therefore, when each pixel has two subpixels, it is preferable that the feedthrough voltages of the two subpixels have the same magnitude. The sizes of the two subpixels are appropriately set in consideration of the required γ characteristics and the like, but it is generally preferable that the area of the bright subpixel is smaller than the area of the dark subpixel.

The liquid crystal display device 200A includes a first auxiliary capacitor CcsA connected to the first subpixel electrode of the first subpixel pixA and the first auxiliary capacitor line CcsLA, the second subpixel electrode of the second subpixel pixB, and the second subpixel electrode. It further has a second auxiliary capacitance CcsB connected to the auxiliary capacitance line CcsLB. The magnitude (capacitance) of the first auxiliary capacitance CcsA and the second auxiliary capacitance CcsB and / or the magnitude of the first auxiliary capacitance voltage and the second auxiliary capacitance voltage supplied from the first auxiliary capacitance line CcsLA and the second auxiliary capacitance line CcsLB. By adjusting the height (amplitude), the magnitudes of the feedthrough voltages of the first subpixel pixA and the second subpixel pixB can be made equal. Here, the first auxiliary capacitance line CcsLA and the second auxiliary capacitance line CcsLB are illustrated as wirings that are electrically independent from each other. However, the present invention is not limited to this, and the auxiliary capacitance line (auxiliary capacitance voltage) includes two subpixels. In common, the capacitance value of the first auxiliary capacitor CcsA and the capacitance value of the second auxiliary capacitor CcsB may be made different from each other to adjust only the magnitude of the capacitance value.

Further, as in the liquid crystal display device 200B, a capacitor may be provided between each subpixel electrode and the gate bus line. Since this capacitance is a gate-drain capacitance, it is expressed as a GD capacitance. The liquid crystal display device 200B includes a first GD capacitor CgdA connected to the first subpixel electrode of the first subpixel pixA and the gate bus line GL connected to the TFT to which the first subpixel electrode is connected; It further has a second GD capacitor CgdB connected to the second subpixel electrode of the second subpixel pixB and the gate bus line GL connected to the TFT to which the second subpixel electrode is connected. The capacitance value of the first GD capacitor CgdA and the capacitance value of the second GD capacitor CgdB are made different from each other, and the size of the capacitance value is adjusted to thereby adjust the feedthrough voltage of the first subpixel pixA and the second subpixel pixB. The size can be made equal.

Of course, the structure of the liquid crystal display device 200A and the structure of the liquid crystal display device 200B may be combined.

Next, specific examples of the liquid

crystal display devices

200A and 200B will be described with reference to FIGS. 24 (a) and 24 (b). FIG. 24A is a schematic plan view of a TFT substrate included in the liquid crystal display device 200A1, and FIG. 24B is a schematic plan view of a TFT substrate included in the liquid crystal display device 200B1.

A liquid crystal display device 200A1 shown in FIG. 24A is obtained by applying the structure of the liquid crystal display device 200A to the liquid crystal display device 100A1 shown in FIG.

In the liquid crystal display device 200A1, the first auxiliary capacitance line CcsLA and the second auxiliary capacitance line parallel to the gate bus line 12 are provided at approximately the center of each of the first subpixel electrode 10A (n) and the second subpixel electrode 10B (n). The capacitor wiring CcsLB is included. The first auxiliary capacitance line CcsLA and the second auxiliary capacitance line CcsLB are formed of the same conductive layer as the gate bus line 12 and are covered with the gate insulating layer 13 (see FIG. 11). The first auxiliary capacitance line CcsLA has a wide portion 18A at a position overlapping the contact hole 15VA, and the extended portion of the drain electrode of the TFTA overlaps with the wide portion 18A and the gate insulating layer 13 therebetween. Yes. This portion forms the first auxiliary capacitor CcsA. Similarly, the second auxiliary capacitance line CcsLB has a wide portion 18B at a position overlapping the contact hole 15VB, and the extended portion of the drain electrode of the TFTB with the wide portion 18B and the gate insulating layer 13 interposed therebetween. Are overlapping. This portion forms a second auxiliary capacitor CcsB.

It goes without saying that the configurations of the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB are not limited to this, and various known configurations can be applied.

A liquid crystal display device 200B1 shown in FIG. 24B is obtained by applying the structure of the liquid crystal display device 200B to the liquid crystal display device 100A1 shown in FIG.

In the liquid crystal display device 200B1, the gate bus line 12 has

wide portions

12A and 12B. A portion where the wide portion 12A of the gate bus line 12 and the extended portion of the drain electrode of the TFTA overlap with each other via the gate insulating layer 13 (see FIG. 11) forms the first GD capacitor CgdA. . Similarly, a portion where the wide portion 12B of the gate bus line 12 and the extended portion of the drain electrode of the TFTB overlap with each other via the gate insulating layer 13 (see FIG. 11) forms the second GD capacitor CgdB. is doing.

It goes without saying that the configurations of the first GD capacitor CgdA and the second GD capacitor CgdB are not limited to this, and various known configurations can be applied.

Further, as is apparent from FIGS. 24A and 24B, a liquid crystal display device having the first auxiliary capacitor CcsA and the second auxiliary capacitor CcsB, and the first GD capacitor CgdA and the second GD capacitor CgdB is easily manufactured. be able to.

Next, the structure of a liquid crystal display device according to still another embodiment of the present invention will be described with reference to FIGS. This embodiment can be combined with the liquid crystal display devices of all the embodiments described above.

FIG. 25A is a diagram illustrating an equivalent circuit of a liquid crystal display device 300 according to still another embodiment of the present invention, and FIG. 25B is a diagram illustrating source bus lines SL and TFTs (T1, T1, T) in the liquid crystal display device 300a. It is a schematic diagram which shows the connection relationship (series) with T2). FIG. 25C is a schematic diagram showing the connection relationship (parallel) between the source bus line SL and the TFTs (T1, T2) in all the previous embodiments.

In the liquid crystal display device 300 shown in FIG. 25A, either the first TFT (T1) or the second TFT (T2) (here, T2) is connected to the common source bus line SL via the other (here, T1). It is connected to the. That is, the TFT (T1) and the TFT (T2) are connected in series to the common source bus line SL. By adopting such a configuration, the parasitic capacitance C _SG formed between the gate bus line GL and the source bus line SL can be reduced as in the liquid crystal display device 300a shown in FIG. For example, in the liquid crystal display device 100a shown in FIG. 25C, since the TFT (T1) and the TFT (T2) are connected in parallel to the common source bus line SL, the gate bus line GL and the source bus line SL are connected. The parasitic capacitance C _SG formed between the two is large. In the liquid crystal display devices of all the embodiments described above, the parallel connection shown in FIG. 25 (c) is adopted. Therefore, by adopting the series connection shown in FIG. 25 (b), the parasitic capacitance C _SG is adopted. Can be reduced.

Note that when the series connection shown in FIG. 25B is adopted, the current supplied from the TFT (T2) to the second subpixel electrode is reduced as compared with the case of the parallel connection. At this time, as the TFT (T1 and T2), for example, a TFT having an oxide semiconductor layer containing an IGZO-based semiconductor is preferably used. Since the mobility of the oxide semiconductor layer is about 10 times that of the amorphous silicon layer, a sufficient charging capability can be obtained. Needless to say, the semiconductor layer is not limited to the oxide semiconductor layer, and a known semiconductor layer such as a microcrystalline silicon layer can be used.

Next, an example of a method for obtaining a display signal voltage based on an input video signal in the liquid crystal display device according to the embodiment of the present invention will be described with reference to FIG.

As described above, the liquid crystal display according to the embodiment of the present invention uses the display signal voltage supplied to the pixel selected next to a certain pixel to measure the magnitude of the voltage applied to the two sub-pixels ( Since the absolute values are different, the difference between the two sub-pixels depends on the magnitude (absolute value) and polarity (sign) of the display signal voltage supplied next to the pixel.

Accordingly, when a driving circuit (not shown) included in the liquid crystal display device according to the embodiment of the present invention receives an input video signal and generates a display signal based on the input video signal, a display signal voltage supplied to a certain pixel. As a function of the display signal voltage supplied next to a pixel.

For example, in a liquid crystal display device in which a bright subpixel of a certain pixel Pix (n) is connected to a dark subpixel of a pixel Pix (n + 1) adjacent to the pixel in the column direction via a transfer capacitor Ctr (n), Consider a case where 128 gradations are displayed with Pix (n) and 128 gradations are displayed with Pix (n + 1) and 255 gradations are displayed (Case A and Case B in Table 1 below). The displayable gradations are 0 to 255 gradations, and the transmittance in Table 1 shows a relative value with the transmittance being 1 at 255 gradations. The voltage indicates a voltage finally applied to the liquid crystal layer of each sub-pixel, and the unit is V (volt). The voltage is obtained by the above formulas (1) and (2). Here, α in equation (2) was set to 0.205. The area ratio between the bright subpixel and the dark subpixel was 1 (bright): 2 (dark).

Case A is a case where the same pixel (Pix (n)) and the next pixel (Pix (n + 1)) display the same 128 gradations. In case A, VSL (n) = Vpix (n) A = Vpix (n + 1) A = 2.44V, and from the above equation (2), Vpix (n) B = 2.44 + 0.205 · 2.2 · 2. 44 = 3.44. That is, when displaying 128 gradations, the gradation data of the input video signal is converted from 128 gradations to 56 gradations, and the display signal voltage (2.44 V) corresponding to the 56 gradations is converted to the own pixel Pix ( n).

Case B is a case in which 128 gradations are displayed for the own pixel (Pix (n)) and 255 gradations are displayed for the next pixel (Pix (n + 1)). Case B1 is a case where the same gradation conversion as in case A is performed.

That is, when the own pixel (Pix (n)) displays 128 gradations, the next pixel (Pix (n + 1)) displays 255 gradations (the corresponding display signal voltage is 5.50 V). Also, the display signal voltage (2.44 V) corresponding to the 56 gradations is supplied to the own pixel (Pix (n)). Then, from the above equation (2), Vpix (n) B = 2.44 + 0.205 · 2.5.50 = 4.70V. As a result, as shown in FIG. 26A, the display gradation of the bright sub-pixel of the own pixel (Pix (n)) is 243 gradations, and the entire own pixel (Pix (n)) has 153 gradations. Display is performed, and a deviation occurs from the 128 gradations to be displayed.

Therefore, as shown in case B2, when the next pixel (Pix (n + 1)) displays 255 gradations, the gradation data of the input video signal is converted from 128 gradations to 0 gradations, A display signal voltage (1.26V) corresponding to the tone is supplied to the own pixel (Pix (n)). Then, from the above equation (2), Vpix (n) B = 1.26 + 0.205 · 2 · 5.50 = 3.52, and the bright subpixel of its own pixel (Pix (n)) has 211 gradations. indicate. As a result, as shown in FIG. 26B, 128 gradations can be displayed in the entire self pixel (Pix (n)).

The conversion for obtaining the table signal voltage described above is performed by using a look that stores data of a preset display signal voltage in accordance with the gradation data of the input video signal (gradation data of the current horizontal scanning period and the next horizontal scanning period). It may be performed using an up table, or may be performed by calculation based on the gradation data of the input video signal.

As described above, in the liquid crystal display device according to the embodiment of the present invention, as in the liquid crystal display device described in Patent Document 1, auxiliary capacitors that are electrically independent from each other are provided for each subpixel, and the auxiliary capacitors are provided. It is not necessary to change the counter voltage so as to satisfy a predetermined condition. That is, it is possible to suppress a decrease in aperture ratio due to the provision of an electrically independent auxiliary capacity wiring and / or an increase in power consumption due to a change in the auxiliary capacity counter voltage (for example, a constant period of vibration).

The liquid crystal display device according to the embodiment of the present invention is used for various applications, and is particularly preferably used for mobile applications.

10A, 10B Subpixel electrode 12 Gate bus line 12C Second electrode of first transition capacitor 13 Gate insulating layer 14 Source bus line 14C First electrode of first transition capacitor 14DA, 14DB Drain electrode 14SA, 14SB Source electrode 15 Interlayer insulating layer 15VA,

15VB Contact hole

16A, 16B TFT
20 liquid crystal layer 30 counter electrode 100 liquid crystal display device Pix (n, m) pixel pix (n) A first subpixel pix (n) B second subpixel Ctr (n) first transition capacitance

Claims

A plurality of pixels arranged in a matrix having rows and columns, a plurality of TFTs, a plurality of gate bus lines, and a plurality of source bus lines;
Each of the plurality of pixels includes a first subpixel having a first subpixel electrode, a second subpixel having a second subpixel electrode, and a first electrode and a second electrode facing each other through a dielectric layer. A first transition capacity having
The first electrode of the first transition capacitor of a certain pixel is connected to the second subpixel electrode of the certain pixel, and the second electrode of the first transition capacitor of the certain pixel is the certain pixel A liquid crystal display device connected to an electrode to which a display signal voltage is supplied next.
2. The liquid crystal display device according to claim 1, wherein the second electrode of the first transition capacitor of the certain pixel is connected to the first subpixel electrode of a pixel adjacent to the certain pixel in a column direction.
3. The liquid crystal display device according to claim 1, wherein a display signal voltage supplied to the certain pixel and a display signal voltage supplied next to the certain pixel have opposite polarities.
3. The liquid crystal display device according to claim 1, wherein the display signal voltage supplied to the certain pixel and the display signal voltage supplied next to the certain pixel have the same polarity.
The first subpixel electrode and the second subpixel electrode of the certain pixel and the first subpixel electrode and the second subpixel electrode of the pixel adjacent to the certain pixel in the column direction are the same source bus line The liquid crystal display device according to claim 1, wherein the liquid crystal display device is connected to the liquid crystal display device.
The first subpixel electrode and the second subpixel electrode of a plurality of pixels constituting a certain column are connected to different source bus lines for every k consecutive rows (k is an integer of 2 or more). A liquid crystal display device according to 1.
Display signal voltages having different polarities are simultaneously supplied from two different source bus lines to two pixels adjacent in the column direction.
2. The liquid crystal display device according to claim 1, wherein a display signal voltage supplied to two pixels separated in a column direction of the certain pixel is supplied to the second electrode of the first transition capacitor of the certain pixel. .
The plurality of pixels arranged in the column direction are divided into an even number of groups, and each of the even number of groups has pixels arranged in succession,
When numbers are assigned to groups in order from one end in the column direction, display signal voltages having different polarities are supplied from different source bus lines to pixels belonging to the odd-numbered group and pixels belonging to the even-numbered group. ,
2. The liquid crystal display device according to claim 1, wherein display signal voltages having different polarities are simultaneously supplied to one pixel belonging to the odd-numbered group and one pixel belonging to the even-numbered group.
Each of the plurality of pixels further includes a third subpixel having a third subpixel electrode, and a second transition capacitor having a third electrode and a fourth electrode facing each other through a dielectric layer,
The third electrode of the second transition capacitor of the pixel is connected to the third subpixel electrode of the pixel, and the fourth electrode of the second transition capacitor of the pixel is the second electrode. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is connected to the first electrode or the second subpixel electrode having one transition capacitance.
The apparatus further comprises a first auxiliary capacitor connected to the first subpixel electrode and a first auxiliary capacitor line, and a second auxiliary capacitor connected to the second subpixel electrode and a second auxiliary capacitor line. Item 10. The liquid crystal display device according to any one of Items 1 to 9.
11. The liquid crystal display device according to claim 10, wherein the first auxiliary capacitor and the second auxiliary capacitor have different capacitance values.
12. The liquid crystal display device according to claim 10, wherein the first auxiliary capacitance line and the second auxiliary capacitance line are electrically independent from each other.
A first GD capacitor connected to the first subpixel electrode and a gate bus line connected to a TFT to which the first subpixel electrode is connected; the second subpixel electrode; and the second subpixel electrode. The liquid crystal display device according to claim 10, further comprising a second GD capacitor connected to a gate bus line connected to a TFT to which a pixel electrode is connected.
A first TFT connected to the first subpixel electrode; and a second TFT connected to the second subpixel electrode. The first TFT and the second TFT are connected to a common gate bus line. The liquid crystal display device according to claim 1.
A first TFT connected to the first subpixel electrode; and a second TFT connected to the second subpixel electrode. The first TFT and the second TFT are connected to a common source bus line. The liquid crystal display device according to claim 1.
16. The liquid crystal display device according to claim 15, wherein one of the first TFT and the second TFT is connected to the common source bus line through the other.
The liquid crystal display device according to claim 1, wherein the plurality of TFTs include an oxide semiconductor layer.
And a driving circuit that receives an input video signal and generates a display signal based on the input video signal, the display signal including a display signal voltage corresponding to each pixel. The liquid crystal display device according to claim 1, wherein a display signal voltage supplied to the certain pixel is obtained as a function of a display signal voltage supplied next to the certain pixel.