WO2013088636A1 - Soiウェーハの製造方法 - Google Patents
Soiウェーハの製造方法 Download PDFInfo
- Publication number
- WO2013088636A1 WO2013088636A1 PCT/JP2012/007267 JP2012007267W WO2013088636A1 WO 2013088636 A1 WO2013088636 A1 WO 2013088636A1 JP 2012007267 W JP2012007267 W JP 2012007267W WO 2013088636 A1 WO2013088636 A1 WO 2013088636A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- ion implantation
- soi
- soi wafer
- temperature
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68764—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68771—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting more than one semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Definitions
- the present invention relates to a method for manufacturing an SOI wafer, and in particular, a method for manufacturing an SOI wafer by bonding a silicon single crystal wafer implanted with hydrogen ions or the like to a base wafer serving as a support substrate through an oxide film and then peeling the wafer.
- a silicon single crystal wafer implanted with hydrogen ions or the like to a base wafer serving as a support substrate through an oxide film and then peeling the wafer.
- an ion implantation separation method a technique also called a smart cut method (registered trademark)
- a gas such as hydrogen ions or rare gas ions is formed from the upper surface of one silicon wafer (bond wafer).
- ions are implanted to form a microbubble layer (encapsulation layer) inside the wafer
- the surface into which the ions are implanted is brought into close contact with the other silicon wafer (base wafer) through an oxide film, and then heat treatment is performed.
- an SOI wafer having a good mirror surface as a cleavage plane (peeling surface) and high uniformity in the thickness of the SOI layer can be obtained relatively easily.
- polishing polish Removal: about 100 nm
- a flattening process for improving the surface roughness by performing a high-temperature heat treatment instead of the touch polish has been performed.
- a heat treatment in a reducing atmosphere containing hydrogen rapid heating / rapid cooling heat treatment (RTA treatment)
- RTA treatment rapid cooling heat treatment
- the SOI wafer after peeling is subjected to sacrificial oxidation treatment after planarization heat treatment in an inert gas, hydrogen gas, or mixed gas atmosphere thereof, thereby planarizing the peeled surface and OSF. Achieving avoidance at the same time.
- a flattening process that improves the surface roughness by performing a high-temperature heat treatment has been performed, and at present, the SOI layer thickness Range (maximum in-plane) is 300 mm in diameter.
- An SOI wafer having excellent film thickness uniformity within 3 nm (a value obtained by subtracting the minimum value from the value) has been obtained at the mass production level by the ion implantation delamination method.
- the depth (range) distribution of ion implantation is directly reflected in the film thickness distribution of the SOI layer after delamination, but the depth distribution of ion implantation occurs.
- the cone angle effect is known.
- the batch type ion implanter includes a rotating body 1 and a plurality of wafer holders 2 provided on the rotating body 1 and on which a substrate 3 is arranged.
- the wafer holder 2 is slightly inclined inward from the rotating surface of the rotating body 1.
- the second cause of film thickness distribution is that channeling occurs in the manufacture of Thin BOX type SOI wafers.
- the effect of scattering by the oxide film is weakened, and channeling occurs in ion implantation with an implantation angle of 0 degree.
- the crystal plane and the angle of the ion beam are perpendicular to the center of the substrate, so that the effect of channeling is increased and the ion implantation depth is increased.
- the implantation angle is generated by the cone angle at both ends of the substrate in the scanning direction, the influence of channeling becomes relatively weak and the ion implantation depth becomes shallow.
- the effect of the cone angle is particularly emphasized by channeling.
- a method of injecting at an inclined injection angle is generally known.
- the cone angle effect differs between the two ends of the substrate in the scanning direction.
- the distribution becomes large.
- the SOI film thickness distribution of the SOI wafer after delamination is Concentric convex film thickness distribution which is thick at the part and thin at the outer peripheral part of the wafer.
- a thermal oxide film is removed by sacrificial oxidation treatment (thermal oxidation + oxide film removal).
- thermal oxide film is removed by sacrificial oxidation treatment (thermal oxidation + oxide film removal).
- thermal oxide film is removed by sacrificial oxidation treatment (thermal oxidation + oxide film removal).
- thermal oxide film thermal oxide film
- an in-plane distribution of a thermal oxide film cannot be used to obtain a convex shape, and an oxidation furnace or processing batch in which a convex-shaped oxide film distribution that offsets the film thickness distribution during wafer peeling is formed.
- productivity is necessary to experimentally find a specific boat slot position and selectively use it to perform sacrificial oxidation treatment.
- the present invention has been made in view of the above problem, and forms a thermal oxide film having a substantially concentric film thickness distribution, and performs sacrificial oxidation treatment to remove the formed thermal oxide film, thereby providing a surface.
- An object of the present invention is to provide an SOI wafer manufacturing method capable of manufacturing an SOI wafer having an improved inner film thickness distribution with high productivity.
- the SOI layer of the SOI wafer is reduced in thickness by subjecting the SOI wafer to thermal oxidation on the surface of the SOI layer and performing sacrificial oxidation treatment to remove the formed thermal oxide film.
- a method for manufacturing an SOI wafer having a step of adjusting Forming a substantially concentric oxide film thickness distribution on the surface of the SOI layer by performing thermal oxidation in the sacrificial oxidation treatment at least during temperature increase and temperature decrease using a batch heat treatment furnace.
- a thermal oxide film having a substantially concentric oxide film thickness distribution can be formed. Therefore, for example, the in-plane film thickness distribution of the SOI layer caused by ion implantation delamination can be offset, and the final obtained SOI wafer with a greatly improved in-plane film thickness distribution is mass-produced. Can be manufactured.
- the thermal oxidation in the sacrificial oxidation process is performed at a predetermined temperature and at least one of the temperature rising to the predetermined temperature and the temperature falling from the predetermined temperature.
- the thermal oxidation during the temperature decrease and / or the thermal oxidation during the temperature increase is performed in combination with an oxidation treatment at a predetermined temperature performed by conventional sacrificial oxidation. That is, thermal oxidation is performed 1) during temperature increase to a predetermined temperature + predetermined temperature + temperature lowering from a predetermined temperature 2) during temperature increase to a predetermined temperature + predetermined temperature 3) predetermined temperature + during temperature decrease from a predetermined temperature It is preferable to carry out either of these. Thereby, a thicker concentric thermal oxide film can be formed.
- pyrogenic oxidation treatment or wet oxidation treatment can be used as thermal oxidation in the sacrificial oxidation treatment.
- the sacrificial oxidation treatment can be performed by forming a thermal oxide film by pyrogenic oxidation treatment or wet oxidation treatment and removing the formed thermal oxide film.
- the SOI wafer subjected to the sacrificial oxidation treatment is formed by ion-implanting at least one kind of gas ions of hydrogen ions and rare gas ions from the surface of the bond wafer made of silicon single crystal, It is preferable to manufacture by bonding the ion-implanted surface of the bond wafer and the surface of the base wafer through an insulating film, and then peeling the bond wafer with the ion-implanted layer.
- the sacrificial oxidation treatment according to the present invention is very effective for an SOI wafer manufactured by the ion implantation separation method having the influence of the cone angle effect or channeling.
- a heat treatment is applied at a temperature of about 500 ° C. or higher in an inert gas atmosphere, the bond wafer can be peeled off by the ion implantation layer.
- plasma treatment on the bonding surface at room temperature in advance, it is possible to perform peeling by applying external force without performing heat treatment (or after performing heat treatment not to peel).
- the ion implantation includes a rotating body and a plurality of wafer holders arranged on the rotating body and arranged on the substrate, and is a batch in which ions are implanted into a plurality of revolving substrates arranged on the wafer holder. It is assumed that it is divided into a plurality of times using an ion implanter, and after each ion implantation, the bond wafer arranged on the wafer holder is rotated by a predetermined rotation angle, and the rotation is subsequently performed at the arranged position. It is preferable to perform ion implantation.
- the bond wafer can be loaded into the wafer holder in a different direction for each ion implantation, and by avoiding ion implantation at overlapping positions.
- the variation in the ion implantation depth distribution can be improved, and the in-plane film thickness distribution after peeling becomes close to a concentric distribution. Therefore, by performing the sacrificial oxidation process in the present invention and controlling the oxide film thickness distribution of the thermal oxide film to a substantially concentric shape after that, it becomes easier to improve the SOI film thickness distribution than immediately after peeling. Furthermore, an SOI wafer with an improved film thickness Range can be obtained.
- the ion implantation is performed in two steps, and after the first ion implantation, the bond wafer is rotated 90 degrees or 180 degrees, and the second ion implantation is performed at the rotated arrangement position. Is preferred.
- the film thickness distribution can be easily corrected by the film thickness reduction adjustment by the sacrificial oxidation treatment in the present invention.
- the ion implantation is performed in four steps, and the second and subsequent ion implantations are rotated by any rotation angle of 90, 180, or 270 degrees with respect to the first ion implantation. Preferably it is done in position.
- the variation can be further reduced as compared with the case in which the ion implantation is performed in two times, and the ion implantation depth distribution becomes closer to a concentric circular distribution.
- the film thickness distribution can be corrected more easily by adjusting the film thickness reduction by the sacrificial oxidation treatment.
- the insulating film is preferably a silicon oxide film having a thickness of 100 nm or less.
- the in-plane film thickness Range is used.
- the ion implantation is preferably performed each time by setting the angle between the crystal plane of the surface of the bond wafer and the ion implantation direction to be vertical.
- the film thickness distribution of the SOI layer after peeling is changed. Variations can be further suppressed. Therefore, it is preferable because the film thickness distribution can be more easily corrected by the film thickness reduction adjustment by the sacrificial oxidation process in the present invention.
- the SOI wafer manufacturing method of the present invention it is possible to form a thermal oxide film having a substantially concentric film thickness distribution in the thermal oxidation of the sacrificial oxidation process. Accordingly, since an SOI wafer having a dramatically improved film thickness uniformity can be manufactured at a mass production level, the threshold voltage of a device using such an SOI wafer can be stabilized and the device yield can be improved. .
- the process flowchart which showed an example of the manufacturing method of the SOI wafer of this invention is shown. It is explanatory drawing of the film thickness distribution improvement by multiple times (2 times) ion implantation peeling and sacrificial oxidation process in this invention. It is the graph which showed thermal oxidation conditions in Examples 1 and 2 and a comparative example. It is the figure which showed the oxide film thickness distribution of the thermal oxide film after the thermal oxidation (1) in Example 1, 2 and thermal oxidation (2).
- a schematic view of a batch type ion implantation apparatus is shown. It is explanatory drawing explaining a cone angle effect.
- an oxide film having a substantially concentric film thickness distribution capable of canceling the substantially concentric film thickness distribution (for example, convex shape) of the SOI layer of the SOI wafer caused by ion implantation separation or the like.
- an SOI wafer manufacturing method capable of manufacturing an SOI wafer with an improved in-plane film thickness distribution with good productivity by performing a sacrificial oxidation treatment that can be formed.
- the inventors of the present invention As a result of earnest examination and research on the method of controlling and producing a substantially concentric circular thermal oxide film, the inventors of the present invention, as a result, in a batch-type heat treatment furnace, when the oxidation treatment is performed at a temperature drop or a temperature rise, a substantially concentric circle shape is obtained. It was found that the oxide film thickness distribution is easily formed in the plane. That is, the present invention includes a step of performing a sacrificial oxidation process on the SOI wafer by thermally oxidizing the surface of the SOI layer and removing the formed thermal oxide film, thereby adjusting the thickness of the SOI layer of the SOI wafer.
- the thermal oxidation in the sacrificial oxidation treatment is performed at least during the temperature rise and the temperature fall using a batch heat treatment furnace, so that the surface of the SOI layer has a substantially concentric shape.
- An SOI wafer manufacturing method characterized by forming an oxide film thickness distribution is provided. The present invention will be described in detail below.
- FIG. 1 is a process flow diagram showing an example of a method for manufacturing an SOI wafer according to the present invention.
- a method for manufacturing an SOI wafer for performing the sacrificial oxidation treatment in the present invention is not particularly limited, but an ion implantation separation method can be used.
- FIG. 1 shows a process flow diagram of an SOI wafer manufacturing method of the present invention when an ion implantation delamination method is used.
- an ion implantation layer is formed by ion implantation of at least one kind of gas ions of hydrogen ions and rare gas ions from the surface of a bond wafer made of silicon single crystal (ion implantation step).
- hydrogen molecular ions are also included in “hydrogen ions”.
- an insulating film in advance on the surface of the bond wafer before ion implantation.
- the effect of cone angle is emphasized by channeling.
- a thin BOX type thin film SOI wafer was prototyped and the transition of the in-plane film thickness range of the SOI was investigated. As a result, it was found that the in-plane film thickness range had already exceeded 1 nm immediately after peeling.
- the bond wafer is a silicon single crystal wafer having a diameter of 300 mm or more in which the cone angle effect is remarkable and the insulating film is a silicon oxide film of 100 nm or less, or 50 nm or less, the film thickness is excellent.
- Thin BOX type thin film SOI wafers can be manufactured.
- the batch type ion implanter 10 includes a rotating body 1 and a plurality of wafer holders 2 provided on the rotating body 1 and on which a substrate 3 is arranged, and a plurality of substrates 3 arranged and revolved on the wafer holder 2. Ion implantation.
- ion implantation into the bond wafer 3 in the ion implantation step is performed in a plurality of times, and after each ion implantation, It is preferable that the bond wafer 3 disposed on the holder 2 is rotated by a predetermined rotation angle, and the next ion implantation is performed at the rotated position.
- FIG. 1A shows an example in which ion implantation is performed n times (n ⁇ 2). After the first ion implantation, the bond wafer 3 is rotated 90 ° (notch 3 ′ position is 90 °), and the second ion implantation is performed at the rotated arrangement position.
- the ion implantation depth is relatively deep in the center of the bond wafer and the outer periphery of the bond wafer is the entire circumference. Shallow, uniform distribution, close to concentric distribution.
- the ion implantation is not limited to two times, and ion implantation is performed in four times, and the second and subsequent ion implantations are performed at any rotation angle of 90, 180, and 270 degrees with respect to the first ion implantation.
- the distribution of concentric circles is more uniform than in the case of double injection by performing the rotation at the position where only the rotation is performed.
- the crystal axis orientation of the bond wafer to be used is slightly shifted due to the influence of processing accuracy, even if the implantation angle is set to 0 degrees with respect to the wafer surface, the crystal axis and the ion beam actually have an angle. . For this reason, since the two-fold symmetrical distribution in the scanning direction is broken, the depth distribution of concentric circles may not be obtained by the two-fold divided injection. In this case, if the wafer orientation of the two-time split implantation is set to 180 degrees, the crystal axis deviation can be canceled out, so that a concentric distribution can be obtained.
- the influence of the crystal axis shift can be further suppressed by setting the angle that offsets the crystal axis shift (off-angle) as the ion beam implantation angle. That is, by making the angle between the crystal plane of the bond wafer surface and the ion implantation direction perpendicular (setting the ion implantation angle with respect to the crystal plane to 0 degree), variation in the film thickness distribution of the thin film after the peeling process is reduced. Further, it can be suppressed, which is preferable.
- the ion-implanted surface of the bond wafer and the surface of the base wafer are bonded together via an insulating film (bonding step).
- a silicon single crystal wafer can be used as the base wafer, but is not particularly limited. Normally, the wafers are bonded to each other without using an adhesive or the like by bringing the surfaces of the bond wafer and the base wafer into contact with each other in a clean atmosphere at room temperature.
- an SOI wafer having an SOI layer on the base wafer is manufactured by peeling the bond wafer with an ion implantation layer (peeling step). For example, if heat treatment is performed at a temperature of about 500 ° C. or higher in an inert gas atmosphere, the bond wafer can be peeled off by the ion implantation layer. In addition, by performing plasma treatment on the bonding surface at room temperature in advance, it is possible to perform peeling by applying external force without performing heat treatment (or after performing heat treatment not to peel).
- the SOI layer immediately after such a peeling process has a large diameter of 300 mm or 450 mm, and even if it is a Thin BOX type with an insulating film of 100 nm or less, the film thickness distribution is improved such that the film thickness is 1 nm or less. In particular, the film thickness distribution is close to a concentric shape.
- the SOI layer surface of the SOI wafer is subjected to sacrificial oxidation treatment for thermally oxidizing the surface of the SOI layer and removing the formed thermal oxide film. Adjust the thickness reduction.
- the thermal oxidation in the sacrificial oxidation treatment is performed at least during the temperature rise and the temperature fall using a batch heat treatment furnace, so that the surface of the SOI layer is oxidized in a substantially concentric shape. A film thickness distribution is formed.
- the outer peripheral portion of the wafer is more likely to dissipate heat than the central portion of the wafer, resulting in a relatively low temperature. Therefore, when thermal oxidation is performed during the temperature drop, the oxide film thickness distribution of the thermal oxide film is a convex, substantially concentric circle.
- the convex shape formed by the temperature drop oxidation has a high temperature during the temperature drop oxidation, a large temperature difference between the initial temperature and the end of the oxidation, a strong temperature gradient, and a large gap between the upper surface wafer in the batch.
- a convex, substantially concentric circular shape having a desired distribution within the oxide film thickness is obtained.
- a thermal oxide film is obtained.
- a batch type heat treatment for obtaining a substantially concentric thermal oxide film thickness distribution it is preferable to use a vertical heat treatment furnace having a mechanism for horizontally rotating a wafer being thermally oxidized on the wafer surface.
- the ion implantation depth is relatively deep in the center portion of the bond wafer and the outer periphery portion of the bond wafer is shallow all around, and is uniform.
- the distribution is close to the distribution of convex concentric circles. Therefore, if an SOI wafer having a convex film thickness distribution immediately after peeling is thermally oxidized by the above-described temperature-fall oxidation and the formed thermal oxide film is removed, the SOI film thickness distribution is controlled and improved. can do.
- FIG. 2 illustrates an in-plane film thickness distribution of the SOI layer in the case where ion implantation is performed twice and then sacrificial oxidation treatment by temperature-fall oxidation is performed.
- sacrificial oxidation treatment and planarization heat treatment (high temperature heat treatment in an atmosphere of inert gas, hydrogen gas, or a mixed gas thereof) May be performed in combination.
- planarization heat treatment the SOI layer is slightly etched, but at this time, the etching amount is larger in the outer peripheral portion of the wafer than in the central portion of the wafer. Therefore, the SOI film thickness distribution after the planarization heat treatment is convex. Tends to deteriorate by about 0.5 to 2 nm. Therefore, if the sacrificial oxidation in the present invention is applied, the SOI film thickness distribution deteriorated during the planarization heat treatment can be improved.
- oxidation treatment temperature increase oxidation
- the temperature during the temperature increase is relatively higher in the outer peripheral portion near the heater than in the central portion.
- a concave in-plane distribution is obtained for the oxide film thickness.
- the size of the concave shape can also be controlled by the temperature at which the temperature is oxidized, the temperature difference between the initial temperature and the end of oxidation, the temperature gradient, and the size of the gap between the upper surface wafer in the batch (Slot interval). .
- the film thickness distribution of the SOI wafer Thermal oxidation can be adapted to improve the temperature.
- the thermal oxidation in the sacrificial oxidation treatment is preferably performed at a predetermined temperature and at least one of the temperature rising to the predetermined temperature and the temperature falling from the predetermined temperature. That is, the temperature decrease or temperature increase oxidation can be performed before or after the oxidation at a predetermined temperature (for example, 800 ° C. to 1000 ° C.) performed as an oxidation process such as conventional sacrificial oxidation, or the temperature decrease oxidation or temperature increase as a single process. It is also possible to carry out only the thermal oxidation treatment. By performing thermal oxidation for a predetermined time at a predetermined temperature, the thickness of the oxide film to be formed can be increased, and the temperature and time can be adjusted according to the required reduction margin.
- the temperature increase / decrease rate can be set to 0.1 to 10 ° C./min, for example.
- temperature-raising oxidation that is, (oxidation at a predetermined temperature) + (temperature-raising oxidation from a predetermined temperature)
- temperature-raising oxidation can be performed while raising the temperature to a temperature higher than the predetermined temperature.
- Example 1 In Example 1, a buried oxide film of 25 nm is formed on a silicon wafer having a crystal orientation of ⁇ 100> and having a diameter of 300 mm (surface crystal plane is (100) just, no angular deviation), and then hydrogen ion implantation is performed. went. The ion implantation is divided into two using a batch type ion implanter, and the implantation of H + , 30 keV, 2.6e16 cm ⁇ 2 , implantation angle 0 degree, and notch orientation angle 0 degree is performed as the first implantation. As the second injection, the injection was performed at H + , 30 keV, 2.6e16 cm ⁇ 2 , an injection angle of 0 degree, and a notch orientation angle of 90 degrees.
- the hydrogen ion implantation After the hydrogen ion implantation, it was bonded to the base wafer and peeled off at the hydrogen ion implanted layer by a nitrogen atmosphere heat treatment at 500 ° C. for 30 minutes. Then, as shown in FIG. 3, the temperature-fall oxidation process which continues the pyrogenic oxidation process to 850 degreeC at the time of the temperature drop after 900 degreeC pyrogenic oxidation process was performed (thermal oxidation (1)).
- the oxide film thickness after thermal oxidation was 250 nm.
- the in-plane oxide film thickness Range (Max-Min) was 1.1 nm due to the temperature-decreasing oxidation treatment, the center part was thick, and the outer part was thin. It was a distribution of concentric circles. Then, after performing the planarization heat processing in Ar atmosphere, the oxidation by the conventional fixed temperature of 950 degreeC was performed (thermal oxidation (2)). The in-plane oxide film thickness Range after the oxidation treatment was 0.9 nm. Regarding the film thickness distribution of 10 nm SOI after the sacrificial oxide film removal, the in-plane SOI film thickness distribution was 0.7 nm in range, and a good in-plane distribution was obtained.
- Example 2 After performing ion implantation separation in the same manner as in Example 1, as shown in FIG. 3, oxidation was performed at a conventional constant temperature of 900 ° C. (thermal oxidation (1)).
- the oxide film thickness after thermal oxidation was 250 nm.
- the concentric circle distribution was broken and the in-plane oxide film thickness Range was 0.4 nm.
- the temperature-fall oxidation process which continues the oxidation process by pyrogenic to 900 degreeC at the time of the temperature drop after the pyrogenic oxidation process of 950 degreeC was performed (thermal oxidation (2)).
- the oxide film thickness after thermal oxidation was 440 nm.
- the in-plane oxide film thickness Range (Max-Min) obtained by the temperature drop oxidation treatment was 1.4 nm, and the distribution was a concentric circle with a thick central part and a thin outer periphery.
- the in-plane SOI film thickness distribution was 0.8 nm in range, and a good in-plane distribution was obtained.
- Example 3 A thin-film SOI wafer having an SOI film thickness of 10 nm was produced under the same conditions as in Example 1 except that the thermal oxidation (2) in Example 1 was changed to a temperature-falling oxidation similar to the thermal oxidation (2) in Example 2.
- the film thickness distribution of 10 nm SOI was 0.5 nm in Range, and a very good in-plane distribution was obtained.
- Table 1 shows the ion implantation separation conditions, sacrificial oxidation treatment conditions, and results of Examples 1 and 2 and the comparative example.
- FIG. 4 shows the oxide film thickness distribution of the PW monitor after thermal oxidation (thermal oxidation (1), thermal oxidation (2)) in Examples 1 and 2.
- thermal oxidation was performed using a vertical heat treatment furnace having a wafer rotation mechanism.
- the in-plane SOI film thickness distribution was lower than the target of 1 nm in Range in Example 1 and Example 2 where the temperature-fall oxidation was performed, and even better in-plane distribution was obtained in Example 3. On the other hand, it was found that the target range of 1 nm or less cannot be obtained in the comparative example.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Element Separation (AREA)
Abstract
Description
ところが、SOI層に機械加工的要素を含む研磨をしてしまうと、研磨の取りしろが均一でないために、水素イオンなどの注入、剥離によって達成されたSOI層の膜厚均一性が悪化してしまうという問題が生じる。
例えば、特許文献2では、剥離熱処理後(又は結合熱処理後)に、SOI層の表面を研磨することなく水素を含む還元性雰囲気下の熱処理(急速加熱・急速冷却熱処理(RTA処理))を加えることを提案している。さらに、特許文献3では、剥離熱処理後(又は結合熱処理後)に、酸化性雰囲気下の熱処理によりSOI層に酸化膜を形成した後に該酸化膜を除去し、次に還元性雰囲気の熱処理(急速加熱・急速冷却熱処理(RTA処理))を加えることを提案している。
このように、タッチポリッシュの代わりに高温熱処理を行って表面粗さを改善する平坦化処理が行われるようになったことによって、現在では、直径300mmでSOI層の膜厚Range(面内の最大値から最小値を引いた値)が3nm以内の優れた膜厚均一性を有するSOIウェーハが、イオン注入剥離法によって量産レベルで得られている。
これにより回転体1が回転している際、遠心力により基板3をウェーハ保持具2に押し付ける力が働き、ウェーハ保持具2は基板3を保持するようになっている。ただし、このように回転体1の回転面と基板3の表面が平行でない場合、イオンビームを基板3に対して一定角度で注入しようとしても、基板中心部とビームスキャン方向の基板両端部では回転体の回転に応じて注入角度にごくわずかなズレが生じ、これによりイオン注入深さが基板中央部では深く、スキャン方向の基板両端部では浅くなる。これをコーンアングル効果と呼んでいる。この為、イオン注入剥離法におけるイオン注入においては、図6で示されるように、基板3とイオンビームの設定角度は、基板表面とイオンビームとの角度が垂直になる注入角0度(α=0°)に設定することで、スキャン方向の基板両端部で注入角度が同程度ずれる様にして、注入の深さの面内分布が比較的均一になるようにしている。
2つ目の膜厚分布発生要因は、Thin BOX型のSOIウェーハ作製においてチャネリングが発生することである。100nm以下のBOX層(シリコン酸化膜層)膜厚を有するThin BOX型のSOIウェーハの作製においては、酸化膜による散乱の効果が弱くなり注入角度0度設定のイオン注入ではチャネリングが発生する。バッチ式イオン注入機の場合、基板中央部では結晶面とイオンビームの角度が垂直になる為、チャネリングの効果が大きくなりイオン注入深さは深くなる。一方、スキャン方向の基板両端ではコーンアングルにより注入角が生じる為、チャネリングの影響は相対的に弱くなりイオン注入深さが浅くなる。この様に、Thin BOX型のSOIウェーハの作製においては、特にコーンアングルの効果がチャネリングによって強調される。
コーンアングル効果は、ウェーハ中央部とスキャン方向のウェーハ両端部の間で生じる深さ分布の為、2回対称の分布になる。この為、例えばイオン注入を2分割し、各イオン注入でウェーハを90度回転(自転)させれば、ウェーハ中央部では相対的に深く、ウェーハ外周部は全周で浅くなり、同心円の分布に近くなる。また、2回分割に限らず、4回分割でイオン注入し、各イオン注入の際のウェーハを90度ずつ回転(自転)させれば、2回注入よりも更に同心円の分布が整う。
前記犠牲酸化処理における熱酸化を、バッチ式熱処理炉を使用して、少なくとも昇温中、降温中の一方で行うことにより、前記SOI層の表面に略同心円形状の酸化膜厚分布を形成することを特徴とするSOIウェーハの製造方法を提供する。
即ち、本発明らは、SOIウェーハに対し、SOI層表面を熱酸化し、形成された熱酸化膜を除去する犠牲酸化処理を施すことにより、前記SOIウェーハのSOI層を減厚調整する工程を有するSOIウェーハの製造方法において、前記犠牲酸化処理における熱酸化を、バッチ式熱処理炉を使用して、少なくとも昇温中、降温中の一方で行うことにより、前記SOI層の表面に略同心円形状の酸化膜厚分布を形成することを特徴とするSOIウェーハの製造方法を提供する。以下、本発明について更に詳述する。
本発明における犠牲酸化処理を施すためのSOIウェーハを製造する方法は、特に限定されないが、イオン注入剥離法を用いることができる。図1は、イオン注入剥離法を用いた場合の本発明のSOIウェーハの製造方法の工程フロー図を示す。図1(A)に記載のように、シリコン単結晶からなるボンドウェーハの表面から水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入してイオン注入層を形成する(イオン注入工程)。尚、本発明においては、水素分子イオンも「水素イオン」に含まれるものとする。
しかし、本発明においては、ボンドウェーハをコーンアングル効果が顕著に現れる直径300mm以上のシリコン単結晶ウェーハとし、絶縁膜を100nm以下、あるいは50nm以下のシリコン酸化膜としても、膜厚均一性に優れたThin BOX型の薄膜SOIウェーハを製造することができる。
ベースウェーハとしては、シリコン単結晶ウェーハを用いることができるが、特に限定されない。通常は、常温の清浄な雰囲気下でボンドウェーハとベースウェーハの表面同士を接触させることにより、接着剤等を用いることなくウェーハ同士が接着する。
例えば、不活性ガス雰囲気下約500℃以上の温度で熱処理を加えれば、イオン注入層でボンドウェーハを剥離させることができる。また、常温での貼り合わせ面に予めプラズマ処理を施すことによって、熱処理を加えずに(あるいは剥離しない程度の熱処理を加えた後)、外力を加えて剥離することもできる。
ここで、本発明は、前記犠牲酸化処理における熱酸化を、バッチ式熱処理炉を使用して、少なくとも昇温中、降温中の一方で行うことにより、前記SOI層の表面に略同心円形状の酸化膜厚分布を形成することを特徴とする。
尚、略同心円形状の熱酸化膜厚分布を得るためのバッチ式熱処理としては、熱酸化中のウェーハをウェーハ表面に水平方向に回転させる機構を有する縦型熱処理炉を使用することが好ましい。
平坦化熱処理では、SOI層がわずかにエッチングされるが、その際、ウェーハ中央部に比べてウェーハ外周部の方がエッチング量が大きくなるため、平坦化熱処理後のSOI膜厚分布は、凸状に0.5~2nm程度悪化する傾向がある。従って、本発明における犠牲酸化を適用すれば、平坦化熱処理時に悪化したSOI膜厚分布を改善することもできる。
尚、昇温/降温速度は、例えば、0.1~10℃/minとすることができる。
実施例1では結晶方位<100>のシリコン単結晶からなる直径300mmのシリコンウェーハ(表面の結晶面は(100)ジャストであり、角度ズレなし)に埋め込み酸化膜を25nm作製後、水素イオン注入を行った。イオン注入はバッチ式イオン注入機を使用して2回に分割して行い、1回目の注入としてH+,30keV,2.6e16cm-2,注入角度0度、ノッチオリエンテーション角度0度の注入を、2回目の注入としてH+,30keV,2.6e16cm-2,注入角度0度,ノッチオリエンテーション角度90度で注入を行った。水素イオン注入後、ベースウェーハと貼り合せ、500℃30分の窒素雰囲気熱処理により、水素イオン注入層で剥離した。その後、図3に示すように、900℃のパイロジェニック酸化処理後の降温時に850℃までパイロジェニックによる酸化処理を継続する降温酸化処理を行った(熱酸化(1))。熱酸化後の酸化膜厚は250nmであった。鏡面研磨されたシリコン単結晶からなるPWモニターにより酸化膜厚分布を測定したところ降温酸化処理による面内の酸化膜厚Range(Max-Min)は1.1nmで、中央部が厚く、外周で薄くなる同心円の分布であった。その後、Ar雰囲気での平坦化熱処理を行った後、従来の一定温度950℃による酸化を行った(熱酸化(2))。酸化処理後の面内酸化膜厚Rangeは0.9nmであった。
犠牲酸化膜除去後の10nmSOIの膜厚分布は、面内のSOI膜厚分布がRangeで0.7nmであり、良好な面内分布が得られた。
実施例1と同様にイオン注入剥離を行った後、図3に示すように、従来の一定温度900℃による酸化を行った(熱酸化(1))。熱酸化後の酸化膜厚は250nmであった。同心円分布は崩れており、面内酸化膜厚Rangeは0.4nmであった。その後、Ar雰囲気での平坦化熱処理を行った後、950℃のパイロジェニック酸化処理後の降温時に900℃までパイロジェニックによる酸化処理を継続する降温酸化処理を行った(熱酸化(2))。熱酸化後の酸化膜厚は440nmであった。PWモニターにより酸化膜厚分布を測定したところ降温酸化処理による面内酸化膜厚Range(Max-Min)は1.4nmで、中央部が厚く、外周で薄くなる同心円の分布であった。
犠牲酸化膜除去後の10nmSOIの膜厚分布は、面内のSOI膜厚分布がRangeで0.8nmであり、良好な面内分布が得られた。
実施例1の熱酸化(2)を、実施例2の熱酸化(2)と同様の降温酸化とした以外は、実施例1と同一条件でSOI膜厚10nmの薄膜SOIウェーハを作製した。10nmSOIの膜厚分布は、Rangeで0.5nmであり、極めて良好な面内分布が得られた。
実施例1と同様にイオン注入剥離を行った後、図3に示すように、従来の一定温度900℃による酸化を行った(熱酸化(1))。熱酸化後の酸化膜厚は250nmであった。同心円分布は崩れており、面内酸化膜厚Rangeは0.4nmであった。その後、Ar雰囲気での平坦化熱処理を行った後、従来の一定温度950℃による酸化を行った(熱酸化(2))結果、面内酸化膜厚Rangeは0.9nmであった。
犠牲酸化膜除去後の10nmSOIの膜厚分布は、比較例ではRangeが1.2nmであった。
Claims (9)
- SOIウェーハに対し、SOI層表面を熱酸化し、形成された熱酸化膜を除去する犠牲酸化処理を施すことにより、前記SOIウェーハのSOI層を減厚調整する工程を有するSOIウェーハの製造方法において、
前記犠牲酸化処理における熱酸化を、バッチ式熱処理炉を使用して、昇温中、降温中のどちらか一方又は両方で行うことにより、前記SOI層の表面に略同心円形状の酸化膜厚分布を形成することを特徴とするSOIウェーハの製造方法。
- 前記犠牲酸化処理における熱酸化を所定温度で行い、かつ、該所定温度への昇温中、前記所定温度からの降温中のどちらか一方又は両方でも行うことを特徴とする請求項1に記載のSOIウェーハの製造方法。
- 前記犠牲酸化処理における熱酸化として、パイロジェニック酸化処理又はウェット酸化処理を用いることを特徴とする請求項1又は請求項2に記載のSOIウェーハの製造方法。
- 前記犠牲酸化処理を施すSOIウェーハを、シリコン単結晶からなるボンドウェーハの表面から水素イオン、希ガスイオンの一種類以上のガスイオンをイオン注入してイオン注入層を形成し、前記ボンドウェーハのイオン注入した表面とベースウェーハの表面とを絶縁膜を介して貼り合わせた後、前記イオン注入層でボンドウェーハを剥離することにより製造することを特徴とする請求項1乃至請求項3のいずれか一項に記載のSOIウェーハの製造方法。
- 前記イオン注入は、回転体と該回転体に設けられ基板を配置する複数のウェーハ保持具とを備え、該ウェーハ保持具に配置され公転している複数の基板にイオン注入するバッチ式イオン注入機を使用して複数回に分割して行うものとし、各回のイオン注入後に、前記ウェーハ保持具に配置されたボンドウェーハを所定の回転角度だけ自転させ、自転させた配置位置で次のイオン注入を行うことを特徴とする請求項4に記載のSOIウェーハの製造方法。
- 前記イオン注入を2回に分けて行うものとし、1回目のイオン注入後に、前記ボンドウェーハを90度又は180度自転させ、自転させた配置位置で2回目のイオン注入を行うことを特徴とする請求項5に記載のSOIウェーハの製造方法。
- 前記イオン注入を4回に分けて行うものとし、2回目以降のイオン注入を、1回目のイオン注入に対して90、180及び270度のいずれかの回転角度だけ自転させた配置位置で行うことを特徴とする請求項5に記載のSOIウェーハの製造方法。
- 前記絶縁膜を100nm以下のシリコン酸化膜とすることを特徴とする請求項4乃至請求項7のいずれか一項に記載のSOIウェーハの製造方法。
- 前記ボンドウェーハの表面の結晶面と前記イオン注入方向との角度を垂直に設定して、前記各回のイオン注入を行うことを特徴とする請求項5乃至請求項8のいずれか一項に記載のSOIウェーハの製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020147016030A KR101873203B1 (ko) | 2011-12-15 | 2012-11-13 | Soi 웨이퍼의 제조방법 |
SG11201402630XA SG11201402630XA (en) | 2011-12-15 | 2012-11-13 | Method for manufacturing soi wafer |
US14/360,545 US9240344B2 (en) | 2011-12-15 | 2012-11-13 | Method for manufacturing SOI wafer |
EP12858247.5A EP2793250B1 (en) | 2011-12-15 | 2012-11-13 | Soi wafer fabrication method |
CN201280061446.4A CN103988284B (zh) | 2011-12-15 | 2012-11-13 | Soi晶片的制造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-274999 | 2011-12-15 | ||
JP2011274999A JP5927894B2 (ja) | 2011-12-15 | 2011-12-15 | Soiウェーハの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013088636A1 true WO2013088636A1 (ja) | 2013-06-20 |
Family
ID=48612117
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/007267 WO2013088636A1 (ja) | 2011-12-15 | 2012-11-13 | Soiウェーハの製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9240344B2 (ja) |
EP (1) | EP2793250B1 (ja) |
JP (1) | JP5927894B2 (ja) |
KR (1) | KR101873203B1 (ja) |
SG (1) | SG11201402630XA (ja) |
WO (1) | WO2013088636A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015177150A (ja) * | 2014-03-18 | 2015-10-05 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
CN106062923A (zh) * | 2014-03-10 | 2016-10-26 | 信越半导体株式会社 | 贴合式soi晶圆的制造方法 |
US10115580B2 (en) | 2014-09-24 | 2018-10-30 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing an SOI wafer |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3007891B1 (fr) * | 2013-06-28 | 2016-11-25 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite |
JP6090184B2 (ja) | 2014-01-27 | 2017-03-08 | 信越半導体株式会社 | 半導体ウェーハの洗浄槽及び貼り合わせウェーハの製造方法 |
US10573627B2 (en) | 2015-01-09 | 2020-02-25 | Silicon Genesis Corporation | Three dimensional integrated circuit |
US20180175008A1 (en) | 2015-01-09 | 2018-06-21 | Silicon Genesis Corporation | Three dimensional integrated circuit |
FR3034565B1 (fr) * | 2015-03-30 | 2017-03-31 | Soitec Silicon On Insulator | Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme |
FR3058561B1 (fr) * | 2016-11-04 | 2018-11-02 | Soitec | Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif |
JP6686962B2 (ja) * | 2017-04-25 | 2020-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP6747386B2 (ja) | 2017-06-23 | 2020-08-26 | 信越半導体株式会社 | Soiウェーハの製造方法 |
TWM588362U (zh) * | 2017-12-01 | 2019-12-21 | 美商矽基因股份有限公司 | 三維積體電路 |
FR3099291A1 (fr) * | 2019-07-23 | 2021-01-29 | Soitec | procédé de préparation d’une couche mince, incluant une séquence d’étapes pour ameliorer l’uniformité d’epaisseur de ladite couche mince |
JP6864145B1 (ja) * | 2020-09-07 | 2021-04-28 | 信越半導体株式会社 | ウェーハの表面形状調整方法 |
US11410984B1 (en) | 2021-10-08 | 2022-08-09 | Silicon Genesis Corporation | Three dimensional integrated circuit with lateral connection layer |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211128A (ja) | 1991-09-18 | 1993-08-20 | Commiss Energ Atom | 薄い半導体材料フィルムの製造方法 |
JPH11307472A (ja) | 1998-04-23 | 1999-11-05 | Shin Etsu Handotai Co Ltd | 水素イオン剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
WO2003009386A1 (fr) | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Procede de production de plaquettes de liaison |
JP2006324051A (ja) * | 2005-05-17 | 2006-11-30 | Nissin Ion Equipment Co Ltd | 荷電粒子ビーム照射方法および装置 |
JP2007242972A (ja) * | 2006-03-09 | 2007-09-20 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
JP2010129839A (ja) * | 2008-11-28 | 2010-06-10 | Sumco Corp | 貼り合わせウェーハの製造方法 |
JP2010161134A (ja) * | 2009-01-07 | 2010-07-22 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2011120340A (ja) | 2009-12-01 | 2011-06-16 | Mitsui High Tec Inc | 固定子積層鉄心 |
WO2011086628A1 (ja) * | 2010-01-12 | 2011-07-21 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
WO2012164822A1 (ja) * | 2011-05-30 | 2012-12-06 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法及び貼り合わせsoiウェーハ |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6254089A (ja) * | 1985-09-02 | 1987-03-09 | Hitachi Ltd | ウエハ自公転機構 |
FR2797714B1 (fr) | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
JP4795755B2 (ja) * | 2005-08-25 | 2011-10-19 | 株式会社日立ハイテクノロジーズ | 半導体基板の製造装置 |
JP5020547B2 (ja) * | 2006-06-02 | 2012-09-05 | 株式会社Sen | ビーム処理装置及びビーム処理方法 |
JP4961218B2 (ja) * | 2007-01-18 | 2012-06-27 | 株式会社日立国際電気 | 基板処理装置および半導体装置の製造方法 |
JP5272329B2 (ja) * | 2007-05-22 | 2013-08-28 | 信越半導体株式会社 | Soiウエーハの製造方法 |
JP5183969B2 (ja) * | 2007-05-29 | 2013-04-17 | 信越半導体株式会社 | Soiウェーハのシリコン酸化膜形成方法 |
JP5135935B2 (ja) * | 2007-07-27 | 2013-02-06 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
US20090166564A1 (en) * | 2007-12-31 | 2009-07-02 | Moser Benjamin G | Methods for monitoring implanter performance |
US8445358B2 (en) * | 2010-03-31 | 2013-05-21 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device |
-
2011
- 2011-12-15 JP JP2011274999A patent/JP5927894B2/ja active Active
-
2012
- 2012-11-13 US US14/360,545 patent/US9240344B2/en active Active
- 2012-11-13 WO PCT/JP2012/007267 patent/WO2013088636A1/ja active Application Filing
- 2012-11-13 KR KR1020147016030A patent/KR101873203B1/ko active Active
- 2012-11-13 EP EP12858247.5A patent/EP2793250B1/en active Active
- 2012-11-13 SG SG11201402630XA patent/SG11201402630XA/en unknown
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211128A (ja) | 1991-09-18 | 1993-08-20 | Commiss Energ Atom | 薄い半導体材料フィルムの製造方法 |
JPH11307472A (ja) | 1998-04-23 | 1999-11-05 | Shin Etsu Handotai Co Ltd | 水素イオン剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
WO2003009386A1 (fr) | 2001-07-17 | 2003-01-30 | Shin-Etsu Handotai Co.,Ltd. | Procede de production de plaquettes de liaison |
JP2006324051A (ja) * | 2005-05-17 | 2006-11-30 | Nissin Ion Equipment Co Ltd | 荷電粒子ビーム照射方法および装置 |
JP2007242972A (ja) * | 2006-03-09 | 2007-09-20 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
JP2010129839A (ja) * | 2008-11-28 | 2010-06-10 | Sumco Corp | 貼り合わせウェーハの製造方法 |
JP2010161134A (ja) * | 2009-01-07 | 2010-07-22 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2011120340A (ja) | 2009-12-01 | 2011-06-16 | Mitsui High Tec Inc | 固定子積層鉄心 |
WO2011086628A1 (ja) * | 2010-01-12 | 2011-07-21 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
WO2012164822A1 (ja) * | 2011-05-30 | 2012-12-06 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法及び貼り合わせsoiウェーハ |
Non-Patent Citations (1)
Title |
---|
See also references of EP2793250A4 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106062923A (zh) * | 2014-03-10 | 2016-10-26 | 信越半导体株式会社 | 贴合式soi晶圆的制造方法 |
US9793154B2 (en) | 2014-03-10 | 2017-10-17 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded SOI wafer |
EP3118889A4 (en) * | 2014-03-10 | 2017-10-18 | Shin-Etsu Handotai Co., Ltd. | Process for producing bonded soi wafer |
JP2015177150A (ja) * | 2014-03-18 | 2015-10-05 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US10115580B2 (en) | 2014-09-24 | 2018-10-30 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing an SOI wafer |
Also Published As
Publication number | Publication date |
---|---|
EP2793250B1 (en) | 2016-12-28 |
KR101873203B1 (ko) | 2018-07-03 |
US9240344B2 (en) | 2016-01-19 |
EP2793250A4 (en) | 2015-07-22 |
EP2793250A1 (en) | 2014-10-22 |
CN103988284A (zh) | 2014-08-13 |
US20140329372A1 (en) | 2014-11-06 |
SG11201402630XA (en) | 2014-09-26 |
JP5927894B2 (ja) | 2016-06-01 |
KR20140104429A (ko) | 2014-08-28 |
JP2013125909A (ja) | 2013-06-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5927894B2 (ja) | Soiウェーハの製造方法 | |
KR102361311B1 (ko) | 접합웨이퍼의 제조방법 | |
CN103563049B (zh) | 贴合晶片的制造方法 | |
EP3118889B1 (en) | Process for producing bonded soi wafer | |
EP3522202B1 (en) | Bonded soi wafer manufacturing method | |
JP5910352B2 (ja) | 貼り合わせウェーハの製造方法 | |
JP2016201454A (ja) | Soiウェーハの製造方法 | |
JP2010040729A (ja) | Soiウェーハの製造方法 | |
WO2016059748A1 (ja) | 貼り合わせウェーハの製造方法 | |
JP2010161134A (ja) | 貼り合わせウェーハの製造方法 | |
TWI774781B (zh) | Soi晶圓的製造方法 | |
JP2006013179A (ja) | Soiウェーハの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12858247 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14360545 Country of ref document: US |
|
REEP | Request for entry into the european phase |
Ref document number: 2012858247 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012858247 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20147016030 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |