WO2013042622A1 - Display device and drive method for same - Google Patents

Abstract

Provided are a display device capable of rapidly writing an image signal onto a pixel-forming unit, and a drive method therefor. A batch drive signal (VBD) for simultaneously bring a plurality of scanning signal lines into a selection state is simultaneously applied to the plurality of scanning signal lines in a blanking period, whereby a selection is made and a plurality of pixel-forming units are simultaneously pre-charged. Next, a plurality of scanning signal lines are selected in order, a plurality of image signals representing an image which should be displayed are generated as signals where the voltage polarity on each individual data signal line is inverted, and each are applied to the plurality of data signal lines. At this time, given that charging is started from a state in which a voltage close to the image signal voltage has been previously charged in each pixel-forming unit, it is possible to write the image signal rapidly onto the pixel forming unit.

Description

Display device and driving method thereof

The present invention relates to a display device and a driving method thereof, and more particularly to a display device having a high-definition display unit or a display unit (display panel) driven at high speed and a driving method thereof.

Recently, in order to improve the display quality, liquid crystal display devices have come to use high-definition display units and display units driven at high speed. As a result, the load on the source signal line increases due to high definition even though the video signal must be written to the pixel formation portion formed in the display portion at high speed. It is difficult to write in.

Japanese Unexamined Patent Application Publication No. 2010-26528 describes a display device that can suppress a shortage of gradation voltage. Specifically, after the gate driver selects pixels for four rows at a time, the other four rows of pixels are sequentially selected for each row by double gate driving. At this time, the source driver collectively supplies gradation voltages corresponding to black data to the pixels for four rows, and then sequentially supplies gradation voltages corresponding to image data to the pixels for the other four rows. Thereby, since the shortage of gradation voltage is suppressed, the display device can display a high-quality image.

Japanese Unexamined Patent Publication No. 2010-26528

However, in the display device described in Japanese Patent Application Laid-Open No. 2010-26528, the pixel formation portion is precharged by using a signal that depends on the gradation voltage corresponding to the image data several lines before by double gate driving. Done. If black data is written in this precharge, the precharge becomes insufficient, and the display device cannot write the gradation voltage corresponding to the image data to the pixel formation portion at high speed.

Therefore, an object of the present invention is to provide a display device capable of writing a video signal in a pixel formation portion at a high speed and a driving method thereof.

A first aspect of the present invention is an active matrix display device,
The plurality of data signal lines, the plurality of scanning signal lines intersecting with the plurality of data signal lines, and the intersections of the plurality of data signal lines and the plurality of scanning signal lines are arranged in a matrix. A display unit having a plurality of pixel formation units;
A data signal line driving circuit for driving the plurality of data signal lines;
A scanning signal line driving circuit for driving the plurality of scanning signal lines,
The data signal line driving circuit generates a plurality of video signals representing a video to be displayed as a signal whose voltage polarity is inverted for each data signal line and every predetermined number of frame periods, to the plurality of data signal lines. Each of the plurality of data signal lines is applied with a precharge signal having a voltage corresponding to an intermediate gray level of a video signal in order to precharge the plurality of pixel formation portions in the blanking period of the frame period. Applied,
The scanning signal line driving circuit applies a collective driving signal for simultaneously selecting the plurality of scanning signal lines to the plurality of scanning signal lines during the blanking period, and the plurality of video signals are the plurality of video signals. When applied to each of the data signal lines, a scanning signal for sequentially selecting the plurality of scanning signal lines is applied to each of the plurality of scanning signal lines.

According to a second aspect of the present invention, in the first aspect of the present invention,
The voltage of the precharge signal is different between a data signal line to which a positive video signal is applied and a data signal line to which a negative video signal is applied.

According to a third aspect of the present invention, in the second aspect of the present invention,
Further comprising a backlight unit provided on the back of the display unit,
The backlight unit is lit in a period from when each of the plurality of video signals is written to all of the plurality of pixel formation portions to when the next frame period starts.

According to a fourth aspect of the present invention, in the second aspect of the present invention,
The scanning signal line drive circuit and the data signal line drive circuit stop operating in a period from when the plurality of video signals are written to all of the plurality of pixel formation portions until the next frame period starts. It is characterized by.

According to a fifth aspect of the present invention, in the second aspect of the present invention,
Of the plurality of pixel forming portions, each pixel forming portion arranged in parallel with the plurality of data signal lines is connected to a data signal line adjacent in the same direction.

According to a sixth aspect of the present invention, in the second aspect of the present invention,
Among the plurality of pixel forming portions, each pixel forming portion arranged in parallel with the plurality of data signal lines alternately has a predetermined number of data signal lines adjacent in the same direction and data signal lines adjacent in the opposite direction. It is connected.

According to a seventh aspect of the present invention, in the first aspect of the present invention,
The scanning signal line driving circuit has a configuration in which a plurality of unit circuits each composed of a transistor of the same conductivity type are connected in multiple stages, and includes a shift register that operates based on a two-phase clock composed of a first clock and a second clock. Prepared,
The unit circuit is
An output terminal for outputting the scanning signal and the collective driving signal to the scanning signal line;
An output signal generation circuit that generates an on-voltage and an off-voltage and outputs the output voltage as the scanning signal to the output terminal;
A collective drive circuit that outputs an on-voltage to the output terminal as the collective drive signal;
When an ON voltage is simultaneously applied to the collective drive circuit of the plurality of unit circuits during the blanking period of the frame period, the collective drive circuit simultaneously outputs the collective drive signal to the plurality of scanning signal lines. It is characterized by.

According to an eighth aspect of the present invention, in the seventh aspect of the present invention,
The collective drive circuit has one transistor,
The transistor has one conduction terminal connected to the output terminal, and outputs the pulse signal applied to the other conduction terminal to the output terminal as the collective drive signal when the ON voltage is applied to the control terminal. It is characterized by that.

According to a ninth aspect of the present invention, in a seventh aspect of the present invention,
The collective drive circuit has one transistor,
The transistor has one conduction terminal connected to the output terminal and outputs the power supply voltage connected to the other conduction terminal to the output terminal as a collective drive signal when the ON voltage is applied to the control terminal. It is characterized by.

According to a tenth aspect of the present invention, a plurality of data signal lines, a plurality of scanning signal lines intersecting with the plurality of data signal lines, and intersections of the plurality of data signal lines and the plurality of scanning signal lines are respectively provided. A drive method for an active matrix display device comprising a plurality of pixel forming portions arranged correspondingly in a matrix,
In a blanking period of a frame period, a precharge signal having a voltage corresponding to an intermediate gray level of a video signal is applied to the plurality of data signal lines in order to precharge the plurality of pixel formation units, and the plurality of data signal lines Simultaneously writing the precharge signal to the plurality of pixel forming portions by applying a collective driving signal for simultaneously selecting the scanning signal lines to the plurality of scanning signal lines;
A plurality of video signals representing video to be displayed are generated for each data signal line as a signal whose voltage polarity is inverted every predetermined number of frame periods, applied to each of the plurality of data signal lines, and Applying scanning signals for sequentially selecting scanning signal lines to the plurality of scanning signal lines, respectively, and writing the plurality of video signals to the plurality of pixel forming portions, respectively.

According to the first aspect, during the blanking period of the frame period, a plurality of scanning signal lines are simultaneously applied to the plurality of scanning signal lines to simultaneously select the plurality of scanning signal lines, thereby selecting the plurality of scanning signal lines. In order to precharge a plurality of pixel formation portions, a precharge signal having a voltage corresponding to an intermediate gray level of the video signal is applied to the plurality of data signal lines. Thereby, a precharge signal having a voltage close to the voltage of the video signal to be written next is written in all the pixel formation portions. Next, scanning signals for sequentially selecting a plurality of scanning signal lines are applied to the plurality of scanning signal lines, the plurality of scanning signal lines are sequentially selected, and a plurality of video signals representing the video to be displayed are displayed for each data signal line. In addition, a signal whose polarity is inverted every predetermined number of frame periods is generated and applied to a plurality of data signal lines. Thereby, each scanning signal line is selected in order, and a video signal is written for each pixel formation portion connected to the same scanning signal line. At this time, a voltage close to the voltage of the video signal to be written next is charged in advance in each pixel formation portion, so that the video signal can be written in the pixel formation portion at a high speed.

According to the second aspect, a positive video signal is then applied to a data signal line to which a precharge signal having a positive polarity voltage is applied among two different voltages. A negative video signal is then applied to the data signal line to which a precharge signal having a negative voltage is applied. As a result, a video signal can be written at high speed in the pixel formation portion connected to any data signal line regardless of its polarity.

According to the third aspect, after the video signal is written in all of the plurality of pixel forming portions, the backlight is irradiated from the back surface of the display portion. As a result, since the minimum holding time can be secured even in the pixel forming portion where the video signal is held for the shortest time, the display quality of the video can be maintained above a certain level.

According to the fourth aspect, the scanning signal line drive circuit and the data signal line drive circuit stop operating in a period from when the video signal is written to all of the plurality of pixel formation portions until the next frame period starts. To do. As a result, variations in the effective voltage in the screen during one frame period can be reduced, so that the display quality of the video can be maintained above a certain level.

According to the fifth aspect, each pixel forming portion arranged in parallel with the data signal line among the plurality of pixel forming portions is connected to the data signal line adjacent in the same direction. Wiring is not complicated. Thereby, the aperture ratio of a pixel formation part can be improved.

According to the sixth aspect, each pixel forming portion arranged in parallel with the data signal line among the plurality of pixel forming portions has a predetermined number of data signal lines adjacent in the same direction and a data signal line adjacent in the opposite direction. Each number is connected alternately. Thus, the display device is driven by the pseudo dot inversion driving method. As a result, the occurrence of flicker and crosstalk is suppressed, so that the display quality of the display device can be improved.

According to the seventh aspect, the shift register included in the scanning signal line driving circuit includes a plurality of unit circuits connected in cascade. When an ON voltage is applied to the collective drive circuit of each unit circuit during the blanking period of each frame period, the collective drive circuit outputs a collective drive signal to each of the plurality of scanning signal lines simultaneously. Thus, the precharge signal can be simultaneously written in all the pixel formation portions.

According to the eighth aspect, when the on-voltage is applied to the control terminal of the transistor included in the collective drive circuit, the pulse signal applied to the other conduction terminal is output to the output terminal as the collective drive signal. . A collective drive circuit having such a simple configuration can simultaneously output collective drive signals to the scanning signal lines.

According to the ninth aspect, when the on-voltage is applied to the control terminal of the transistor included in the collective drive circuit, the power supply voltage applied to the other conduction terminal is output to the output terminal as the collective drive signal. . In this way, the collective driving circuit applies the power supply voltage to the drain terminal of the transistor, so that it is not necessary to generate a pulse signal to be applied to the drain terminal. For this reason, the display device can be easily designed, and the cost can be reduced. Further, since the power supply voltage applied to the drain terminal is not a pulse signal, the voltage of each scanning signal line can be stabilized in a short time.

1 is a block diagram showing an overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. FIG. 6 is a diagram for explaining a column inversion driving method as a driving method of the liquid crystal display device in the first embodiment, and more specifically, (A) explains a column inversion driving method in an odd-numbered frame period. (B) is a diagram for explaining a column inversion driving method in an even-numbered frame period. FIG. 3 is a block diagram showing a configuration of a gate driver of the liquid crystal display device in the first embodiment. FIG. 3 is a block diagram illustrating a configuration of a shift register included in the gate driver of the liquid crystal display device in the first embodiment. 4 is a circuit diagram of a unit circuit constituting a shift register included in the gate driver of the liquid crystal display device in the first embodiment. FIG. 4 is a timing chart showing an operation of a unit circuit in the first embodiment. 4 is a timing chart illustrating an operation of the liquid crystal display device according to the first embodiment. It is a block diagram which shows the whole structure of the liquid crystal display device which has a backlight unit which concerns on the said 1st Embodiment. It is a block diagram which shows the structure of the shift register contained in the gate driver of the liquid crystal display device which concerns on the modification of 1st Embodiment. FIG. 6 is a circuit diagram of a unit circuit that constitutes a shift register included in a gate driver of a liquid crystal display device according to a modification of the first embodiment. 6 is a timing chart showing an operation of a unit circuit in a modification of the first embodiment. 6 is a timing chart illustrating an operation of a liquid crystal display device according to a modified example of the first embodiment. FIG. 7 is a diagram for explaining a pseudo dot inversion driving method which is a driving method of a liquid crystal display device in a second embodiment of the present invention, and more specifically, (A) is a pseudo dot inversion driving in an odd-numbered frame period. It is a figure for demonstrating a system, (B) is a figure for demonstrating the pseudo dot inversion drive system in the even-numbered frame period. FIG. 10 is a diagram for explaining another pseudo dot inversion driving method which is a driving method of the liquid crystal display device in the second embodiment, and more specifically, (A) shows another pseudo dot in an odd-numbered frame period. It is a figure for demonstrating an inversion drive system, (B) is a figure for demonstrating the other pseudo dot inversion drive systems in the even-numbered frame period.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<1. First Embodiment>
<1.1 Overall configuration and operation>
FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. As shown in FIG. 1, the liquid crystal display device includes a display unit 10, a display control circuit 20, a source driver (data signal line driving circuit) 30, and a gate driver (scanning signal line driving circuit) 40.

The display unit 10 includes a plurality (m) of source signal lines (data signal lines) SL1 to SLm, a plurality (n) of gate signal lines (scanning signal lines) GL1 to GLn, and these source signal lines SL1. A plurality of (n × m) pixel forming portions provided corresponding to the respective intersections of .about.SLm and the gate signal lines GL1 to GLn are provided.

A plurality of pixel forming portions are arranged in a matrix to form a pixel array. Each pixel formation portion includes a thin film transistor (TFT) 11 that is a switching element having a gate terminal connected to a gate signal line passing through a corresponding intersection and a source terminal connected to a source signal line passing through the intersection. A pixel electrode connected to the drain terminal of the TFT 11 and a counter electrode Ec provided in common to the plurality of pixel formation portions are provided, and a liquid crystal is provided between the pixel electrodes of the plurality of pixel formation portions and the counter electrode Ec. Layers are sandwiched. These pixel electrode, counter electrode Ec, and liquid crystal layer form a pixel capacitor Cp. In many cases, the pixel capacitor Cp further includes an auxiliary capacitor connected in parallel to the liquid crystal capacitor so that the voltage can be reliably held. However, since the auxiliary capacitor is not directly related to the present invention, in the present specification, the pixel capacitor Cp will be described as being composed of only a liquid crystal capacitor.

The display control circuit 20 receives an externally supplied digital video signal DAT and a timing signal group TG such as a horizontal synchronizing signal and a vertical synchronizing signal, and receives a digital video signal DV and a source start for controlling video display on the display unit 10. Pulse signal SSP, source clock signal SCK, latch strobe signal LS, gate start pulse signal GSP as scanning start signal, first gate clock signal GCK1, second gate clock signal GCK2, all-on control signal AON, and precharge voltage signal Outputs VGP.

The source driver 30 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 20, and drives the video signals for the source signal lines SL1 to SLm. S (1) to S (m) are respectively applied. In order to perform column inversion driving, the source driver 30 has an odd column source signal line SL (2j + 1) (j is an integer greater than or equal to zero) and an even column source signal line SL (2j) having different polarities for each frame period. Apply the video signal. For example, in a certain frame period, a positive video signal is applied to the odd-numbered source signal line SL (2j + 1), and a negative video signal is applied to the even-numbered source signal line SL (2j). The negative video signal is applied to the odd-numbered source signal line SL (2j + 1), and the positive video signal is applied to the even-numbered source signal line SL (2j). As described above, since the configuration of the source driver 30 that applies the video signal having the opposite polarity to each source signal line for each frame period is well known, the description thereof is omitted.

The gate driver 40 is active every frame period (one vertical scanning period) based on the first gate clock signal GCK1, the second gate clock signal GCK2, and the gate start pulse signal GSP output from the display control circuit 20. The scanning signals GOUT1 to GOUTn are sequentially applied to the corresponding gate signal lines GL1 to GLn. Further, the gate driver 40 simultaneously applies the high-level collective drive signal VBD to the gate signal lines GL1 to GLn based on the precharge voltage signal VGP and the all-on control signal AON at the beginning of each frame period.

As described above, the video signals S (1) to S (m) are applied to the source signal lines SL1 to SLm, respectively, and the scanning signals GOUT1 to GOUTn are applied to the gate signal lines GL1 to GLn, respectively. An image based on the digital video signal DAT supplied from the outside is displayed on the display unit 10.

In the blanking period of each frame period, the collective drive signal VBD is simultaneously applied to the gate signal lines GL1 to GLn, so that all the pixel forming portions are precharged simultaneously. In other words, the median value of the positive polarity gradation voltage (hereinafter referred to as “the intermediate voltage on the positive polarity side”) is precharged in the pixel formation portion where the positive polarity video signal is written, and at the same time the negative polarity video signal The pixel formation portion to be written is precharged with a median value of negative gradation voltage (hereinafter referred to as “intermediate voltage on the negative polarity side”). Note that the voltage precharged in the pixel formation portion may be different between the pixel formation portion to which the positive video signal is written and the pixel formation portion to which the negative video signal is written. Further, the precharged voltage may be a voltage corresponding to an intermediate gray level of the video signal regardless of the polarity of the video signal.

<1.2 Polarity inversion driving method of liquid crystal display device>
When driving a liquid crystal display device, if a direct current voltage (DC voltage) is continuously applied to liquid crystal molecules for a long time, the characteristics of the liquid crystal deteriorate. Therefore, in order to prevent the deterioration of characteristics, the liquid crystal display device uses a polarity inversion driving method in which driving is performed while periodically inverting the polarity of the voltage applied to the liquid crystal layer. Such polarity inversion driving methods include a line inversion driving method, a column inversion driving method, a dot inversion driving method, and the like, but this embodiment is applied to a liquid crystal display device driven by a column inversion method. Therefore, the column inversion driving method will be described.

FIG. 2 is a diagram for explaining the column inversion driving method. In the column inversion driving method, as shown in FIG. 2A, in the first frame period, for example, a positive video signal is applied to the odd-numbered source signal line SL (2j + 1), and the even-numbered source signal line SL is applied. A negative video signal is applied to (2j). Next, as shown in FIG. 2B, in the second frame period, a negative video signal is applied to the odd-numbered source signal line SL (2j + 1), and the even-numbered source signal line SL (2j) is applied. A positive video signal is applied. Similarly, in the same manner as in the first frame period in the odd-numbered frame period, and in the same manner as in the second frame period in the even-numbered frame period, positive and negative video signals are respectively transmitted. Applied to the source signal lines SL1 to SLm. Since the pixel formation portion is connected to each of the source signal lines SL1 to SLm adjacent to the left side for each column, as shown in FIG. 2A, in the first frame period, a positive electrode is connected to the pixel formation portion in the odd column. The voltage of the negative video signal is charged, and the voltage of the negative video signal is charged in the pixel formation portions in the even columns. Further, as shown in FIG. 2B, in the second frame period, the voltage of the video signal having the opposite polarity is charged in each pixel formation portion.

Note that in the odd-numbered frame period and the even-numbered frame period, the polarity of the video signal applied to each source signal line may be opposite to the polarity shown in FIG.

<1.3 Shift register configuration>
FIG. 3 is a block diagram showing a configuration of the gate driver 40. As shown in FIG. 3, the gate driver 40 includes a shift register 410 in which n unit circuits SRa (1) to SRa (n) are connected in cascade. The n unit circuits SRa are provided in a one-to-one correspondence with each row of the pixel array of n rows × m columns formed in the display unit 10. The unit circuits SRa (1) to SRa (n) of the shift register 410 not only output high-level scanning signals to the gate signal lines GL1 to GLn in each row in each frame period, but also in each frame period. During the blanking period, the high-level collective drive signal VBD is simultaneously output to all the gate signal lines GL1 to GLn.

FIG. 4 is a block diagram showing the configuration of the shift register 410 in the gate driver 40. As shown in FIG. With reference to FIG. 4, signals provided to the input terminals of the unit circuits SRa (1) to SRa (n) constituting the shift register 410 will be described. In each of the unit circuits SRa (1) to SRa (n), two-phase clocks CKA (hereinafter referred to as “first clock”) and CKB (hereinafter referred to as “second clock”) whose phases are shifted from each other by 180 degrees are provided. An input terminal for receiving each, an input terminal for receiving a set signal SET that is a signal for starting scanning, an input terminal for receiving a reset signal RESET that is a signal for ending scanning, and an all-on control signal AON An input terminal for receiving, an input terminal for receiving the precharge voltage signal VGP, and an output terminal for outputting the scanning signals GOUT1 to GOUTn or the collective driving signal VBD to the gate signal lines GL1 to GLn are provided. Yes.

The first clock CKA and the second clock CKB will be described. In the first stage unit circuit SRa (1), the first gate clock signal GCK1 is supplied as the first clock CKA, and the second gate clock signal GCK2 is supplied as the second clock CKB. In the second stage unit circuit SRa (2), the second gate clock signal GCK2 is supplied as the first clock CKA, and the first gate clock signal GCK1 is supplied as the second clock CKB. The unit circuits SRa (3) to SRa (n) from the third stage to the nth stage also have two stages similar to the above-described unit circuits SRa (1) and SRa (2) of the first stage and the second stage. Repeated one by one. The first gate clock signal GCK1 and the second gate clock signal GCK2 are signals that are 180 degrees out of phase with each other.

The set signal SET will be described. Focusing on the unit circuit SRa (k) in the k-th stage (k is a positive integer), the scanning signal GOUT (k−1) output from the unit circuit SRa (k−1) in the (k−1) -th stage Unit circuit SRa (k) is applied as set signal SET. However, the first stage unit circuit SRa (1) is supplied with the gate start pulse signal GSP as the set signal SET.

The reset signal RESET will be described. Focusing on the k-th unit circuit SRa (k), the scanning signal GOUT (k + 1) output from the (k + 1) -th unit circuit SRa (k + 1) is given to the unit circuit SRa (k) as the reset signal RESET. . However, an externally input signal is given as a reset signal RESET to the nth unit circuit SRa (n) which is the final stage. Instead of inputting from the outside, a dummy unit circuit SRa (n + 1) is provided at the (n + 1) stage, and the scanning signal GOUT (n + 1) output from the unit circuit SRa (n + 1) is supplied to the unit circuit SRa (n). The reset signal RESET may be used.

Next, signals output from the output terminal of the k-th unit circuit SRa (k) will be described. A scanning signal GOUTk for selecting the k-th gate signal line GLk is output from the output terminal of the k-th unit circuit SRa (k). The scanning signal GOUTk is supplied to the unit circuit SRa (k−1) at the (k−1) stage as the reset signal RESET and to the unit circuit SRa (k + 1) at the (k + 1) stage as the set signal SET. It is done. Further, the unit circuit SRa (k) outputs the high-level collective drive signal VBD to the gate signal line GLk during the blanking period of each frame period.

<1.4 Unit circuit configuration>
FIG. 5 is a circuit diagram showing a configuration of the unit circuit SRa included in the shift register 410. As shown in FIG. 5, the unit circuit SRa includes five thin film transistors (hereinafter referred to as “transistors”) T1 to T5 of the same conductivity type, and one capacitor C. Hereinafter, the voltage (signal level) that turns on the transistor when applied to the gate terminal is referred to as on-voltage (on level), and the voltage (signal level) that turns off the transistor is referred to as off-voltage (off level). In an N-channel transistor, a high level voltage is an on-voltage (high level signal is on level), and a low level voltage is an off voltage (low level signal is off level). The opposite is true for P-channel transistors. In the following description, the transistors included in the unit circuit SRa are all assumed to be N-channel type, but may be all P-channel type.

The unit circuit SRa has six input terminals 41 to 46 and one output terminal 61. These input terminals 41 to 46 are an input terminal 41 for receiving a set signal SET, an input terminal 42 for receiving a reset signal RESET, an input terminal 43 for receiving a first clock CKA, and an input terminal for receiving a second clock CKB. 44, an input terminal 45 for receiving the all-on signal, and an input terminal 46 for receiving the precharge voltage signal VGP.

The connection relationship of each component in this unit circuit SRa will be described. In the following description, a connection portion where the source terminal of the transistor T1, the drain terminal of the transistor T2, and the gate terminal of the transistor T3 are connected to each other is referred to as a node NC.

As for the transistor T1, the drain terminal and the gate terminal are connected to the input terminal 41 (that is, diode connection), and the source terminal is connected to the node NC. As for the transistor T2, the gate terminal is connected to the input terminal 42, the drain terminal is connected to the node NC, and the source terminal is connected to the low-level power supply voltage VSS. As for the transistor T3, the gate terminal is connected to the node NC, the drain terminal is connected to the input terminal 43, and the source terminal is connected to the output terminal 61. As for the transistor T4, the gate terminal is connected to the input terminal 44, the drain terminal is connected to the output terminal 61, and the source terminal is connected to the low-level power supply voltage VSS. As for the transistor T5, the gate terminal is connected to the input terminal 45, the drain terminal is connected to the input terminal 46, and the source terminal is connected to the output terminal 61. One end of the capacitor C is connected to the node NC, and the other end is connected to the output terminal 61.

Next, the operation of the unit circuit SRa will be described. FIG. 6 is a timing chart showing the operation of the unit circuit SRa. The unit circuit SRa outputs an output signal that becomes the scanning signal GOUT as an ordinary shift register to the output terminal 61 and outputs an output signal that becomes the collective drive signal VBD.

First, the operation when the collective drive signal VBD is output to the output terminal 61 will be described. Of the periods t0 to t3, the periods t0 to t03 correspond to a blanking period, and the periods t1 to t3 correspond to a part of the display period. In the period t01 to t02, the on-level all-on control signal AON is given to the input terminal 45, so that the transistor T5 is turned on. Among these, in the period t01, since the high-level precharge voltage signal VGP is supplied to the input terminal 46, an output signal serving as the collective drive signal VBD is output to the output terminal 61. However, since the precharge voltage signal VGP changes from the high level to the low level during the period t02, the voltage at the output terminal 61 also changes from the high level to the low level.

In the period t03, since the all-on control signal AON given to the input terminal 45 changes from the on level to the off level, the transistor T5 is turned off. Further, in the period t03, the input terminal 41 is supplied with the set signal SET that is turned on. As a result, the transistor T1 is turned on, and the voltage at the node NC increases.

During the period t1, the first clock CKA applied to the input terminal 43 changes from low level to high level. At this time, since the voltage at the node NC is increased, the transistor T3 is turned on, and the voltage at the output terminal 61 is increased. Further, since the capacitor C is provided between the node NC and the output terminal 61, the voltage at the node NC further increases as the voltage at the output terminal 61 increases (the node NC is bootstrapped). As a result, a voltage higher than the ON voltage is applied to the gate terminal of the transistor T3, and the level of the first clock CKA is output to the output terminal 61 without being lowered by the threshold voltage of the transistor T3. As a result, the voltage of the output terminal 61 becomes the same voltage as the high level voltage of the first clock CKA, so that the gate signal line connected to the output terminal 61 of the unit circuit SRa is selected. Note that in the period t1, since the second clock CKB is in the off level, the transistor T4 maintains the off state. For this reason, the voltage of the drain terminal of the transistor T4, that is, the output terminal 61 does not become low level.

During the period t2, the on-level second clock CKB is supplied to the input terminal 44. As a result, the transistor T4 is turned on, and the voltage of the output terminal 61 becomes low level. Further, an on-level reset signal RESET is given to the input terminal 42. As a result, the transistor T2 is turned on, and the voltage at the node NC is also low.

In the unit circuit SRa, the transistors T1 to T4 and the capacitor C function as an output signal generation circuit that generates and outputs a scanning signal, and the transistor T5 functions as a collective drive circuit that outputs a collective drive signal.

<1.5 Shift register operation>
Next, the operation of the liquid crystal display device will be described using a timing chart. FIG. 7 is a timing chart in one frame period of the liquid crystal display device. In FIG. 7, the period from the period t01 to the period t (n + 1) is one frame period. Further, in one frame period, a period t01 to a period t03 is a blanking period, and a period t1 to a period t (n + 1) is a display period. Each of the periods t01 to tn is one horizontal period, and the period t (n + 1) is a period longer than one horizontal period. In FIG. 7, for the sake of convenience, the length of the period t (n + 1) is depicted as a period having the same length as the period t1 or the like, but actually, the length of the period t (n + 1) is the period t1 or the like. Is set to a sufficiently long period.

First, the period t01 to t03 will be described. During the period t01 to t02, all the unit circuits SRa (1) to SRa (n) are supplied with the on-level all-on control signal AON, and during the period t01, the high-level precharge voltage signal VGP is applied. As a result, the unit circuits SRa (1) to SRa (n) apply the high-level collective drive signal VBD to the corresponding gate signal lines GL1 to GLn, respectively, during the period t01. As described above, in the period t01, the high-level collective driving signal VBD is simultaneously applied to the gate signal lines GL1 to GLn regardless of the levels of the first gate clock signal GCK1 and the second gate clock signal GCK2. Thereby, the TFTs 11 of all the pixel formation portions are turned on.

At this time, the positive intermediate voltage SPC + is applied from the source driver 30 to the odd-numbered source signal lines SL (2j + 1), and the intermediate signal is applied to all the pixel formation portions connected to the odd-numbered source signal lines SL (2j + 1). The voltage SPC + is charged. Further, the intermediate voltage SPC− on the negative polarity side is applied to the source signal line SL (2j) in the even column, and the intermediate voltage SPC− is applied to all the pixel formation portions connected to the source signal line SL (2j) in the even column. Charged. A signal having an intermediate voltage SPC + on the positive polarity side and an intermediate voltage SPC− on the negative polarity side is sometimes referred to as a precharge signal.

In the period t02, since the precharge voltage signal VGP changes from the high level to the low level, the voltage of the output terminal 61 also becomes the low level. As a result, the voltages of the gate signal lines GL1 to GLn corresponding to the unit circuits SRa (1) to SRa (n) respectively become low level, and the TFTs 11 of all the pixel formation portions are turned off. As a result, the pixel formation portion connected to the odd-numbered column source signal line SL (2j + 1) holds the intermediate voltage SPC + on the positive polarity side, and the pixel formation portion connected to the even-numbered column source signal line SL (2j) The intermediate voltage SPC− on the negative polarity side is maintained. In this way, all the pixel forming portions are precharged.

In the unit circuit SRa (1), an on-level gate start pulse signal GSP is given as the set signal SET to the drain terminal of the transistor T1. As a result, the voltage at the node NC of the unit circuit SRa (1) increases.

Next, display periods (hereinafter referred to as “periods”) t1 to t (n + 1) will be described. In the period t1, the gate start pulse signal GSP given to the unit circuit SRa (1) is turned off. As a result, the transistor T1 is turned off and the node NC is in a floating state. Since the high-level first clock CKA is applied to the drain terminal of the transistor T3, the voltage at the node NC is bootstrapped by the capacitor C and becomes higher than the on-voltage of the transistor T3, and the transistor T3 becomes fully conductive. In this state, when the high-level first clock CKA is applied to the drain terminal of the transistor T3, the high-level first clock CKA is output to the output terminal without being lowered by the threshold voltage of the transistor T3. The unit circuit SRa (1) at the stage applies the high level scanning signal GOUT1 to the gate signal line GL1. At this time, a positive video signal is supplied from the source driver 30 to the odd-numbered source signal line SL (2j + 1), and a negative video signal is supplied to the even-numbered source signal line SL (2j). Therefore, among the pixel formation portions connected to the gate signal line GL1 in the first row, the pixel formation portions connected to the odd-numbered source signal lines SL (2j + 1) are charged with the voltage of the positive video signal. The Further, the voltage of the negative-polarity video signal is charged in the pixel formation portion connected to the even-numbered source signal line SL (2j). As described above, in the pixel forming portion, since the writing of the video signal is started while the intermediate voltage SPC + or SPC− close to the voltage of the video signal to be written is held, the video signal is written at a high speed.

The high-level scanning signal GOUT1 output from the first stage unit circuit SRa (1) is also supplied as the set signal SET of the transistor T1 of the second stage unit circuit SRa (2). As a result, the transistor T1 of the unit circuit SRa (2) is turned on, and the voltage at the node NC of the unit circuit SRa (2) increases.

In the period t2, in the first-stage unit circuit SRa (1), the second clock CKB at the on level is supplied to the transistor T4. As a result, the transistor T4 is turned on, and the voltage of the output terminal 61 becomes low level. For this reason, the voltage of the gate signal line GL1 connected to the unit circuit SRa (1) becomes low level. As a result, the TFT 11 in each pixel formation portion in the first row is turned off, and each pixel formation portion in the first row holds the voltage of the written video signal.

Further, the high level scanning signal GOUT1 is supplied as the set signal SET from the unit circuit SRa (1) to the transistor T1 of the second stage unit circuit SRa (2). As a result, the transistor T1 of the unit circuit SRa (2) is turned on, and the voltage at the node NC increases. Therefore, when the first clock CKA at the high level is applied to the drain terminal of the transistor T3, the voltage at the node NC is bootstrapped, and the transistor T3 is brought into a complete conduction state. In this state, when the high-level first clock CKA is applied to the drain terminal of the transistor T3, the first clock CKA is output to the output terminal without being lowered by the threshold voltage of the transistor T3. The unit circuit SRa (2) applies the high level scanning signal GOUT2 to the gate signal line GL2. At this time, a positive video signal is applied from the source driver 30 to the odd-numbered source signal lines SL (2j + 1), and a negative video signal is applied to the even-numbered source signal lines SL (2j). The Among the pixel formation portions connected to the gate signal line GL2 in the second row, the pixel formation portions connected to the odd-numbered source signal lines SL (2j + 1) are charged with the voltage of the video signal having the positive polarity. The pixel formation portion connected to the source signal line SL (2j) is charged with a negative video signal voltage.

At this time, the high-level scanning signal GOUT2 output from the second stage unit circuit SRa (2) is also supplied as the set signal SET of the transistor T1 of the third stage unit circuit SRa (3). As a result, the transistor T1 of the unit circuit SRa (3) is turned on, and the voltage at the node NC increases. The high-level scanning signal GOUT2 output from the second stage unit circuit SRa (2) is also supplied as the reset signal RESET of the transistor T2 of the first stage unit circuit SRa (1). As a result, the transistor T2 of the unit circuit SRa (1) is turned on, and the voltage at the node NC changes from the high level to the low level.

During the period t3, the on-level second clock CKB is supplied to the transistor T4 of the second stage unit circuit SRa (2). As a result, the transistor T4 is turned on, and the voltage of the output terminal becomes low level. For this reason, the voltage of the gate signal line GL2 connected to the unit circuit SRa (2) becomes low level. As a result, the TFT 11 in each pixel formation portion in the second row is turned off, and each pixel formation portion in the second row holds the voltage of the written video signal.

Further, the high-level scanning signal GOUT2 is given as the set signal SET to the transistor T1 of the third-stage unit circuit SRa (3) from the second-stage unit circuit SRa (2). As a result, the transistor T1 of the third-stage unit circuit SRa (3) is turned on, and the voltage at the node NC increases. When the high-level first clock CKA is applied to the drain terminal of the transistor T3, the voltage at the node NC is bootstrapped and the transistor T3 is brought into a fully conductive state. In this state, the level of the first clock CKA is output to the output terminal without being lowered by the threshold voltage of the transistor T3, and the unit circuit SRa (3) at the third stage outputs the high level scanning signal GOUT3 to the gate signal line GL3. Is applied. At this time, a positive video signal is supplied from the source driver 30 to the odd-numbered source signal line SL (2j + 1), and a negative video signal is supplied to the even-numbered source signal line SL (2j). . Of the pixel formation portions connected to the gate signal line GL3 in the third row, the pixel formation portions connected to the odd-numbered source signal lines SL (2j + 1) are charged with the voltage of the positive video signal, The pixel forming portion connected to the source signal line SL (2j) is charged with a negative video signal voltage.

Further, the high-level scanning signal GOUT3 is supplied as the set signal SET to the transistor T1 of the fourth-stage unit circuit SRa (4) from the third-stage unit circuit SRa (3). As a result, the transistor T1 of the unit circuit SRa (4) is turned on, and the voltage at the node NC increases. The high-level scanning signal GOUT3 is supplied as the reset signal RESET from the third-stage unit circuit SRa (3) to the transistor T2 of the second-stage unit circuit SRa (2). As a result, the transistor T2 of the unit circuit SRa (2) is turned on, and the voltage at the node NC becomes low level.

In the period t4, the on-level second clock CKB is supplied to the transistor T4 of the third-stage unit circuit SRa (3). For this reason, like the TFT 11 of each pixel formation portion in the first row, the TFT 11 of each pixel formation portion in the third row is turned off, and each pixel formation portion in the third row applies the voltage of the written video signal. Hold.

Similarly, the unit circuits SRa (4) to SRa (n) apply the high level scanning signals GOUT1 to GOUTn to the gate signal lines GL3 to GLn in order in the same manner for each period up to the period tn. In this way, the high level scanning signals GOUT4 to GOUTn are sequentially applied to the gate signal lines GL1 to GLn, respectively. As a result, among the pixel formation portions connected to the gate signal lines GL4 to GLn in the 4th to nth rows, the pixel formation portion connected to the odd-numbered source signal line SL (2j + 1) is the voltage of the positive video signal. And the pixel formation portion connected to the source signal line SL (2j) in the even-numbered column holds the voltage of the negative video signal.

Next, in the period t (n + 1), the liquid crystal display device displays an image on the display unit 10 based on the voltage of the image signal held in each pixel formation unit. Here, the reason why a period t (n + 1) longer than one horizontal period is provided at the end of one frame period will be described. By providing the period t (n + 1), a sufficient time can be secured from the application of the scanning signal GOUTn to the gate signal line GLn in the n-th row until the start of the next frame period. As a result, the effective voltage applied to the liquid crystal layer during one frame period is the pixel formation portion in the first row even in the pixel formation portion in the nth row having the longest time from precharging to writing the video signal. Since the voltage is almost the same as the effective voltage at, the video display quality can be kept above a certain level.

As described above, when the period t (n + 1) elapses, the next frame period starts, and the operation in the period t01 is started again. However, in this frame period, the polarity of the video signal held in each pixel formation portion is reversed. In other words, the pixel formation portion connected to the odd-numbered source signal line SL (2j + 1) holds the voltage of the negative video signal, and the pixel formation portion connected to the even-numbered source signal line SL (2j) has the positive polarity. Hold the video signal voltage.

In the driving method as described above, for example, as in field sequential driving, a video signal is written to all the pixel forming portions and then the backlight is turned on to display the video, or the n-th gate signal line GLn is set to the high level. After the scanning signal GOUTn is output, the liquid crystal display device is suitable for displaying an image by pause driving for reducing power consumption by providing a pause period during which the operations of the source driver 30 and the gate driver 40 are stopped.

FIG. 8 is a block diagram showing the overall configuration of the liquid crystal display device having the backlight unit 50. As shown in FIG. 8, the backlight unit 50 is disposed on the back surface of the display unit 10, and the backlight unit 50 is turned on when the period t (n + 1) is reached. Thereby, the light from the backlight unit 50 is irradiated on the back surface of the display unit 10, and an image is displayed on the display unit 10. Since the constituent elements other than the backlight unit 50 are the same as the constituent elements of the liquid crystal display device shown in FIG. 1, the same reference numerals are given and description thereof is omitted. Further, in a liquid crystal display device that displays an image by pause driving, variation in the screen of the effective voltage applied to the liquid crystal layer during one frame period can be reduced, so that the display quality of the image can be maintained above a certain level.

In the above embodiment, the polarity of the video signal applied to the adjacent source signal line is inverted every frame period. However, for example, the polarity of the video signal applied to the source signal line may be inverted, for example, every 2 frame periods or every 3 frame periods.

<1.6 Effect>
According to the above embodiment, in the column inversion drive type liquid crystal display device, all the pixel forming portions are placed on the positive polarity side or the negative polarity side during the period t01 to t03 which is the blanking period provided at the beginning of each frame period. Are precharged to intermediate voltages SPC + and SPC−. For this reason, when charging the voltage of the video signal to each pixel forming portion, it is possible to start from a state in which a voltage close to the voltage of the video signal is charged in advance. Accordingly, the voltage of the video signal can be charged to each pixel formation portion at high speed, so that the display portion 10 having high definition can be provided or the display quality of the liquid crystal display device driven at high speed can be improved. be able to.

In addition, since the pixel formation portions arranged in one column are all connected to the same source signal line, wiring in the pixel formation portion does not become complicated. Thereby, the aperture ratio of a pixel formation part can be improved.

<1.7 Modification>
FIG. 9 is a block diagram showing a configuration of the shift register 420 in a modification of the present embodiment, and FIG. 10 is a circuit diagram showing a configuration of the unit circuit SRb included in the shift register 420 shown in FIG.

As shown in FIG. 9, the shift register 420 is configured by cascading n unit circuits SRb (1) to SRb (n). The n unit circuits SRb (1) to SRb (n) are provided so as to have a one-to-one correspondence with the gate signal lines GL1 to GLn of each row of the pixel array of n rows × m columns formed in the display unit 10. ing. Similarly to the shift register 410 shown in FIG. 4, the shift register 420 not only sequentially outputs the high level scanning signals GOUT1 to GOUTn to the gate signal lines GL1 to GLn, but also shifts the high level during the blanking period of each frame period. Simultaneously output the level collective drive signal VBD.

In this shift register 420, components that are different from the shift register 410 shown in FIG. 4 will be described, and the same components will be denoted by the same reference numerals and description thereof will be omitted. In the shift register 420, the clear signal CLR is supplied to all the unit circuits SRb (1) to SRb (n) instead of the precharge voltage signal VGP in the blanking period.

As shown in FIG. 10, the configuration of the unit circuit SRb included in the shift register 420 is partially different from the configuration of the unit circuit SRa shown in FIG. Therefore, in the unit circuit SRb, the same constituent elements as those of the unit circuit SRa are denoted by the same reference numerals, description thereof is omitted, and different constituent elements will be described. In the unit circuit SRb, a transistor T6 and an input terminal 47 connected to the transistor T6 are further added to the unit circuit SRa. Accordingly, the unit circuit SRb has six transistors T1 to T6 of the same conductivity type, one capacitor C, six input terminals 41 to 45, 47, and one output terminal 61. ing.

Next, the connection relationship of the transistor T6 will be described. The gate terminal of the transistor T6 is connected to the input terminal 47, the drain terminal is connected to the output terminal 61, and the source terminal is connected to the low-level power supply voltage VSS. The drain terminal of the transistor T5 is connected to the high-level power supply voltage VDD instead of the input terminal 46 that supplies the precharge voltage signal VGP.

In the unit circuit SRb, similarly to the unit circuit SRa, the transistors T1 to T4 and T6 and the capacitor C function as an output signal generation circuit that generates and outputs a scanning signal, and the transistor T5 is collectively driven. It functions as a collective drive circuit that outputs signals.

Next, the operation of the unit circuit SRb will be described. FIG. 11 is a timing chart showing the operation of the unit circuit SRb. The unit circuit SRb also outputs an output signal as a scanning signal as an ordinary shift register to the output terminal 61 and outputs an output signal as a collective drive signal VBD to the output terminal 61. However, the operation of the unit circuit SRb when outputting an output signal as a scanning signal as a normal shift register is the same as the operation of the unit circuit SRa. Therefore, hereinafter, an operation when an output signal serving as the collective drive signal VBD is output will be described.

Among the periods t01 to t03 corresponding to the blanking period, the off-level clear signal CLR is supplied to the input terminal 47 in the period t01, so that the transistor T6 is in the off state. At this time, since the on-level all-on control signal AON is applied to the input terminal 45, the transistor T5 is turned on, and the high-level power supply voltage VDD connected to the drain terminal is output to the output terminal 61. As a result, an output signal serving as the collective drive signal VBD is output to the output terminal 61.

In the period t02, the all-on control signal AON changed from the on level to the off level is given to the input terminal 45, so that the transistor T5 is turned off. At this time, since the on-level clear signal CLR is applied to the input terminal 47, the transistor T6 is turned on, and the output terminal 61 becomes the low-level power supply voltage VSS. As a result, the voltages of the gate signal lines GL1 to GLn corresponding to the unit circuits SRb (1) to SRb (n) become low level.

In the period t03, the high-level gate start pulse signal GSP is supplied as the set signal SET to the drain terminal of the transistor T1. As a result, the voltage at the node NC increases, and the transistor T3 is turned on.

Note that the timing chart in the period t1 to t (n + 1) corresponding to the display period is the same as the timing chart shown in FIG.

Next, the operation of the shift register 420 in this modification will be described using a timing chart. FIG. 12 is a timing chart of the shift register 420 in one frame period. In the following, the operation of the shift register 420 in the period t1 to t (n + 1) is the same as the operation of the shift register 410 shown in FIG. 7, and thus the description thereof is omitted, and only the period t01 to t03 that is the blanking period. explain.

During period t01, all unit control circuits SRb (1) to SRb (n) are supplied with the on-level all-on control signal AON. As a result, the TFTs 5 of the unit circuits SRb (1) to SRb (n) are turned on, and the high level power supply voltage VDD connected to the drain terminal of the TFT 5 is changed to the unit circuits SRb (1) to SRb (n). Is output to the output terminal. As a result, in the period t01, the unit circuits SRb (1) to SRb (n) apply the high-level scanning signals GOUT1 to GOUTn to the corresponding gate signal lines GL1 to GLn, respectively. As described above, the shift register 420 simultaneously applies the high-level collective drive signal VBD to the gate signal lines GL1 to GLn in the period t01 regardless of the levels of the first gate clock signal GCK1 and the second gate clock signal GCK2. To do. Thereby, the TFTs 11 of all the pixel formation portions are turned on.

At this time, the positive intermediate voltage SPC + is applied from the source driver 30 to the odd-numbered source signal lines SL (2j + 1), and the intermediate signal is applied to all the pixel formation portions connected to the odd-numbered source signal lines SL (2j + 1). The voltage SPC + is charged. Further, the intermediate voltage SPC− on the negative polarity side is output to the source signal line SL (2j) in the even column, and the intermediate voltage SPC− is applied to all the pixel formation portions connected to the source signal line SL (2j) in the even column. Charged.

In the period t02, the all-on control signal AON changes from the on level to the off level, so that the transistor T5 is turned off. On the other hand, the clear signal CLR of the on level is given to the gate terminal of the transistor T6, and the transistor T6 is turned on. As a result, the voltages at the output terminals of the unit circuits SRb (1) to SRb (n) become low level, and the TFTs 11 of all the pixel formation portions connected to the gate signal lines GL1 to GLn are turned off. As a result, the pixel formation portion connected to the odd-numbered column source signal line SL (2j + 1) holds the intermediate voltage SPC + on the positive polarity side, and the pixel formation portion connected to the even-numbered column source signal line SL (2j) The intermediate voltage SPC− on the negative polarity side is maintained. In this way, all the pixel forming portions are precharged.

Also during the period t03, the voltages of the output terminals of the unit circuits SRb (1) to SRb (n) remain at the low level, so that the voltages of the gate signal lines GL1 to GLn also maintain the low level.

According to such a unit circuit SRb, unlike the unit circuit SRa shown in FIG. 4, since the precharge voltage signal VGP is not used, the following effects are obtained. That is, the precharge voltage signal VGP used in the unit circuit SRa is a pulse signal for simultaneously turning on / off all the gate signal lines GL1 to GLn, and therefore a large buffer circuit capable of driving a large load is provided in the display control circuit 20. There is a need. On the other hand, in the unit circuit SRb, since the power supply voltage VDD is applied to the drain terminal of the transistor T5, it is not necessary to provide the large buffer circuit as described above in the display control circuit 20. Thereby, cost can be reduced. Further, since the power supply voltage VDD applied to the input terminal is not a pulse signal like the precharge voltage signal VGP, the voltages of the gate signal lines GL1 to GLn can be stabilized in a short time.

<2. Second Embodiment>
Next, a liquid crystal display device according to a second embodiment of the present invention will be described. The block diagram showing the configuration of the liquid crystal display device is substantially the same as the block diagram showing the configuration of the liquid crystal display device shown in FIG. In the liquid crystal display device according to the present embodiment, unlike the liquid crystal display device shown in FIG. 1, among the signals supplied from the display control circuit 20 to the gate driver 40, the clear signal CLR is applied instead of the precharge voltage signal VGP. It is done.

<2.1 Polarity inversion drive method of liquid crystal display device>
The liquid crystal display device according to the present embodiment is driven by a driving method (hereinafter referred to as “pseudo dot inversion driving method”) obtained by modifying the column inversion driving method. FIG. 13 is a diagram for explaining the pseudo dot inversion driving method of the present embodiment. As in the column inversion method shown in FIG. 2, the pseudo dot inversion driving method of the present embodiment is applied to the odd-numbered source signal lines SL (2j + 1) in the first frame period, as shown in FIG. 13A. A positive video signal is applied, and a negative video signal is applied to the even-numbered source signal lines SL (2j). Next, as shown in FIG. 13B, in the second frame period, a negative video signal is applied to the odd-numbered source signal line SL (2j + 1), and the even-numbered source signal line SL (2j). A positive video signal is applied to the. Similarly, in the odd-numbered frame period, as in the first frame period, in the even-numbered frame period, as in the second frame period, the positive and negative video signals are transferred to the source signal lines. Applied to each of SL1 to SLm.

However, unlike the column inversion method shown in FIG. 2, each of the pixel formation portions arranged in the column direction is not connected to the source signal line on the left side, but alternately on the left side. It is connected to the source signal line or connected to the source signal line on the right. For example, in the case shown in FIG. 13, the odd-row pixel formation portions are connected to the odd-column source signal lines SL (2j + 1), and the even-row pixel formation portions are connected to the even-column source signal lines SL (2j). Has been. Accordingly, as shown in FIG. 13A, in the odd-numbered frame period, the polarity of the video signal written in each pixel formation portion is positive or negative in both the row direction and the column direction. This is substantially the same arrangement (staggered arrangement) as in the case of alternately arranged dot inversion driving. Further, as shown in FIG. 13B, in the even-numbered frame period, the polarities of the video signals applied to the odd-numbered column source signal lines SL (2j + 1) and the even-numbered column source signal lines SL (2j) respectively. This is the reverse of the case shown in FIG. For this reason, the polarity of the voltage of the video signal written to each pixel forming portion is also reversed.

Note that the polarities of the video signals applied to the odd-numbered source signal lines SL (2j + 1) and the even-numbered source signal lines SL (2j) in the odd-numbered and even-numbered frames are shown in FIG. Also, the case shown in FIG. 13B may be reversed.

The configuration and timing chart of the shift register included in the gate driver 40 of such a liquid crystal display device are the same as the shift register 410 and its timing chart shown in FIGS. 4 and 7, respectively. The configuration of the unit circuit and its timing chart Are the same as the unit circuit SRa and its timing chart shown in FIGS. 5 and 6, respectively. For this reason, those figures and description are omitted. As the shift register and the unit circuit of the liquid crystal display device according to the present embodiment, the shift register 420 shown in FIG. 9 and the unit circuit SRb shown in FIG. 10, which are modifications of the first embodiment, can be used.

<2.2 Effect>
According to the liquid crystal display device of this embodiment, as in the case of the first embodiment, when the voltage of the video signal is charged in each pixel forming unit, a voltage close to the voltage of the video signal is charged in advance. Charging can be started from the state. As a result, a video signal can be written to each pixel formation portion at high speed, so that the display portion 10 with high definition can be provided or the display quality of a liquid crystal display device driven at high speed can be improved. .

Further, since the liquid crystal display device of the present embodiment is driven by the pseudo dot inversion driving method, the occurrence of flicker and crosstalk is suppressed. Thereby, the display quality of a liquid crystal display device can be improved.

<2.3 Modification>
For each of the plurality of gate signal lines, the polarities of the video signals applied to the odd-numbered source signal lines SL (2j + 1) and the even-numbered source signal lines SL (2j) may be reversed. FIG. 14 is a diagram for explaining a pseudo dot inversion driving method in which the polarity of the video signal held in the pixel formation unit is inverted every two gate signal lines. A video signal having the same polarity as that of the source signal line shown in FIG. 13 is applied to each source signal line. However, as shown in FIG. 14, the upper two rows of pixel formation portions are connected to the odd-numbered column source signal lines SL (2j + 1), and the next two rows of pixel formation portions are the even-numbered column source signal lines SL (2j). It is connected to the. For this reason, as shown in FIG. 14A, in the odd-numbered frame period, the upper two rows of pixel forming units alternately hold positive and negative video signals in order from the left side, The next two rows of pixel formation units alternately hold a negative video signal and a positive video signal in order from the left. Further, as shown in FIG. 14B, in the even-numbered frame period, the polarity of the video signal held in each pixel formation portion is opposite to that shown in FIG. As a result, the polarity of the video signal written in each pixel forming unit is such that the pixel forming unit holding the positive and negative video signals every two rows in the row direction and every column in the column direction. This is substantially the same arrangement (staggered arrangement) as in the case of arranged dot inversion driving. The liquid crystal display device having the display unit 10 having such an arrangement also has the same effect as the liquid crystal display device having the arrangement shown in FIG. Note that the number of gate signal lines connected together to the odd-numbered source signal lines SL (2j + 1) and the even-numbered source signal lines SL (2j) is not limited to two, and may be more than that. Good.

The display device of the present invention can be used for a high-definition display device because a video signal can be written to the pixel formation portion at high speed.

DESCRIPTION OF SYMBOLS 10 ... Display part 11 ... Thin-film transistor 30 ... Source driver (data signal line drive circuit)
40. Gate driver (scanning signal line driving circuit)
410, 420: Shift registers SRa (1) to SRa (n), SRb (1) to SRb (n) ... Unit circuit T5 ... Transistor (collective drive circuit)
AON: all-on control signal VGP: precharge voltage signal GCK1, GCK2: first gate clock signal, second gate clock signal CKA, CKB: first clock, second clock GL1-GLn: gate signal lines (scanning signal lines)
SL1 to SLm ... Source signal line (data signal line)
VBD: Batch drive signal S (1) to S (m) ... Video signal (data signal)
GOUT1 to GOUTn: Scanning signal SPC +, SPC-: Intermediate voltage on the positive polarity side and intermediate voltage on the negative polarity side of the precharge signal

Claims (10)

1. An active matrix display device,
   The plurality of data signal lines, the plurality of scanning signal lines intersecting with the plurality of data signal lines, and the intersections of the plurality of data signal lines and the plurality of scanning signal lines are arranged in a matrix. A display unit having a plurality of pixel formation units;
   A data signal line driving circuit for driving the plurality of data signal lines;
   A scanning signal line driving circuit for driving the plurality of scanning signal lines,
   The data signal line driving circuit generates a plurality of video signals representing a video to be displayed as a signal whose voltage polarity is inverted for each data signal line and every predetermined number of frame periods, to the plurality of data signal lines. Each of the plurality of data signal lines is applied with a precharge signal having a voltage corresponding to an intermediate gray level of a video signal in order to precharge the plurality of pixel formation portions in the blanking period of the frame period. Applied,
   The scanning signal line driving circuit applies a collective driving signal for simultaneously selecting the plurality of scanning signal lines to the plurality of scanning signal lines during the blanking period, and the plurality of video signals are the plurality of video signals. A display device, wherein when applied to each of the data signal lines, a scanning signal for sequentially selecting the plurality of scanning signal lines is applied to each of the plurality of scanning signal lines.
2. The voltage of the precharge signal is different between a data signal line to which a positive video signal is applied and a data signal line to which a negative video signal is applied. The display device described.
3. Further comprising a backlight unit provided on the back of the display unit,
   3. The backlight unit according to claim 2, wherein the backlight unit is turned on during a period from when the plurality of video signals are respectively written to all of the plurality of pixel formation portions to when the next frame period starts. Display device.
4. The scanning signal line drive circuit and the data signal line drive circuit stop operating in a period from when the plurality of video signals are written to all of the plurality of pixel formation portions until the next frame period starts. The display device according to claim 2, wherein:
5. The pixel formation unit arranged in parallel with the plurality of data signal lines among the plurality of pixel formation units is connected to a data signal line adjacent in the same direction. Display device.
6. Among the plurality of pixel forming portions, each pixel forming portion arranged in parallel with the plurality of data signal lines alternately has a predetermined number of data signal lines adjacent in the same direction and data signal lines adjacent in the opposite direction. The display device according to claim 2, wherein the display device is connected.
7. The scanning signal line driving circuit has a configuration in which a plurality of unit circuits each composed of a transistor of the same conductivity type are connected in multiple stages, and includes a shift register that operates based on a two-phase clock composed of a first clock and a second clock. Prepared,
   The unit circuit is
   An output terminal for outputting the scanning signal and the collective driving signal to a scanning signal line;
   An output signal generation circuit that generates an on-voltage and an off-voltage and outputs the output voltage as the scanning signal to the output terminal;
   A collective drive circuit that outputs an on-voltage to the output terminal as the collective drive signal;
   When an ON voltage is simultaneously applied to the collective drive circuit of the plurality of unit circuits during the blanking period of the frame period, the collective drive circuit simultaneously outputs the collective drive signal to the plurality of scanning signal lines. The display device according to claim 1, wherein:
8. The collective drive circuit has one transistor,
   The transistor has one conduction terminal connected to the output terminal, and outputs the pulse signal applied to the other conduction terminal to the output terminal as the collective drive signal when the ON voltage is applied to the control terminal. The display device according to claim 7, wherein:
9. The collective drive circuit has one transistor,
   The transistor has one conduction terminal connected to the output terminal and outputs the power supply voltage connected to the other conduction terminal to the output terminal as the collective driving signal when the ON voltage is applied to the control terminal. The display device according to claim 7, wherein:
10. The plurality of data signal lines, the plurality of scanning signal lines intersecting with the plurality of data signal lines, and the intersections of the plurality of data signal lines and the plurality of scanning signal lines are arranged in a matrix. A driving method of an active matrix display device comprising a plurality of pixel forming portions,
    In the blanking period of the frame period, a precharge signal having a voltage corresponding to an intermediate gray level of a video signal is applied to each of the plurality of data signal lines in order to precharge the plurality of pixel formation portions. Simultaneously writing the precharge signal to the plurality of pixel forming portions by applying a collective driving signal for simultaneously selecting the scanning signal lines to the plurality of scanning signal lines;
    A plurality of video signals representing video to be displayed are generated for each data signal line as a signal whose voltage polarity is inverted every predetermined number of frame periods, applied to each of the plurality of data signal lines, and And writing each of the plurality of video signals to the plurality of pixel forming portions by applying a scanning signal for sequentially selecting the scanning signal lines to each of the plurality of scanning signal lines. Driving method.

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