WO2013002191A1

WO2013002191A1 - Holding circuit, display drive circuit, display panel, and display device

Info

Publication number: WO2013002191A1
Application number: PCT/JP2012/066194
Authority: WO
Inventors: 真横山; 成古田; 村上　祐一郎; 業天　誠二郎
Original assignee: シャープ株式会社
Priority date: 2011-06-30
Filing date: 2012-06-25
Publication date: 2013-01-03

Abstract

Provided is a latch circuit (15) that, while holding a signal (CMI) acquired when a signal (SROn) is active, outputs a signal (OUTn) that is in response to the signal (CMI). An inverter (18) is configured from a CMOS circuit comprising an N-channel transistor (TN1) and a P-channel transistor (TP1), and a low-level initialization signal (INITB) is input to the source terminal of the P-channel transistor (TP1). As a result, initialization is performed without increasing the number of elements.

Description

Holding circuit, display driving circuit, display panel, and display device

The present invention relates to a holding circuit capable of holding an acquired data signal and outputting based on the data signal, and a display driving circuit, a display panel, and a display device including the holding circuit.

Conventionally, a latch circuit (holding circuit) that captures and outputs a second signal while the first signal is active has been widely used. In addition to being used alone, the latch circuit is used by forming a shift register or the like by connecting in multiple stages. For example, in a liquid crystal display device, a number of latch circuits are mounted on a display drive circuit that drives a liquid crystal panel.

Here, in the latch circuit, if it is uncertain which reference power source the internal node of the latch circuit is connected to when the power is turned on, an unexpected potential may occur and a malfunction may occur, or a short circuit may occur with a node of a different potential. There was a problem that an overcurrent flowed. Therefore, a latch circuit has been proposed that can be initialized so that the internal node is reliably connected to a stable potential when the power is turned on (see, for example, Patent Documents 1 to 3).

FIG. 37 is a circuit diagram showing a configuration of a latch circuit 900 with an initialization function described in Patent Document 1. As shown in FIG. 37, the latch circuit 900 includes clocked

inverters

901 and 902 and a NAND circuit 903. The latch circuit 900 can be initialized by the initialization signal INITB, takes in the video signal DAT according to the Q signal / QB signal, and outputs it as an output signal LOUT while holding it. 904 in FIG. 37 is a control circuit for performing initialization.

The

clocked inverters

901 and 902 have a general clocked inverter configuration. FIG. 38 is a diagram showing a configuration of a general clocked inverter 910, in which (a) shows a circuit configuration and (b) shows a logic circuit symbol. The clocked inverter 910 includes two P-channel transistors P1 and P2 and two N-channel transistors N1 and N2.

In the clocked inverter 910, when the control signal is at a high level, an inverted signal of the input signal IN is output as the output signal OUT. In FIG. 38, the Q signal is used as the control signal. However, the QB signal can be used as the control signal by supplying the Q signal to the transistor P1 and the QB signal to the transistor N2. The clocked inverter 901 uses the QB signal as a control signal, and the clocked inverter 902 uses the Q signal as a control signal.

FIG. 39 is a timing chart when the latch circuit 900 shown in FIG. 37 operates.

First, the normal operation will be described. Normally, the initialization signal INITB is fixed at the high level (Vdd). When the Q signal changes from the high level (active) to the low level (inactive) in the first frame, that is, when the QB signal changes from the low level (inactive) to the high level (active), the video signal DAT (here, the video signal DAT) Low level) is captured, and an inverted signal of the video signal DAT is output from the clocked inverter 901. As a result, a low level (Vss) output signal LOUT is output from the NAND circuit 903 that receives the high level output signal from the clocked inverter 901 and the high level initialization signal INITB. Note that the output of the clocked inverter 902 is in a high impedance period while the QB signal is at a high level.

Thereafter, when the QB signal changes from the high level to the low level, the output of the clocked inverter 901 becomes high impedance, and the output is disconnected from the input. At this time, since the Q signal is at the high level, the clocked inverter 902 holds the output signal LOUT at the low level. This output signal LOUT continues to be output until the QB signal becomes high level next time.

Subsequently, when the QB signal changes from the low level to the high level, the clocked inverter 901 takes in the video signal DAT (here, high level) at this time, and outputs the inverted signal to the NAND circuit 903. As a result, a high level (Vdd) output signal LOUT is output from the NAND circuit 903, and this output signal LOUT continues to be output even after the QB signal changes from the high level to the low level.

In this way, the latch circuit 900 repeats the latch output operation at the normal time. Next, the operation at initialization will be described.

When initialization is desired, the initialization signal INITB is set to low level (Vss). When the initialization signal INITB becomes low level, the NAND circuit 903 generates a high level (Vdd) output signal LOUT regardless of the potential of the other input terminal. As a result, the potential of the output signal LOUT is forcibly fixed to a high level. Therefore, by providing the low-level initialization signal INITB, it is possible to eliminate the indefinite state when the power is turned on, stabilize the internal circuit, and avoid the malfunction of the subsequent circuit.

Japanese Patent Publication “Japanese Patent Laid-Open No. 11-52931 (published on February 26, 1999)” Japanese Patent Publication “Japanese Patent Laid-Open No. 10-39823 (published on February 13, 1998)” Japanese Patent Publication “Japanese Patent Laid-Open No. 2000-259132 (published on September 22, 2000)”

Incidentally, in recent years, in order to narrow the frame of a liquid crystal display device, there has been a demand for downsizing a display driving circuit for driving a liquid crystal panel. Since the scale of the display driving circuit greatly affects the number of transistors included in the circuit, it is important to reduce the number of transistors. As described above, since a large number of latch circuits are mounted on the display driving circuit, reducing the number of transistors in the latch circuit greatly contributes to narrowing the frame of the liquid crystal display device.

However, in order to add an initialization function to the latch circuit, it is necessary to add a control circuit for initialization like the control circuit 904 in FIG. For this reason, a control circuit and terminal wiring are added to a normal latch circuit, and there is a problem that the number of elements and wiring area increase, and the circuit scale increases. Since the addition of the initialization function leads to an increase in the frame size, it is not suitable for narrowing the frame of the liquid crystal display device.

The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a holding circuit, a display driving circuit, a display panel, and a display device that can be initialized without increasing the number of elements. There is.

In order to solve the above problems, the holding circuit of the present invention provides
A holding circuit that captures a holding target signal when the control signal becomes active, and outputs an output signal corresponding to the holding target signal while holding the holding target signal until the control signal becomes active next,
Comprising at least one inverter for holding the hold target signal;
The inverter includes a CMOS circuit in which gate terminals and drain terminals of a P-channel first transistor and an N-channel second transistor are connected to each other.
An initialization signal having a high level or a low level at the time of initialization is input to the source terminal of the first transistor or the source terminal of the second transistor.

According to the above configuration, the initialization target signal that is at the high level or the low level at the time of initialization is input to the source terminal of the first transistor or the second transistor of the inverter, whereby the retention target signal is retained. It is possible to fix the potential of the input terminal and the output terminal of the inverter related to the potential and the output potential of the output signal at a desired potential. Further, the potential of the initialization signal is set to a potential that does not generate a large through current in the circuit (for example, when the initialization signal is input to the source terminal of the first transistor, the initialization signal is set to the low level). When the signal is input to the source terminal, the signal can be stably fixed.

In addition, the initialization signal should not be supplied by adding a new initialization control circuit or terminal wiring, but should use the inverter power supply wiring that was provided before the initialization function was added. Can do.

Therefore, the holding circuit can be initialized without increasing the number of elements.

In order to solve the above problems, the display driving circuit of the present invention provides
A display driving circuit for driving a display panel provided with a pixel electrode and a signal line forming a capacitor included in a pixel,
A shift register including a plurality of stages provided corresponding to each of the plurality of scanning signal lines;
And at least one holding circuit provided corresponding to each stage of the shift register,
The holding circuit is the holding circuit described above, and the output signal of each stage of the shift register is used as the control signal,
When an output signal of one stage of the shift register becomes active, a holding circuit corresponding to this stage takes in the holding target signal and holds it, and outputs an output signal corresponding to the holding target signal to this stage. The signal line is supplied to the corresponding signal line.

According to the above configuration, since the holding circuit that can be initialized without increasing the number of elements is provided, the display driving circuit can be stabilized by the initialization, and the circuit scale can be reduced. Since it is possible to reduce the size, for example, it is possible to contribute to the narrowing of the frame of a display device equipped with a display drive circuit.

As described above, in the holding circuit of the present invention, a high-level or low-level initialization signal is input to any one of the source terminal of the first transistor and the source terminal of the second transistor. It has a configuration. Therefore, there is an effect that initialization can be performed without increasing the number of elements.

FIG. 3 is a circuit diagram showing a configuration of a latch circuit according to the first embodiment. 3 is a timing chart during operation of the latch circuit of FIG. 1. FIG. 6 is a circuit diagram showing a modification of the latch circuit according to the first embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a latch circuit according to a second embodiment. 5 is a timing chart at the time of initialization of the latch circuit of FIG. 4. 5 is a timing chart at the time of initialization of the latch circuit of FIG. 4. 5 is a timing chart at the time of initialization of the latch circuit of FIG. 4. 5 is a timing chart at the time of initialization of the latch circuit of FIG. 4. FIG. 9 is a circuit diagram showing a modification of the latch circuit according to the second embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a latch circuit according to a third embodiment. 11 is a timing chart at the time of initialization of the latch circuit of FIG. 10. 11 is a timing chart at the time of initialization of the latch circuit of FIG. 10. 11 is a timing chart at the time of initialization of the latch circuit of FIG. 10. 11 is a timing chart at the time of initialization of the latch circuit of FIG. 10. FIG. 10 is a circuit diagram showing a modification of the latch circuit according to the third embodiment. FIG. 6 is a block diagram illustrating a schematic configuration of a liquid crystal display device according to a fourth embodiment. FIG. 17 is an equivalent circuit diagram illustrating an electrical configuration of a pixel of the liquid crystal display device of FIG. 16. 3 is a circuit diagram of a unit circuit included in a common electrode driving circuit according to Embodiment 1. FIG. FIG. 3 is a circuit diagram of a generation circuit that generates a polarity signal CMIZ input to the common electrode drive circuit according to the first embodiment. 3 is a timing chart during operation of the common electrode drive circuit according to the first embodiment. FIG. 6 is a diagram schematically illustrating a timing chart during operation of the common electrode driving circuit according to the first embodiment. 3 is a timing chart at the time of initialization of the common electrode drive circuit according to the first embodiment. 3 is a timing chart at the time of initialization of the common electrode drive circuit according to the first embodiment. 6 is a circuit diagram of a unit circuit included in a common electrode drive circuit according to Embodiment 2. FIG. FIG. 10 is a circuit diagram of a generation circuit that generates a polarity signal CMIZ input to a common electrode drive circuit according to the second embodiment. 6 is a circuit diagram of a unit circuit included in a common electrode driving circuit according to Example 3. FIG. FIG. 10 is a circuit diagram of a generation circuit that generates a polarity signal CMIZ input to a common electrode drive circuit according to a third embodiment. FIG. 10 is a circuit diagram of a unit circuit included in a common electrode driving circuit according to Example 4. FIG. 10 is a circuit diagram of a generation circuit that generates a polarity signal CMIZ input to a common electrode drive circuit according to a fourth embodiment. FIG. 10 is a block diagram illustrating a modification of the liquid crystal display device according to the fourth embodiment. FIG. 10 is a block diagram illustrating a schematic configuration of a liquid crystal display device according to a fifth embodiment. FIG. 3 is a circuit diagram of a unit circuit included in the storage capacitor line driving circuit according to the first embodiment. 4 is a timing chart during operation of the storage capacitor wiring drive circuit according to the first embodiment. FIG. 6 is a diagram schematically illustrating a timing chart during operation of the storage capacitor wiring driving circuit according to the first embodiment. 3 is a timing chart at the time of initialization of the storage capacitor wiring driving circuit according to the first embodiment. 3 is a timing chart at the time of initialization of the storage capacitor wiring driving circuit according to the first embodiment. It is a circuit diagram which shows the structure of the latch circuit with the conventional initialization function. It is a figure which shows the structure of a general clocked inverter, (a) shows a circuit structure, (b) shows a logic circuit symbol. FIG. 38 is a timing chart during operation of the conventional latch circuit of FIG. 37. FIG.

[Embodiment 1]
The following describes Embodiment 1 of the present invention with reference to the drawings.

FIG. 1 is a circuit diagram showing one configuration example of the latch circuit 15 of the present embodiment. As shown in FIG. 1, the latch circuit 15 (holding circuit) includes clocked

inverters

16 and 17 and an inverter 18 (first inverter). The latch circuit 15 is mounted on, for example, a display drive circuit that drives a liquid crystal panel. Here, the polarity signal CMI (holding target signal) is determined according to the output signal SROn (control signal) of each stage of the shift register. And outputting the output signal OUTn while holding this will be described.

The clocked

inverters

16 and 17 have the configuration of the clocked inverter 910 shown in FIG. The clocked inverter 16 uses the output signal SROn as a control signal, and the clocked inverter 17 uses the output signal SROBn as a control signal. The polarity signal CMI is supplied to the input terminal of the clocked inverter 16, and the output terminal of the clocked inverter 16 is connected to the input terminal of the inverter 18. The input terminal of the clocked inverter 17 is connected to the output terminal of the inverter 18, and the output terminal of the clocked inverter 17 is connected to the input terminal of the inverter 18.

The inverter 18 is composed of a CMOS circuit including a P-channel transistor TP1 (first transistor) and an N-channel transistor TN1 (second transistor). An initialization signal INITB is supplied to the source terminal of the transistor TP1, the gate terminal of the transistor TP1 is connected to the input terminal of the inverter 18, and the drain terminal of the transistor TP1 is connected to the output terminal of the inverter 18. The source voltage Vss is applied to the source terminal of the transistor TN1, the gate terminal of the transistor TN1 is connected to the input terminal of the inverter 18, and the drain terminal of the transistor TN1 is connected to the output terminal of the inverter 18. An output signal OUTn is output from the output terminal of the inverter 18. The initialization signal INITB is a signal that is at a high level (Vdd) during normal operation and is at a low level (Vss) at initialization (when active).

(About operation)
Next, the operation of the latch circuit 15 will be described. FIG. 2 is a timing chart when the latch circuit 15 operates.

CMI is a polarity signal whose polarity is inverted every horizontal scanning period (1H). INITB indicates the potential of the initialization signal INITB. SROn indicates the potential of the n-th output signal SROn of the shift register, and SROBn indicates the potential of the inverted signal of the output signal SROn. OUTn indicates the potential of the output signal OUTn of the latch circuit 15, and OUTBn indicates the potential of the inverted signal of the output signal OUTn. Note that FIG. 2 shows the first and subsequent frames from which the normal operation is started after the power is turned on.

First, the normal operation will be described. In the first frame, when the output signal SRon of the shift register changes from the low level (inactive) to the high level (active), the polarity signal CMI (here, high level (Vdd)) is taken in by the clocked inverter 16, and the polarity signal An inverted signal of CMI is output from the clocked inverter 16. Since the initialization signal INITB is fixed at Vdd (high level) in the normal time, the transistor TP1 is turned on in the inverter 18 and the transistor TN1 is turned off, so that the output signal of the inverter 18 is Vdd (high level). As a result, a high level (Vdd) output signal OUTn is output. Note that the output of the clocked inverter 17 is in a high impedance period while the output signal SRon is at a high level.

Thereafter, when the output signal SROn of the shift register changes from the high level to the low level, the output of the clocked inverter 16 becomes high impedance, and the output is disconnected from the input. At this time, since the output signal SROBn is at the high level, the clocked inverter 17 holds the output signal OUTn at the high level. This output signal OUTn continues to be output until the next output signal SRon becomes high level.

Subsequently, when the output signal SRon of the shift register changes from the low level to the high level, the clocked inverter 16 takes in the polarity signal CMI (here, the low level (Vss)) at this time, and the inverted signal is input to the inverter 18. Is output. As a result, the output signal OUTn of the low level (Vss) is output from the inverter 18, and this output signal OUTn continues to be output even after the output signal SROn changes from the high level to the low level. In this way, the latch circuit 15 repeats the latch output operation at the normal time.

(About initialization operation)
Next, the operation at initialization will be described. At initialization, the initialization signal INITB is set to Vss (low level).

At initialization, when the output signal SRon of the shift register is Vss (low level), the operation is as follows (see FIG. 2).

When the initialization signal INITB becomes low level, the output signal of the inverter 18, that is, the potential of the output signal OUTn is forcibly fixed to Vss (low level). At this time, since the clocked inverter 17 functions as an inverter, the potential of the output signal OUTBn becomes Vdd (high level) when the potential of the output signal OUTn becomes Vss. Further, since the clocked inverter 16 has high impedance, the output signal OUTBn is electrically disconnected from the polarity signal CMI. Therefore, the output signal OUTn can be stabilized at the Vss potential and the output signal OUTBn can be stabilized at the Vdd potential.

On the other hand, when the output signal SROn of the shift register is Vdd (high level) at the time of initialization, the operation is as follows (not shown).

When the initialization signal INITB becomes low level, the potential of the output signal OUTn that is the output signal of the inverter 18 is forcibly fixed to Vss (low level). At this time, the clocked inverter 16 functions as an inverter, and the clocked inverter 17 has a high impedance. Thereby, the potential of the output signal OUTBn is fixed to the inverted potential of the polarity signal CMI. Therefore, both the output signal OUTn and the output signal OUTBn can be stabilized at the Vss potential and the inverted potential of the polarity signal CMI.

As described above, in the latch circuit 15, regardless of whether the output signal SROn is high level or low level, the initialization signal INITB of low level (Vss) is given to the source terminal of the transistor TP1, thereby providing the internal signal. It becomes possible to fix the potential at a stable potential.

In addition, the initialization signal INITB can be supplied by newly adding a control circuit and terminal wiring for initialization, but the inverter 18 provided in the latch circuit before the initialization function is added. The power supply VDD wiring is used.

Therefore, the latch circuit 15 can be initialized without increasing the number of elements.

During normal operation, the initialization signal INITB is fixed at Vdd (high level), so the initialization signal INITB performs the same function as the power supply voltage Vdd. Is possible.

(Modification)
In the latch circuit 15, the initialization signal INITB is supplied to the source terminal of the transistor TP1, but the initialization signal INIT can be supplied to the source terminal of the transistor TN1 and similarly initialized.

FIG. 3 is a circuit diagram showing a configuration example of the latch circuit 19. As shown in FIG. 3, the latch circuit 19 (holding circuit) differs from the latch circuit 15 of FIG. 1 in the signals and power supply voltages supplied to the source terminal of the transistor TP1 and the source terminal of the transistor TN1, respectively. Yes. Specifically, the power supply voltage Vdd is supplied to the source terminal of the transistor TP1, and the initialization signal INIT is supplied to the source terminal of the transistor TN1. The initialization signal INIT is a signal that becomes low level (Vss) during normal operation and becomes high level (Vdd) during initialization.

(About initialization operation)
Here, the operation at the time of initialization will be described. At initialization, the initialization signal INIT is set to Vdd (high level).

At initialization, if the output signal SRon of the shift register is Vss (low level), the operation is as follows.

When the initialization signal INIT becomes high level, the output signal of the inverter 18, that is, the potential of the output signal OUTn is forcibly fixed to Vdd (high level). At this time, since the clocked inverter 17 functions as an inverter, when the potential of the output signal OUTn becomes Vdd, the potential of the output signal OUTBn becomes Vss (low level). Since the clocked inverter 16 has high impedance, the output signal OUTBn is electrically disconnected from the polarity signal CMI. Therefore, the output signal OUTn can be stabilized at the Vdd potential and the output signal OUTBn can be stabilized at the Vss potential.

On the other hand, when the output signal SROn of the shift register is Vdd (high level) at the time of initialization, the operation is as follows.

When the initialization signal INIT becomes high level, the potential of the output signal OUTn that is the output signal of the inverter 18 is forcibly fixed to Vdd (high level). At this time, the clocked inverter 16 functions as an inverter, and the clocked inverter 17 has a high impedance. Thereby, the potential of the output signal OUTBn is fixed to the inverted potential of the polarity signal CMI. Therefore, the output signal OUTn can be stabilized at the Vdd potential, and the output signal OUTBn can be stabilized at the inverted potential of the polarity signal CMI.

As described above, in the latch circuit 19, regardless of whether the output signal SRon is high level or low level, the initialization signal INIT of high level (Vdd) is given to the source terminal of the transistor TN 1, thereby It becomes possible to fix the potential at a stable potential.

In addition, the initialization signal INIT is not made to be able to be supplied by newly adding a control circuit and terminal wiring for initialization, but is an inverter 18 provided in the latch circuit before the initialization function is added. The power supply VSS wiring is used.

Therefore, the latch circuit 19 can be initialized without increasing the number of elements.

In the normal operation, the initialization signal INIT is fixed at Vss (low level), so that the initialization signal INIT performs the same function as the power supply voltage Vss. Therefore, the latch circuit 19 can perform the same operation as a normal latch circuit, and can operate in the same manner as the normal operation of the latch circuit 15 described above.

[Embodiment 2]
Embodiment 2 of the present invention will be described below with reference to the drawings. In the present embodiment, the polarity signal CMI is taken in accordance with the output signal SROUT (k−1) of the previous stage (k−1 stage) of the shift register, and the output of the own stage (k stage) is held while holding it. A latch circuit that outputs the output signal OUTk will be described.

FIG. 4 is a circuit diagram showing a configuration example of the latch circuit 31 of the present embodiment. As shown in FIG. 4, the latch circuit 31 (holding circuit) includes an inverter INV1 (first inverter), an inverter INV2 (second inverter), an inverter INV3, an analog switch circuit ASW1, and an analog switch circuit ASW2. Note that a connection point between the output terminal of the analog switch circuit ASW1 and the input terminal of the inverter INV2 is a node N1, and a connection point between the output terminal of the inverter INV1 and the input terminal of the analog switch circuit ASW2 is a node N2 (see FIG. 4). ).

The input terminal of the inverter INV3 is connected to the input terminal INs of the latch circuit 31. The analog switch circuit ASW1 includes an N-channel transistor T1 and a P-channel transistor T2, and the transistor T1 has a gate terminal connected to the input terminal INs, a source terminal connected to the input terminal INc, and a transistor T2 including a gate. The terminal is connected to the output terminal of the inverter INV3, and the source terminal is connected to the input terminal INc. The output signal SROUT (k−1) of the previous stage of the shift register is supplied to the input terminal INs, and the polarity signal CMI is supplied to the input terminal INc.

The inverter INV2 includes a P-channel transistor T3 (first transistor) and an N-channel transistor T4 (second transistor). The inverter INV2 is connected to the input terminal (the gate terminal of the transistor T3 and the gate terminal of the transistor T4). The point (node N1)) is connected to the output terminal of the analog switch circuit ASW1 (drain terminals of the transistors T1 and T2). The power supply voltage Vdd is applied to the source terminal of the transistor T3, and the drain terminal of the transistor T3 is connected to the output terminal of the inverter INV2 (the connection point between the drain terminal of the transistor T3 and the drain terminal of the transistor T4). The source terminal is supplied with the power supply voltage Vss, and the drain terminal of the transistor T4 is connected to the output terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the output terminal OUT of the latch circuit 31 and the input terminal of the inverter INV1 (gate terminals of the transistors T5 and T6).

The inverter INV1 includes a P-channel transistor T5 (first inverter) and an N-channel transistor T6 (second inverter). The input terminal of the inverter INV1 (the gate terminals of the transistors T5 and T6) is the output terminal of the inverter INV2. It is connected to the. The initialization signal INITB is given to the source terminal of the transistor T5, and the drain terminal of the transistor T5 is connected to the input terminal of the analog switch circuit ASW2 (the connection point between the source terminal of the transistor T7 and the source terminal of the transistor T8 (node N2 )), The power supply voltage Vss is applied to the source terminal of the transistor T6, and the drain terminal of the transistor T6 is connected to the input terminal of the analog switch circuit ASW2.

The analog switch circuit ASW2 includes an N-channel transistor T7 and a P-channel transistor T8. The transistor T7 has a gate terminal connected to the output terminal of the inverter INV3, a source terminal connected to the output terminal of the inverter INV1, and a drain. The terminal is connected to the input terminal of the inverter INV2, the transistor T8 has a gate terminal connected to the input terminal INs, a source terminal connected to the output terminal of the inverter INV1, and a drain terminal connected to the input terminal of the inverter INV2. .

According to the above configuration, in the latch circuit 31, the output signal SROUT (k−1) of the previous stage (k−1 stage) of the shift register is input to the input terminal INs, and the output signal SROUT (k−1) is When activated, the polarity signal CMI is taken from the input terminal INc, and while holding it, the output signal OUTk is output from the output terminal OUT as the output of the own stage (kth stage). The output signal OUTk is output after switching between a high level (Vdd) and a low level (Vss). The initialization signal INITB is a signal that is at a high level (Vdd) during normal operation and is at a low level (Vss) at initialization (when active).

(About operation)
Next, the operation of the latch circuit 31 will be described.

First, we will briefly explain the normal operation. Normally, the initialization signal INITB is fixed at Vdd (high level).

In the latch circuit 31, when the output signal SROUT (k-1) changes from low level (inactive) to high level (active), the analog switch circuit ASW1 is turned on (transistors T1 and T2 are turned on), and the analog switch circuit ASW2 is turned on. It is off (transistors T7 and T8 are off). As a result, the node N1 is electrically connected to the polarity signal CMI and has the same potential. Node N1 is electrically disconnected from node N2. Therefore, when the polarity signal CMI is Vdd (high level), the output of the inverter INV2 is Vss (low level), and the output signal OUTk of low level (Vss) is output. On the other hand, when the polarity signal CMI is Vss (low level), the output of the inverter INV2 is Vdd (high level), and the output signal OUTk of high level (Vdd) is output.

Subsequently, when the output signal SROUT (k−1) changes from the high level (active) to the low level (inactive), the analog switch circuit ASW1 is turned off (the transistors T1 and T2 are turned off), and the analog switch circuit ASW2 is turned on ( The transistors T7 and T8 are turned on). Thereby, the output terminal of the inverter INV2 and the input terminal of the inverter INV1 are electrically connected to each other, and the output terminal of the inverter INV1 and the input terminal of the inverter INV2 are electrically connected to each other. The potential held immediately before is held by the latch operation by the inverters INV1 and INV2. Therefore, the output signal OUTk continues to be output with the potential output immediately before. The output signal OUTk continues to be output until the output signal SROUT (k−1) next becomes high level (active), and when the output signal SROUT (k−1) becomes high level, the latch output operation is performed in the same manner. . In this way, the latch circuit 31 repeats the latch output operation at the normal time.

(About initialization operation)
Next, the operation at initialization will be described. At initialization, the initialization signal INITB is set to Vss (low level). FIG. 5 is a timing chart at the time of initialization of the latch circuit 31 when the output signal SROUT of all stages of the shift register is at the high level and the polarity signal CMI is at the high level. FIG. 6 is a timing chart at the time of initialization of the latch circuit 31 when the output signal SROUT of all stages of the shift register is at the high level and the polarity signal CMI is at the low level. FIG. 7 is a timing chart at the time of initialization of the latch circuit 31 when the output signal SROUT of all stages of the shift register is at the low level and the polarity signal CMI is at the high level. FIG. 5 is a timing chart at the time of initialization of the latch circuit 31 when the output signal SROUT of all stages of the shift register is at the low level and the polarity signal CMI is at the low level.

5 to 8, CMI is a polarity signal whose polarity is inverted every horizontal scanning period (1H). INITB indicates the potential of the initialization signal INITB. SR (k-1) indicates the potential of the output signal SROUT (k-1) at the (k-1) stage of the shift register. Node1 and Node2 indicate potentials of the nodes N1 and N2, respectively. OUTk indicates the potential of the output signal OUTk of the latch circuit 31.

When the output signal SROUT of all stages of the shift register is at high level (all on) at initialization, the operation is as follows.

First, when the output signal SROUT (k-1) becomes high level, the switch circuit ASW1 is always turned on, and the polarity signal CMI is always connected (short-circuited) to the node N1. The node N1 is connected to the input terminal of the inverter INV2, and the output terminal of the inverter INV2 is connected to the output terminal OUT. As a result, the output signal OUTk having the inverted potential of the node N1 is always output from the output terminal OUT.

The initialization signal INITB is fixed at the Vss potential. Therefore, regardless of whether the output signal OUTk is the Vdd potential or the Vss potential, the potential of the node N2 that is the output terminal of the inverter INV1 becomes the Vss potential.

Therefore, when the polarity signal CMI is Vdd (high level), the node N1 can be fixed at the Vdd potential, the output signal OUTk can be fixed at the Vss potential, and the node N2 can be fixed at the Vss potential (see FIG. 5). When the polarity signal CMI is Vss (low level), the node N1 can be fixed at the Vss potential, the output signal OUTk can be fixed at the Vdd potential, and the node N2 can be fixed at the Vss potential (see FIG. 6). At this time, since the switch circuit ASW2 is always off, the node N1 and the node N2 are disconnected (electrically disconnected). Therefore, even if the polarity signal CMI is either high level or low level, initialization can be performed without causing a short circuit and generating an overcurrent.

On the other hand, when the output signal SROUT of all stages of the shift register is low level (all off) at the time of initialization, the operation is as follows.

Since the initialization signal INITB is fixed at the Vss potential, the node N2 that is the output terminal of the inverter INV1 is fixed at the Vss potential regardless of whether the output signal OUTk is the Vdd potential or the Vss potential.

Here, when the output signal SROUT (k−1) becomes a low level, the switch circuit ASW2 is always turned on, so that the node N1 and the node N2 are always connected (short-circuited). Therefore, the node N1 becomes the Vss potential, and thereby the output signal OUTk becomes the Vdd potential. At this time, since the switch circuit ASW1 is always turned off, the polarity signal CMI and the node N1 are disconnected. Therefore, the potentials of the node N1, the node N2, and the output signal OUTk are the same regardless of whether the polarity signal CMI is high level or low level (see FIGS. 7 and 8). Thus, initialization can be performed without causing a short circuit and generating an overcurrent.

In this way, in the latch circuit 31, the initialization signal INITB at the low level (Vss) is supplied to the source terminal of the transistor T5 regardless of whether the output signal SROUT at all stages of the shift register is at the high level or the low level. It is possible to fix the internal potential at a stable potential.

In addition, the initialization signal INITB can be supplied by adding a new initialization control circuit and terminal wiring, but is not provided in the inverter INV1 provided in the latch circuit before the initialization function is added. The power supply VDD wiring is used.

Therefore, the latch circuit 31 can be initialized without increasing the number of elements.

In the normal operation, the initialization signal INITB becomes Vdd (high level), and the initialization signal INITB performs the same function as the power supply voltage Vdd, so that the same operation as that of a normal latch circuit is possible.

(Modification)
In the latch circuit 31, the initialization signal INITB is supplied to the source terminal of the transistor T5. However, the initialization signal INIT can be supplied to the source terminal of the transistor T6 and similarly initialized.

FIG. 9 is a circuit diagram showing a configuration example of the latch circuit 32. As shown in FIG. 9, the latch circuit 32 (holding circuit) differs from the latch circuit 31 of FIG. 4 in the signals and power supply voltages supplied to the source terminal of the transistor T5 and the source terminal of the transistor T6, respectively. Yes. Specifically, the power supply voltage Vdd is supplied to the source terminal of the transistor T5, and the initialization signal INIT is supplied to the source terminal of the transistor T6. The initialization signal INIT is a signal that becomes low level (Vss) during normal operation and becomes high level (Vdd) during initialization.

First, when the output signal SROUT (k−1) becomes a high level, the switch circuit ASW1 is always fully turned on, and the polarity signal CMI is always connected (short-circuited) to the node N1. The node N1 is connected to the input terminal of the inverter INV2, and the output terminal of the inverter INV2 is connected to the output terminal OUT. As a result, the output signal OUTk having the inverted potential of the node N1 is always output from the output terminal OUT.

Further, since the initialization signal INIT is fixed at the Vdd potential, the node N2 that is the output terminal of the inverter INV1 is fixed at the Vdd potential regardless of whether the output signal OUTk is the Vdd potential or the Vss potential. The

Therefore, when the polarity signal CMI is Vdd (high level), the node N1 can be fixed at the Vdd potential, the output signal OUTk can be fixed at the Vss potential, and the node N2 can be fixed at the Vdd potential. When the polarity signal CMI is Vss (low level), the node N1 can be fixed at the Vss potential, the output signal OUTk can be fixed at the Vdd potential, and the node N2 can be fixed at the Vdd potential. At this time, since the switch circuit ASW2 is always turned off, the node N1 and the node N2 are disconnected (electrically disconnected). Therefore, even if the polarity signal CMI is either high level or low level, initialization can be performed without causing a short circuit and generating an overcurrent.

On the other hand, when the output signal SROUT of all stages of the shift register is at low level (all off) at the time of initialization, the operation is as follows.

Since the initialization signal INIT is fixed at the Vdd potential, the node N2 that is the output terminal of the inverter INV1 is fixed at the Vdd potential regardless of whether the output signal OUTk is the Vdd potential or the Vss potential.

Here, when the output signal SROUT (k−1) becomes a low level, the switch circuit ASW2 is always fully turned on, so that the node N1 and the node N2 are always connected (short-circuited). Therefore, the node N1 becomes the Vdd potential, and thereby the output signal OUTk becomes the Vss potential. At this time, since the switch circuit ASW1 is always turned off, the polarity signal CMI and the node N1 are disconnected. Therefore, the potentials of the node N1, the node N2, and the output signal OUTk are the same regardless of whether the polarity signal CMI is high level or low level. Thus, initialization can be performed without causing a short circuit and generating an overcurrent.

As described above, in the latch circuit 32, the high level (Vdd) initialization signal INIT is supplied to the source terminal of the transistor T6 regardless of whether the output signal SROUT of all stages of the shift register is high level or low level. It is possible to fix the internal potential at a stable potential.

In addition, the initialization signal INIT is not made to be able to be supplied by newly adding a control circuit and terminal wiring for initialization, but is an inverter INV1 provided in the latch circuit before adding the initialization function. The power supply VSS wiring is used.

Therefore, the latch circuit 32 can be initialized without increasing the number of elements.

In the normal operation, the initialization signal INIT is fixed at Vss (low level), so that the initialization signal INIT performs the same function as the power supply voltage Vss. Therefore, the latch circuit 32 can perform the same operation as a normal latch circuit, and can operate in the same manner as the normal operation of the latch circuit 31 described above.

[Embodiment 3]
Embodiment 3 of the present invention will be described below with reference to the drawings. In the present embodiment, a latch circuit capable of reducing the circuit area as compared with the latch circuit 31 of the second embodiment will be described. For convenience of explanation, members having the same functions as those shown in the above-described embodiments are denoted by the same reference numerals, and description thereof is omitted. In addition, the terms defined in the above embodiment are used in accordance with the definitions in this embodiment unless otherwise specified. This is common to the following embodiments.

FIG. 10 is a circuit diagram showing a configuration example of the latch circuit 33 of the present embodiment. As shown in FIG. 10, the latch circuit 33 (holding circuit) includes inverters INV1 and INV2 and an analog switch circuit ASW3. Note that a connection point between the output terminal of the analog switch circuit ASW3 and the input terminal of the inverter INV2 is a node N1 (see FIG. 10).

The analog switch circuit ASW3 is composed of an N-channel transistor T1, and the transistor T1 has a gate terminal connected to the input terminal INs and a source terminal connected to the input terminal INc. The output signal SROUT (k−1) of the previous stage of the shift register is supplied to the input terminal INs, and the polarity signal CMI is supplied to the input terminal INc.

The input terminal of the inverter INV2 (the connection point (node N1) between the gate terminal of the transistor T3 and the gate terminal of the transistor T4) is connected to the output terminal of the analog switch circuit ASW3 (drain terminal of the transistor T1). The output terminal of the inverter INV2 is connected to the output terminal OUT of the latch circuit 33 and the input terminal of the inverter INV1 (gate terminals of the transistors T5 and T6).

In the inverter INV1 of the latch circuit 33, a resistor R1 (second resistor) and a resistor R2 (first resistor) are added to the inverter INV1 of the latch circuit 31 (see FIG. 4) described above. Specifically, a resistor R2 is connected in series to the source terminal of the transistor T5, and a resistor R1 is connected in series to the source terminal of the transistor T6. As a result, the initialization signal INITB is applied to the source terminal of the transistor T5 via the resistor R2, and the power supply voltage Vss is applied to the source terminal of the transistor T6 via the resistor R1.

According to the above configuration, in the latch circuit 33, the output signal SROUT (k−1) of the previous stage (k−1 stage) of the shift register is input to the input terminal INs, and the output signal SROUT (k−1) is When activated, the polarity signal CMI is taken from the input terminal INc, and while holding it, the output signal OUTk is output from the output terminal OUT as the output of the own stage (kth stage). The output signal OUTk is output after switching between a high level (Vdd) and a low level (Vss). The initialization signal INITB is a signal that is at a high level (Vdd) during normal operation and is at a low level (Vss) at initialization (when active).

(About operation)
Next, the operation of the latch circuit 33 will be described.

In the latch circuit 33, when the output signal SROUT (k-1) changes from the low level (inactive) to the high level (active), the analog switch circuit ASW3 is turned on (the transistor T1 is turned on). Thereby, the node N1 is electrically connected to the polarity signal CMI.

At this time, when the polarity signal CMI is Vdd (high level), the node N1 has a Vdd-Vth potential (Vth: threshold). Since the potential of the node N1 is sufficient to turn on the transistor T4 of the inverter INV2, the output of the inverter INV2 becomes Vss (low level).

Here, immediately before the output signal SROUT (k−1) becomes high level (active), if the potential of the node N1 is held at Vss (low level) and the transistor T6 is turned on, When the signal SROUT (k−1) changes from the low level (inactive) to the high level (active), the Vdd (high level) of the polarity signal CMI and the power supply VSS (low level) are short-circuited via the node N1. It will be. In this respect, since the resistor R1 is provided between the power source VSS and the node N1, the potential of the node N1 is drawn to the polarity signal CMI side and rises to a potential close to Vdd (high level) of the polarity signal CMI. .

Thereafter, the output of the inverter INV2 (Vss (low level)) is fed back to the input of the inverter INV1, and the potential of the node N1 rises further from the potential close to Vdd of the polarity signal CMI to Vdd by the output of the inverter INV1. Therefore, the output of the inverter INV2 becomes Vss (low level), and the output signal OUTk of low level (Vss) is output.

On the other hand, when the polarity signal CMI is Vss (low level), the node N1 is at the Vss potential, so that the output of the inverter INV2 is Vdd (high level).

Here, immediately before the output signal SROUT (k−1) becomes high level (active), if the potential of the node N1 is held at Vdd (high level) and the transistor T5 is turned on, When the signal SROUT (k−1) is changed from the low level (inactive) to the high level (active), the Vss (low level) of the polarity signal CMI and the initialization signal INITB are input via the node N1. (INITB terminal) (high level) is short-circuited. In this respect, since the resistor R2 is provided between the INITB terminal (high level) and the node N1, the potential of the node N1 is drawn to the polarity signal CMI side and is close to Vss (low level) of the polarity signal CMI. Decreasing to potential.

Thereafter, the output (Vdd (high level)) of the inverter INV2 is fed back to the input of the inverter INV1, and the potential of the node N1 is further lowered from the potential close to Vss of the polarity signal CMI to Vss by the output of the inverter INV1. Therefore, the output of the inverter INV2 becomes Vdd (high level), and the output signal OUTk of high level (Vdd) is output.

Subsequently, when the output signal SROUT (k−1) changes from the high level (active) to the low level (inactive), the analog switch circuit ASW3 is turned off (the transistor T1 is turned off), and the input of the polarity signal CMI is cut off. The node N1 holds the potential held immediately before by the latch operation by the inverters INV1 and INV2. Therefore, the output signal OUTk continues to be output with the potential output immediately before. The output signal OUTk continues to be output until the output signal SROUT (k−1) next becomes high level (active), and when the output signal SROUT (k−1) becomes high level, the latch output operation is performed in the same manner. . In this way, the latch circuit 33 repeats the latch output operation at the normal time.

(About initialization operation)
Next, the operation at initialization will be described. At initialization, the initialization signal INITB is set to Vss (low level). FIG. 11 is a timing chart at the time of initialization of the latch circuit 33 when the output signal SROUT of all stages of the shift register is at the high level and the polarity signal CMI is at the high level. FIG. 12 is a timing chart when the latch circuit 33 is initialized when the output signals SROUT of all stages of the shift register are at the high level and the polarity signal CMI is at the low level. FIG. 13 is a timing chart when the latch circuit 33 is initialized when the output signals SROUT of all stages of the shift register are at the low level and the polarity signal CMI is at the high level. FIG. 14 is a timing chart at the time of initialization of the latch circuit 33 when the output signal SROUT of all stages of the shift register is at the low level and the polarity signal CMI is at the low level.

11 to 14, CMI is a polarity signal whose polarity is inverted every horizontal scanning period (1H). INITB indicates the potential of the initialization signal INITB. SR (k-1) indicates the potential of the output signal SROUT (k-1) at the (k-1) stage of the shift register. Node1 indicates the potential of the node N1. OUTk indicates the potential of the output signal OUTk of the latch circuit 33.

First, when the output signal SROUT (k-1) becomes high level, the switch circuit ASW3 is always turned on, and the polarity signal CMI is always connected (short-circuited) to the node N1. The node N1 is connected to the input terminal of the inverter INV2, and the output terminal of the inverter INV2 is connected to the output terminal OUT. As a result, the output signal OUTk having the inverted potential of the node N1 is always output from the output terminal OUT.

Here, when the polarity signal CMI is Vdd (high level), the node N1 has a Vdd-Vth potential (Vth: threshold) (see FIG. 11). Since the potential of the node N1 is sufficient to turn on the transistor T4 of the inverter INV2, a low level (Vss) output signal OUTk is output by the inverter INV2. The output signal OUTk turns on the transistor T5 of the inverter INV1, and the INITB terminal is connected to the node N1 through the resistor R2. At this time, the initialization signal INITB is fixed at Vss (low level), but since it is connected to the node N1 via the resistor R2, the node N1 is stable without overcurrent flowing in the vicinity of Vdd-Vth. Can be realized.

When the polarity signal CMI is Vss (low level), the node N1 has a Vss potential (see FIG. 12). As a result, the transistor T3 of the inverter INV2 is turned on, and a high level (Vdd) output signal OUTk is output. The output signal OUTk turns on the transistor T6 of the inverter INV1, and the power source VSS is connected to the node N1 through the resistor R1. Therefore, the node N1 can be stabilized at the Vss potential.

Since the initialization signal INITB is fixed at the Vss potential, the node N1 is fixed at the Vss potential output from the inverter INV1 regardless of whether the output signal OUTk is the Vdd potential or the Vss potential.

Here, when the output signal SROUT (k−1) becomes a low level, the switch circuit ASW3 is always turned off, so that the polarity signal CMI and the node N1 are disconnected. Therefore, regardless of whether the polarity signal CMI is at a high level or a low level, the node N1 has a Vss potential and the output signal OUTk has a Vdd potential (see FIGS. 13 and 14). Thus, initialization can be performed without causing a short circuit and generating an overcurrent.

As described above, in the latch circuit 33, the initialization signal INITB at the low level (Vss) is supplied to the source terminal of the transistor T5 regardless of whether the output signal SROUT at all stages of the shift register is at the high level or the low level. It is possible to fix the internal potential at a stable potential.

Therefore, the latch circuit 33 can be initialized without increasing the number of elements.

(Modification)
In the latch circuit 33, the initialization signal INITB is supplied to the source terminal of the transistor T5. However, the initialization signal INIT can be supplied to the source terminal of the transistor T6 and similarly initialized.

FIG. 15 is a circuit diagram showing a configuration example of the latch circuit 34. As shown in FIG. 15, the latch circuit 34 (holding circuit) differs from the latch circuit 33 of FIG. 10 in the signals and power supply voltages supplied to the source terminal of the transistor T5 and the source terminal of the transistor T6, respectively. Yes. Specifically, the power supply voltage Vdd is supplied to the source terminal of the transistor T5, and the initialization signal INIT is supplied to the source terminal of the transistor T6. The initialization signal INIT is a signal that becomes low level (Vss) during normal operation and becomes high level (Vdd) during initialization.

Here, when the polarity signal CMI is Vdd (high level), the node N1 has a potential of Vdd-Vth (Vth: threshold). Since the potential of the node N1 is sufficient to turn on the transistor T4 of the inverter INV2, a low level (Vss) output signal OUTk is output by the inverter INV2. The output signal OUTk turns on the transistor T5 of the inverter INV1, and the power supply VDD is connected to the node N1 through the resistor R2. Therefore, the node N1 can be stabilized near Vdd−Vth.

When the polarity signal CMI is Vss (low level), the node N1 is at the Vss potential. As a result, the transistor T3 of the inverter INV2 is turned on, and a high level (Vdd) output signal OUTk is output. The output signal OUTk turns on the transistor T6 of the inverter INV1, and the terminal (INIT terminal) to which the initialization signal INIT is input is connected to the node N1 through the resistor R1. At this time, the initialization signal INIT is fixed to Vdd (high level), but since it is connected to the node N1 via the resistor R1, the node N1 is stable without overcurrent flowing in the vicinity of Vdd-Vth. Can be realized.

Since the initialization signal INIT is fixed at the Vdd potential, the node N1 is fixed at the Vdd potential output from the inverter INV1 regardless of whether the output signal OUTk is the Vdd potential or the Vss potential.

Here, when the output signal SROUT (k−1) becomes a low level, the switch circuit ASW3 is always turned off, so that the polarity signal CMI and the node N1 are disconnected. Therefore, regardless of whether the polarity signal CMI is high level or low level, the node N1 has the Vdd potential and the output signal OUTk has the Vss potential. Thus, initialization can be performed without causing a short circuit and generating an overcurrent.

In this way, in the latch circuit 34, the high level (Vdd) initialization signal INIT is supplied to the source terminal of the transistor T6 regardless of whether the output signal SROUT of all stages of the shift register is high level or low level. It is possible to fix the internal potential at a stable potential.

Therefore, the latch circuit 34 can be initialized without increasing the number of elements.

In the normal operation, the initialization signal INIT is fixed at Vss (low level), so that the initialization signal INIT performs the same function as the power supply voltage Vss. Therefore, the latch circuit 34 can operate in the same manner as a normal latch circuit, and can operate in the same manner as the normal operation of the latch circuit 33 described above.

As described above, the latch circuits of the first to third embodiments described above can be applied to a circuit including a latch circuit, for example, a level shifter or a shift register. The latch circuit according to this embodiment is particularly effective for a common electrode driving circuit and a capacitor wiring driving circuit having a large number of latch circuits, which are display driving circuits mounted on a liquid crystal display device. Therefore, embodiments of the latch circuit mounted on the common electrode driving circuit and the capacitor wiring driving circuit will be described in the following embodiments.

[Embodiment 4]
Embodiment 4 according to the present invention will be described below. In this embodiment, a common electrode driving circuit including a latch circuit mounted on a liquid crystal display device will be described.

FIG. 16 is a block diagram illustrating a schematic configuration of the liquid crystal display device 1 according to the fourth embodiment, and FIG. 17 is an equivalent circuit diagram illustrating an electrical configuration of the pixel P of the liquid crystal display device 1.

First, a schematic configuration of the liquid crystal display device 1 will be described with reference to FIGS. 16 and 17. The liquid crystal display device 1 includes a scanning signal line driving circuit 100 (gate driver), a common electrode driving circuit 200 (COM driver), a data signal line driving circuit 300 (source driver), and a display panel 400. Further, the liquid crystal display device 1 includes a control circuit (not shown) that controls each drive circuit. Each drive circuit may be formed monolithically on the pixel circuit and the active matrix substrate.

The display panel 400 is configured by sandwiching liquid crystal between an active matrix substrate (not shown) and a counter substrate, and has a large number of pixels P (FIG. 17) arranged in a matrix.

The display panel 400 includes a scanning signal line 41 (GLn) (gate line), a common line 42 (common electrode wiring) (CMLn), a data signal line 43 (SLi) (source line), a thin film transistor on an active matrix substrate. (Thin Film Transistor; hereinafter also referred to as “TFT”) 44 and a pixel electrode 45. I and n are integers of 2 or more.

One scanning signal line 41 is formed in each row so as to be parallel to each other in the row direction (lateral direction), and the data signal line 43 is arranged in each column so as to be parallel to each other in the column direction (vertical direction). One by one. As shown in FIG. 17, the TFT 44 and the pixel electrode 45 are formed corresponding to each intersection of the scanning signal line 41 and the data signal line 43, and the gate electrode g of the TFT 44 is connected to the scanning signal line 41. The electrode s is connected to the data signal line 43, and the drain electrode d is connected to the pixel electrode 45. Further, the pixel electrode 45 forms a capacitance Clc (including a liquid crystal capacitance) between the common line 42.

As a result, the gate of the TFT 44 is turned on by the gate signal (scanning signal) supplied to the scanning signal line 41, the source signal (data signal) from the data signal line 43 is written to the pixel electrode 45, and the pixel electrode 45 is written in the above-described manner. It is possible to realize gradation display according to the source signal by setting the potential according to the source signal and applying a voltage according to the source signal to the liquid crystal interposed between the common line 42. it can.

The display panel 400 having the above configuration is driven by the scanning signal line driving circuit 100, the common electrode driving circuit 200, the data signal line driving circuit 300, and a control circuit for controlling them.

In this embodiment, in the active period (effective scanning period) in the vertical scanning period that is periodically repeated, the horizontal scanning period of each row is sequentially assigned, and each row is sequentially scanned.

Therefore, the scanning signal line driving circuit 100 sequentially outputs a gate signal for turning on the TFT 44 to the scanning signal line 41 of the row in synchronization with the horizontal scanning period of each row.

Based on the output signal (SROUT) of the shift register 10 constituting the scanning signal line driving circuit 100, the common electrode driving circuit 200 applies a high level signal (Vcomh) (first potential) or a low level to each common line 42. A signal (Vcoml) (second potential) is supplied.

The data signal line driving circuit 300 outputs a source signal to each data signal line 43. This source signal is a signal obtained by assigning a video signal supplied to the data signal line driving circuit 300 from the outside of the liquid crystal display device 1 through the control circuit to each column in the data signal line driving circuit 300 and performing boosting or the like. is there.

The control circuit controls the scanning signal line driving circuit 100, the common electrode driving circuit 200, and the data signal line driving circuit 300 described above to output a gate signal, a source signal, and a common signal from each of these circuits.

The liquid crystal display device 1 according to the present embodiment has a configuration in which a stable operation is performed while reducing the potential level of the output signal of the common electrode driving circuit 200 while reducing the circuit area. Hereinafter, specific configurations of the scanning signal line driving circuit 100 and the common electrode driving circuit 200 will be described.

The shift register 10 constituting the scanning signal line driving circuit 100 is configured by connecting m (m is an integer of 2 or more) unit circuits 11 in multiple stages. The unit circuit 11 has a clock terminal (CK terminal), a set terminal (S terminal), a reset terminal (R terminal), an initialization terminal (INITB terminal), and an output terminal OUT. Hereinafter, a signal input / output via each terminal is referred to by the same name as the terminal (for example, a signal input via the clock terminal CK is referred to as a clock signal CK).

The shift register 10 is supplied with a start pulse (not shown) and two-phase clock signals CK1 and CK2 from the outside. The start pulse is given to the S terminal of the unit circuit 11 in the first stage. The clock signal CK1 is supplied to the CK terminal of the odd-numbered unit circuit 11, and the clock signal CK2 is supplied to the CK terminal of the even-numbered unit circuit 11. The output of the unit circuit 11 is output from the output terminal OUT to the corresponding scanning signal line GL as the output signal SROUT, and is given to the S terminal of the subsequent unit circuit 11 and the R terminal of the previous unit circuit 11. The output signal SROUT of the unit circuit 11 is input to the unit circuit 21 of the corresponding common electrode driving circuit 200.

The common electrode driving circuit 200 is configured by connecting n (n is an integer of 2 or more) unit circuits 21 in multiple stages. The unit circuit 21 has input terminals INs and INc, an initialization terminal INITB, and an output terminal OUT. The output signal SROUT of the shift register 10 is input to the input terminal INs of the unit circuit 21, and the polarity signal CMIZ (holding target signal) is input to the input terminal INc of the unit circuit 21. An initialization signal INITB is input to the initialization terminal INITB of the unit circuit 21. The output of the unit circuit 21 is output to the common line (COM line) CML as the output signal CMOUT.

Specifically, the output signal SROUT of the unit circuit 11 in the (k−1) -th stage of the shift register 10 is connected to the unit circuit 21 in the k-th stage (k is an integer of 1 to n) of the common electrode driving circuit 200. (K−1) is input, and the unit circuit 21 in the k-th stage outputs the output signal CMOUTk to the common line CMLk. As described above, the common electrode driving circuit 200 sequentially outputs the output signals CMOUT1 to CMOUTn to the common lines CML1 to CMLn according to the shift operation of the shift register 10. Note that the start pulse of the shift register 10 is supplied to the unit circuit 21 in the first stage.

A well-known configuration can be applied to the shift register 10. Therefore, a detailed description of the shift register 10 is omitted, and a detailed configuration of the common electrode driving circuit 200 will be described below.

Example 1
FIG. 18 is a circuit diagram of the unit circuit 21 included in the common electrode driving circuit 200 according to the first embodiment. As shown in FIG. 18, the unit circuit 21 includes a latch-through circuit 21a (holding circuit) and a buffer 21b. The latch through circuit 21a is configured by an inverter INV1 (first inverter), an inverter INV2 (second inverter), and an analog switch circuit SW1, and the buffer 21b is configured by two transistors. In addition, in the inverter INV2, the connection point between the output terminal of the inverter INV1 and the input terminal of the inverter INV2 is a node N1, and the connection point between the input terminal of the inverter INV1 and the output terminal of the inverter INV2 is a node N2 (see FIG. 18). ).

The analog switch circuit SW1 includes an N-channel transistor T1, an N-channel transistor T9, and a capacitor C1, a power supply voltage Vdd is applied to the gate terminal of the transistor T9, a source terminal is connected to the input terminal INs, and a drain terminal Is connected to the gate terminal of the transistor T1. The capacitor C1 is provided between the gate terminal and the drain terminal of the transistor T1. Note that a connection point between the capacitor C1 and the gate terminal of the transistor T1 is a node N3. The source terminal of the transistor T1 is connected to the input terminal INc. The output signal SROUT of the unit circuit 11 of the shift register 10 is supplied to the input terminal INs, and the polarity signal CMIZ is supplied to the input terminal INc.

The inverter INV2 includes a P-channel transistor T3 and an N-channel transistor T4. An input terminal of the inverter INV2 (a connection point (node N1) between the gate terminal of the transistor T3 and the gate terminal of the transistor T4) is an analog switch. The output terminal of the circuit SW1 (the drain terminal of the transistor T1) is connected. The power supply voltage Vdd is applied to the source terminal of the transistor T3, and the drain terminal of the transistor T3 is connected to the output terminal of the inverter INV2 (the connection point (node N2) between the drain terminal of the transistor T3 and the drain terminal of the transistor T4). The power supply voltage Vss is applied to the source terminal of the transistor T4, and the drain terminal of the transistor T4 is connected to the output terminal (node N2) of the inverter INV2. The node N2 is connected to the output terminal out of the latch through circuit 21a and the input terminal of the inverter INV1 (gate terminals of the transistors T5 and T6).

The inverter INV1 includes a P-channel transistor T5, an N-channel transistor T6, and resistors R1 and R2, and is provided with an initialization terminal (INITB terminal). An input terminal of the inverter INV1 (gate terminals of the transistors T5 and T6) is connected to an output terminal (node N2) of the inverter INV2. The initialization signal INITB is input to the source terminal of the transistor T5 via the resistor R2. The drain terminal of the transistor T5 is connected to the output terminal of the inverter INV1 (the connection point between the drain terminal of the transistor T5 and the drain terminal of the transistor T6). The power supply voltage Vss is applied to the source terminal of the transistor T6 via the resistor R1, and the drain terminal of the transistor T6 is connected to the output terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the input terminal (node N1) of the inverter INV2. The output terminal out of the latch through circuit 21a is connected to the input terminal in of the buffer 21b.

The buffer 21b includes a P-channel transistor T7 and an N-channel transistor T8, the gate terminals of the transistors T7 and T8 are connected to the input terminal in, the power supply voltage Vcomh is applied to the source terminal of the transistor T7, and the transistor T7 Is connected to the output terminal OUT of the unit circuit 21, the source terminal of the transistor T8 is supplied with the power supply voltage Vcoml, and the drain terminal of the transistor T8 is connected to the output terminal OUT of the unit circuit 21.

As a result, the output signal SROUT (k−1) of the (k−1) th unit circuit 11 of the shift register 10 is input to the input terminal INs of the kth unit circuit 21, and the kth unit. An output signal CMOUTk is output from the output terminal OUT of the circuit 21 to the common line CMLk of the k-th row.

The common electrode driving circuit 200 including the unit circuit 21 having the above configuration performs an operation of sequentially outputting the output signals CMOUT1 to CMOUTn in which the high level (Vcomh) and the low level (Vcoml) are switched for each frame one by one. Hereinafter, unless otherwise specified, the internal signal of the common electrode driving circuit 200 including the clock signals CK1 and CK2 and the potential of the input / output signal are assumed to be Vdd when the level is high and Vss when the level is low. In the following, the polarity signal CMIZ is also set to Vdd when it is at a high level and Vss when it is at a low level. However, the potential level of the polarity signal CMIZ is not limited to this, and the “high level” only needs to be higher than the inversion potential of the inverter INV2, and the “low level” only needs to be lower than the inversion potential of the inverter INV2.

As shown in FIG. 19, the polarity signal CMIZ is generated by a generation circuit 210 composed of a NAND circuit and an inverter, and is provided outside the common electrode drive circuit 200. The polarity signal CMIZ is input to the unit circuit 21 at each stage.

(About operation)
The operation of the common electrode driving circuit 200 will be described with reference to FIGS. FIG. 20 is a timing chart during operation of the common electrode driving circuit 200, and FIG. 21 is a diagram schematically illustrating a timing chart during operation of the common electrode driving circuit 200. FIG. 20 shows input / output signals in the unit circuit 21 at the (k−1) th stage, the unit circuit 21 at the kth stage, and the unit circuit 21 at the (k + 1) th stage.

CK1 is a clock signal supplied to the CK terminal of the odd-numbered unit circuit 11, and CK2 is a clock signal supplied to the CK terminal of the even-numbered unit circuit 11. The initialization signal INITB is a signal that is at a high level (Vdd) during normal operation and is at a low level (Vss) at initialization (when active). That is, the initialization signal INITB performs the same function as the power supply VDD during normal operation. The polarity signal CMIZ is a signal that inverts every horizontal scanning period (1H) in the same manner as the polarity signal CMI during normal operation, but goes to a low level during initialization.

SR (k−2), SR (k−1), and SRn are the unit circuit 11 in the (k−2) th stage, the unit circuit 11 in the (k−1) th stage, and the kth stage of the shift register 10, respectively. The potentials of the output signals SROUT (k−2), SROUT (k−1) and SROUTk of the unit circuit 11 are shown. N1 and N2 indicate the potentials of the nodes N1 and N2 shown in FIG. 18, respectively. CM (k−1), CMk, and CM (k + 1) are the unit circuit 21 at the (k−1) th stage, the unit circuit 21 at the kth stage, and the unit circuit at the (k + 1) th stage of the common electrode driving circuit 200, respectively. 21 output signals CMOUT (k−1), CMOUTk, CMOUT (k + 1). Note that a period from when the output signal SROUT (k-2) is output to when the next output signal SROUT (k-2) is output corresponds to one vertical scanning period (1 frame: 1 V). Also, FIG. 20 shows arbitrary continuous frames F (t), F (t + 1), and F (t + 2).

First, as normal operations, the operations of the frames F (t) and F (t + 1) in the k-th unit circuit 21 will be described.

First, in frame F (t), the output signal SROUT (k−1) (high level) of the (k−1) th unit circuit 11 of the shift register 10 is applied to the input terminal INs of the kth unit circuit 21. (Active)) is entered. As a result, the transistor T1 is turned on, and the polarity signal CMIZ (low level; Vss) is taken into the latch-through circuit 21a.

Here, immediately before the output signal SROUT (k−1) becomes high level (active), the potential of the node N1 is held at Vdd (high level), and the transistor T5 is turned on. When SROUT (k−1) becomes high level (active), Vss (low level) of the polarity signal CMIZ and the INITB terminal (high level) are short-circuited. In this respect, since the resistor R2 is provided between the INITB terminal (high level) and the node N1, the potential of the node N1 is drawn to the polarity signal CMIZ side and is close to Vss (low level) of the polarity signal CMIZ. It drops to the potential (potential lower than the inversion potential of the inverter INV2) (see FIG. 21).

Thereafter, the transistor T3 is turned on, and the output of the inverter INV2 (node N2; Vdd (high level)) is fed back to the input of the inverter INV1, whereby the transistor T5 is turned off and the transistor T6 is turned on. Become. As a result, the potential of the node N1 drops from a potential close to Vss of the polarity signal CMIZ to Vss (see FIG. 21).

When the potential of the node N1 becomes close to Vss (low level) or Vss (low level), the transistor T3 of the inverter INV2 is turned on and the transistor T4 is turned off. When the transistor T3 is turned on, the potential of the node N2 becomes Vdd (high level), and Vdd (high level) is output from the latch-through circuit 21a. In the buffer 21b to which Vdd (high level) is input, the transistor T7 is turned off and the transistor T8 is turned on, whereby Vcoml is output from the buffer 21b and supplied to the k-th common line CMLk. Is done.

Subsequently, when the output signal SROUT (k−1) of the shift register 10 changes from the high level (active) to the low level (inactive), the transistor T1 is turned off, the input of the polarity signal CMIZ is cut off, and the node N1 Holds the potential (Vss (low level)) held immediately before by the latch operation by the inverters INV1 and INV2, and until the output signal SROUT (k-1) becomes high level (active) in the frame F (t + 1). Vcoml is output from the buffer 21b and continues to be supplied to the k-th common line CMLk.

Next, in frame F (t + 1), when the output signal SROUT (k−1) of the unit circuit 11 at the (k−1) stage of the shift register 10 becomes high level (active), the potential of the node N3 becomes Vdd−Vth. Transistor T9 is turned off. At the node N1, the transistor T1 is turned on by the output signal SROUT (k−1) (high level), and the Vdd (high level) of the polarity signal CMIZ is input, so that Vss (low level) to Vdd (high level). Level). Then, the potential of the node N3 is pushed up to Vdd−Vth + α through the capacitor C1 due to the potential fluctuation of the node N1. As a result, the polarity signal CMIZ (Vdd) is input without dropping the threshold value (Vth), and the potential of the node N1 becomes Vdd (bootstrap operation).

Here, immediately before the output signal SROUT (k−1) becomes high level (active) (frame F (t)), the potential of the node N1 is held at Vss (low level), and the transistor T6 is turned on. Therefore, when the output signal SROUT (k−1) becomes high level (active), the polarity signal CMIZ Vdd (high level) and the power source VSS (low level) are short-circuited. In this respect, since the resistor R1 is provided between the power source VSS and the node N1, the potential of the node N1 is drawn to the polarity signal CMIZ side, and is a potential close to Vdd (high level) of the polarity signal CMIZ (inverter INV2 (Potential higher than the reversal potential of) (see FIG. 21).

Thereafter, the output of the inverter INV2 (node N2; Vss (low level)) is fed back to the input of the inverter INV1, whereby the transistor T5 is turned on and the transistor T6 is turned off. As a result, the potential of the node N1 rises from a potential close to Vdd of the polarity signal CMIZ to Vdd (see FIG. 21).

When the potential of the node N1 becomes close to Vdd (high level) or Vdd (high level), the transistor T4 of the inverter INV2 is turned on and the transistor T3 is turned off. When the transistor T4 is turned on, the potential of the node N2 becomes Vss (low level), and Vss (low level) is output from the latch through circuit 21a. In the buffer 21b to which Vss (low level) is input, the transistor T8 is turned off and the transistor T7 is turned on, whereby Vcomh is output from the buffer 21b and supplied to the k-th common line CMLk. Is done.

Subsequently, when the output signal SROUT (k−1) of the shift register 10 changes from the high level (active) to the low level (inactive), the transistor T1 is turned off, the input of the polarity signal CMIZ is cut off, and the node N1 Holds the potential (Vdd (high level)) held immediately before by the latch operation by the inverters INV1 and INV2, and until the output signal SROUT (k-1) becomes high level (active) in the frame F (t + 2). Vcomh is output from the buffer 21b and is continuously supplied to the k-th common line CMLk. After the frame F (t + 2), the operations of the frames F (t) and F (t + 1) are repeated.

In this way, in the unit circuits 21 other than the k-th stage, the same latch output operation as described above is performed based on the output signals SROUT sequentially output from the unit circuits 11 of the shift register 10.

According to the unit circuit 21 of the first embodiment, since the circuit scale of the common electrode driving circuit 200 can be reduced, the frame of the liquid crystal display device can be further reduced. In addition, there is no problem of operation due to the reduction in circuit scale.

(About initialization operation)
Next, the operation at initialization will be described. When the output signal SROUT of the unit circuits 11 in all stages of the shift register 10 is at the high level at the time of initialization, the operation is as follows (see FIG. 22).

First, when the output signal SROUT becomes high level, the transistor T1 is turned on in the unit circuits 21 in all stages, and the nodes N1 and the polarity signal CMIZ in all stages are connected (short-circuited). In an indefinite state immediately before initialization, the potential held at the node N1 is also indeterminate, so that the output of the inverter INV2 connected to the polarity signal CMIZ is also Vdd (high level) or Vss (low level) at each stage. ) Or indefinite state.

Here, if the initialization signal INITB connected to the node N1 is Vdd, the polarity signal CMIZ connected to the node N1 in all stages is supplied to the power supply VSS and the stage connected to the power supply VDD of the inverter INV1. The connected stages are connected at the same time, and a large current is generated when the power supply VDD and the power supply VSS are short-circuited via the polarity signal CMIZ, and the potential of the node N1 becomes an intermediate potential. It cannot be initialized.

In this regard, in the configuration of the unit circuit 21, since the polarity signal CMIZ and the initialization signal INITB are both controlled to be Vss (low level) at the time of initialization, the node N1 is always Vss (low level). Level) and can be reliably initialized.

On the other hand, when the output signal SROUT of the unit circuits 11 in all stages of the shift register 10 is at the low level at the time of initialization, the operation is as follows (see FIG. 23).

When the node N1 is Vdd (high level) in an undefined state before initialization, the gate terminal of the transistor T5 is Vss (low level), and the transistor T5 is on. Here, since the initialization signal INITB is Vss (low level) at the time of initialization, the potential of the node N1 becomes a low level (Vss + Vth) that has fallen the threshold value (Vth) through the transistor T5. When the output of the inverter INV1 is input to the inverter INV2, the inverter INV2 outputs Vdd. Since the output (node N2) of the inverter INV2 is connected to the input of the inverter INV1, the output (Vdd) of the inverter INV2 is fed back to the inverter INV1, and the transistor T6 is turned on. As a result, the node N1 of Vss + Vth becomes Vss (low level), so that it can be reliably initialized.

When the node N1 is Vss (low level) in an indeterminate state before initialization, the transistor T5 is in an off state, so the signal of the initialization signal INITB is not input to the node N1, but is already desired. Since this is the potential (Vss), it is the same as the initialized state.

Thus, according to the unit circuit 21, the common electrode driving circuit 200 can be initialized stably. That is, in the unit circuit 21, the initialization signal INITB at the low level (Vss) is applied to the transistor regardless of whether the output signal SROUT of the unit circuit 11 of all the stages of the shift register 10 is high level or low level. By applying to the source terminal of T5, the internal potential can be fixed at a stable potential.

In addition, the initialization signal INITB can be supplied by adding a new initialization control circuit and terminal wiring, but is not provided in the inverter INV1 provided in the unit circuit before the initialization function is added. The power supply VDD wiring is used.

Therefore, the unit circuit 21 can be initialized without increasing the number of elements.

In the normal operation, the initialization signal INITB becomes Vdd (high level), and the initialization signal INITB performs the same function as the power supply voltage Vdd. Therefore, the same operation as a normal unit circuit is possible.

Next, another embodiment of the common electrode driving circuit 200 (COM driver) will be described. In the following description, differences from the common electrode driving circuit 200 (unit circuit 21) according to the first embodiment will be mainly described, and the same functions as the components described in the first embodiment are provided. The same reference numerals are given to the constituent elements, and the description thereof is omitted.

(Example 2)
FIG. 24 is a circuit diagram of the unit circuit 22 included in the common electrode driving circuit 200 according to the second embodiment.

The unit circuit 22 has a function for initializing the common electrode drive circuit 200 as in the unit circuit 21 of the first embodiment. Specifically, in the unit circuit 22 of the first embodiment (FIG. 18), the power supply VSS of the inverter INV1 is omitted, an initialization terminal (INIT terminal) is provided, and the unit circuit 22 is for initialization. The terminal (INITB terminal) is omitted, and the power supply VDD of the inverter INV1 is provided. The initialization signal INIT is input to the source terminal of the transistor T6 via the resistor R1.

The initialization signal INIT becomes a low level (Vss) during normal operation and becomes a high level (Vdd) during initialization (active). The polarity signal CMIZ is a signal that inverts the polarity every horizontal scanning period (1H) in the normal operation as in the polarity signal CMI, but becomes high level at the time of initialization. The polarity signal CMIZ is input to the unit circuit 22 at each stage. Further, as shown in FIG. 25, the polarity signal CMIZ is generated by a generation circuit 220 including a NOR circuit and an inverter, and is provided outside the common electrode drive circuit 200.

(About operation)
When the output signal SROUT of the unit circuits 11 in all stages of the shift register 10 is at high level at the time of initialization, the operation is as follows.

In an indefinite state immediately before initialization, both the potential of the node N1 and the output of the inverter INV2 are indefinite, but at the time of initialization, both the polarity signal CMIZ and the initialization signal INIT are set to Vdd (high level). Therefore, the node N1 is always at Vdd (high level) and can be reliably initialized.

On the other hand, when the output signal SROUT of the unit circuits 11 in all stages of the shift register 10 is at the low level at the time of initialization, the operation is as follows.

When the node N1 is Vss (low level) in an undefined state before initialization, the gate terminal of the transistor T6 is Vdd (high level), and the transistor T6 is on. Here, since the initialization signal INIT is Vdd (high level) at the time of initialization, the potential of the node N1 becomes a high level (Vdd−Vth) that has fallen by the threshold (Vth) via the transistor T6. When the output of the inverter INV1 is input to the inverter INV2, the inverter INV2 outputs Vss. Since the output (node N2) of the inverter INV2 is connected to the input of the inverter INV1, the output (Vss) of the inverter INV2 is fed back to the inverter INV1, and the transistor T5 is turned on. As a result, the node N1 of Vdd−Vth becomes Vdd (high level), so that initialization can be surely performed.

When the node N1 is Vdd (high level) in an indeterminate state before initialization, the transistor T6 is in an off state, so that the signal for the initialization signal INIT is not input to the node N1, but is already desired. Since this is the potential (Vdd), it is the same as the initialized state.

Thus, according to the unit circuit 22, the common electrode driving circuit 200 can be initialized stably. That is, in the unit circuit 22, the initialization signal INIT of the high level (Vdd) is applied to the transistor regardless of whether the output signal SROUT of the unit circuits 11 of all the stages of the shift register 10 is high level or low level. By applying the voltage to the source terminal of T6, the internal potential can be fixed at a stable potential. Further, the initialization signal INIT uses the wiring of the power source VSS of the original inverter INV1. Therefore, the unit circuit 22 can be initialized without increasing the number of elements.

In the normal operation, the initialization signal INIT becomes Vss (low level), and the initialization signal INIT performs the same function as the power supply VSS, so that the same operation as a normal unit circuit is possible.

(Example 3)
FIG. 26 is a circuit diagram of the unit circuit 23 included in the common electrode driving circuit 200 according to the third embodiment.

The unit circuit 23 has a function for initializing the common electrode drive circuit 200 as in the unit circuit 21 of the first embodiment. Specifically, in the unit circuit 23, the power supply VDD of the inverter INV2 is omitted in the unit circuit 21 of the first embodiment, an initialization terminal (INITB terminal) is provided, and an initialization terminal (INITB terminal) is provided. ) Is omitted, and the power supply VDD of the inverter INV1 is provided. The initialization signal INITB is input to the source terminal of the transistor T3.

The initialization signal INITB is a signal that is at a high level (Vdd) during normal operation and is at a low level (Vss) at initialization (when active). The polarity signal CMIZ is a signal that inverts the polarity every horizontal scanning period (1H) in the normal operation as in the polarity signal CMI, but becomes high level at the time of initialization. The polarity signal CMIZ is input to the unit circuit 23 in each stage. In addition, the polarity signal CMIZ is generated by a generation circuit 230 including a NOR circuit and an inverter and provided outside the common electrode drive circuit 200, as shown in FIG.

In an indeterminate state immediately before initialization, both the potential of the node N1 and the output of the inverter INV2 (node n2) are indefinite, but at the time of initialization, the polarity signal CMIZ is Vdd (high level) and the initialization signal INITB is Since it is controlled to be Vss (low level), the node N2 becomes Vss (low level), the output (Vss) of the inverter INV2 is fed back to the inverter INV1, and the transistor T5 is turned on. Thereby, since the node N1 becomes Vdd, it can be initialized reliably.

When the node N2 is Vdd (high level) in an undefined state before initialization, the gate terminal of the transistor T3 is Vss (low level), and the transistor T3 is on. Here, since the initialization signal INITB is Vss (low level) at the time of initialization, the potential of the node N2 becomes a low level (Vss + Vth) that is lower than the threshold (Vth) via the transistor T3. Since the output (node N2) of the inverter INV2 is connected to the input of the inverter INV1, the output (Vss + Vth) of the inverter INV2 is fed back to the inverter INV1, and the transistor T5 is turned on. As a result, the node N1 is set to Vdd (high level), the transistor T4 is turned on, and the node N2 of Vss + Vth is set to Vss (low level), so that initialization can be surely performed.

When the node N2 is Vss (low level) in an indefinite state before initialization, the transistor T3 is in an off state, so that the signal for the initialization signal INITB is not input to the node N2, but is already desired. Since this is the potential (Vss), it is the same as the initialized state.

Thus, according to the unit circuit 23, the common electrode driving circuit 200 can be initialized stably. That is, in the unit circuit 23, the initialization signal INITB at the low level (Vss) is applied to the transistor regardless of whether the output signal SROUT of the unit circuits 11 of all the stages of the shift register 10 is high level or low level. By applying the voltage to the source terminal of T3, the internal potential can be fixed at a stable potential. The initialization signal INITB uses the wiring of the power supply VDD of the original inverter INV2. Therefore, the unit circuit 23 can be initialized without increasing the number of elements.

In the normal operation, the initialization signal INITB becomes Vdd (high level), and the initialization signal INITB performs the same function as the power supply VDD, so that the same operation as a normal unit circuit is possible.

(Example 4)
FIG. 28 is a circuit diagram of the unit circuit 24 included in the common electrode driving circuit 200 according to the fourth embodiment.

The unit circuit 24 has a function for initializing the common electrode driving circuit 200 as in the unit circuit 21 of the first embodiment. Specifically, in the unit circuit 24, the power supply VSS of the inverter INV2 is omitted in the unit circuit 21 of the first embodiment, an initialization terminal (INIT terminal) is provided, and an initialization terminal (INITB terminal) is provided. ) Is omitted, and the power supply VDD of the inverter INV1 is provided. The initialization signal INIT is input to the source terminal of the transistor T4.

The initialization signal INIT becomes a low level (Vss) during normal operation and becomes a high level (Vdd) during initialization (active). The polarity signal CMIZ is a signal that inverts every horizontal scanning period (1H) in the same manner as the polarity signal CMI during normal operation, but goes to a low level during initialization. The polarity signal CMIZ is input to the unit circuit 24 at each stage. In addition, the polarity signal CMIZ is generated by a generation circuit 240 including a NOR circuit and an inverter and provided outside the common electrode drive circuit 200, as shown in FIG.

In an indefinite state immediately before initialization, both the potential of the node N1 and the output of the inverter INV2 (node n2) are indefinite, but at the time of initialization, the polarity signal CMIZ is Vss (low level) and the initialization signal INIT is Since it is controlled to be Vdd (high level), the node N2 becomes Vdd (high level), the output (Vdd) of the inverter INV2 is fed back to the inverter INV1, and the transistor T6 is turned on. Thereby, since the node N1 becomes Vss, it can be initialized reliably.

When the node N2 is Vss (low level) in an indefinite state before initialization, the gate terminal of the transistor T4 is Vdd (high level), and the transistor T4 is on. Here, since the initialization signal INIT is Vdd (high level) at the time of initialization, the potential of the node N2 becomes a high level (Vdd−Vth) that has fallen by the threshold (Vth) via the transistor T4. Since the output (node N2) of the inverter INV2 is connected to the input of the inverter INV1, the output (Vdd−Vth) of the inverter INV2 is fed back to the inverter INV1, and the transistor T6 is turned on. As a result, the node N1 is set to Vss (low level), the transistor T3 is turned on, and the node N2 of Vdd−Vth is set to Vdd (high level), so that the initialization can be surely performed.

When the node N2 is Vdd (high level) in an indefinite state before initialization, the transistor T4 is in an off state, so that the signal of the initialization signal INIT is not input to the node N2, but is already desired. Since this is the potential (Vdd), it is the same as the initialized state.

Thus, according to the unit circuit 24, the common electrode driving circuit 200 can be initialized stably. That is, in the unit circuit 24, the initialization signal INIT of the high level (Vdd) is transferred to the transistor regardless of whether the output signal SROUT of the unit circuits 11 of all the stages of the shift register 10 is high level or low level. By applying to the source terminal of T4, the internal potential can be fixed at a stable potential. The initialization signal INIT uses the power supply VSS wiring of the original inverter INV2. Therefore, the unit circuit 24 can be initialized without increasing the number of elements.

(Modification)
The latch-through circuit 21a of each unit circuit constituting the common electrode driving circuit 200 according to the fourth embodiment includes the latch circuits (latch

circuits

15, 19, 31 to 34) described in the first to third embodiments. The same circuit configuration can be applied.

(Switching scanning direction)
The liquid crystal display device 1 may include a switching circuit UDSW that switches the scanning direction (shift direction) of the shift register 10. FIG. 30 is a block diagram showing a liquid crystal display device 2 which is a modification of the liquid crystal display device 1. As shown in FIG. 30, the liquid crystal display device 2 includes a switching circuit UDSW provided corresponding to each stage of the shift register 10 in addition to the configuration of the liquid crystal display device 1 of FIG.

The switching signals UD and UDB, which are signals whose polarities are reversed, are supplied to the switching circuit UDSW. For example, when the switching signal UD is at a high level (the switching signal UDB is at a low level), the switching circuit UDSW switches the output signal SROUT (k−1) of the unit circuit 11 at the (k−1) -th stage. When the circuit UDSW is input to the k-th unit circuit 21 and the switching signal UDB is at a high level (the switching signal UD is at a low level), the output signal SROUT (k + 1) of the (k + 1) -th unit circuit 11 is The signal output is switched so as to be input to the k-th unit circuit 21 from the switching circuit UDSW.

Thereby, the scanning direction of the shift register 10 can be switched (a first direction from the first stage to the n-th stage and a second direction from the n-th stage to the first stage are mutually switched). Note that the switching circuit UDSW can be applied to the above-described embodiments.

[Embodiment 5]
The following describes Embodiment 5 of the present invention with reference to the drawings. In this embodiment, a storage capacitor wiring driving circuit (CS driver) including a latch circuit mounted on a liquid crystal display device will be described.

FIG. 31 is a block diagram showing a schematic configuration of the liquid crystal display device 3 according to the fifth embodiment. The liquid crystal display device 3 includes a scanning signal line drive circuit 100, a storage capacitor line drive circuit 500 (CS driver), a data signal line drive circuit 300, and a display panel 400. Each drive circuit may be formed monolithically on the pixel circuit and the active matrix substrate.

The display panel 400 is driven by the scanning signal line driving circuit 100, the storage capacitor line driving circuit 500, the data signal line driving circuit 300, and a control circuit for controlling them.

Based on the output signal (SROUT) of the shift register 10 constituting the scanning signal line drive circuit 100, the storage capacitor line drive circuit 500 applies a high level signal (Vcsh) (modulation signal) to each storage capacitor line 46 (CS line). ) Or a low level signal (Vcsl) (modulation signal).

The control circuit controls the scanning signal line drive circuit 100, the storage capacitor line drive circuit 500, and the data signal line drive circuit 300 to output a gate signal, a source signal, and a CS signal from each of these circuits.

The liquid crystal display device 3 according to the present embodiment has a configuration in which the circuit area is reduced and a stable operation is performed by preventing a decrease in the potential level of the output signal of the storage capacitor wiring drive circuit 500. Hereinafter, specific configurations of the scanning signal line driving circuit 100 and the storage capacitor wiring driving circuit 500 will be described.

The shift register 10 is supplied with a start pulse (not shown) and two-phase clock signals CK1 and CK2 from the outside. The start pulse is given to the S terminal of the unit circuit 11 in the first stage. The clock signal CK1 is supplied to the CK terminal of the odd-numbered unit circuit 11, and the clock signal CK2 is supplied to the CK terminal of the even-numbered unit circuit 11. The output of the unit circuit 11 is supplied from the output terminal OUT to the corresponding scanning signal line GL as the output signal SROUT, and is also supplied to the S terminal of the subsequent unit circuit 11 and the R terminal of the previous unit circuit 11. Further, the output signal SROUT of the unit circuit 11 is supplied to the unit circuit 51 of the corresponding storage capacitor line driving circuit 500.

Specifically, as shown in FIG. 31, the (k−1) -th unit circuit 11 is connected to the S terminal of the k-th unit circuit 11 of the shift register 10 (k is an integer of 1 to n). The output signal SROUT (k−1) is input, and the k-th unit circuit 11 outputs the output signal SROUTk to the scanning signal line GLk. As described above, the shift register 10 sequentially outputs the output signals SROUT1 to SROUTn to the scanning signal lines GL1 to GLn by the shift operation.

The storage capacitor wiring drive circuit 500 is configured by connecting n (n is an integer of 2 or more) unit circuits 51 in multiple stages. The unit circuit 51 has input terminals INs1, INs2, and INc, an initialization terminal (INITB terminal), and an output terminal OUT. The output signal SROUT of the shift register 10 is input to the input terminals INs1 and INs2 of the unit circuit 51, the polarity signal CMIZ is input to the input terminal INc, and the initialization terminal (INITB terminal) is used for initialization. A signal (INITB) is input. The output of the unit circuit 51 is supplied as an output signal CSOUT to a storage capacitor line (CS line) CSL.

Specifically, as shown in FIG. 31, the k-th unit circuit 51 (k is an integer not smaller than 1 and not larger than n) of the storage capacitor line driving circuit 500 has the k-th stage of the shift register 10 connected to the input terminal INs1. Output SROUTk is input, and the (k + 1) -th output SROUT (k + 1) of the shift register 10 is input to the input terminal INs2. The k-th unit circuit 51 receives the output signal CSOUTk as a storage capacitor line CSLk. Output to. In this manner, the storage capacitor line driving circuit 500 sequentially outputs the output signals CSOUT1 to CSOUTn to the storage capacitor lines CSL1 to CSLn according to the shift operation of the shift register 10.

A well-known configuration can be applied to the shift register 10. Therefore, a detailed description of the shift register 10 is omitted, and a detailed configuration of the storage capacitor line driving circuit 500 will be described below.

Example 1
FIG. 32 is a circuit diagram of the unit circuit 51 included in the storage capacitor line driving circuit 500 according to the first embodiment. The unit circuit 51 includes a latch-through circuit 51a (holding circuit) and a buffer 51b. The latch-through circuit 51a is configured by an inverter INV1, an inverter INV2, and an analog switch circuit SW1a, and the buffer 51b is configured by two transistors. The inverter INV1 is provided with a resistor R1 and a resistor R2. In addition, in the inverter INV2, the connection point between the output terminal of the inverter INV1 and the input terminal of the inverter INV2 is a node N1, and the connection point between the input terminal of the inverter INV1 and the output terminal of the inverter INV2 is a node N2 (see FIG. 32). ).

The analog switch circuit SW1a includes an N-channel transistor T1, a channel transistor T2, N-channel transistors T91 and T92, and capacitors C1 and C2. The power supply voltage Vdd is applied to the gate terminal of the transistor T91, the source terminal is connected to the input terminal INs1, and the drain terminal is connected to the gate terminal of the transistor T1. The capacitor C1 is provided between the gate terminal and the drain terminal of the transistor T1. Note that a connection point between the capacitor C1 and the gate terminal of the transistor T1 is a node N3. The power supply voltage Vdd is applied to the gate terminal of the transistor T92, the source terminal is connected to the input terminal INs2, and the drain terminal is connected to the gate terminal of the transistor T2. The capacitor C2 is provided between the gate terminal and the drain terminal of the transistor T2. Note that a connection point between the capacitor C2 and the gate terminal of the transistor T2 is a node N4. The input terminal INs1 is supplied with the output SROUTk of the shift register 10 at its own stage (kth stage), and the input terminal INs2 is supplied with the output SROUT (k + 1) of the next stage ((k + 1) th stage) of the shift register 10. Supplied. The source terminals of the transistors T1 and T2 are connected to the input terminal INc, and the polarity signal CMIZ is supplied to the input terminal INc.

The inverter INV2 includes a P-channel transistor T3 and an N-channel transistor T4. An input terminal of the inverter INV2 (a connection point (node N1) between the gate terminal of the transistor T3 and the gate terminal of the transistor T4) is an analog switch. The circuit SW1a is connected to the output terminal (the drain terminals of the transistors T1 and T2). The power supply voltage Vdd is applied to the source terminal of the transistor T3, and the drain terminal of the transistor T3 is connected to the output terminal of the inverter INV2 (the connection point (node N2) between the drain terminal of the transistor T3 and the drain terminal of the transistor T4). The power supply voltage Vss is applied to the source terminal of the transistor T4, and the drain terminal of the transistor T4 is connected to the output terminal (node N2) of the inverter INV2. The node N2 is connected to the output terminal out of the latch through circuit 51a and the input terminal of the inverter INV1 (gate terminals of the transistors T5 and T6).

The inverter INV1 includes a P-channel transistor T5, an N-channel transistor T6, and resistors R1 and R2, and is provided with an initialization terminal (INITB terminal). An input terminal of the inverter INV1 (gate terminals of the transistors T5 and T6) is connected to an output terminal (node N2) of the inverter INV2. The initialization signal INITB is input to the source terminal of the transistor T5 via the resistor R2. The drain terminal of the transistor T5 is connected to the output terminal of the inverter INV1 (the connection point between the drain terminal of the transistor T5 and the drain terminal of the transistor T6). The power supply voltage Vss is applied to the source terminal of the transistor T6 via the resistor R1, and the drain terminal of the transistor T6 is connected to the output terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the input terminal (node N1) of the inverter INV2. The output terminal out of the latch through circuit 51a is connected to the input terminal in of the buffer 51b.

The buffer 51b includes a P-channel transistor T7 and an N-channel transistor T8, the gate terminals of the transistors T7 and T8 are connected to the input terminal in, the power supply voltage Vcsh is applied to the source terminal of the transistor T7, and the transistor T7 Is connected to the output terminal OUT of the unit circuit 51, the source terminal of the transistor T8 is supplied with the power supply voltage Vcsl, and the drain terminal of the transistor T8 is connected to the output terminal OUT of the unit circuit 51.

As a result, the output signal SROUT (k + 1) of the (k + 1) th unit circuit 11 of the shift register 10 is input to the input terminal INs2 of the kth unit circuit 51, and the input of the kth unit circuit 51 is input. The output signal SROUTk of the kth unit circuit 11 of the shift register 10 is input to the terminal INs1, and the output signal CSOUTk is output from the output terminal OUT of the kth unit circuit 51 to the kth storage capacitor line CSLk. Is output.

The storage capacitor line driving circuit 500 including the unit circuit 51 having the above configuration performs an operation of sequentially outputting the output signals CSOUT1 to CSOUTn in which the high level (Vcsh) and the low level (Vcsl) are switched for each frame one by one. Hereinafter, the potentials of the internal signals of the storage capacitor line driving circuit 500 including the clock signals CK1 and CK2 and the input / output signals are assumed to be Vdd when the level is high and Vss when the level is low unless otherwise specified. The initialization signal INITB is a signal that is at a high level (Vdd) during normal operation and is at a low level (Vss) during initialization. In the following, the polarity signal CMIZ is also set to Vdd when it is at a high level and Vss when it is at a low level. However, the potential level of the polarity signal CMIZ is not limited to this, and the “high level” only needs to be higher than the inversion potential of the inverter INV2, and the “low level” only needs to be lower than the inversion potential of the inverter INV2.

(About operation)
Next, the operation of the storage capacitor line driving circuit 500 will be described with reference to FIGS. FIG. 33 is a timing chart during operation of the storage capacitor line driving circuit 500, and FIG. 34 is a diagram schematically showing a timing chart during operation of the storage capacitor line driving circuit 500. In FIG. 33, the input / output signals in the (k−1) -th unit circuit 51, the k-th unit circuit 51, the (k + 1) -th unit circuit 51, and the potential of the pixel P corresponding to each stage are shown. Show.

CK1 is a clock signal supplied to the CK terminal of the odd-numbered unit circuit 51, and CK2 is a clock signal supplied to the CK terminal of the even-numbered unit circuit 51. CMIZ is a signal (polarity signal) whose polarity is inverted every horizontal scanning period (1H) in the normal operation as in the case of CMI, but at the time of initialization. SR (k−1), SRk, SR (k + 1), SR (k + 2) are the (k−1) -th unit circuit 11, the k-th unit circuit 11, and the (k + 1) -th stage of the shift register 10, respectively. The potentials of the output signals SROUT (k−1), SROUTk, SROUT (k + 1), SROUT (k + 2) of the unit circuit 11 of the eye and the unit circuit 11 of the (k + 2) stage are shown. N1 and N2 indicate the potentials of the nodes N1 and N2 shown in FIG. 32, respectively. CS (k−1), CSk, and CS (k + 1) are the unit circuit 51 in the (k−1) stage, the unit circuit 51 in the k stage, and the unit in the (k + 1) stage, respectively, of the storage capacitor wiring driving circuit 500. The potentials of the output signals CSOUT (k−1), CSOUTk, CSOUT (k + 1) of the circuit 51 are shown. S indicates a data signal, which has the same polarity for all pixels in the same row, and has a waveform in which the polarity is reversed every row (one horizontal scanning period) (1 line (1H) inversion drive). Note that a period from when the output signal SROUTk is output to when the next output signal SROUTk is output corresponds to one vertical scanning period (1 frame: 1 V). In FIG. 33, arbitrary continuous frames F (t), F (t + 1), and F (t + 2) are shown. Although not shown in FIG. 33, the initialization signal INITB is at a high level (Vdd) during normal operation.

Here, the operations of the frames F (t) and F (t + 1) in the k-th pixel Pk (one pixel of the pixel group connected to the scanning signal line GLk) and the unit circuit 51 will be described.

First, in frame F (t), when the output signal SROUTk of the k-th unit circuit 11 of the shift register 10 becomes high level (active), the scanning signal line GLk becomes active, and the data signal S ( Negative polarity) is written.

Here, if the frame F (t) is a frame after the second frame, the potential of the node N1 is held at Vdd (high level) immediately before the output signal SROUTk becomes high level (active). Even if the output signal SROUTk becomes high level (active), the potential of the node N1 continues to hold Vdd (high level). Therefore, Vcsh is output from the buffer 51b and supplied to the kth storage capacitor line CSLk.

Thereafter, when the output signal SROUTk of the shift register 10 changes from the high level (active) to the low level (inactive), the transistor T1 is turned off, the input of the polarity signal CMIZ is cut off, and the node N1 is connected to the inverters INV1, INV2. The potential (Vdd (high level)) held immediately before is held by the latch operation.

Subsequently, when the output signal SROUT (k + 1) of the (k + 1) -th unit circuit 11 of the shift register 10 becomes high level (active), the output signal SROUT (k + 1) is input to the input terminal INs2 of the k-th unit circuit 51. (High level) is input, and the polarity signal CMIZ (low level; Vss) is taken into the latch-through circuit 51a.

Here, immediately before the output signal SROUT (k + 1) becomes high level (active), the potential of the node N1 is held at Vdd (high level), and the transistor T5 is in an on state, so that the output signal SROUT ( When k + 1) becomes high level (active), Vss (low level) of the polarity signal CMIZ and the INITB terminal (high level) are short-circuited. In this respect, since the resistor R2 is provided between the INITB terminal and the node N1, the potential of the node N1 is drawn to the polarity signal CMIZ side, and the potential (inverter INV2) is close to Vss (low level) of the polarity signal CMIZ. (The potential is lower than the inversion potential) (see FIG. 34).

Thereafter, the transistor T3 is turned on, and the output of the inverter INV2 (node N2; Vdd (high level)) is fed back to the input of the inverter INV1, whereby the transistor T5 is turned off and the transistor T6 is turned on. Become. As a result, the potential of the node N1 drops from a potential close to Vss of the polarity signal CMIZ to Vss (see FIG. 34).

When the potential of the node N1 becomes close to Vss (low level) or Vss (low level), the transistor T3 of the inverter INV2 is turned on and the transistor T4 is turned off. When the transistor T3 is turned on, the potential of the node N2 becomes Vdd (high level), and Vdd (high level) is output from the latch through circuit 51a.

In the buffer 51b to which Vdd (high level) is input, the transistor T7 is turned off and the transistor T8 is turned on, whereby Vcsl is output from the buffer 51b and is supplied to the kth storage capacitor line CSLk. Supplied. Here, immediately before the output signal SROUT (k + 1) becomes high level (active), since the potential of the node N1 is held at Vdd (high level), the potential of the storage capacitor wiring CSLk in the k-th row is Vcsh. is there. Therefore, the potential of the pixel Pk in the floating state is pushed down by changing the potential of the storage capacitor line CSLk in the k-th row from Vcsh to Vcsl (potential shift).

Subsequently, when the output signal SROUT (k + 1) of the shift register 10 changes from the high level (active) to the low level (inactive), the analog switch circuit SW1a is turned off, the input of the polarity signal CMIZ is cut off, and the node N1 Holds the potential (Vss (low level)) held immediately before by the latch operation by the inverters INV1 and INV2. Thus, until the output signal SROUT (k + 1) becomes high level (active) in the next frame F (t + 1), Vcsl is output from the buffer 51b and is continuously supplied to the kth storage capacitor line CSLk. The potential of Pk is maintained as the potential after being pushed down (shifted).

Next, in frame F (t + 1), when the output signal SROUTk of the k-th unit circuit 11 of the shift register 10 becomes high level (active), the scanning signal line GLk becomes active, and the data signal S (plus) is applied to the pixel Pk. Polarity) is written.

Here, immediately before the output signal SROUTk becomes high level (active), the potential of the node N1 is held at Vss (low level). Therefore, even if the output signal SROUT (k + 1) becomes high level (active), The potential of the node N1 continues to hold Vss (low level). Accordingly, Vcsl is output from the buffer 51b and supplied to the kth storage capacitor line CSLk.

Thereafter, when the output signal SROUTk of the shift register 10 changes from the high level (active) to the low level (inactive), the transistor T1 is turned off, the input of the polarity signal CMIZ is cut off, and the node N1 is connected to the inverters INV1, INV2. The potential (Vss (low level)) held immediately before is held by the latch operation.

Subsequently, when the output signal SROUT (k + 1) of the unit circuit 11 in the (k + 1) stage of the shift register 10 becomes high level (active), the potential of the node N4 is charged to Vdd−Vth, and then the transistor T92 is turned off. It becomes a state. At the node N1, the transistor T2 is turned on by the output signal SROUT (k + 1) (high level), and the Vdd (high level) of the polarity signal CMIZ is input, so that Vss (low level) to Vdd (high level). Begin to rise. Then, the potential of the node N4 is pushed up to Vdd−Vth + α through the capacitor C2 due to the potential fluctuation of the node N1. As a result, the polarity signal CMIZ (Vdd) is input without dropping the threshold value (Vth), and the potential of the node N1 becomes Vdd (bootstrap operation).

Here, immediately before the output signal SROUT (k + 1) becomes high level (active) (frame F (t)), the potential of the node N1 is held at Vss (low level), and the transistor T6 is turned on. Therefore, when the output signal SROUT (k + 1) becomes high level (active), the polarity signal CMIZ Vdd (high level) and the power source VSS (low level) are short-circuited. In this respect, since the resistor R1 is provided between the power supply VSS and the node N1, the potential of the node N1 is drawn to the polarity signal CMIZ side, and the potential (inverter INV2) is close to Vdd (high level) of the polarity signal CMIZ. (Potential lower than the inversion potential) (see FIG. 34).

Thereafter, the output of the inverter INV2 (node N2; Vss (low level)) is fed back to the input of the inverter INV1, whereby the transistor T5 is turned on and the transistor T6 is turned off. As a result, the potential of the node N1 rises from a potential close to Vdd of the polarity signal CMIZ to Vdd (see FIG. 34).

When the potential of the node N1 becomes close to Vdd (high level) or Vdd (high level), the transistor T4 of the inverter INV2 is turned on and the transistor T3 is turned off. When the transistor T4 is turned on, the potential of the node N2 becomes Vss (low level), and Vss (low level) is output from the latch through circuit 51a.

In the buffer 51b to which Vss (low level) is input, the transistor T8 is turned off and the transistor T7 is turned on, whereby Vcsh is output from the buffer 51b and is supplied to the kth storage capacitor line CSLk. Supplied. Here, immediately before the output signal SROUT (k + 1) becomes high level (active) (frame F (t)), the potential of the node N1 is held at Vss (low level). The potential of the wiring CSLk is Vcsl. Therefore, the potential of the pixel Pk in the floating state is pushed up (potential shift) when the potential of the storage capacitor wiring CSLk in the k-th row changes from Vcsl to Vcsh.

Subsequently, when the output signal SROUT (k + 1) of the shift register 10 changes from the high level (active) to the low level (inactive), the analog switch circuit SW1a is turned off, the input of the polarity signal CMIZ is cut off, and the node N1 Holds the potential (Vdd (high level)) held immediately before by the latch operation by the inverters INV1 and INV2. As a result, Vcsh is output from the buffer 51b and is continuously supplied to the kth storage capacitor line CSLk until the output signal SROUT (k + 1) becomes high level (active) in the next frame F (t + 2). The potential after Pk is held as the potential of Pk. After the frame F (t + 2), the operations of the frames F (t) and F (t + 1) are repeated.

In this way, the pixel P and the unit circuit 51 other than the k-th stage perform the same latch output operation as described above based on the output signal SROUT sequentially output from each unit circuit 11 of the shift register 10.

According to the unit circuit 51 of the first embodiment, since the circuit scale of the storage capacitor line driving circuit 500 can be reduced, the frame of the liquid crystal display device can be further reduced. In addition, there is no problem of operation due to the reduction in circuit scale.

(About the first frame)
By the way, in the initial state when the power is turned on, the potentials (CS signals) of all the storage capacitor wirings CSL are set to the low level. Therefore, in the first frame, the potentials of the CS signals in the even rows (or odd rows). There is a known problem that the shift is not properly performed and a horizontal stripe occurs in the display image. In other words, in the unit circuit of the row that generates the low-level CS signal in the first frame, the potential of the CS signal does not fluctuate, so that the potential of the pixel P in which the negative polarity data signal is written cannot be shifted. On the other hand, in the pixels P in the previous and subsequent rows, the CS signal shifts from the low level to the high level, so that the pixel potential rises appropriately. As a result, lateral stripes are generated.

In this respect, according to the unit circuit 51 having the above-described configuration, an appropriate CS signal can be generated by taking in the output signal SROUTk of its own stage (k stage), so that the potential is appropriately shifted in all pixels. It is possible to prevent the display quality of the first frame from deteriorating.

As an example, the operation of the first frame of the k-th unit circuit 51 when a negative polarity data signal is written to the k-th pixel Pk in the first frame will be described. 35 and 36 are timing charts at the time of operation including initialization of the storage capacitor wiring driving circuit 500. FIG. FIG. 35 and FIG. 36 show the first frame (frame F1) and the second frame (frame F2) following F1 in which the normal operation after power-on is started after the power is turned on. 35 shows a case where the output signal SROUT of all the unit circuits 11 of the shift register 10 is at a high level at the time of initialization, and FIG. 36 shows the unit circuits 11 of all the stages of the shift register 10 at the time of initialization. The output signal SROUT of FIG. The initialization operation immediately after the power is turned on will be described later.

In the frame F1, when the output signal SROUTk of the k-th unit circuit 11 of the shift register 10 becomes high level (active), the scanning signal line GLk becomes active, and the data signal S (negative polarity) is written to the pixel Pk. . At the same time, the output signal SROUTk (high level) is input to the input terminal INs1 of the k-th unit circuit 51, and the polarity signal CMIZ (high level; Vdd) is taken into the latch-through circuit 51a by the bootstrap operation described above. Subsequent operations of the unit circuit 51 are the same as those in FIG. 33, whereby Vcsh is output from the unit circuit 51 and supplied to the storage capacitor line CSLk in the k-th row.

Subsequently, when the output signal SROUT (k + 1) of the (k + 1) -th unit circuit 11 of the shift register 10 becomes high level (active), the output signal SROUT (k + 1) is input to the input terminal INs2 of the k-th unit circuit 51. (High level) is input, and the polarity signal CMIZ (low level; Vss) is taken into the latch-through circuit 51a. As a result, Vcsl is output from the unit circuit 51 and supplied to the storage capacitor line CSLk in the k-th row. Here, the potential of the pixel Pk in the floating state is pushed down by changing the potential of the storage capacitor line CSLk in the k-th row from Vcsh to Vcsl (potential shift).

In this manner, the unit circuit 51 can appropriately shift the potential of the pixel P to which the negative polarity data signal is written in the first frame, and can prevent the display quality of the first frame from being deteriorated.

(About initialization operation)
Next, the initialization operation immediately after the power is turned on will be described. When the output signal SROUT of the unit circuits 11 in all stages of the shift register 10 is at the high level at the time of initialization, the operation is as follows (see FIG. 35).

First, when the output signal SROUT becomes high level, the transistors T1 and T2 are turned on in the unit circuits 51 in all stages, and the nodes N1 and polarity signals CMIZ in all stages are connected (short circuited). In an indefinite state immediately before initialization, the potential held at the node N1 is also indefinite, so that the output of the inverter INV2 connected to the polarity signal CMIZ is also Vdd (high level) or Vss (low level) at each stage. Level) or indeterminate.

Here, if the initialization signal INITB connected to the node N1 is Vdd, the polarity signal CMIZ connected to the node N1 in all stages is supplied to the power supply VSS and the stage connected to the power supply VDD of the inverter INV1. The connected stages are connected simultaneously, and a large current is generated when the power supply VDD and the power supply VSS are short-circuited via the polarity signal CMIZ, and the potential of the node N1 becomes an intermediate potential. It cannot be initialized.

In this regard, in the configuration of the unit circuit 51, since the polarity signal CMIZ and the initialization signal INITB are both controlled to be Vss (low level) at the time of initialization, the node N1 is always Vss (low level). Level) and can be reliably initialized.

On the other hand, when the output signal SROUT of the unit circuits 11 in all stages of the shift register 10 is at the low level at the time of initialization, the operation is as follows (see FIG. 36).

Thus, according to the unit circuit 51, the storage capacitor wiring drive circuit 500 can be initialized stably. That is, in the unit circuit 51, the initialization signal INITB at the low level (Vss) is applied to the transistor regardless of whether the output signal SROUT of the unit circuits 11 of all the stages of the shift register 10 is high level or low level. By applying to the source terminal of T5, the internal potential can be fixed at a stable potential.

Therefore, the unit circuit 51 can be initialized without increasing the number of elements.

(Modification)
The circuit configuration of the unit circuit 51 constituting the storage capacitor line driving circuit 500 according to the fifth embodiment is the same as the common electrode driving circuit 200 shown in the fourth embodiment except for the power supplies VCSH and VCSL of the buffer 51b. The unit circuit 21 is the same. That is, the unit circuit constituting the storage capacitor line driving circuit 500 can have the same circuit configuration as each unit circuit (unit circuits 21 to 24) constituting the common electrode driving circuit 200 shown in the fourth embodiment. . The operation of each unit circuit of the storage capacitor line driving circuit 500 is the same as that of each unit circuit of the common electrode driving circuit 200.

Here, in each of the unit circuits 21 to 24 of the common electrode driving circuit 200, the output SROUT (k−1) of the unit circuit of the preceding stage ((k−1) stage) of the shift register 10 is added to its own stage (for example, k stage). However, the present invention is not limited to this, and the stage before (k-1) stage (for example, (k-2) stage or (k-3) The output (SROUT (k−2) or SROUT (k−3)) of the unit circuit of the stage may be input. On the other hand, in each unit circuit of the storage capacitor line driving circuit 500, the output SROUT (k + 1) of the unit circuit of the next stage ((k + 1) stage) of the shift register 10 is input to the own stage (for example, k stage) ( However, the present invention is not limited to this, and the output (SROUT (k + 2)) of the unit circuit at the subsequent stage (for example, (k + 2) stage or (k + 3) stage) after the (k + 1) stage, Alternatively, SROUT (k + 3)) may be input.

In the holding circuit according to the embodiment of the present invention, when the initialization signal is input to the source terminal of the first transistor, the initialization signal is fixed at a low level at the time of initialization, and at the time of initialization. Other than the above, it is desirable to be fixed at a high level.

In the holding circuit according to the embodiment of the present invention, when the initialization signal is input to the source terminal of the second transistor, the initialization signal is fixed at a high level at the time of initialization, and at the time of initialization. It is desirable that the level is fixed at a low level except for.

The holding circuit according to the embodiment of the present invention includes a first inverter as the inverter, and the holding target signal is input to the first inverter when the control signal becomes active, and the output signal is the first inverter. The output is based on the output of the inverter, and when the control signal is inactive, the input terminal and the output terminal of the first inverter are electrically connected to each other so as to have an inverted potential. You can also.

The holding circuit according to the embodiment of the present invention includes a first inverter and a second inverter as the inverter, and the holding target signal is input to the second inverter when the control signal becomes active, and the output signal is And when the control signal is inactive, the input terminal of the first inverter and the output terminal of the second inverter are electrically connected to each other when the control signal is inactive. When the output terminal of the first inverter and the input terminal of the second inverter are electrically connected to each other and the control signal is active, the output terminal of the first inverter and the input terminal of the second inverter are It can also be set as the structure interrupted | blocked electrically.

The holding circuit according to the embodiment of the present invention includes a first inverter and a second inverter as the inverter, and the holding target signal is input to the second inverter when the control signal becomes active, and the output signal is And when the control signal is active, the input terminal of the first inverter and the output terminal of the second inverter are electrically connected to each other, and The output terminal of the first inverter and the input terminal of the second inverter may be electrically connected to each other.

In the holding circuit according to the embodiment of the present invention, a first resistor is connected in series to a source terminal of the first transistor of the first inverter, and a source terminal of the second transistor of the first inverter is connected to the source terminal of the first transistor. The second resistor may be connected in series.

The display driver circuit according to the embodiment of the present invention is used in a display device that supplies a signal of a first potential or a second potential to a common electrode wiring that forms a capacitor with a pixel electrode. When the output signal of the previous stage of the shift register is input and the output signal of the previous stage of the shift register becomes active, the holding circuit of the own stage takes in the holding target signal and holds the holding target signal. The output signal that becomes the first potential or the second potential according to the above may be supplied to the common electrode wiring that forms a capacitor with the pixel electrode of the pixel in its own stage.

The display driving circuit according to the embodiment of the present invention is used in a display device that supplies a modulation signal corresponding to the polarity of a signal potential written to a pixel electrode to a storage capacitor wiring that forms a capacitor with the pixel electrode. When the output signal at the subsequent stage of the shift register is input to the holding circuit at the own stage, and the output signal at the subsequent stage of the shift register becomes active, the holding circuit at the own stage captures and holds the hold target signal. However, an output signal corresponding to the holding target signal may be supplied as the modulation signal to the holding capacitor wiring that forms a capacitor with the pixel electrode of the pixel of the own stage.

The display panel according to the embodiment of the present invention is characterized in that the display driving circuit and the pixel circuit described above are formed monolithically.

A display device according to an embodiment of the present invention includes the display drive circuit described above.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

The present invention is suitable for a latch circuit and each drive circuit of a display device.

1-3 Liquid crystal display device (display device)
DESCRIPTION OF SYMBOLS 10 Shift register 11 Shift

register unit circuits

15 and 19 Latch circuit (holding circuit)
18 Inverter (first inverter)
21 to 24 Unit circuit 21a of common electrode driving circuit Latch-through circuit (holding circuit)
21b Buffers 31 to 34 Latch circuit (holding circuit)
41 Scanning signal line (gate line)
42 Common electrode wiring (common line)
43 Data signal line (source line)
44 TFT
45 Pixel electrode 46 Storage capacitor wiring (CS line)
51 Unit Circuit 51a of Retention Capacity Wiring Drive Circuit Latch Through Circuit (Retention Circuit)
51b Buffer 100 Scanning signal line drive circuit (gate driver)
200 Common electrode drive circuit (COM driver)
300 Data signal line drive circuit (source driver)
400 Display panel 500 Retention capacity wiring drive circuit (CS driver)
TP1 transistor (first transistor)
TN1 transistor (second transistor)
T3 transistor (first transistor)
T4 transistor (second transistor)
T5 transistor (first transistor)
T6 transistor (second transistor)
INV1 inverter (first inverter)
INV2 inverter (second inverter)
R1 resistance (second resistance)
R2 resistance (first resistance)

Claims

A holding circuit that captures a holding target signal when the control signal becomes active, and outputs an output signal corresponding to the holding target signal while holding the holding target signal until the control signal becomes active next,
Comprising at least one inverter for holding the hold target signal;
The inverter includes a CMOS circuit in which gate terminals and drain terminals of a P-channel first transistor and an N-channel second transistor are connected to each other.
A holding circuit, wherein an initialization signal having a high level or a low level is input to a source terminal of the first transistor or a source terminal of the second transistor at the time of initialization.
When the initialization signal is input to the source terminal of the first transistor, the initialization signal is fixed at a low level during initialization, and is fixed at a high level except during initialization. The holding circuit according to claim 1.
When the initialization signal is input to the source terminal of the second transistor, the initialization signal is fixed at a high level during initialization, and is fixed at a low level except during initialization. The holding circuit according to claim 1.
A first inverter as the inverter;
The holding target signal is input to the first inverter when the control signal becomes active,
The output signal is output based on the output of the first inverter,
The input terminal and the output terminal of the first inverter are electrically connected to each other so as to have an inverted potential when the control signal is inactive. The holding circuit according to Item 1.
The inverter includes a first inverter and a second inverter,
The holding target signal is input to the second inverter when the control signal becomes active,
The output signal is output based on the output of the second inverter,
When the control signal is inactive, the input terminal of the first inverter and the output terminal of the second inverter are electrically connected to each other, and the output terminal of the first inverter and the second inverter The input terminals are electrically connected to each other,
4. The output terminal of the first inverter and the input terminal of the second inverter are electrically cut off when the control signal is active. Holding circuit.
The inverter includes a first inverter and a second inverter,
The holding target signal is input to the second inverter when the control signal becomes active,
The output signal is output based on the output of the second inverter,
When the control signal is active, the input terminal of the first inverter and the output terminal of the second inverter are electrically connected to each other, and the output terminal of the first inverter and the input of the second inverter The holding circuit according to any one of claims 1 to 3, wherein the terminals are electrically connected to each other.
A first resistor is connected in series to the source terminal of the first transistor of the first inverter,
The holding circuit according to claim 6, wherein a second resistor is connected in series to a source terminal of the second transistor of the first inverter.
A display driving circuit for driving a display panel provided with a pixel electrode and a signal line forming a capacitor included in a pixel,
A shift register including a plurality of stages provided corresponding to each of the plurality of scanning signal lines;
And at least one holding circuit provided corresponding to each stage of the shift register,
The holding circuit according to any one of claims 1 to 7, wherein an output signal of each stage of the shift register is used as the control signal,
When an output signal of one stage of the shift register becomes active, a holding circuit corresponding to this stage takes in the holding target signal and holds it, and outputs an output signal corresponding to the holding target signal to this stage. A display driving circuit, characterized by being supplied to the corresponding signal line.
Used for a display device that supplies a signal of a first potential or a second potential to a common electrode wiring that forms a capacitor with a pixel electrode;
The output signal of the previous stage of the shift register is input to the holding circuit of the own stage,
When the output signal of the previous stage of the shift register becomes active, the holding circuit of its own stage takes in the holding target signal and holds it, and becomes the first potential or the second potential according to the holding target signal. 9. The display drive circuit according to claim 8, wherein an output signal is supplied to the common electrode wiring that forms a capacitor with a pixel electrode of a pixel in its own stage.
Used in a display device that supplies a modulation signal corresponding to the polarity of a signal potential written to a pixel electrode to a storage capacitor wiring that forms a capacitor with the pixel electrode,
The output signal of the latter stage of the shift register is input to the holding circuit of the own stage,
When the output signal of the subsequent stage of the shift register becomes active, the holding circuit of the own stage takes in the holding target signal and holds it, and outputs the output signal according to the holding target signal to the pixel of the own stage pixel. 9. The display driving circuit according to claim 8, wherein the modulation signal is supplied to the storage capacitor wiring that forms a capacitance with an electrode.
A display panel, wherein the display driving circuit according to any one of claims 8 to 10 and the pixel circuit are formed monolithically.
A display device comprising the display drive circuit according to any one of claims 8 to 10.