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WO2012137472A1 - Substrat à matrice active et dispositif d'affichage à cristaux liquides - Google Patents

Substrat à matrice active et dispositif d'affichage à cristaux liquides Download PDF

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Publication number
WO2012137472A1
WO2012137472A1 PCT/JP2012/002296 JP2012002296W WO2012137472A1 WO 2012137472 A1 WO2012137472 A1 WO 2012137472A1 JP 2012002296 W JP2012002296 W JP 2012002296W WO 2012137472 A1 WO2012137472 A1 WO 2012137472A1
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WIPO (PCT)
Prior art keywords
data
liquid crystal
gate
lines
pixel
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PCT/JP2012/002296
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English (en)
Japanese (ja)
Inventor
誠二 金子
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シャープ株式会社
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Publication of WO2012137472A1 publication Critical patent/WO2012137472A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present invention relates to an active matrix substrate and a liquid crystal display device.
  • the present invention relates to an active matrix substrate and a liquid crystal display device that can be driven at a low frequency and suppress display deterioration due to flickering of screen luminance.
  • Measures for reducing the power consumption of the display panel include increasing the aperture ratio of the panel in order to ensure excellent luminance and driving the panel at a low frequency.
  • the output of adjacent pixels is set to have a reverse polarity (dot inversion drive). This is because, by setting the outputs of adjacent pixels to opposite polarities, writing is averaged between the positive polarity and the negative polarity, and flicker becomes difficult to be visually recognized.
  • Patent Document 1 alternately generates a first timing signal corresponding to a first timing at which a positive drive voltage is to be applied and a second timing signal corresponding to a second timing at which a negative drive voltage is to be applied.
  • a timing generation driver for outputting to each of the liquid crystal display cells connected to the first data driver via the first data line and corresponding to the first timing signal input via the first gate line.
  • the first switching element for applying voltage to the second liquid crystal display cell connected to the second data driver via the second data line and input via the second gate line to the corresponding one liquid crystal display cell.
  • a liquid crystal display device including a second switching element that applies a voltage is disclosed.
  • the polarity of the drive voltage applied to the adjacent liquid crystal display element can be reversed without inverting the polarity of the data line drive voltage every horizontal period. It is described that a high-quality display without occurrence of luminance unevenness can be obtained and that the power consumed by driving the liquid crystal panel can be reduced.
  • Patent Document 1 Japanese Patent Document 1
  • two types of data drivers are required per panel, and a large amount of power is required to drive each data driver, and the manufacturing cost increases.
  • two gate lines and two data lines are required per pixel, the aperture ratio is reduced, and the power consumption of the backlight is increased accordingly.
  • An object of the present invention is to perform high-speed writing in an active matrix substrate and a liquid crystal display device including the same, thereby reducing power consumption and further reducing manufacturing costs.
  • the active matrix substrate of the present invention is m ⁇ n pixel units arranged in a matrix of m rows and n columns (m and n are integers of 2 or more);
  • the m first gate lines and the m second gate lines respectively corresponding to the m pixel rows of the m ⁇ n pixel portions extend in parallel with each other in the row direction and are spaced apart from each other in the column direction.
  • the gate line Including a data line to which a positive data signal is applied and a data line to which a negative data signal is applied, along the column direction so as to partition n pixel columns of the m ⁇ n pixel units.
  • each of the m pixel units included in the kth column (1 ⁇ k ⁇ n) pixel column is A liquid crystal element;
  • the (k + 1) th column data line and And a second switching element that switches a connection state with the liquid crystal element In response to a control signal disposed between the first and second gate lines corresponding to the pixel portion and applied to the other of the first and second gate lines, the (k + 1) th column data line and And a second switching element that switches a connection state with the liquid crystal element.
  • the pixel portion (herein referred to as the first pixel portion) included in the k-th pixel column, and the pixel column adjacent to it in the row direction and in the k + 1-th column (1 ⁇ k ⁇ n) will be described with respect to the pixel portion included in the pixel (here, the second pixel portion).
  • a positive data signal is applied to the kth and k + 2th data lines
  • a negative data signal is applied to the k + 1th data line
  • the first The first switching element of the pixel portion is provided to switch a connection state between the data line of the kth column and the liquid crystal element in response to a control signal applied to the first gate line.
  • a second switching element is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the second gate line, and the first switching element of the second pixel unit
  • a switching element is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the first gate line, and the second switching of the second pixel unit Device applied to second gate line It will be described which is provided to switch the connection state between the (k + 2) th column data line and the liquid crystal element in response to a control signal.
  • the control signal is applied to any one of the m first gate lines, while the control signal is not applied to any of the m second gate lines.
  • the control signal is applied to any one of the m second gate lines, while the control signal is not applied to any of the m first gate lines.
  • Driving is performed. Therefore, in the first driving period, when the first gate line corresponding to the first and second pixel portions is selected and the control signal is applied, the first pixel portion responds to the control signal.
  • the first switching element is turned on, and a positive driving voltage is applied to the liquid crystal element via the kth column data line to which the positive data signal is applied.
  • the first switching element is turned on in response to the control signal, and the liquid crystal element is negatively driven through the (k + 1) th column data line to which the negative data signal is applied. A voltage will be applied.
  • the first pixel portion receives a second signal in response to the control signal.
  • the switching element is turned on, and a negative drive voltage is applied to the liquid crystal element via the data line of the (k + 1) th column to which the negative data signal is applied.
  • the second switching element is turned on in response to the control signal, and the liquid crystal element is positively driven through the k + 2th column data line to which the positive data signal is applied. A voltage will be applied.
  • the first switching element of the first pixel unit is provided so as to switch a connection state between the data line of the kth column and the liquid crystal element in response to a control signal applied to the second gate line.
  • a second switching element of one pixel unit is provided to switch a connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the first gate line.
  • the first switching element is provided to switch the connection state between the data line of the (k + 1) th column and the liquid crystal element in response to a control signal applied to the second gate line, and Similarly, when the second switching element is provided so as to switch the connection state between the data line of the (k + 2) th column and the liquid crystal element in response to a control signal applied to the first gate line, Dot inversion Motion can be carried out.
  • the polarity of the data signal applied to each data line is not charged / discharged for each frame and inverted, and the drive voltage applied to each liquid crystal element of the adjacent first pixel portion and second pixel portion is determined. Since the polarity can be reversed, the power consumed by driving can be suppressed.
  • two switching elements are provided in one pixel portion, but one data line (here, the data line of the (k + 1) th column (1 ⁇ k ⁇ n))
  • a data signal is supplied to the second switching element of the pixel portion (first pixel portion) included in the k-th pixel row, while the pixel portion (second pixel portion) of the pixel portion (second pixel portion) included in the k + 1-th pixel row. Since the data signal is supplied to one switching element, it is only necessary to arrange one data line in each part that partitions adjacent pixel columns. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first and second switching elements, and a large aperture ratio of the active matrix substrate can be ensured. The power consumption of the light can be suppressed.
  • the n + 1 data lines are arranged so that the data lines to which the positive data signal is applied and the data lines to which the negative data signal is applied are alternately arranged.
  • These data lines can be driven by a single type of data driver, and power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
  • the first switching elements or the second switching elements are on both sides of the first gate line and / or the second gate line. It is preferable that they are arranged to face each other.
  • the active matrix substrate of the present invention is preferably arranged so that the first gate lines and the second gate lines are alternately arranged in the column direction.
  • a pair of the first gate line and the second gate line is arranged so as to partition each pixel portion in the column direction. While the control signal is applied to the first gate line in the first driving period, the control signal is not applied to the second gate line, and the control signal is applied to the second gate line in the second driving period. On the other hand, no control signal is applied to the first gate line. That is, since a control signal is not applied to both the first gate line and the second gate line within the same frame, each pair of the first gate line and the second gate line is connected to each other. Even if a pair of both are arranged close to each other so as to partition the pixel portion in the column direction, it is possible to suppress deterioration in driving characteristics due to parasitic capacitance between the first gate line and the second gate line. .
  • the active matrix substrate of the present invention is preferably a thin film transistor (hereinafter also referred to as “TFT”) in which each of the first switching element and the second switching element includes an oxide semiconductor film.
  • TFT thin film transistor
  • each of the first switching element and the second switching element is a TFT including an oxide semiconductor film, high-speed writing drive is possible, and a change in luminance of the screen can be suppressed. It is possible to reduce the change in pixel potential due to TFT off-leak during the writing suspension period. Therefore, display deterioration due to flicker can be further suppressed.
  • the liquid crystal display device of the present invention includes the above-described active matrix substrate of the present invention, In the row direction, the data signals are applied to the n + 1 data lines so that the data lines to be applied with the positive data signal and the data lines to be applied with the negative data signal are alternately arranged in the row direction.
  • a first gate driver that does not apply a control signal to any of the gate lines; In the first driving period, no control signal is applied to any of the m second gate lines, and in the second driving period, any one of the m second gate lines.
  • a second gate driver for applying a control signal to be transmitted to the second switching element It is characterized by providing.
  • each data is arranged such that the data line to which the data driver applies the positive data signal and the data line to which the negative data signal is applied are alternately arranged in the row direction.
  • a signal is applied to each of the n + 1 data lines, and the first gate driver and the second gate driver are connected to any one of the m first gate lines in the first driving period. While the control signal transmitted to the first switching element is applied, the control signal is not applied to any of the m second gate lines, and the m second gates are applied during the second driving period.
  • a control signal to be transmitted to the second switching element is applied to any one of the lines, while a control signal is not applied to any of the m first gate lines.
  • Apply a voltage of Bets can be, also, it is possible to perform dot inversion driving for inverting the polarity of each pixel unit for each drive period.
  • a single type of data driver has alternating data lines to which positive data signals are applied and data lines to which negative data signals are applied in the row direction. Since the data signals are respectively applied to the n + 1 data lines so as to line up with each other, power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Further, the frame can be narrower than when a plurality of types of data drivers are provided.
  • m first gate lines and m second gate lines respectively corresponding to m pixel rows of the pixel portion extend in parallel to each other in the row direction.
  • N + 1 data lines that are arranged and extend so as to partition the n pixel columns of the pixel portion are alternately arranged with data lines to which positive data signals are applied and data lines to which negative data signals are applied.
  • the pixel units are arranged side by side, and each pixel portion is connected to the liquid crystal element and the liquid crystal element in response to a control signal applied to one of the first and second gate lines.
  • the first A control signal is applied to the first gate line in the driving period to turn on the first switching element, and then a control signal is applied to the second gate line in the second driving period to activate the second switching element.
  • the voltage applied to the liquid crystal element in the adjacent pixel portion can be reversed, and the polarity of the voltage applied to each liquid crystal element can be reversed every driving period. That is, dot inversion driving can be performed.
  • the active matrix substrate By driving the active matrix substrate in this way, the polarity of the voltage applied to each liquid crystal element can be reversed without charging and discharging the polarity of the data signal applied to each data line. As a result, driving power can be suppressed.
  • two switching elements are provided in one pixel portion, but one data line (here, the data line in the (k + 1) th column (1 ⁇ k ⁇ n))
  • the control signal is supplied to the second switching element of the pixel unit included in the kth pixel column, while the control signal is supplied to the first switching element of the pixel unit included in the k + 1th pixel column.
  • the control signal is supplied to the first switching element of the pixel portion included in the k-th pixel column, while the control signal is supplied to the second switching element of the pixel portion included in the k + 1-th pixel column. Therefore, it is only necessary that one data line is arranged in each part that partitions adjacent pixel columns. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first and second switching elements, and a large aperture ratio of the active matrix substrate can be ensured. The power consumption of the light can be suppressed.
  • the n + 1 data lines are arranged so that the data lines to which the positive data signal is applied and the data lines to which the negative data signal is applied are alternately arranged.
  • These data lines can be driven by a single type of data driver, and power consumption for driving the data driver can be suppressed as compared with the case where a plurality of types of data drivers are provided. Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
  • FIG. 1 is a schematic configuration diagram of a liquid crystal display device of Embodiment 1.
  • FIG. FIG. 2 is an enlarged view of regions of four pixel portions Pjk, Pj (k + 1), P (j + 1) k, and P (j + 1) (k + 1) in FIG. 3 is an operation timing chart of the first embodiment.
  • FIG. 6 is an image diagram for explaining the operation of the first embodiment in (a) a first driving period and (b) a second driving period.
  • the graph which shows the relationship between the writing time and panel surface brightness
  • FIG. 1 shows a schematic configuration of the liquid crystal display device 10.
  • the liquid crystal display device 10 includes a reference voltage generation circuit 11 that generates and outputs a reference voltage of the entire device, a current amplifier 12 that amplifies a voltage signal from the reference voltage generation circuit 11 and outputs the current signal to a data driver 15 described later.
  • a plurality of first gate lines Ga (1), Ga (2),... And a plurality of second gate lines Gb (1), Gb (2),... (Hereinafter referred to as a plurality of second gate lines Gb (1), Gb (2),...) Based on the horizontal synchronization signal.
  • the two gate lines may be collectively referred to as a second gate line Gb.) And a plurality of data lines D (1) and D (2) based on the horizontal synchronization signal. , ... (Hereafter, data is collected from multiple data lines. Also referred to as D.) Of it comprises a single type of data driver 15 for applying a data signal to each of the.
  • the data driver 15 may be configured by one data driver, or may be configured by combining all the same types of data drivers.
  • the first gate line Ga, the second gate line Gb, and the data line D are formed on the active matrix substrate 20.
  • m ⁇ n pixel portions P11, P12,... are arranged in a matrix of m rows ⁇ n columns.
  • m and n are integers of 2 or more.
  • Each of the m ⁇ n pixel portions P is an intersection of the jth pixel row and the kth pixel column at integers j and k where 1 ⁇ j ⁇ m and 1 ⁇ k ⁇ n + 1.
  • the pixel portion Pjk is arranged in the area to be processed.
  • the plurality of first gate lines Ga are provided so as to correspond to m pixel rows of the m ⁇ n pixel portions and to extend in parallel with each other in the row direction.
  • Each of the m first gate lines Ga has the first gate line Ga (j) arranged in the j-th row.
  • a plurality of second gate lines Gb are provided so as to respectively correspond to m pixel rows of the m ⁇ n pixel portions and to extend in parallel with each other along the row direction.
  • Each of these m second gate lines Gb has the second gate line Gb (j) arranged in the j-th row.
  • the first gate line Ga (j) and the second gate line Gb (j) in the j-th row are arranged so as to be separated from each other in the column direction.
  • the n + 1 data lines D are provided so as to extend in parallel with each other along the column direction so as to partition n pixel columns of the m ⁇ n pixel portions P. Each of these n + 1 data lines D has a data line D (k) arranged in the k-th column.
  • the n + 1 data lines D include a data line to which a positive data signal is applied and a data line to which a negative data signal is applied, and a data line to which a positive data signal is applied and a negative data signal. Are arranged so as to be alternately arranged with data lines to which is applied.
  • Each pixel portion P includes a liquid crystal element 21, a first TFT 22 that is a first switching element, a second TFT 23 that is a second switching element, and a storage capacitor 24 for memory.
  • Each of the first TFT 22 and the second TFT includes an oxide semiconductor film as a semiconductor film. Examples of the oxide semiconductor film include indium gallium zinc composite oxide (IGZO).
  • the liquid crystal element 21 has one terminal connected to the counter electrode.
  • the storage capacitor 24 has one terminal connected to the common sources 22S and 23S of the first TFT 22 and the second TFT 23, and the other terminal connected to the counter electrode.
  • the first TFT 22 is disposed between the first gate line Ga (j) and the second gate line Gb (j).
  • the first TFT 22 can switch the connection state between the data line D (k) in the kth column and the liquid crystal element 21 (liquid crystal element CLa) in response to a control signal applied to the first gate line Ga (j).
  • the gate 22G is connected to the first gate line Ga (j) in the j-th row
  • the drain 22D is connected to the data line D (k) in the k-th column
  • the source 22S is connected to the other terminal of the liquid crystal element 21. It is connected to the.
  • the second TFT 23 is disposed between the first gate line Ga (j) and the second gate line Gb (j).
  • the second TFT 23 has a gate so that the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 can be switched in response to a control signal applied to the second gate line Gb (j).
  • 23G is connected to the second gate line Gb (j) of the jth row, the drain 23D is connected to the data line D (k + 1) of the (k + 1) th column, and the source 23S is connected to the other terminal of the liquid crystal element 21. It is connected.
  • the first TFT 22 switches the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 (liquid crystal element CLb) in response to a control signal applied to the first gate line Ga (j).
  • the gate 22G is connected to the first gate line Ga (j) in the jth row
  • the drain 22D is connected to the data line D (k + 1) in the (k + 1) th column
  • the source 22S is connected to the liquid crystal element 21. Is connected to the other terminal.
  • the second TFT 23 has a gate so that the connection state between the data line D (k + 2) in the (k + 2) th column and the liquid crystal element 21 can be switched in response to a control signal applied to the second gate line Gb (j).
  • 23G is connected to the second gate line Gb (j) of the jth row
  • the drain 23D is connected to the data line D (k + 2) of the (k + 2) th column
  • the source 23S is connected to the other terminal of the liquid crystal element 21. It is connected.
  • the first TFT 22 switches the connection state between the data line D (k) in the kth column and the liquid crystal element 21 (liquid crystal element CLc) in response to a control signal applied to the second gate line Gb (j + 1).
  • the gate 22G is connected to the second gate line Gb (j + 1) in the (j + 1) th row
  • the drain 22D is connected to the data line D (k) in the kth column
  • the source 22S is connected to the liquid crystal element 21. Is connected to the other terminal.
  • the second TFT 23 can switch the connection state between the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 in response to a control signal applied to the first gate line Ga (j + 1).
  • the gate 23G is connected to the first gate line Ga (j + 1) of the (j + 1) th row
  • the drain 23D is connected to the data line D (k + 1) of the (k + 1) th column
  • the source 23S is connected to the liquid crystal element 21. Connected to the other terminal.
  • the first TFT 22 is connected to the data line D (k + 1) of the (k + 1) th column and the liquid crystal element 21 (liquid crystal element CLd) in response to a control signal applied to the second gate line Gb (j + 1).
  • the gate 22G is connected to the second gate line Gb (j + 1) of the (j + 1) th row
  • the drain 22D is connected to the data line D (k + 1) of the (k + 1) th column
  • the source 22S Is connected to the other terminal of the liquid crystal element 21.
  • the second TFT 23 can switch the connection state between the liquid crystal element 21 and the data line D (k + 2) of the (k + 2) th column in response to a control signal applied to the first gate line Ga (j + 1).
  • the gate 23G is connected to the first gate line Ga (j + 1) in the (j + 1) th row
  • the drain 23D is connected to the data line D (k + 2) in the (k + 2) th column
  • the source 23S is connected to the liquid crystal element 21. Connected to the other terminal.
  • the n + 1 data lines D are arranged such that data lines to which positive data signals are always applied and data lines to which negative data signals are always applied are alternately arranged in the row direction. That is, the data driver 15 always applies a positive data signal to the data line D (o) in the o-th column with respect to the odd integer o (1 ⁇ o ⁇ n + 1) and is an even integer e. A negative data signal is always applied to the data line D (e) of the e-th column with respect to (2 ⁇ e ⁇ n + 1), or for an integer o (1 ⁇ o ⁇ n + 1) which is an odd number.
  • a negative-polarity data signal is always applied to the o-th data line D (o), and the even-numbered integer e (2 ⁇ e ⁇ n + 1) is applied to the e-th data line D (e).
  • e even-numbered integer
  • e negative-polarity data signal
  • a positive data signal is always applied to the data lines D (k) and D (k + 2), and a negative data signal is always applied to the data line D (k + 1).
  • a signal is applied.
  • the first gate driver 13 selects the first gate line Ga (j), and the first gate line Ga (j) becomes H level. Thereby, a control signal is applied to the first TFT 22 of the pixel portion Pjk from the first gate driver 13 to be turned on, and a positive data signal is transmitted from the data driver 15 through the data line D (k). Therefore, a positive drive voltage is applied to the liquid crystal element CLa during the first drive period.
  • a first gate line Ga (j) is becomes H level
  • the control signal from the first gate driver 13 is turned on is applied to the 1TFT22 pixel portion Pj (k + 1), A negative data signal is transmitted from the data driver 15 via the data line D (k + 1). Therefore, a negative drive voltage is applied to the liquid crystal element CLb during the first drive period.
  • the first gate line Ga (j + 1) becomes the H level.
  • the control signal is applied to the second TFT 23 of the pixel portion P (j + 1) k from the first gate driver 13 to be turned on, and the negative polarity is transmitted from the data driver 15 via the data line D (k + 1). Data signals are transmitted. Therefore, a negative drive voltage is applied to the liquid crystal element CLc during the first drive period.
  • the first gate driver 13 selects the forward first following gate line Ga on the basis of the horizontal synchronizing signal, in a first drive period, positive or negative driving voltage to each liquid crystal element Applied.
  • the second gate driver 14 selects the second gate line Gb to (j), the second gate line Gb (j) becomes the H level.
  • a control signal is applied to the second TFT 23 of the pixel portion Pjk from the second gate driver 14 to turn it on, and a negative data signal is transmitted from the data driver 15 via the data line D (k + 1).
  • the Therefore, a negative drive voltage is applied to the liquid crystal element CLa during the second drive period.
  • the second gate driver 14 selects second gate line Gb the (j + 1) at time t 4, the second gate line Gb (j + 1) becomes the H level.
  • a control signal is applied to the first TFT 22 of the pixel portion P (j + 1) k from the second gate driver 14 to turn it on, and positive data from the data driver 15 via the data line D (k).
  • a signal is transmitted. Therefore, a positive drive voltage is applied to the liquid crystal element CLc during the second drive period.
  • the second gate driver 14 selects the forward order second gate line Gb based on a horizontal synchronizing signal, in a second drive period, positive or negative driving voltage to each liquid crystal element Applied.
  • a positive data signal is always applied to the data line D (k) and the data line D (k + 2), and a negative data signal is always applied to the data line D (k + 1).
  • positive, negative, negative, and positive drive voltages are applied to the liquid crystal elements CLa, CLb, CLc, and CLd, respectively.
  • negative, positive, positive, and negative drive voltages are applied to the liquid crystal elements CLa, CLb, CLc, and CLd, respectively. Therefore, the polarity of the data signal applied to each data line D can be reversed between adjacent liquid crystal elements without reversing the polarity, and the voltage applied to each liquid crystal element CLa, CLb, CLc, CLd. Can be inverted every frame.
  • the first gate driver 13, the second gate driver 14, and the data driver 15 are provided outside the active matrix substrate 20, but these are formed in the peripheral region of the active matrix substrate 20. It may be.
  • each liquid crystal element 21 is transmitted by always transmitting a positive polarity data signal or a negative polarity data signal without charging and discharging the polarity of the data signal applied to each data line D. Since the polarity of the voltage applied to can be reversed, driving power consumption can be suppressed. In addition, since the polarity of the voltage applied to each liquid crystal element 21 can be inverted without charging and discharging the polarity of the data signal applied to each data line D, stable control can be performed at high speed. Is possible.
  • FIGS. 5A to 5C show the relationship between the writing time and the panel surface brightness when the flicker pattern is displayed on the screen in the drive that pauses after high-speed writing.
  • the write time for each frame in FIG. 5A is A [msec]
  • FIG. 5B is the write time 2/3 ⁇ A [msec]
  • FIG. 5C is the write time 1/2 ⁇ . A case of A [msec] is shown. From FIG. 5, it is known that as the writing time for each frame becomes shorter, the luminance amplitude becomes smaller and the flickering of the screen luminance is reduced.
  • first TFT 22 and second TFT 23 are provided in one pixel portion P, but one data line D (here, for example, the data line in the (k + 1) th column) D (k + 1)) provides a data signal to the second TFT 23 of the pixel unit Pjk included in the kth pixel column, while the pixel unit Pj (k + 1) included in the k + 1th pixel column.
  • the first TFT 22 is configured to provide a data signal, or a data signal is applied to the first TFT 22 of the pixel portion P (j + 1) k included in the kth pixel column, while the k + 1th column.
  • the data signal is supplied to the second TFT 23 of the pixel portion P (j + 1) (k + 1) included in the pixel column, the adjacent pixel columns (the k-th column and the k + 1-th column) It is only necessary that one data line D is arranged in each part that divides the area. Therefore, it is not necessary to arrange two data lines per pixel column in order to drive each of the first TFT 22 and the second TFT 23, and the aperture ratio of the active matrix substrate 20 can be secured large. As a result, the backlight Power consumption can be suppressed.
  • the n + 1 data lines D are arranged such that data lines to which a positive data signal is applied and data lines to which a negative data signal is applied are alternately arranged. Therefore, it is possible to drive these data lines D with a single type of data driver 15, and power consumption for driving the data driver 15 can be suppressed as compared with the case where a plurality of types of data drivers are provided. . Further, the manufacturing cost can be reduced as compared with the case where a plurality of types of data drivers are provided. Furthermore, the frame can be narrower than when a plurality of types of data drivers are provided.
  • the first gate lines Ga and the second gate lines Gb are arranged on the active matrix substrate 20 so as to be alternately arranged in the column direction.
  • a pair of the first gate line Ga (j + 1) and the second gate line Gb (j) is arranged so as to partition the pixel row of the jth row and the pixel row of the j + 1th row in the column direction.
  • the Rukoto In the first driving period, a control signal is applied to the first gate line Ga, while no control signal is applied to the second gate line Gb, and in the second driving period, a control signal is applied to the second gate line Gb. On the other hand, no control signal is applied to the first gate line Ga.
  • the first gate line Ga (j + 1) and the second gate line Gb (j) are arranged so as to partition the j-th pixel row and the j + 1-th pixel row in the column direction, the pair of first gate lines Ga ( j + 1) and the second gate line Gb (j) can suppress the deterioration of drive characteristics due to parasitic capacitance.
  • the first gate lines Ga and the second gate lines Gb are arranged so as to be alternately arranged in the column direction on the active matrix substrate 20, but as shown in FIG.
  • the first gate line Ga and the second gate line Gb may be arranged so as not to be arranged alternately.
  • the second TFT 23 of the pixel portion Pjk and the first TFT 22 of the pixel portion P (j + 1) k are two second gate lines. They are arranged opposite to each other across Gb (j) and Gb (j + 1).
  • the second TFT 23 of the pixel portion P (j ⁇ 1) k and the first TFT 22 of the pixel portion Pjk are two first gate lines. They are arranged opposite to each other across Gb (j-1) and Gb (j). That is, the first TFT 22 and the second TFT 23 are arranged opposite to each other via the two first gate lines Ga or the two second gate lines Gb, thereby ensuring a large aperture ratio of the active matrix substrate 20. can do.
  • the n + 1 data lines D are described as including a data line to which a positive data signal is always applied and a data line to which a negative data signal is always applied.
  • a positive data signal is applied to a specific data line D (here, data line D (k)), and in another case, a negative data signal is applied to the data line D (k).
  • the polarity of the voltage applied to the specific data line D (k) may be inverted every plural frames. Even in this case, since the dot inversion drive can be performed without inverting the polarity of the data signal applied to each data line for each frame, the polarity of the voltage applied to the data line for each frame as described above. The power consumption can be reduced as compared with the case of inversion.
  • the present invention is useful for an active matrix substrate and a liquid crystal display device.
  • the present invention is useful for an active matrix substrate and a liquid crystal display device that can be driven at a low frequency and suppress display deterioration due to flickering of screen brightness.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention concerne un substrat à matrice active comportant (n+1) lignes de données (D), les lignes de données auxquelles est appliqué un signal de données anodique et les lignes de données auxquelles est appliqué un signal de données cathodique étant disposées alternativement dans la direction des rangées. Les sections de pixels (P1k - Pmk) comprennent chacune : un élément cristallin liquide (21) ; un premier élément de commutation (22) qui inverse l'état de connexion de l'élément cristallin liquide (21) et de la ligne de données (D(k)) de la kème colonne en réponse à un signal de commande appliqué à une première ou une deuxième ligne de grille (Ga(j), Gb(j)) ; et un deuxième élément de commutation (23) qui inverse l'état de connexion de l'élément cristallin liquide (21) et de la ligne de données (D(k+1)) de la (k+1)ème colonne en réponse à un signal de commande appliqué à l'autre des première et deuxième lignes de grille (Ga(j), Gb(j)). Selon la présente invention, la consommation d'énergie peut être réduite parce que la commande d'inversion de points peut être appliquée sans inverser la polarité du signal de données qui est appliqué à chacune des lignes de données de chaque trame individuelle. La présente invention peut s'appliquer à des dispositifs d'affichage à cristaux liquides.
PCT/JP2012/002296 2011-04-05 2012-04-02 Substrat à matrice active et dispositif d'affichage à cristaux liquides WO2012137472A1 (fr)

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JP2011083959 2011-04-05

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113409718A (zh) * 2021-05-27 2021-09-17 惠科股份有限公司 一种显示面板和显示装置
CN114333726A (zh) * 2021-12-29 2022-04-12 惠科股份有限公司 一种显示面板和显示装置
JP7529758B2 (ja) 2020-03-19 2024-08-06 京東方科技集團股▲ふん▼有限公司 表示基板及び表示装置

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Publication number Priority date Publication date Assignee Title
JP2006139288A (ja) * 2004-11-12 2006-06-01 Samsung Electronics Co Ltd 表示装置及びその駆動方法
JP2007121767A (ja) * 2005-10-28 2007-05-17 Nec Lcd Technologies Ltd 液晶表示装置
JP2010135780A (ja) * 2008-11-07 2010-06-17 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006139288A (ja) * 2004-11-12 2006-06-01 Samsung Electronics Co Ltd 表示装置及びその駆動方法
JP2007121767A (ja) * 2005-10-28 2007-05-17 Nec Lcd Technologies Ltd 液晶表示装置
JP2010135780A (ja) * 2008-11-07 2010-06-17 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7529758B2 (ja) 2020-03-19 2024-08-06 京東方科技集團股▲ふん▼有限公司 表示基板及び表示装置
CN113409718A (zh) * 2021-05-27 2021-09-17 惠科股份有限公司 一种显示面板和显示装置
CN113409718B (zh) * 2021-05-27 2022-02-18 惠科股份有限公司 一种显示面板和显示装置
CN114333726A (zh) * 2021-12-29 2022-04-12 惠科股份有限公司 一种显示面板和显示装置

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