[go: up one dir, main page]

WO2012121373A1 - Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package - Google Patents

Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package Download PDF

Info

Publication number
WO2012121373A1
WO2012121373A1 PCT/JP2012/056125 JP2012056125W WO2012121373A1 WO 2012121373 A1 WO2012121373 A1 WO 2012121373A1 JP 2012056125 W JP2012056125 W JP 2012056125W WO 2012121373 A1 WO2012121373 A1 WO 2012121373A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal foil
carrier metal
flip chip
chip connection
forming
Prior art date
Application number
PCT/JP2012/056125
Other languages
French (fr)
Japanese (ja)
Inventor
田村 匡史
沙織 川崎
若林 昭彦
邦司 鈴木
坪松 良明
Original Assignee
日立化成工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2011051378A external-priority patent/JP5769001B2/en
Application filed by 日立化成工業株式会社 filed Critical 日立化成工業株式会社
Priority to KR1020137025239A priority Critical patent/KR101585305B1/en
Priority to CN201280012341.XA priority patent/CN103443916B/en
Publication of WO2012121373A1 publication Critical patent/WO2012121373A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1536Temporarily stacked PCBs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the present invention relates to a method for manufacturing a package substrate for mounting a semiconductor element capable of increasing the density, a package substrate for mounting a semiconductor element, and a semiconductor package, and more particularly, includes a flip chip connection terminal for connecting to a semiconductor element having bumps.
  • the present invention relates to a semiconductor device mounting package substrate manufacturing method, a semiconductor device mounting package substrate, and a semiconductor package.
  • solder element mounting package substrate As a method of electrically connecting the connection terminals of a semiconductor element and a semiconductor element mounting package substrate (hereinafter, “semiconductor element mounting package substrate” may be referred to as “package substrate”), flip-chip connection is used. Yes. In this flip chip connection, a preliminary solder is formed on the flip chip connection terminal of the package substrate for the purpose of forming a good solder fillet between the bump of the semiconductor element, and the preliminary solder and the bump of the semiconductor element are formed. In many cases, a method is used in which the amount of solder is secured by both solders and connected to bumps provided on a semiconductor element. On the other hand, along with miniaturization and high density of electronic components, it is necessary to arrange connection terminals with semiconductor elements at high density, and miniaturization of flip chip connection terminals is required.
  • the flip chip connection terminal 26 When the flip chip connection terminal is miniaturized, the area of the connection terminal on which the preliminary solder is formed is reduced, so that the amount of the preliminary solder formed on the flip chip connection terminal is also reduced. There is a problem that the formation of the solder fillet to be formed becomes insufficient and the connection reliability is lowered. Further, when an amount of preliminary solder sufficient for connection to a semiconductor element is formed on a fine flip chip connection terminal, as shown in FIG. 1, in a general manufacturing method, the flip chip connection terminal 26 is a package. Since it is formed in a convex shape with respect to the surface of the substrate, there is a problem in that the preliminary solder 19 wraps around the side surface of the flip chip connection terminal 26 and bridges the preliminary solder 19 between the adjacent flip chip connection terminals 26.
  • Patent Document 2 a method of increasing the amount of solder in this region by forming a wiring pattern in a region to be a flip chip connection terminal on a package substrate relatively long, and flip chip A method (Patent Document 2) is disclosed in which the amount of preliminary solder on a flip chip connection terminal is increased by partially increasing the width of a wiring pattern in a region to be a connection terminal as compared with other regions.
  • the circuit pattern forming the flip chip connection terminal 26 is a circuit pattern formed in a convex shape from the surface of the package substrate 1 (hereinafter, sometimes referred to as a “convex circuit”). Only the bottom surface of the convex circuit 32 is in close contact with the surface of the insulating layer 3 of the package substrate 1.
  • the convex circuit 32 is generally formed by a method involving etching such as a semi-additive method, so-called undercut occurs, and as a result, the width of the circuit pattern is thicker than the top (surface side).
  • the present invention has been made in view of the above-described problems, and can form a flip chip connection terminal that secures an adhesive force even if it is fine, and a preliminary solder necessary for flip chip connection with a bump of a semiconductor element.
  • a semiconductor device mounting package substrate a semiconductor device mounting package substrate, and a semiconductor package that can cope with high density and have high reliability by providing flip chip connection terminals with sufficient amount.
  • a multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate.
  • a method of manufacturing a package substrate for mounting a semiconductor element comprising: forming a three-dimensional circuit on the insulating layer on the surface of the stacked body; or forming a recess shape on the first pattern plating on the surface of the
  • a multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. Physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and on the second carrier metal foil of the core substrate Forming a laminated body by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating; and A step of physically peeling and separating the laminate from the core substrate together with the second carrier metal foil between the second carrier metal foil and the base metal foil; and on the second carrier metal foil of the peeled laminate Second pattern plating is performed on Then, etching is performed by forming an etching resist on the second carrier metal foil other than the portion where the second pattern plating is performed, and the portion other than the portion where the second pattern plating is performed and the portion where the etching resist
  • a method for manufacturing a mounting package substrate is a step of forming a laminate by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating, and the second carrier metal foil of the multilayer metal foil. Between the base metal foil and the base metal foil, and the step of physically separating the laminate from the core substrate together with the second carrier metal foil, and forming a desired number of insulating layers and conductor circuits A manufacturing method of a package substrate for mounting a semiconductor device, comprising a step. 4). 4.
  • the flip chip connection terminal is three-dimensionally formed on the first pattern plating on the surface of the multilayer body.
  • a semiconductor device mounting package substrate manufactured by the method for manufacturing a semiconductor mounting package substrate according to any one of Items 1 to 4, wherein the insulating layer and a buried surface provided such that an upper surface is exposed on the surface of the insulating layer.
  • Embedded circuit and a solder resist provided on the insulating layer and the embedded circuit, and the embedded circuit disposed in the opening of the solder resist forms a flip chip connection terminal, and this flip chip connection
  • the package substrate for mounting a semiconductor element according to Item 5 wherein a via is connected to a bottom surface of the embedded circuit forming the flip chip connection terminal. 7.
  • Item 8. The package substrate for mounting a semiconductor element according to any one of Items 5 to 7, wherein a concave shape is formed in a part of the flip chip connection terminal in the longitudinal direction. 9.
  • Item 9. The package board for mounting a semiconductor element according to any one of Items 5 to 8, wherein the tip of the flip chip connection terminal is disposed in the opening of the solder resist. 10.
  • Item 10 The package substrate for mounting a semiconductor element according to any one of Items 5 to 9, wherein an embedded circuit having a portion extended to both sides or one side in the longitudinal direction of the flip chip connection terminal is provided. 11.
  • the present invention it is possible to form a flip chip connection terminal having a sufficient adhesion even if it is fine, and a flip chip connection terminal having an amount of preliminary solder necessary for flip chip connection with a bump of a semiconductor element.
  • a manufacturing method of a package substrate for mounting a semiconductor element which can cope with high density and excellent in reliability, a package substrate for mounting a semiconductor element, and a semiconductor package.
  • FIG. 4A is a plan view
  • FIG. 5B is a cross-sectional view taken along the line A-A ′
  • FIG. 5C is a cross-sectional view taken along the line B-B ′
  • FIG. 4A is a plan view
  • FIG. 5B is a cross-sectional view taken along the line A-A ′ in the vicinity of the flip chip connection terminal of the package substrate of the present invention.
  • FIG. 4A is a plan view
  • FIG. 5B is a cross-sectional view taken along the line A-A ′
  • FIG. 5C is a cross-sectional view taken along the line B-B ′.
  • FIG. 4A is a plan view and FIG. 5B is a cross-sectional view taken along the line A-A ′ in the vicinity of the flip chip connection terminal of the package substrate of the present invention.
  • FIG. 4A is a plan view and FIG. 5B is a cross-sectional view taken along the line A-A ′ in the vicinity of the flip chip connection terminal of the package substrate of the present invention.
  • FIG. 4A is a plan view and FIG. 5B is a cross-sectional view taken along the line A-A ′ in the vicinity of the flip chip connection terminal of the package substrate of the present invention.
  • FIG. 3A is a plan view, FIG.
  • FIG. 2B is a cross-sectional view taken along the line A-A ′, and FIG. It is sectional drawing of the flip-chip connection terminal vicinity of the package of this invention. It is sectional drawing of the multilayer metal foil used for this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is sectional drawing of the semiconductor package produced using the manufacturing method of the package
  • the upper surface is exposed on the surface of the insulating layer 3 and the insulating layer 3.
  • Embedded circuit 2 provided in this manner, and solder resist 4 provided on insulating layer 3 and embedded circuit 2, and embedded circuit 2 disposed in opening 31 of solder resist 4.
  • the flip chip connection terminal 26 is formed by the embedded circuit 2 whose upper surface is exposed on the surface of the insulating layer 3.
  • the embedded circuit 2 forming the flip chip connection terminal 26 has a fine line / space level of 20 ⁇ m / 20 ⁇ m or less. Even with a simple circuit pattern, it is possible to form the flip-chip connection terminal 26 that secures the adhesion to the insulating layer 3. In the case of having the embedded circuit 2 extended on both sides in the longitudinal direction of the flip chip connecting terminal 26, the embedded circuit 2 fixes the flip chip connecting terminal 26 from both sides. However, in the present invention, compared to the convex circuit 32 as shown in FIG.
  • the flip-chip connection terminal 26 that ensures the adhesion with the insulating layer 3 even if it is fine. For this reason, as shown in FIG. 3, it is possible to provide the embedded circuit 2 extended only on one side in the longitudinal direction of the flip chip connection terminal 26. In this case, the size of the flip chip connection terminal 26 is reduced. Therefore, it is desirable in that the density can be increased. Moreover, as shown in FIG. 4, it is also possible to provide both the embedded circuit 2 extended to the one side and both sides of the flip chip connection terminal 26 in the longitudinal direction. As described above, the embedded circuit 2 extended in the longitudinal direction of the flip chip connection terminal 26 may be provided on both sides of the flip chip connection terminal 26 in the longitudinal direction or may be provided on only one side. Can be increased.
  • the flip chip connection terminal 26 is covered with the preliminary solder 19 having a thickness of 3 ⁇ m or more, it is possible to secure the amount of solder necessary for the flip chip connection with the bump 25 of the semiconductor element 15. Therefore, it is possible to provide the package substrate 1 for mounting a semiconductor element that can cope with high density and has excellent reliability.
  • the insulating layer of the present invention refers to an insulating substrate, a core substrate, a film, an interlayer insulating layer, a build-up layer, etc. formed using an organic insulating material.
  • an insulating layer what is generally used for a package substrate can be used, and a prepreg in which a glass cloth is impregnated with an epoxy resin or a polyimide resin, an epoxy adhesive sheet or a polyimide adhesive sheet is heated and pressurized. are formed.
  • the embedded circuit of the present invention refers to a circuit provided so that at least a part of the bottom surface and side surfaces are embedded in the insulating layer and at least the top surface is exposed on the surface of the insulating layer.
  • a metal foil is used as a power feeding layer, a predetermined circuit pattern is formed thereon by pattern electroplating, an insulating layer is formed on the circuit pattern, and the circuit pattern is embedded in the insulating layer. Thereafter, the metal foil serving as the power feeding layer is removed by etching or the like, so that the surface of the circuit pattern embedded in the pattern insulating layer is exposed from the insulating layer, which can be formed by a so-called transfer method.
  • the solder resist of the present invention protects the surface of the package substrate so that the preliminary solder does not adhere to portions other than the embedded circuit that becomes the flip chip connection terminal. Further, the opening provided in the solder girest defines a portion to be the flip chip connection terminal in the embedded circuit, so that the embedded circuit in the opening forms the flip chip connection terminal.
  • a photosensitive solder resist is preferable because a minute opening of a level of 100 ⁇ m in length ⁇ 100 ⁇ m in width for forming a flip chip connection terminal can be formed with high accuracy.
  • the flip chip connection terminal of the present invention means a connection terminal used for mounting a semiconductor element on a package substrate by flip chip connection.
  • Flip chip connection refers to a method of connecting the active element surface of a semiconductor element to the package substrate. Bumps as electrodes are formed on the semiconductor element, and the semiconductor element is turned over to match the mounting position on the package substrate. Thereafter, the bumps of the semiconductor element are connected to the flip chip connection terminals formed on the package substrate.
  • the flip-chip connection terminal of the present invention is not only a connection part that actually contacts the bump of the semiconductor element, but is an embedded circuit connected to the bump of the semiconductor element, and includes an insulating layer within the opening of the solder resist. The part exposed on the surface.
  • nickel / gold plating nickel plating and gold plating formed thereon
  • nickel / palladium / gold to prevent the surface from oxidation and ensure wettability of the pre-solder Protective plating such as plating (nickel plating and palladium plating thereon and gold plating formed thereon)
  • plating nickel plating and palladium plating thereon and gold plating formed thereon
  • the preliminary solder of the present invention refers to a solder provided on a flip chip connection terminal for flip chip connection with a semiconductor element.
  • the preliminary solder can be formed by a method of printing solder paste and reflowing, or other known methods.
  • solder paste solder particles such as Sn (tin) -Pb (lead) and Sn (tin) -Ag (silver) -Cu (copper) used for mounting electronic components are rosin or organic solvents. And the like.
  • a metal mask, a silk screen, or the like can be used for printing the solder paste.
  • the reflow can be performed using infrared reflow, hot air reflow, VPS (vapor phase soldering) reflow, or the like generally used in mounting electronic components.
  • the reflow conditions differ depending on the solder paste. For example, if the Sn-Pb (tin and lead) system is used, the peak temperature is about 240 ° C, and if the Sn (tin) -Ag (silver) -Cu (copper) system is used. The condition that the peak temperature is about 260 ° C. is mentioned.
  • the flip chip connection terminal is covered with a preliminary solder having a thickness of 3 ⁇ m or more. If the thickness of the preliminary solder is less than 3 ⁇ m, it is not sufficient to form a solder fillet between the flip chip connection terminal and the bump of the semiconductor element, and it is difficult to ensure connection reliability. On the other hand, when the thickness of the preliminary solder exceeds 20 ⁇ m, there is a possibility that the preliminary solder and the solder bridge on the adjacent flip chip connecting terminals are generated. For this reason, the thickness of the preliminary solder is desirably 3 ⁇ m or more and 20 ⁇ m or less.
  • the preliminary solder formed by reflowing solder paste or the like is formed in a substantially semi-cylindrical shape (kamaboko shape) due to the surface tension of the solder. Is done.
  • the thickness of the preliminary solder is formed to be the thickest at substantially the center in the longitudinal direction (length direction) and the short direction (width direction) of the flip chip connection terminal. Therefore, in the present invention, the thickness of the preliminary solder is determined so that the step between the solder resist surface and the solder surface is a non-contact type at approximately the center in the longitudinal direction (length direction) and the short direction (width direction) of the flip chip connection terminal. It was determined by measurement using a level difference measuring machine.
  • FIG. 5 As a second example of the package substrate of the present invention, as shown in FIG. 5, there is one in which a via 18 is connected to the bottom surface of the embedded circuit 2 including the flip chip connection terminal 26. Note that the preliminary solder is omitted.
  • vias 18 are formed on both the bottom surface of the flip chip connection terminal 26 and the bottom surface of the embedded circuit 2 extending in the longitudinal direction from the flip chip connection terminal 26. 18 may be formed. That is, in this second example, the bottom surface of the flip chip connection terminal 26 embedded in the insulating layer 3, the bottom surface of the embedded circuit 2 extending in the longitudinal direction from the flip chip connection terminal 26, or both of them.
  • a via 18 is formed on the bottom surface of.
  • the via 18 is connected to the bottom surface in this way, the flip chip connection terminal 26 or the embedded circuit 2 extended in the longitudinal direction from the flip chip connection terminal 26 is fixed to the insulating layer 3 by the via 18. It is possible to further strengthen the adhesion between the flip chip connection terminal 26 and the insulating layer 3 than in the first example.
  • the via is used to connect the layers of the wiring layer provided in multiple layers on the package substrate.
  • plating or the like is formed in the hole. Can be formed.
  • the via is preferably formed by so-called filled via plating.
  • a convex shape 27 is formed on a part of the flip chip connection terminal 26 in the longitudinal direction.
  • the convex shape 27 can be formed, for example, by forming a plating resist and pattern plating on a part of the portion that becomes the flip chip connection terminal 26 of the embedded circuit.
  • an etching resist is formed, and a part of the protruded embedded circuit is left protruding.
  • the other portions can also be formed by etching so as to be flush with the surface of the insulating layer 3.
  • the height of the convex shape 27 is desirably about 3 ⁇ m to 8 ⁇ m, and the range in which the convex shape 27 is provided is 50% to 100% of the dimension in the short direction (width direction) of the flip chip connection terminal 26, and the flip chip connection terminal It is desirable that it is about 10% to 70% of the dimension in the longitudinal direction (length direction) of 26.
  • the convex shape 27 By forming the convex shape 27 on a part of the flip chip connection terminal 26 in the longitudinal direction, solder accumulates on the stepped portion of the convex shape 27 (not shown), so that compared to the case where the surface is flat, The amount of solder disposed on the flip chip connection terminal 26 can be increased. Further, the convex shape 27 becomes a trigger for attracting other portions of the solder, and the solder aggregates around the convex shape 27, so that a protruding solder pool is formed at a predetermined position in the longitudinal direction of the flip chip connection terminal 26. You can also Therefore, a protruding portion on the flip chip connection terminal 26 can be provided in correspondence with the position of the bump of the semiconductor element mounted on the flip chip connection terminal 26. Therefore, the bump of the flip chip connection terminal 26 and the semiconductor element can be provided. Can be securely connected.
  • the recessed shape 28 is formed by, for example, forming an embedded circuit whose upper surface is exposed from the surface of the insulating layer 3 and then forming an etching resist so that a part of the upper surface of the embedded circuit whose upper surface is exposed is insulated. It can be formed by etching so that it is recessed from the surface of the layer 3 and the other part remains as it is.
  • the depth of the concave shape 28 is desirably about 3 ⁇ m to 8 ⁇ m.
  • the range of the concave shape 28 is 50% to 100% of the dimension in the short direction (width direction) of the flip chip connection terminal 26. Desirably, it is about 10% to 70% of the dimension in the longitudinal direction (length direction).
  • the tip of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4. Note that the preliminary solder is omitted.
  • the circuit pattern is a convex circuit 32 (FIG. 1). Only the bottom surface of the formed flip chip connection terminal 26 is bonded to the insulating layer 3. Further, since the circuit pattern is formed by etching, the circuit pattern formed by the convex circuit 32 causes a so-called undercut in which the width on the bottom surface side is narrower than the surface side of the circuit pattern when viewed from the cross section.
  • the circuit pattern is fixed from above by covering with the solder resist 4, and the flip chip connection terminal 26 is exposed from the opening 31 of the solder resist 4.
  • a method of fixing both sides of the flip chip connection terminal 26 in the longitudinal direction with the solder resist 4 is adopted.
  • the width of the opening 31 of the solder resist 4 is defined by the resolution limit of the solder resist 4, it is necessary to make the flip chip connection terminal 26 longer than the resolution limit of the solder resist 4. It was. For this reason, the degree of freedom of circuit pattern routing is also limited.
  • the flip chip connection terminal 26 is formed by the embedded circuit whose upper surface is exposed on the surface of the insulating layer 3, the adhesion is ensured even if it is fine. It becomes possible. Therefore, it is not necessary to cover and fix the circuit pattern extended on both sides in the longitudinal direction of the flip chip connection terminal 26 with the solder resist 4 and fix the tip of the flip chip connection terminal 26 to the opening 31 of the solder resist 4. Can be formed inside. Therefore, since the flip chip connection terminal 26 can be miniaturized without being limited by the resolution of the solder resist 4, it is possible to achieve higher density and to improve the degree of freedom of circuit pattern design. .
  • the package substrate of the present invention As a sixth example of the package substrate of the present invention, as shown in FIG. 4, there is one provided with embedded circuits 2 extending on both sides or one side of the flip chip connection terminal 26 in the longitudinal direction.
  • the flip chip connection terminal 26 can be miniaturized without being limited by the resolution of the solder resist 4, so that higher density can be achieved. It is possible to increase the degree of freedom of circuit pattern design.
  • a part of the flip chip connection terminal 26 has a portion 33 extended in the short direction (width direction).
  • the tip of the flip chip connection terminal 26 may be formed in the opening 31 of the solder resist 4.
  • the preliminary solder is omitted. Since the flip chip connection terminal 26 has a portion 33 that is partially expanded in the short direction (width direction), the contact area with the insulating layer 3 is increased. Therefore, the flip chip connection terminal 26, the insulating layer 3, The amount of the preliminary solder 19 can be secured more, and the preliminary solder 19 in the portion 33 expanded in the short side direction (width direction) is affected by the surface tension. Since the solder pool is formed by pulling the solder of other parts, the solder pool can be stably formed at a predetermined position.
  • a semiconductor element 15 mounted on the package substrate 1 of the above first to seventh examples by flip-chip connection can be mentioned.
  • the underfill material 23 is preferably filled between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26 of the package substrate 1 for mounting the semiconductor element. According to this, it becomes possible for the underfill material 23 to further strengthen the adhesion between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26. Therefore, it is possible to provide the semiconductor package 24 that can cope with high density and has excellent reliability.
  • a multilayer metal foil 9 in which a first carrier metal foil 10, a second carrier metal foil 11, and a base metal foil 12 are laminated in this order is prepared.
  • the first carrier metal foil 10 is for protecting the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) and physically peels from the second carrier metal foil 11. It is possible.
  • the material and thickness are not particularly limited as long as the surface of the second carrier metal foil 11 can be protected. However, from the viewpoint of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is preferably 1 to 35 ⁇ m.
  • a peeling layer (not shown) for stabilizing the peeling strength between the first carrier metal foil 10 and the second carrier metal foil 11 as the peeling layer. are preferably those that have a stable peel strength even if they are heated and pressurized a plurality of times when laminated with an insulating resin.
  • Examples of such a release layer include those in which a metal oxide layer and an organic agent layer disclosed in JP-A-2003-181970 are formed, and Cu—Ni—Mo alloys disclosed in JP-A-2003-094553. And those containing a metal oxide of Ni and W or a metal oxide of Ni and Mo shown in re-published patent WO2006 / 013735.
  • the peel layer is peeled off while being attached to the first carrier metal foil 10 side. What does not remain on the surface of the carrier metal foil 11 is desirable.
  • the second carrier metal foil 11 serves as a seed layer (feeding layer) for supplying a current to perform the first pattern plating 13 on the surface after the first carrier metal foil 10 is peeled off. It can be physically peeled between the metal foil 10 and the base metal foil 12. It only needs to function as a power feeding layer together with the base metal foil 12, and the material and thickness are not particularly limited. However, from the viewpoint of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is 1 to 18 ⁇ m. Can be used. However, as will be described later, when the outer layer circuit 2 is formed (FIGS. 16 (12), (13), and (14)), it is removed by etching.
  • an ultrathin metal foil of 1 to 5 ⁇ m is preferable.
  • a release layer (not shown) as described above is provided between the first carrier metal foil 10 and the base metal foil 12 in order to stabilize the peel strength between them.
  • the release layer is preferably conductive so that the second carrier metal foil 11 and the base metal foil 12 are integrated to act as a seed layer.
  • this peeling layer physically peels between the 2nd carrier metal foil 11 and the base metal foil 12, it peels in the state adhering to the base metal foil 12 side, and the 2nd carrier metal foil 11 Those that do not remain on the surface are desirable.
  • the base metal foil 12 is positioned on the side laminated with the base material 16 when the multilayer metal foil 9 is laminated with the base material 16 to produce the core substrate 17. It can be physically peeled between.
  • the material and the thickness are not particularly limited as long as they have adhesiveness with the base material 16, but the material is copper foil or aluminum foil in terms of versatility and handleability.
  • the thickness is preferably 9 to 70 ⁇ m.
  • between the 2nd carrier metal foil 11 it is preferable to provide the above peeling layers (not shown).
  • this peeling layer physically peels between the 2nd carrier metal foil 11 and the base metal foil 12, it peels in the state adhering to the base metal foil 12 side, and the 2nd carrier metal foil 11 Those that do not remain on the surface are desirable.
  • the multilayer metal foil 9 is a multilayer metal foil 9 having three or more layers of metal foils (for example, as described above, the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12), Physical separation between at least two locations (for example, as described above, between the first carrier metal foil 10 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the base metal foil 12) Use what is possible.
  • foreign matter such as resin powder may adhere to the surface of the first carrier metal foil 10.
  • the second carrier metal that is not affected by foreign matters such as resin powder is obtained by physically peeling the first carrier metal foil 10 from the second carrier metal foil 11. Since the surface of the foil 11 is formed, a high-quality metal foil surface can be secured. Therefore, even when the first pattern plating 13 is performed using the second carrier metal foil 11 as a seed layer, the occurrence of defects can be suppressed, so that the yield can be improved.
  • the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 are laminated to form a core substrate 17.
  • the base material 16 is laminated and integrated with the multilayer metal foil 9 to form the core substrate 17.
  • the base material 16 is generally used as the insulating layer 3 of the semiconductor element mounting package substrate 1. Can be used. Examples of the substrate 16 include glass epoxy and glass polyimide.
  • the core substrate 17 serves as a support substrate when the package substrate 1 is manufactured using the multilayer metal foil 9. By ensuring rigidity, workability is improved and damage during handling is prevented. The main role is to improve the yield. For this reason, it is desirable that the substrate 16 has a reinforcing material such as glass fiber.
  • the first carrier metal foil 10 is physically peeled between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9.
  • the first carrier metal foil 10 On the surface of the first carrier metal foil 10, there may be a case where foreign matters such as resin powder from a prepreg or the like that becomes a material of the base material 16 at the time of lamination adhere.
  • foreign matter such as resin powder adhered to the surface may cause defects such as disconnection or short circuit in the circuit, leading to a decrease in yield. there is a possibility.
  • the first carrier metal foil 10 is peeled and removed in this way, a circuit can be formed using the second carrier metal foil 11 to which no foreign matter such as resin powder adheres.
  • the occurrence of defects can be suppressed, and the yield can be improved.
  • the peeling work can be easily performed by adjusting the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. Can do.
  • the release layer (not shown) between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9 moves to the first carrier metal foil 10 side.
  • the peel strength between the second carrier metal foil 11 and the base metal foil 12 is greater than the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. It is desirable that the multilayer metal foil 9 be formed. This suppresses simultaneous peeling between the second carrier metal foil 11 and the base metal foil 12 when physically peeling between the first carrier metal foil 10 and the second carrier metal foil 11. be able to.
  • the peel strength is 2 N / m to 50 N / m between the first carrier metal foil 10 and the second carrier metal foil 11 in the initial stage before heating and pressing, and the second carrier metal foil 11 and the base metal foil 12.
  • the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11 is the peel strength between the second carrier metal foil 11 and the base metal foil 12.
  • the strength When the strength is made 5N / m to 20N / m smaller than the strength, it will not be peeled off during handling in the manufacturing process, but on the other hand, it is easy to peel off, and when the first carrier metal foil 10 is peeled off. Since the second carrier metal foil 11 can be prevented from peeling off at the same time, workability is good.
  • the adjustment of the peel strength is performed by using the second carrier metal foil 11 serving as the base of the release layer. It becomes possible by adjusting the roughness of the surface (between the first carrier metal foil 10) and adjusting the plating solution composition and conditions for forming a metal oxide or alloy plating layer to be a release layer. .
  • the first pattern plating 13 is performed on the second carrier metal foil 11 remaining on the core substrate 17.
  • the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) does not adhere to foreign matters such as resin powder from the prepreg used at the time of lamination, so the circuit resulting from this Defects can be suppressed.
  • the first pattern plating 13 can be performed using electroplating after forming a plating resist (not shown) on the second carrier metal foil 11.
  • a plating resist a photosensitive resist used in the manufacturing process of the package substrate 1 can be used.
  • electroplating copper sulfate plating used in the manufacturing process of the package substrate 1 can be used.
  • the multilayer metal foil 9 is formed on the surface of the second carrier metal foil 11 provided with irregularities having an average roughness (Ra) of 0.3 ⁇ m to 1.2 ⁇ m in advance via a release layer (not shown).
  • Ra average roughness
  • a multilayer metal foil 9 in which the foil 10 is laminated is desirable.
  • the surface of the second carrier metal foil 11 after physically peeling the first carrier metal foil 10 together with the release layer has irregularities with an average roughness (Ra) provided in advance of 0.3 ⁇ m to 1.2 ⁇ m.
  • Ra average roughness
  • the surface roughness of the irregularities provided on the surface of the second carrier metal foil 11 has an average roughness (Ra) of 0.3 to 1.2 ⁇ m, while improving the adhesion and resolution of the plating resist. It is desirable in that the peelability after the pattern plating 13 of 1 can be secured.
  • the average roughness (Ra) is less than 0.3 ⁇ m, the adhesion of the plating resist tends to be insufficient, and when the average roughness (Ra) exceeds 1.2 ⁇ m, the plating resist becomes difficult to follow and the adhesion is insufficient. Tend to occur.
  • the average roughness (Ra) is desirably 0.5 ⁇ m to 0.9 ⁇ m.
  • the average roughness (Ra) is an average roughness (Ra) defined by JIS B 0601 (2001), and can be measured using a stylus type surface roughness meter or the like.
  • adjustment of average roughness (Ra) is the composition (additive etc.) of the electro copper plating at the time of forming the copper foil as the 2nd carrier metal foil 11 if the 2nd carrier metal foil 11 is a copper foil. Including) and adjusting the conditions.
  • the insulating layer 3 is laminated on the second carrier metal foil 11 including the first pattern plating 13 to form a laminate 22.
  • the insulating layer 3 one generally used as the insulating layer 3 of the package substrate 1 can be used.
  • the insulating layer 3 include an epoxy resin and a polyimide resin.
  • an epoxy or polyimide adhesive sheet, a glass epoxy or a glass polyimide prepreg is heated and heated using a hot press or the like. It can be formed by pressing and laminating and integrating.
  • the laminated body 22 refers to one laminated on the second carrier metal foil 11 including the first pattern plating 13 among those laminated and integrated.
  • this conductor layer 20 is also included.
  • the inner layer circuit 6 is formed by the conductor layer 20 or the interlayer connection 5 for connecting the conductor layer 20 is formed, the inner layer circuit 6 and the interlayer connection 5 are also included.
  • the interlayer connection hole 21 may be formed to form the interlayer connection 5 and the inner layer circuit 6.
  • the interlayer connection 5 can be formed, for example, by forming the interlayer connection hole 21 by using a so-called conformal method and then plating the interlayer connection hole 21.
  • electroless copper plating, electrolytic copper plating, filled via plating, or the like can be used as the thick plating after thin electroless copper plating is performed as the base plating.
  • the inner layer circuit 6 can be formed, for example, by plating the interlayer connection hole 21 and then removing the unnecessary conductor layer 20 by etching.
  • the insulating layer 3 and the conductor layer 20 are further formed on the inner layer circuit 6 and the interlayer connection 5,
  • the inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 can be formed so as to have a desired number of layers.
  • the inner layer circuit 6 and the outer layer circuits 2 and 7 may be collectively referred to as a conductor circuit.
  • the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11. Exfoliate and separate.
  • the release layer (not shown) between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9 is moved to the base metal foil 12 side.
  • the surface of the second carrier metal foil 11 is exposed on the laminated body 22 side after the base metal foil 12 is peeled off, so that the etching of the second carrier metal foil 11 performed in a later step is hindered by the peel layer. It will not be done.
  • an etching resist 34 is formed on the second carrier metal foil 11 of the laminated body 22 that has been separated and peeled to form the second carrier metal foil of the laminated body 22.
  • 11 is exposed to expose the first pattern plating 13 on the surface of the insulating layer 3 to form the embedded circuit 2, or the three-dimensional circuit 27 is formed on the first pattern plating 13 or on the insulating layer 3.
  • the second pattern plating 14 was performed on the second carrier metal foil 11 of the laminate 22 separated and peeled, and the second pattern plating was performed.
  • Etching is performed by forming an etching resist on the carrier metal foil other than the portion, and etching is performed to remove the second carrier metal foil 11 other than the portion where the second pattern plating 14 is formed and the portion where the etching resist is formed.
  • the embedded circuit 2 can be formed by exposing the first pattern plating 13 to the surface of the insulating layer 3, or the three-dimensional circuit 27 can be formed on the first pattern plating 13 or the insulating layer 3.
  • 16 (12) to (14) and FIGS. 17 (12) to (14) show only the lower part of the stacked body 22 separated as shown in FIG. 15 (11). In the embedded circuit 2 formed by exposing the first pattern plating 13 from the insulating layer 3 by the steps of FIGS. 16 (12) to (14) or FIGS.
  • flip-chip connection terminals are stacked.
  • the three-dimensional circuit 27 formed on the first pattern plating on the surface of the body can form bumps and pillars, and the three-dimensional circuit 27 formed on the insulating layer on the surface of the laminated body can form dummy terminals.
  • the outer layer circuit 2 formed in the present invention is embedded in the insulating layer 3, not only the bottom surface of the outer layer circuit 2 but also the side surfaces on both sides are in close contact with the insulating layer 3, so that the fine circuit Even so, sufficient adhesion can be ensured.
  • the second carrier metal foil 11 can be removed even with a slight etching amount, so that it is embedded in the insulating layer 3.
  • the surface of the outer layer circuit 2 exposed from the insulating layer 3 is flat, and by using a wire bonding terminal or a flip chip connection terminal, connection reliability can be ensured and used as a connection terminal with a semiconductor element.
  • connection terminal with the semiconductor element can be provided in the outer layer circuit 2 at a position overlapping the interlayer connection 5 in plan view, the connection terminal with the semiconductor element is provided directly above or immediately below the interlayer connection 5. It is possible to cope with downsizing and high density. Furthermore, it is possible to form various conductor circuit configurations such as bumps, pillars, dummy terminals, etc. by forming the three-dimensional circuit 27 at an arbitrary location, and the thickness of the second carrier metal foil 11 or the second pattern plating 14 can be reduced. By changing, it can be formed at an arbitrary height, so that it can correspond to various semiconductor elements (not shown) and connection forms with other package substrates. For example, as shown in FIG.
  • a three-dimensional circuit 27 is provided on the first pattern plating 13 of the package substrate 1 of the present invention to form pillars and connect to the top substrate, thereby forming the cavity. Even if it is not provided, PoP can be configured.
  • the semiconductor element 35 is mounted on the semiconductor element during flip chip connection.
  • the central portion of the semiconductor element 35 is easily bent and deformed, but by providing dummy terminals (in FIG. 18, the three-dimensional circuit 27 formed on the insulating layer). Since the lower surface of the semiconductor element 35 can be supported, deformation can be suppressed.
  • the dummy terminal is formed so as to be connected to the first pattern plating or the interlayer connection 5, the heat from the semiconductor element 35 can be radiated. For this reason, reliability can be improved.
  • the dummy terminal is electrically independent and does not function as an electric circuit.
  • the dummy terminal is formed on the insulating layer. It may be connected to pattern plating or interlayer connection 5.
  • solder resist 4 and protective plating 8 may be formed as necessary.
  • the protective plating 8 nickel plating and gold plating which are generally used as protective plating for connection terminals of the package substrate are desirable.
  • a package substrate having a flat and fine embedded circuit at a position overlapping with an interlayer connection, which is suitable for wire bonding and flip chip connection.
  • a package substrate can be formed.
  • a package substrate having various metal structures such as bumps and pillars can be formed by forming a three-dimensional circuit at an arbitrary location.
  • Example 1 First, as shown in FIG. 10, a multilayer metal foil 9 in which a first carrier metal foil 10, a second carrier metal foil 11, and a base metal foil 12 were laminated in this order was prepared.
  • the first carrier metal foil 10 is a 9 ⁇ m copper foil
  • the second carrier metal foil 11 is a 3 ⁇ m ultrathin copper foil
  • the base metal foil 12 is an 18 ⁇ m copper foil.
  • a release layer (not shown) was provided on the surface of the base metal foil 12 (between the second carrier metal foil 11) so that physical peeling was possible. Further, the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) was previously provided with irregularities having an average roughness (Ra) of 0.7 ⁇ m.
  • a release layer (not shown) was provided on the unevenness, that is, between the first carrier metal foil 10 so as to allow physical peeling.
  • the release layers between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni 30 g / L, Mo 3.0 g / L, It formed by forming a metal oxide layer using the plating bath which has a composition of acid 30g / L.
  • the peel strength was adjusted by adjusting the amount of metal oxide forming the peel layer by adjusting the current.
  • the peel strength at this time was 47 N / m between the base metal foil 12 and the second carrier metal foil 11, and 29 N / m between the second carrier metal foil 11 and the first carrier metal foil 10. Note that the rate of change in peel strength after heating and pressing (after forming the core substrate 17 by laminating the prepreg serving as the base material 16) was about 10% higher than the initial level.
  • the multilayer metal foil 9 shown in FIG. 10 was produced as follows. (1) As the base metal foil 12, an electrolytic copper foil having a thickness of 18 ⁇ m was used, immersed in sulfuric acid 30 g / L for 60 seconds, washed with acid and then washed with running water for 30 seconds.
  • Nickel sulfate 6 as a plating bath containing Ni (nickel), Mo (molybdenum), and citric acid as a cathode, using a washed electrolytic copper foil as a cathode, a Ti (titanium) electrode plate coated with iridium oxide as an anode Hydration of electrolytic copper foil in a bath of 30 g / L hydrate, 3.0 g / L sodium molybdate dihydrate, 30 g / L trisodium citrate dihydrate, pH 6.0, liquid temperature 30 ° C.
  • Electrolytic treatment was performed on the surface at a current density of 20 A / dm 2 for 5 seconds to form a release layer (not shown) containing a metal oxide composed of nickel and molybdenum.
  • electrolytic plating was performed at a current density of 4 A / dm 2 for 200 seconds to form a metal layer to be the second carrier metal foil 11 having a thickness of 3 ⁇ m.
  • the surface after forming the metal layer to be the second carrier metal foil 11 is subjected to electrolytic treatment at a current density of 10 A / dm 2 for 10 seconds using the same bath as in the above (2), from nickel and molybdenum.
  • a release layer (not shown) containing a metal oxide was formed.
  • the surface after forming the release layer 13 is subjected to electrolytic plating at a current density of 4 A / dm 2 for 600 seconds using the same bath as the above (3), and the first carrier metal foil 10 having a thickness of 9 ⁇ m A metal layer was formed.
  • Granular roughened particles were formed on the surface in contact with the substrate 16 by copper sulfate plating, and subjected to chromate treatment and silane coupling agent treatment. Further, the chromate treatment was applied to the surface not in contact with the substrate 16.
  • the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 were laminated to form a core substrate 17.
  • a glass epoxy prepreg was used as the substrate 16, and the multilayer metal foils 9 were stacked on both upper and lower sides of the prepreg, and were laminated and integrated by heating and pressing using a hot press.
  • the first carrier metal foil 10 was physically peeled between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9.
  • the first pattern plating 13 was performed on the second carrier metal foil 11 remaining on the core substrate 17.
  • the first pattern plating 13 was formed using copper sulfate electroplating after forming a photosensitive plating resist on the second carrier metal foil 11.
  • a copper foil (12 ⁇ m) is laminated as the insulating layer 3 and the conductor layer 20 on the second carrier metal foil 11 including the first pattern plating 13 to form a laminate 22.
  • the insulating layer 3 was formed by laminating and integrating an epoxy adhesive sheet by heating and pressing using a hot press.
  • the interlayer connection 5 was formed by forming the interlayer connection hole 21 using a conformal method and then plating the interior of the interlayer connection hole 21. In this plating, thin electroless copper plating was performed as a base plating, a photosensitive plating resist was formed, and thick plating was performed by copper sulfate electroplating. Thereafter, the inner layer circuit 6 was formed by removing the unnecessary conductor layer 20 by etching.
  • the insulating layer 3 and the conductor layer 20 are further formed on the inner layer circuit 6 and the interlayer connection 5,
  • the inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 were formed to form a laminate 22 having four conductor layers 20.
  • the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11. Peeled off and separated.
  • an etching resist 14 is formed on the second carrier metal foil 11 of the laminated body 22 that has been separated and peeled, and the second carrier metal foil of the laminated body 22 is formed.
  • 11 is etched to expose the first pattern plating 13 on the surface of the insulating layer 3 to form the embedded circuit 2 and to form the three-dimensional circuit 27 on the first pattern plating 13 or on the insulating layer 3. did.
  • the embedded circuit 2 formed by exposing the first pattern plating 13 from the insulating layer 3 is a flip chip connection terminal
  • the three-dimensional circuit 27 formed on the first pattern plating on the surface of the laminate is a bump
  • the laminate The solid circuit 27 formed on the insulating layer on the surface was a dummy terminal.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). )
  • the amount of metal oxide forming the release layer is adjusted and changed. It was.
  • the peel strength at this time was 23 N / m between the base metal foil 12 and the second carrier metal foil 11, and 18 N / m between the second carrier metal foil 11 and the first carrier metal foil 10.
  • a package substrate was fabricated in the same manner as in Example 1 except for this.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). )
  • the amount of metal oxide forming the release layer is adjusted and changed. It was.
  • the peel strength at this time was 15 N / m between the base metal foil 12 and the second carrier metal foil 11, and 2 N / m between the second carrier metal foil 11 and the first carrier metal foil 10.
  • a package substrate was fabricated in the same manner as in Example 1 except for this.
  • Example 4 The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). ) By changing the current when forming the metal oxide layer using a plating bath with a composition of 3.0 g / L and citric acid 30 g / L, the amount of metal oxide forming the release layer is adjusted and changed. It was. The peel strength at this time was 68 N / m between the base metal foil 12 and the second carrier metal foil 11, and 48 N / m between the second carrier metal foil 11 and the first carrier metal foil 10.
  • FIGS. 17 (12) to (14) separation and peeling were performed as shown in FIGS. 17 (12) to (14).
  • the second pattern plating 14 is performed on the second carrier metal foil 11 of the laminated body 22, the etching resist 34 is formed on the carrier metal foil other than the portion where the second pattern plating is performed, and etching is performed.
  • the second carrier metal foil 11 other than the portion where the pattern plating 14 is performed and the portion where the etching resist is formed is removed by etching, and the first pattern plating 13 is exposed on the surface of the insulating layer 3 to form the embedded circuit 2.
  • a three-dimensional circuit 27 was formed on the first pattern plating 13 or the insulating layer 3.
  • the embedded circuit 2 formed by exposing the first pattern plating 13 from the insulating layer 3 is a flip chip connection terminal
  • the three-dimensional circuit 27 formed on the first pattern plating on the surface of the stacked body is a pillar
  • the stacked body The solid circuit 27 formed on the insulating layer on the surface was a dummy terminal.
  • a package substrate was fabricated in the same manner as in Example 1 except for this step.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum).
  • the peel strength at this time was 43 N / m between the base metal foil 12 and the second carrier metal foil 11, and 28 N / m between the second carrier metal foil 11 and the first carrier metal foil 10.
  • a package substrate was fabricated in the same manner as in Example 4 except for this.
  • the peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). )
  • the amount of metal oxide forming the release layer is adjusted and changed. It was.
  • the peel strength at this time was 22 N / m between the base metal foil 12 and the second carrier metal foil 11, and 4 N / m between the second carrier metal foil 11 and the first carrier metal foil 10.
  • a package substrate was fabricated in the same manner as in Example 4 except for this.
  • Table 1 shows the finished state of the outer layer circuit 2 embedded in the insulating layer 3 for Examples 1 to 6, the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11, the second The peel strength between the carrier metal foil 11 and the base metal foil 12 and the presence or absence of peeling of the carrier metal foil during handling are shown.
  • in Table 1 indicates no undercut.
  • no undercut had occurred.
  • the second carrier metal foil 11 is made of ultra-thin copper having a thickness of 3 ⁇ m, it is uniformly removed with a slight etching amount, and the surface irregularities of the outer circuit 2 are flat. . Also, in all of Examples 1 to 6, there is a gap between the first carrier metal foil 10 and the second carrier metal foil 11 or between the second carrier metal foil 11 and the base metal foil 12 by handling in the manufacturing process. There was no peeling (“ ⁇ ” in Table 1 indicates no peeling). Further, when peeling between the first carrier metal foil 10 and the second carrier metal foil 11, there was no peeling between the second carrier metal foil 11 and the base metal foil 12.
  • the bump 25 of the semiconductor element 35 is pressed against the embedded circuit 2 of the package substrate (FIG. 17 (14)) manufactured in the fourth embodiment, and is flip-chip connected using solder (not shown).
  • the bumps 25 are in a peripheral arrangement, but the lower surface of the semiconductor element 35 is supported by the three-dimensional circuit 27 serving as a dummy terminal, so that the semiconductor element 35 is not bent.
  • Measurement of the initial peel strength (N / m) before heating / pressurization (before forming the core substrate 17 by laminating the prepreg to be the base material 16) is made of a multilayer metal foil sample cut to a width of 10 mm. Then, using Tensilon RTM-100 (made by Orientec Co., Ltd., trade name, “Tensilon” is a registered trademark), according to JIS Z 0237 90 degree peeling method, One carrier metal foil was peeled off at a speed of 300 mm / min in the 90 ° direction, and then the second carrier metal foil was peeled off at a speed of 300 mm / min in the 90 ° direction.
  • the peel strength after heating and pressurization (after forming the core substrate 17 by laminating the prepreg as the base material 16) was also measured in the same manner as the initial peel strength, and the rate of change relative to the initial value was obtained.
  • the conditions of the heating and pressurization when laminating the multilayer metal foil 9 and the glass epoxy prepreg serving as the base material 16 to form the core substrate 17 are as follows: a pressure of 3 MPa, a temperature of 175.degree. The time is 1.5 hours (hours).
  • Example 7 In the same manner as in Example 1, a package substrate having a flip chip terminal of an embedded circuit was produced. Here, an opening is provided in the solder resist formed on the package substrate, and an embedded circuit serving as a flip chip connection terminal having a line / space of 20 ⁇ m / 20 ⁇ m (40 ⁇ m pitch) is disposed in the opening. .
  • the dimension in the longitudinal direction of the flip chip connection terminal (the length of the flip chip connection terminal) defined by the opening of the solder resist is about 100 ⁇ m.
  • preliminary solder was formed by printing a solder paste on the embedded circuit to be the flip chip connection terminal and reflowing.
  • Sn (tin) -Ag (silver) -Cu (copper) -based eco-solder M705 (trade name, manufactured by Senju Metal Industry Co., Ltd., Eco-Solder is a registered trademark) is used as a pre-solder solder paste.
  • the reflow was performed using an infrared reflow apparatus at a peak temperature of 260 ° C.
  • the cut package substrate includes an insulating layer 3, an embedded circuit 2 provided so that the upper surface is exposed on the surface of the insulating layer 3, the insulating layer 3 and the embedded substrate
  • the solder resist 4 provided on the circuit 2 and the embedded circuit 2 in the opening 31 provided in the solder resist 4 form the flip chip connection terminal 26.
  • the thickness of the preliminary solder 19 that covers the flip chip connection terminal 26 is 3 to 5 ⁇ m.
  • the thickness of the solder is a solder jist and a flip chip before and after forming the preliminary solder 19 using Hi-Somet (trade name, made by Union Optical Co., Ltd., registered trademark), which is a non-contact level difference measuring machine. It measured by measuring the level
  • Hi-Somet trade name, made by Union Optical Co., Ltd., registered trademark
  • the semiconductor element 15 was mounted by flip chip connection.
  • the flip chip connection is performed by using the flip chip connection terminal 26 on the package substrate 1 and the bump 25 of the semiconductor element 15 (Sn (tin) -3.0 mass% Ag (silver) -0.5 mass% Cu (copper on the copper pillar). ) Solder formed, 40 ⁇ m pitch, 25 ⁇ m height))
  • ultrasonic flip chip bonder SH-50MP product name, manufactured by Altex Co., Ltd.
  • the crimping conditions for flip chip connection were held for 4 seconds while raising the temperature to 230 ° C. and applying 50 g per bump while using ultrasonic waves.
  • an underfill agent 23 was filled between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26 of the package substrate 1 to obtain a semiconductor package 24.
  • Example 8 The thickness of the pre-solder covering the flip chip connection terminal is 7 to 10 ⁇ m.
  • a tenth circuit board and a semiconductor package were obtained in the same manner as in Example 7 except for the above.
  • Example 9 The thickness of the pre-solder covering the flip chip connection terminal is 17 to 20 ⁇ m. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in Example 7.
  • Example 1 The thickness of the pre-solder covering the flip chip connection terminal is 1 to 2 ⁇ m. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in Example 7.
  • Example 10 In the same manner as in Example 7, preliminary solder was formed on the embedded circuit to be the flip chip connection terminal.
  • an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31.
  • a via 18 is connected to the bottom surface of the embedded circuit 2 including the flip chip connection terminal 26.
  • the package substrate and the semiconductor package were formed in the same manner as in Example 7.
  • Example 11 As shown in FIGS. 17 (12) to (14), the second pattern plating 14 is performed on the second carrier metal foil 11 by the same method as that of the fourth embodiment, and the flip chip connection terminal of the embedded circuit is obtained. A convex shape (three-dimensional circuit) was formed in a part of the portion. Solder resist formation and nickel / gold plating (nickel plating and gold plating thereon) were formed as protective plating.
  • an opening 31 is provided in the solder resist 4, and an embedded circuit 2 serving as a flip chip connection terminal 26 is disposed in the opening 31.
  • a convex shape 27 is formed on a part of the flip chip connection terminal 26 in the longitudinal direction, and the height of the convex shape 27 is about 5 ⁇ m.
  • the range of the convex shape 27 is 100% of the dimension in the short direction of the flip chip connection terminal 26 and about 30% of the dimension in the longitudinal direction of the flip chip connection terminal 26.
  • Example 12 In the same manner as in Example 1, a package substrate having flip-chip terminals for embedded circuits was produced. After that, an etching resist was formed, and a recessed shape was formed by etching so that a part of the upper surface of the embedded circuit whose upper surface was exposed was recessed from the surface of the insulating layer and the other part remained as it was. Thereafter, solder resist formation and nickel / gold plating (nickel plating and gold plating thereon) were formed as protective plating.
  • an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31.
  • a concave shape 28 is formed in a part of the flip connection terminal 26 in the longitudinal direction, and the depth of the concave shape 28 is about 5 ⁇ m.
  • the range of the recessed shape 28 is 100% of the dimension in the short direction of the flip chip connection terminal 26 and about 30% of the dimension in the longitudinal direction of the flip chip connection terminal 26.
  • Example 13 In the same manner as in Example 7, a package substrate having flip-chip terminals for embedded circuits was produced. Here, as shown in FIG. 3, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. The tip of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in Example 7.
  • Example 14 In the same manner as in Example 7, a package substrate having flip-chip terminals for embedded circuits was produced. Here, as shown in FIG. 4, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. In addition, the embedded circuit 2 is provided that extends to both sides or one side of the flip chip connection terminal 26 in the longitudinal direction. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in Example 7.
  • Example 15 In the same manner as in Example 7, a package substrate having flip-chip terminals for embedded circuits was produced.
  • an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31.
  • a part of the flip chip connection terminal 26 in the longitudinal direction forms a portion 33 extended in the short direction (width direction). That is, the flip chip connection terminal 26 forms a portion 33 that is partially expanded in the lateral direction (width direction).
  • the package substrate and the semiconductor package were formed in the same manner as in Example 7.
  • Example 2 In the same manner as in Example 7, a package substrate having flip-chip terminals for embedded circuits was produced.
  • a circuit pattern (outer layer) by a convex circuit similar to that shown in FIG. 1 is formed on the surface opposite to the surface on which the flip-chip connection terminals of the embedded circuit 2 are arranged.
  • a circuit 7) is arranged.
  • solder resist formation and nickel / gold plating (nickel plating and gold plating thereon) formation as a protective plating were performed on the circuit pattern (outer layer circuit 7) by this convex circuit.
  • an opening is provided in the solder resist, and a circuit pattern by a convex circuit that is a flip chip connection terminal having a line / space of 20 ⁇ m / 20 ⁇ m (40 ⁇ m pitch) is disposed in the opening.
  • preliminary solder was formed by printing and reflowing a solder paste on a circuit pattern (outer layer circuit 7) by a convex circuit, which becomes a flip chip connection terminal.
  • Sn (tin) -Ag (silver) -Cu (copper) -based eco-solder M705 (trade name, manufactured by Senju Metal Industry Co., Ltd., Eco-Solder is a registered trademark) is used as a pre-solder solder paste.
  • the reflow was performed using an infrared reflow apparatus at a peak temperature of 260 ° C.
  • the package substrate includes an insulating layer 3, a circuit pattern formed by a convex circuit 32 provided on the surface of the insulating layer 3, and a circuit pattern formed on the insulating layer 3 and the convex circuit 32.
  • the circuit pattern of the convex circuit 32 in the opening 31 provided in the solder resist 4 forms the flip chip connection terminal 26.
  • the thickness of the preliminary solder 19 that covers the flip chip connection terminal 26 is 3 to 5 ⁇ m.
  • Comparative Example 3 The thickness of the pre-solder covering the flip chip connection terminal is 17 to 20 ⁇ m. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in Comparative Example 3.
  • Table 2 shows the results of examining the cross-sectional shape of the flip chip connection terminal, the solder thickness, and the presence or absence of a solder bridge for the package substrates of Examples 7 to 15, Reference Example 1, and Comparative Examples 1 to 3. Also, the results of examining the state of the solder fillet in the semiconductor packages of Examples 7 to 15, Reference Example 1 and Comparative Examples 1 to 3 are shown.
  • the solder thickness was 3 to 20 ⁇ m, and from the confirmation result of the solder bridge, no solder bridge was generated within this solder thickness range.
  • the solder thickness was as thin as 1 to 2 ⁇ m, and no solder bridge was generated.
  • the solder thickness was as thick as 25 to 28 ⁇ m, and a solder bridge was generated between adjacent flip chip connection terminals.
  • the thickness of the solder was 17 to 20 ⁇ m, but because it was a convex circuit, the solder wraps around the side surface of the flip chip connection terminal, and a solder bridge occurred.
  • the solder fillet formed between the bumps of the semiconductor element is the bump of the semiconductor element and the flip chip of the package substrate.
  • the solder was wet and spread on both of the connection terminals, and the state was good.
  • Comparative Examples 1 and 2 there were portions where the solder wettability was insufficient in some of the bumps of the semiconductor element or the flip chip connection terminals of the package substrate, and the formation of solder fillets was insufficient.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Provided is a method and the like that is for producing a package substrate for mounting a semiconductor element, can support heightened density, and has superior reliability. The method and the like for producing a package substrate for mounting a semiconductor element has: a step for preparing a multi-layer metal foil that laminates a first carrier metal foil, a second carrier metal foil, and a base metal foil, and forming a core substrate by laminating the multi-layer metal foil to a substrate ; a step for physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multi-layer metal foil; a step for performing a first pattern plating on the second carrier metal foil; a step for forming a laminate by forming an insulating layer, a conductive circuit, and an interlayer connection on the first pattern plating; a step for peeling the laminate together with the carrier metal foil from the core substrate; and a step for forming a 3D circuit or an embedded circuit by means of etching.

Description

半導体素子搭載用パッケージ基板の製造方法、半導体素子搭載用パッケージ基板及び半導体パッケージManufacturing method of semiconductor device mounting package substrate, semiconductor device mounting package substrate, and semiconductor package
 本発明は、高密度化が可能な半導体素子搭載用パッケージ基板の製造方法、半導体素子搭載用パッケージ基板及び半導体パッケージに関し、より詳細には、バンプを有する半導体素子と接続するフリップチップ接続端子を備えた半導体素子搭載用パッケージ基板の製造方法、半導体素子搭載用パッケージ基板及び半導体パッケージに関する。 The present invention relates to a method for manufacturing a package substrate for mounting a semiconductor element capable of increasing the density, a package substrate for mounting a semiconductor element, and a semiconductor package, and more particularly, includes a flip chip connection terminal for connecting to a semiconductor element having bumps. The present invention relates to a semiconductor device mounting package substrate manufacturing method, a semiconductor device mounting package substrate, and a semiconductor package.
 半導体素子と半導体素子搭載用パッケージ基板(以下、「半導体素子搭載用パッケージ基板」を「パッケージ基板」ということがある。)の接続端子を電気的に接続する方法として、フリップチップ接続が用いられている。このフリップチップ接続では、半導体素子のバンプとの間に良好なはんだフィレットを形成する目的で、パッケージ基板のフリップチップ接続端子上に予備はんだを形成し、この予備はんだと半導体素子のバンプに形成されたはんだの両者によってはんだ量を確保して半導体素子に設けたバンプと接続する方法が用いられることが多い。一方で、電子部品の小型化や高密度化に伴い、半導体素子との接続端子を高密度に配置する必要が生じており、フリップチップ接続端子の微細化が要求されている。 As a method of electrically connecting the connection terminals of a semiconductor element and a semiconductor element mounting package substrate (hereinafter, “semiconductor element mounting package substrate” may be referred to as “package substrate”), flip-chip connection is used. Yes. In this flip chip connection, a preliminary solder is formed on the flip chip connection terminal of the package substrate for the purpose of forming a good solder fillet between the bump of the semiconductor element, and the preliminary solder and the bump of the semiconductor element are formed. In many cases, a method is used in which the amount of solder is secured by both solders and connected to bumps provided on a semiconductor element. On the other hand, along with miniaturization and high density of electronic components, it is necessary to arrange connection terminals with semiconductor elements at high density, and miniaturization of flip chip connection terminals is required.
 フリップチップ接続端子が微細化すると、予備はんだが形成される接続端子の面積が減少するため、フリップチップ接続端子上に形成される予備はんだの量も減少する結果、半導体素子のバンプとの間に形成されるはんだフィレットの形成が不十分になり、接続信頼性が低下する問題がある。また、微細なフリップチップ接続端子上に、半導体素子との接続に十分な量の予備はんだを形成しようとすると、図1に示すように、一般的な製法では、フリップチップ接続端子26は、パッケージ基板の表面に対して凸状に形成されているので、予備はんだ19がフリップチップ接続端子26の側面に回り込み、隣接するフリップチップ接続端子26との間で予備はんだ19のブリッジを生じる問題がある。つまり、予備はんだ19をフリップチップ接続端子26上に形成するためのはんだを供給しても、かなりの割合のはんだがフリップチップ接続端子26の側面を覆うために使われてしまい、接続に必要なはんだフィレットを形成するために使用できる予備はんだ19の割合が減少してしまうばかりか、隣接するフリップチップ接続端子26とブリッジを生じてしまうのである。 When the flip chip connection terminal is miniaturized, the area of the connection terminal on which the preliminary solder is formed is reduced, so that the amount of the preliminary solder formed on the flip chip connection terminal is also reduced. There is a problem that the formation of the solder fillet to be formed becomes insufficient and the connection reliability is lowered. Further, when an amount of preliminary solder sufficient for connection to a semiconductor element is formed on a fine flip chip connection terminal, as shown in FIG. 1, in a general manufacturing method, the flip chip connection terminal 26 is a package. Since it is formed in a convex shape with respect to the surface of the substrate, there is a problem in that the preliminary solder 19 wraps around the side surface of the flip chip connection terminal 26 and bridges the preliminary solder 19 between the adjacent flip chip connection terminals 26. . That is, even if the solder for forming the preliminary solder 19 on the flip chip connection terminal 26 is supplied, a considerable proportion of the solder is used to cover the side surface of the flip chip connection terminal 26 and is necessary for the connection. This not only reduces the proportion of the pre-solder 19 that can be used to form the solder fillet, but also creates a bridge with the adjacent flip chip connection terminal 26.
 このような問題を改善する方法として、パッケージ基板上のフリップチップ接続端子となる領域の配線パターンを比較的長く形成して、この領域のはんだ量を増加させる方法(特許文献1)や、フリップチップ接続端子となる領域の配線パターンの幅を他の領域に比べて部分的に幅広にすることにより、フリップチップ接続端子上の予備はんだ量を増加させる方法(特許文献2)が開示されている。 As a method for solving such a problem, a method of increasing the amount of solder in this region by forming a wiring pattern in a region to be a flip chip connection terminal on a package substrate relatively long, and flip chip A method (Patent Document 2) is disclosed in which the amount of preliminary solder on a flip chip connection terminal is increased by partially increasing the width of a wiring pattern in a region to be a connection terminal as compared with other regions.
特開2002-329744号公報JP 2002-329744 A 特開2005-101137号公報JP 2005-101137 A
 上記の特許文献1、2の方法によると、半導体素子との接続のためのフリップチップ接続端子上の予備はんだの量はある程度確保できる。しかし、図1に示すように、フリップチップ接続端子26を形成する回路パターンは、パッケージ基板1の表面から凸状に形成されている回路パターン(以下、「凸状回路」ということがある。)であり、パッケージ基板1の絶縁層3の表面と密着しているのは、この凸状回路32の底面のみである。しかも、この凸状回路32は、一般に、セミアディティブ法などのエッチングを伴う方法で形成されるため、いわゆるアンダーカットが生じてしまい、その結果、回路パターンの幅がトップ(表面側)よりも厚み方向の途中やボトム(底面側)で狭くなる。このため、フリップチップ接続端子26が微細化すると、フリップチップ接続端子26とその下の絶縁層3との密着面積の減少や回路パターンの幅の減少によって密着力が低下し、フリップチップ接続の際にわずかな外力が加わるだけで、フリップチップ接続端子26の剥れが生じる可能性がある。 According to the methods of Patent Documents 1 and 2 above, the amount of preliminary solder on the flip chip connection terminal for connection to the semiconductor element can be secured to some extent. However, as shown in FIG. 1, the circuit pattern forming the flip chip connection terminal 26 is a circuit pattern formed in a convex shape from the surface of the package substrate 1 (hereinafter, sometimes referred to as a “convex circuit”). Only the bottom surface of the convex circuit 32 is in close contact with the surface of the insulating layer 3 of the package substrate 1. In addition, since the convex circuit 32 is generally formed by a method involving etching such as a semi-additive method, so-called undercut occurs, and as a result, the width of the circuit pattern is thicker than the top (surface side). Narrows in the middle of the direction and at the bottom (bottom side). For this reason, when the flip chip connection terminal 26 is miniaturized, the contact force is reduced due to a decrease in the contact area between the flip chip connection terminal 26 and the insulating layer 3 below and the width of the circuit pattern. There is a possibility that the flip chip connection terminal 26 may be peeled off only by applying a slight external force.
 本発明は、上記問題点に鑑みなされたものであり、微細であっても密着力を確保したフリップチップ接続端子が形成可能であり、かつ半導体素子のバンプとのフリップチップ接続に必要な予備はんだ量を確保したフリップチップ接続端子を備えることにより、高密度化に対応可能で信頼性にも優れた半導体素子搭載用パッケージ基板の製造方法、半導体素子搭載用パッケージ基板及び半導体パッケージを提供することを目的とする。 The present invention has been made in view of the above-described problems, and can form a flip chip connection terminal that secures an adhesive force even if it is fine, and a preliminary solder necessary for flip chip connection with a bump of a semiconductor element. To provide a semiconductor device mounting package substrate, a semiconductor device mounting package substrate, and a semiconductor package that can cope with high density and have high reliability by providing flip chip connection terminals with sufficient amount. Objective.
 本発明は、以下のものに関する。
1. 第1キャリア金属箔と第2キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、前記多層金属箔の第1キャリア金属箔と第2キャリア金属箔との間で、第1キャリア金属箔を物理的に剥離する工程と、前記コア基板の第2キャリア金属箔上に第1のパターンめっきを行う工程と、前記第1のパターンめっきを含む第2キャリア金属箔上に絶縁層と導体回路と層間接続とを形成して積層体を形成する工程と、前記多層金属箔の第2キャリア金属箔とベース金属箔との間で、前記積層体を第2キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、前記剥離した積層体の第2キャリア金属箔上にエッチングレジストを形成してエッチングを行うことにより、前記積層体表面の絶縁層から第1のパターンめっきを露出させて埋め込み回路を形成する工程、または前記積層体表面の第1のパターンめっき上に立体回路を形成する工程、または前記積層体表面の絶縁層上に立体回路を形成する工程、または前記積層体表面の第1のパターンめっき上に凹み形状を形成する工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
2. 第1キャリア金属箔と第2キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、前記多層金属箔の第1キャリア金属箔と第2キャリア金属箔との間で、第1キャリア金属箔を物理的に剥離する工程と、前記コア基板の第2キャリア金属箔上に第1のパターンめっきを行う工程と、前記第1のパターンめっきを含む第2キャリア金属箔上に絶縁層と導体回路と層間接続とを形成して積層体を形成する工程と、前記多層金属箔の第2キャリア金属箔とベース金属箔との間で、前記積層体を第2キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、前記剥離した積層体の第2キャリア金属箔上に第2のパターンめっきを行う工程と、前記第2のパターンめっきを行った部分以外の第2キャリア金属箔上にエッチングレジストを形成してエッチングを行い、前記第2のパターンめっきを行った部分及びエッチングレジストを形成した部分以外の第2キャリア金属箔をエッチングにより除去することにより、前記積層体表面の絶縁層から第1のパターンめっきを露出させて埋め込み回路を形成する工程、または前記積層体表面の第1のパターンめっき上に立体回路を形成する工程、または前記積層体表面の絶縁層上に立体回路を形成する工程、または前記積層体表面の第1のパターンめっき上に凹み形状を形成する工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
3. 項1または2において、第1のパターンめっきを含む第2キャリア金属箔上に絶縁層と導体回路と層間接続とを形成して積層体を形成する工程と、多層金属箔の第2キャリア金属箔とベース金属箔との間で、前記積層体を第2キャリア金属箔とともにコア基板から物理的に剥離して分離する工程との間に、所望の層数の絶縁層と導体回路とを形成する工程を有する半導体素子搭載用パッケージ基板の製造方法。
4. 項1から3の何れかにおいて、積層体表面の絶縁層から第1のパターンめっきを露出させて埋め込み回路を形成する工程ではフリップチップ接続端子を、積層体表面の第1のパターンめっき上に立体回路を形成する工程ではピラーまたはフリップチップ接続端子の長手方向の一部に凸形状を、積層体表面の絶縁層上に立体回路を形成する工程ではダミー端子を形成する半導体搭載用パッケージ基板の製造方法。
5. 項1から4の何れかの半導体搭載用パッケージ基板の製造方法によって製造される半導体素子搭載用パッケージ基板であって、絶縁層と、この絶縁層の表面に上面が露出するように設けられた埋込回路と、前記絶縁層上及び埋込回路上に設けられたソルダーレジストとを有し、このソルダーレジストの開口内に配置された埋込回路がフリップチップ接続端子を形成し、このフリップチップ接続端子が厚さ3μm以上の予備はんだによって被覆された半導体素子搭載用パッケージ基板。
6. 項5において、フリップチップ接続端子を形成する埋込回路の底面にビアが接続した半導体素子搭載用パッケージ基板。
7. 項5または6において、フリップチップ接続端子の長手方向の一部に凸形状が形成された半導体素子搭載用パッケージ基板。
8. 項5から7の何れかにおいて、フリップチップ接続端子の長手方向の一部に凹み形状が形成された半導体素子搭載用パッケージ基板。
9. 項5から8の何れかにおいて、フリップチップ接続端子の先端が、ソルダーレジストの開口内に配置された半導体素子搭載用パッケージ基板。
10.項5から9の何れかにおいて、フリップチップ接続端子の長手方向の両側または片側に延長された部分を有する埋込回路が設けられた半導体素子搭載用パッケージ基板。
11. 項5から10の何れかにおいて、フリップチップ接続端子の一部が、短手方向に拡張された半導体素子搭載用パッケージ基板。
12. 項5から11の何れかの半導体素子搭載用パッケージ基板のフリップチップ接続端子上に半導体素子のバンプをフリップチップ接続により搭載した半導体パッケージ。
The present invention relates to the following.
1. A multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. Physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and on the second carrier metal foil of the core substrate Forming a laminated body by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating; and A step of physically peeling and separating the laminate from the core substrate together with the second carrier metal foil between the second carrier metal foil and the base metal foil; and on the second carrier metal foil of the peeled laminate An etching resist is formed on Forming a buried circuit by exposing the first pattern plating from the insulating layer on the surface of the laminate by etching, or forming a three-dimensional circuit on the first pattern plating on the surface of the laminate, Alternatively, a method of manufacturing a package substrate for mounting a semiconductor element, comprising: forming a three-dimensional circuit on the insulating layer on the surface of the stacked body; or forming a recess shape on the first pattern plating on the surface of the stacked body.
2. A multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. Physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil, and on the second carrier metal foil of the core substrate Forming a laminated body by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating; and A step of physically peeling and separating the laminate from the core substrate together with the second carrier metal foil between the second carrier metal foil and the base metal foil; and on the second carrier metal foil of the peeled laminate Second pattern plating is performed on Then, etching is performed by forming an etching resist on the second carrier metal foil other than the portion where the second pattern plating is performed, and the portion other than the portion where the second pattern plating is performed and the portion where the etching resist is formed Removing the second carrier metal foil by etching to expose the first pattern plating from the insulating layer on the surface of the laminated body to form an embedded circuit, or on the first pattern plating on the surface of the laminated body Forming a three-dimensional circuit, or forming a three-dimensional circuit on an insulating layer on the surface of the laminate, or forming a concave shape on the first pattern plating on the surface of the laminate. A method for manufacturing a mounting package substrate.
3. Item 2 or 2 is a step of forming a laminate by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating, and the second carrier metal foil of the multilayer metal foil. Between the base metal foil and the base metal foil, and the step of physically separating the laminate from the core substrate together with the second carrier metal foil, and forming a desired number of insulating layers and conductor circuits A manufacturing method of a package substrate for mounting a semiconductor device, comprising a step.
4). 4. In any one of items 1 to 3, in the step of exposing the first pattern plating from the insulating layer on the surface of the multilayer body to form an embedded circuit, the flip chip connection terminal is three-dimensionally formed on the first pattern plating on the surface of the multilayer body. Manufacture of a package substrate for mounting a semiconductor in which a convex shape is formed in a part of the longitudinal direction of the pillar or flip chip connection terminal in the process of forming a circuit, and a dummy terminal is formed in the process of forming a three-dimensional circuit on the insulating layer on the surface of the laminate Method.
5. A semiconductor device mounting package substrate manufactured by the method for manufacturing a semiconductor mounting package substrate according to any one of Items 1 to 4, wherein the insulating layer and a buried surface provided such that an upper surface is exposed on the surface of the insulating layer. Embedded circuit and a solder resist provided on the insulating layer and the embedded circuit, and the embedded circuit disposed in the opening of the solder resist forms a flip chip connection terminal, and this flip chip connection A package substrate for mounting a semiconductor element, in which terminals are covered with a preliminary solder having a thickness of 3 μm or more.
6). Item 6. The package substrate for mounting a semiconductor element according to Item 5, wherein a via is connected to a bottom surface of the embedded circuit forming the flip chip connection terminal.
7. Item 7. The semiconductor device mounting package substrate according to Item 5 or 6, wherein a convex shape is formed on a part of the flip chip connection terminal in the longitudinal direction.
8). Item 8. The package substrate for mounting a semiconductor element according to any one of Items 5 to 7, wherein a concave shape is formed in a part of the flip chip connection terminal in the longitudinal direction.
9. Item 9. The package board for mounting a semiconductor element according to any one of Items 5 to 8, wherein the tip of the flip chip connection terminal is disposed in the opening of the solder resist.
10. Item 10. The package substrate for mounting a semiconductor element according to any one of Items 5 to 9, wherein an embedded circuit having a portion extended to both sides or one side in the longitudinal direction of the flip chip connection terminal is provided.
11. Item 11. The package board for mounting a semiconductor element according to any one of Items 5 to 10, wherein a part of the flip chip connection terminal is extended in the short direction.
12 Item 12. A semiconductor package in which bumps of a semiconductor element are mounted on a flip chip connection terminal of a package substrate for mounting a semiconductor element according to any one of Items 5 to 11 by flip chip connection.
 本発明によれば、微細であっても密着力を確保したフリップチップ接続端子が形成可能であり、かつ半導体素子のバンプとのフリップチップ接続に必要な予備はんだ量を確保したフリップチップ接続端子を備えることにより、高密度化に対応可能で信頼性にも優れた半導体素子搭載用パッケージ基板の製造方法、半導体素子搭載用パッケージ基板及び半導体パッケージを提供することができる。 According to the present invention, it is possible to form a flip chip connection terminal having a sufficient adhesion even if it is fine, and a flip chip connection terminal having an amount of preliminary solder necessary for flip chip connection with a bump of a semiconductor element. By providing, it is possible to provide a manufacturing method of a package substrate for mounting a semiconductor element, which can cope with high density and excellent in reliability, a package substrate for mounting a semiconductor element, and a semiconductor package.
従来のパッケージ基板のフリップチップ接続端子近傍の(a)平面図、(b)A-A’断面図、(c)B-B’断面図である。(A) Plan view, (b) A-A 'sectional view, (c) B-B' sectional view in the vicinity of a flip chip connection terminal of a conventional package substrate. 本発明のパッケージ基板のフリップチップ接続端子近傍の(a)平面図、(b)A-A’断面図、(c)B-B’断面図である。FIG. 4A is a plan view, FIG. 5B is a cross-sectional view taken along the line A-A ′, and FIG. 5C is a cross-sectional view taken along the line B-B ′. 本発明のパッケージ基板のフリップチップ接続端子近傍の(a)平面図及び(b)A-A’断面図である。FIG. 4A is a plan view and FIG. 5B is a cross-sectional view taken along the line A-A ′ in the vicinity of the flip chip connection terminal of the package substrate of the present invention. 本発明のパッケージ基板のフリップチップ接続端子近傍の(a)平面図、(b)A-A’断面図、(c)B-B’断面図である。FIG. 4A is a plan view, FIG. 5B is a cross-sectional view taken along the line A-A ′, and FIG. 5C is a cross-sectional view taken along the line B-B ′. 本発明のパッケージ基板のフリップチップ接続端子近傍の(a)平面図及び(b)A-A’断面図である。FIG. 4A is a plan view and FIG. 5B is a cross-sectional view taken along the line A-A ′ in the vicinity of the flip chip connection terminal of the package substrate of the present invention. 本発明のパッケージ基板のフリップチップ接続端子近傍の(a)平面図及び(b)A-A’断面図である。FIG. 4A is a plan view and FIG. 5B is a cross-sectional view taken along the line A-A ′ in the vicinity of the flip chip connection terminal of the package substrate of the present invention. 本発明のパッケージ基板のフリップチップ接続端子近傍の(a)平面図及び(b)A-A’断面図である。FIG. 4A is a plan view and FIG. 5B is a cross-sectional view taken along the line A-A ′ in the vicinity of the flip chip connection terminal of the package substrate of the present invention. 本発明のパッケージ基板のフリップチップ接続端子近傍の(a)平面図、(b)A-A’断面図、(c)B-B’断面図である。FIG. 3A is a plan view, FIG. 2B is a cross-sectional view taken along the line A-A ′, and FIG. 本発明のパッケージのフリップチップ接続端子近傍の断面図である。It is sectional drawing of the flip-chip connection terminal vicinity of the package of this invention. 本発明に用いる多層金属箔の断面図である。It is sectional drawing of the multilayer metal foil used for this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法の一部を表すフロー図である。It is a flowchart showing a part of manufacturing method of the package substrate of this invention. 本発明のパッケージ基板の製造方法を用いて作製した半導体パッケージの断面図である。It is sectional drawing of the semiconductor package produced using the manufacturing method of the package substrate of this invention.
 本発明の半導体素子搭載用パッケージ基板の例について、図2~図9を用いて以下に説明する。 An example of a package substrate for mounting a semiconductor element according to the present invention will be described below with reference to FIGS.
 本発明の半導体素子搭載用パッケージ基板(以下、「パッケージ基板」という。)の第1の例としては、図2に示すように、絶縁層3と、この絶縁層3の表面に上面が露出するように設けられた埋込回路2と、前記絶縁層3上及び埋込回路2上に設けられたソルダーレジスト4とを有し、このソルダーレジスト4の開口31内に配置された埋込回路2がフリップチップ接続端子26を形成し、このフリップチップ接続端子26が厚さ3μm以上の予備はんだ19によって被覆された半導体素子搭載用パッケージ基板1が挙げられる。この構成によれば、フリップチップ接続端子26が、絶縁層3の表面に上面が露出した埋込回路2によって形成される。このため、フリップチップ接続端子26の側面と底面が絶縁層3に埋め込まれて固定されるので、フリップチップ接続端子26を形成する埋込回路2が、ライン/スペースが20μm/20μm以下レベルの微細な回路パターンであっても、絶縁層3との密着力を確保したフリップチップ接続端子26が形成可能になる。フリップチップ接続端子26の長手方向の両側に延長された埋込回路2を有する方が、フリップチップ接続端子26を埋込回路2が両側からも固定することになるため、密着力の確保の観点からは望ましいが、本発明においては、図1に示すような凸状回路32に比べて、微細であっても絶縁層3との密着力を確保したフリップチップ接続端子26が形成可能になる。このため、図3に示すように、フリップチップ接続端子26の長手方向の片側だけに延長された埋込回路2を設けることも可能であり、この場合はフリップチップ接続端子26のサイズを小さくすることができるので、より高密度化を図ることができる点で望ましい。また、図4に示すように、フリップチップ接続端子26の長手方向の片側及び両側に延長された埋込回路2の両者を設けることも可能である。このように、フリップチップ接続端子26の長手方向に延長された埋込回路2は、フリップチップ接続端子26の長手方向の両側に設けても、片側だけに設けてもよいので、設計の自由度を大きくすることが可能である。また、フリップチップ接続端子26が厚さ3μm以上の予備はんだ19によって被覆されるので、半導体素子15のバンプ25とのフリップチップ接続に必要なはんだ量を確保可能になる。したがって、高密度化に対応可能で信頼性にも優れた半導体素子搭載用パッケージ基板1を提供することができる。 As a first example of the semiconductor device mounting package substrate (hereinafter referred to as “package substrate”) of the present invention, as shown in FIG. 2, the upper surface is exposed on the surface of the insulating layer 3 and the insulating layer 3. Embedded circuit 2 provided in this manner, and solder resist 4 provided on insulating layer 3 and embedded circuit 2, and embedded circuit 2 disposed in opening 31 of solder resist 4. Forming a flip chip connection terminal 26, and the semiconductor chip mounting package substrate 1 in which the flip chip connection terminal 26 is covered with a preliminary solder 19 having a thickness of 3 μm or more. According to this configuration, the flip chip connection terminal 26 is formed by the embedded circuit 2 whose upper surface is exposed on the surface of the insulating layer 3. For this reason, since the side surface and the bottom surface of the flip chip connection terminal 26 are embedded and fixed in the insulating layer 3, the embedded circuit 2 forming the flip chip connection terminal 26 has a fine line / space level of 20 μm / 20 μm or less. Even with a simple circuit pattern, it is possible to form the flip-chip connection terminal 26 that secures the adhesion to the insulating layer 3. In the case of having the embedded circuit 2 extended on both sides in the longitudinal direction of the flip chip connecting terminal 26, the embedded circuit 2 fixes the flip chip connecting terminal 26 from both sides. However, in the present invention, compared to the convex circuit 32 as shown in FIG. 1, it is possible to form the flip-chip connection terminal 26 that ensures the adhesion with the insulating layer 3 even if it is fine. For this reason, as shown in FIG. 3, it is possible to provide the embedded circuit 2 extended only on one side in the longitudinal direction of the flip chip connection terminal 26. In this case, the size of the flip chip connection terminal 26 is reduced. Therefore, it is desirable in that the density can be increased. Moreover, as shown in FIG. 4, it is also possible to provide both the embedded circuit 2 extended to the one side and both sides of the flip chip connection terminal 26 in the longitudinal direction. As described above, the embedded circuit 2 extended in the longitudinal direction of the flip chip connection terminal 26 may be provided on both sides of the flip chip connection terminal 26 in the longitudinal direction or may be provided on only one side. Can be increased. Further, since the flip chip connection terminal 26 is covered with the preliminary solder 19 having a thickness of 3 μm or more, it is possible to secure the amount of solder necessary for the flip chip connection with the bump 25 of the semiconductor element 15. Therefore, it is possible to provide the package substrate 1 for mounting a semiconductor element that can cope with high density and has excellent reliability.
 本発明の絶縁層とは、有機絶縁材料を用いて形成された絶縁基板、コア基板、フィルム、層間絶縁層、ビルドアップ層等をいう。このような絶縁層として、一般にパッケージ基板に用いられるものを使用することができ、ガラスクロスにエポキシ樹脂やポリイミド樹脂を含浸させたプリプレグ、エポキシ系接着シートやポリイミド系接着シート等を加熱、加圧して形成されるものが挙げられる。 The insulating layer of the present invention refers to an insulating substrate, a core substrate, a film, an interlayer insulating layer, a build-up layer, etc. formed using an organic insulating material. As such an insulating layer, what is generally used for a package substrate can be used, and a prepreg in which a glass cloth is impregnated with an epoxy resin or a polyimide resin, an epoxy adhesive sheet or a polyimide adhesive sheet is heated and pressurized. Are formed.
 本発明の埋込回路とは、絶縁層に少なくとも底面及び側面の一部が埋め込まれ、少なくとも上面が絶縁層の表面に露出するように設けられる回路をいう。このような埋込回路は、例えば、金属箔を給電層としてその上にパターン電気めっきで所定の回路パターンを形成し、この回路パターン上に絶縁層を形成して回路パターンを絶縁層に埋め込んだ後、給電層とした金属箔をエッチング等で除去することにより、パターン絶縁層に埋め込まれた回路パターンの表面を絶縁層から露出させる、いわゆる転写法などで形成することができる。 The embedded circuit of the present invention refers to a circuit provided so that at least a part of the bottom surface and side surfaces are embedded in the insulating layer and at least the top surface is exposed on the surface of the insulating layer. In such an embedded circuit, for example, a metal foil is used as a power feeding layer, a predetermined circuit pattern is formed thereon by pattern electroplating, an insulating layer is formed on the circuit pattern, and the circuit pattern is embedded in the insulating layer. Thereafter, the metal foil serving as the power feeding layer is removed by etching or the like, so that the surface of the circuit pattern embedded in the pattern insulating layer is exposed from the insulating layer, which can be formed by a so-called transfer method.
 本発明のソルダーレジストとは、予備はんだがフリップチップ接続端子となる埋込回路以外の部分に付着しないようにパッケージ基板の表面を保護するものである。また、ソルダージレストに設けられる開口によって、埋込回路の中でフリップチップ接続端子となる部分が規定されることにより、この開口内の埋込回路がフリップチップ接続端子を形成するものである。ソルダーレジストとしては、フリップチップ接続端子を形成するための、縦100μm×横100μm以下レベルの微小な開口を精度よく形成できることから感光性のソルダーレジストが好ましい。 The solder resist of the present invention protects the surface of the package substrate so that the preliminary solder does not adhere to portions other than the embedded circuit that becomes the flip chip connection terminal. Further, the opening provided in the solder girest defines a portion to be the flip chip connection terminal in the embedded circuit, so that the embedded circuit in the opening forms the flip chip connection terminal. As the solder resist, a photosensitive solder resist is preferable because a minute opening of a level of 100 μm in length × 100 μm in width for forming a flip chip connection terminal can be formed with high accuracy.
 本発明のフリップチップ接続端子とは、半導体素子をフリップチップ接続によってパッケージ基板に搭載するために用いる接続端子をいう。また、フリップチップ接続とは、半導体素子の能動素子面をパッケージ基板に向けて接続する方法をいい、半導体素子に電極としてのバンプを形成し、半導体素子を裏返してパッケージ基板上の搭載位置に合せた後、半導体素子のバンプとパッケージ基板に形成されたフリップチップ接続端子とを接続する方法である。本発明のフリップチップ接続端子は、実際に半導体素子のバンプと当接する接続部だけをいうのではなく、半導体素子のバンプと接続する埋込回路であって、ソルダーレジストの開口内で絶縁層の表面に露出した部分をいう。フリップチップ接続端子の表面には、表面を酸化から防ぎ、予備はんだの濡れ性を確保するために、ニッケル/金めっき(ニッケルめっきとその上に金めっきを形成したもの)、ニッケル/パラジウム/金めっき(ニッケルめっきとその上にパラジウムめっきとその上に金めっきを形成したもの)等の保護めっきが設けられてもよい。 The flip chip connection terminal of the present invention means a connection terminal used for mounting a semiconductor element on a package substrate by flip chip connection. Flip chip connection refers to a method of connecting the active element surface of a semiconductor element to the package substrate. Bumps as electrodes are formed on the semiconductor element, and the semiconductor element is turned over to match the mounting position on the package substrate. Thereafter, the bumps of the semiconductor element are connected to the flip chip connection terminals formed on the package substrate. The flip-chip connection terminal of the present invention is not only a connection part that actually contacts the bump of the semiconductor element, but is an embedded circuit connected to the bump of the semiconductor element, and includes an insulating layer within the opening of the solder resist. The part exposed on the surface. On the surface of the flip chip connection terminal, nickel / gold plating (nickel plating and gold plating formed thereon), nickel / palladium / gold to prevent the surface from oxidation and ensure wettability of the pre-solder Protective plating such as plating (nickel plating and palladium plating thereon and gold plating formed thereon) may be provided.
 本発明の予備はんだとは、半導体素子とのフリップチップ接続のためにフリップチップ接続端子上に設けられるはんだのことをいう。予備はんだは、はんだペーストを印刷しリフローする方法、その他の公知の方法によって形成することができる。はんだペーストの一例としては、電子部品の実装で用いられる、Sn(スズ)-Pb(鉛)系、Sn(スズ)-Ag(銀)-Cu(銅)系等のはんだ粒子をロジンや有機溶剤と混合したもの等が挙げられる。はんだペーストの印刷には、メタルマスクやシルクスクリーン等を用いることができる。リフローは、電子部品の実装で一般的に用いられる、赤外線リフロー、熱風リフロー、VPS(ベーパーフェイズソルダリング)リフロー等を用いて行なうことができる。リフロー条件は、はんだペーストによっても異なるが、例えばSn-Pb(スズと鉛)系であれば、ピーク温度が240℃程度、Sn(スズ)-Ag(銀)-Cu(銅)系であれば、ピーク温度が260℃程度の条件が挙げられる。 The preliminary solder of the present invention refers to a solder provided on a flip chip connection terminal for flip chip connection with a semiconductor element. The preliminary solder can be formed by a method of printing solder paste and reflowing, or other known methods. As an example of solder paste, solder particles such as Sn (tin) -Pb (lead) and Sn (tin) -Ag (silver) -Cu (copper) used for mounting electronic components are rosin or organic solvents. And the like. A metal mask, a silk screen, or the like can be used for printing the solder paste. The reflow can be performed using infrared reflow, hot air reflow, VPS (vapor phase soldering) reflow, or the like generally used in mounting electronic components. The reflow conditions differ depending on the solder paste. For example, if the Sn-Pb (tin and lead) system is used, the peak temperature is about 240 ° C, and if the Sn (tin) -Ag (silver) -Cu (copper) system is used. The condition that the peak temperature is about 260 ° C. is mentioned.
 本発明のパッケージ基板は、フリップチップ接続端子が、厚さ3μm以上の予備はんだによって被覆される。予備はんだの厚さが3μm未満では、フリップチップ接続端子と半導体素子のバンプとの間にはんだフィレットを形成するのに十分ではなく、接続信頼性を確保することが難しい。一方、予備はんだの厚みが20μmを超えると、隣接するフリップチップ接続端子上の予備はんだとはんだブリッジを生じる可能性がある。このため、予備はんだの厚みは、3μm以上、20μm以下が望ましい。なお、一般的にフリップチップ接続端子の上面が平面視で細長い長方形であるため、はんだペースト等をリフローして形成される予備はんだは、はんだの表面張力によって略半円柱状(かまぼこ状)に形成される。このため、予備はんだの厚みは、フリップチップ接続端子の長手方向(長さ方向)と短手方向(幅方向)の略中央において最も厚く形成される。そこで、本発明において、予備はんだの厚みは、フリップチップ接続端子の長手方向(長さ方向)と短手方向(幅方向)の略中央について、ソルダーレジスト表面とはんだ表面との段差を非接触式段差測定機を用いて測定して求めたものとした。 In the package substrate of the present invention, the flip chip connection terminal is covered with a preliminary solder having a thickness of 3 μm or more. If the thickness of the preliminary solder is less than 3 μm, it is not sufficient to form a solder fillet between the flip chip connection terminal and the bump of the semiconductor element, and it is difficult to ensure connection reliability. On the other hand, when the thickness of the preliminary solder exceeds 20 μm, there is a possibility that the preliminary solder and the solder bridge on the adjacent flip chip connecting terminals are generated. For this reason, the thickness of the preliminary solder is desirably 3 μm or more and 20 μm or less. In general, since the top surface of the flip chip connection terminal is a long and narrow rectangle in plan view, the preliminary solder formed by reflowing solder paste or the like is formed in a substantially semi-cylindrical shape (kamaboko shape) due to the surface tension of the solder. Is done. For this reason, the thickness of the preliminary solder is formed to be the thickest at substantially the center in the longitudinal direction (length direction) and the short direction (width direction) of the flip chip connection terminal. Therefore, in the present invention, the thickness of the preliminary solder is determined so that the step between the solder resist surface and the solder surface is a non-contact type at approximately the center in the longitudinal direction (length direction) and the short direction (width direction) of the flip chip connection terminal. It was determined by measurement using a level difference measuring machine.
 本発明のパッケージ基板の第2の例としては、図5に示すように、フリップチップ接続端子26を含む埋込回路2の底面にビア18が接続されるものが挙げられる。なお、予備はんだは省略して示している。図5では、フリップチップ接続端子26の底面及びこのフリップチップ接続端子26から長手方向に延長された埋込回路2の底面の両方に、ビア18が形成されているが、この何れか一方にビア18が形成されていてもよい。つまり、この第2の例では、絶縁層3に埋め込まれているフリップチップ接続端子26の底面、このフリップチップ接続端子26から長手方向に延長された埋込回路2の底面、または、これらの両者の底面にビア18が形成される。このように底面にビア18が接続されることで、フリップチップ接続端子26またはフリップチップ接続端子26から長手方向に延長された埋込回路2が、ビア18によって絶縁層3に固定されるので、第1の例よりもフリップチップ接続端子26と絶縁層3との密着をさらに強固にすることが可能になる。 As a second example of the package substrate of the present invention, as shown in FIG. 5, there is one in which a via 18 is connected to the bottom surface of the embedded circuit 2 including the flip chip connection terminal 26. Note that the preliminary solder is omitted. In FIG. 5, vias 18 are formed on both the bottom surface of the flip chip connection terminal 26 and the bottom surface of the embedded circuit 2 extending in the longitudinal direction from the flip chip connection terminal 26. 18 may be formed. That is, in this second example, the bottom surface of the flip chip connection terminal 26 embedded in the insulating layer 3, the bottom surface of the embedded circuit 2 extending in the longitudinal direction from the flip chip connection terminal 26, or both of them. A via 18 is formed on the bottom surface of. Since the via 18 is connected to the bottom surface in this way, the flip chip connection terminal 26 or the embedded circuit 2 extended in the longitudinal direction from the flip chip connection terminal 26 is fixed to the insulating layer 3 by the via 18. It is possible to further strengthen the adhesion between the flip chip connection terminal 26 and the insulating layer 3 than in the first example.
 本発明において、ビアとは、パッケージ基板に多層に設けられる配線層の層間を接続するものであり、例えば、配線層の層間接続用の孔をレーザ等で形成した後、この孔内にめっき等を行うことにより形成することができる。なお、フリップチップ接続端子の底面やフリップチップ接続端子から長手方向に延長された埋込回路の底面と、ビアとの接続面積を稼ぐために、ビアはいわゆるフィルドビアめっきにより形成するのが望ましい。 In the present invention, the via is used to connect the layers of the wiring layer provided in multiple layers on the package substrate. For example, after a hole for interlayer connection of the wiring layer is formed by a laser or the like, plating or the like is formed in the hole. Can be formed. In order to increase the connection area between the bottom surface of the flip chip connection terminal and the bottom surface of the embedded circuit extending in the longitudinal direction from the flip chip connection terminal and the via, the via is preferably formed by so-called filled via plating.
 本発明のパッケージ基板の第3の例としては、図6に示すように、フリップチップ接続端子26の長手方向の一部に凸形状27が形成されるものが挙げられる。なお、予備はんだ19は省略して示している。この凸形状27は、例えば、めっきレジストを形成して、埋込回路のフリップチップ接続端子26となる箇所の一部にパターンめっきすることによって形成することができる。また、図示しないが、例えば、絶縁層3の表面から側面の一部と上面が突出した埋込回路を形成した後、エッチングレジストを形成し、突出した埋込回路の一部が突出したまま残り、他の部分は絶縁層3の表面と面一になるようにエッチングすることによっても形成することができる。凸形状27の高さは、3μm~8μm程度が望ましく、凸形状27を設ける範囲は、フリップチップ接続端子26の短手方向(幅方向)の寸法の50%~100%で、フリップチップ接続端子26の長手方向(長さ方向)の寸法の10%~70%程度であるのが望ましい。このようにフリップチップ接続端子26の長手方向の一部に凸形状27を形成することにより、凸形状27の段差部分にはんだが溜まるので(図示しない。)、表面が平坦な場合に比べて、フリップチップ接続端子26の上に配置されるはんだの量を増加させることができる。また、凸形状27は、他の部分のはんだを引き寄せるきっかけとなり、はんだは、凸形状27を中心として凝集するので、突出したはんだ溜まりをフリップチップ接続端子26の長手方向の所定の位置に形成することもできる。このため、フリップチップ接続端子26に搭載される半導体素子のバンプの位置に対応して、フリップチップ接続端子26上の突出する部分を設けることができるので、フリップチップ接続端子26と半導体素子のバンプとを確実に接続することができる。 As a third example of the package substrate of the present invention, as shown in FIG. 6, there is one in which a convex shape 27 is formed on a part of the flip chip connection terminal 26 in the longitudinal direction. Note that the preliminary solder 19 is omitted. The convex shape 27 can be formed, for example, by forming a plating resist and pattern plating on a part of the portion that becomes the flip chip connection terminal 26 of the embedded circuit. Although not shown, for example, after forming an embedded circuit in which a part of the side surface and the upper surface protrude from the surface of the insulating layer 3, an etching resist is formed, and a part of the protruded embedded circuit is left protruding. The other portions can also be formed by etching so as to be flush with the surface of the insulating layer 3. The height of the convex shape 27 is desirably about 3 μm to 8 μm, and the range in which the convex shape 27 is provided is 50% to 100% of the dimension in the short direction (width direction) of the flip chip connection terminal 26, and the flip chip connection terminal It is desirable that it is about 10% to 70% of the dimension in the longitudinal direction (length direction) of 26. Thus, by forming the convex shape 27 on a part of the flip chip connection terminal 26 in the longitudinal direction, solder accumulates on the stepped portion of the convex shape 27 (not shown), so that compared to the case where the surface is flat, The amount of solder disposed on the flip chip connection terminal 26 can be increased. Further, the convex shape 27 becomes a trigger for attracting other portions of the solder, and the solder aggregates around the convex shape 27, so that a protruding solder pool is formed at a predetermined position in the longitudinal direction of the flip chip connection terminal 26. You can also Therefore, a protruding portion on the flip chip connection terminal 26 can be provided in correspondence with the position of the bump of the semiconductor element mounted on the flip chip connection terminal 26. Therefore, the bump of the flip chip connection terminal 26 and the semiconductor element can be provided. Can be securely connected.
 本発明のパッケージ基板の第4の例としては、図7に示すように、フリップチップ接続端子26の長手方向の一部に凹み形状28が形成されるものが挙げられる。なお、予備はんだは省略して示している。この凹み形状28は、図示しないが、例えば、絶縁層3の表面から上面が露出した埋込回路を形成した後、エッチングレジストを形成し、上面が露出した埋込回路の上面の一部が絶縁層3の表面よりも凹み、他の部分はそのまま残るようにエッチングすることによって形成することができる。凹み形状28の深さは、3μm~8μm程度が望ましく、凹み形状28の範囲は、フリップチップ接続端子26の短手方向(幅方向)の寸法の50%~100%で、フリップチップ接続端子26の長手方向(長さ方向)の寸法の10%~70%程度であるのが望ましい。このように凹み形状28を形成することにより、この部分に溶融したはんだが溜まるので、フリップチップ接続端子26上に配置するはんだ(図示しない。)の量を増加させることができる。つまり、凹み形状28は、はんだを溜める容器の役割を果たし、はんだが凹み形状28の中に溜まるので、はんだフィレットを形成するのに十分なはんだをフリップチップ接続端子26上に形成することができる。 As a fourth example of the package substrate of the present invention, as shown in FIG. 7, there is one in which a concave shape 28 is formed in a part of the flip chip connection terminal 26 in the longitudinal direction. Note that the preliminary solder is omitted. Although not shown in the drawing, the recessed shape 28 is formed by, for example, forming an embedded circuit whose upper surface is exposed from the surface of the insulating layer 3 and then forming an etching resist so that a part of the upper surface of the embedded circuit whose upper surface is exposed is insulated. It can be formed by etching so that it is recessed from the surface of the layer 3 and the other part remains as it is. The depth of the concave shape 28 is desirably about 3 μm to 8 μm. The range of the concave shape 28 is 50% to 100% of the dimension in the short direction (width direction) of the flip chip connection terminal 26. Desirably, it is about 10% to 70% of the dimension in the longitudinal direction (length direction). By forming the concave shape 28 in this way, molten solder accumulates in this portion, so that the amount of solder (not shown) disposed on the flip chip connection terminal 26 can be increased. That is, the concave shape 28 serves as a container for storing solder, and since the solder accumulates in the concave shape 28, it is possible to form sufficient solder on the flip chip connection terminal 26 to form a solder fillet. .
 本発明のパッケージ基板の第5の例としては、図3に示すように、フリップチップ接続端子26の先端が、ソルダーレジスト4の開口31内に形成されたものが挙げられる。なお、予備はんだは省略して示している。従来の一般的なパッケージ基板のように、絶縁層3の表面上に接着した金属箔をエッチングすることによって回路パターンが形成される場合、この回路パターンは凸状回路32(図1)であり、形成されるフリップチップ接続端子26は、その底面のみが絶縁層3と接着している。また、エッチングによって形成されるため、凸状回路32による回路パターンは、断面から見て、回路パターンの表面側よりも底面側の方が幅が細くなる、いわゆるアンダーカットを生じる。このため、フリップチップ接続端子26のサイズが微細化すると、凸状回路32による回路パターンの底面と絶縁層3との接着面積が減少するので、絶縁層3との密着力が低下し、フリップチップ接続の際にわずかな外力が加わるだけで剥がれてしまう可能性がある。そこで、絶縁層3とフリップチップ接続端子26との密着力を確保するために、ソルダーレジスト4で被覆して上側から回路パターンを固定し、ソルダーレジスト4の開口31からフリップチップ接続端子26を露出させることで、フリップチップ接続端子26の長手方向の両側をソルダーレジスト4で固定する方法が採られる。しかし、この方法では、ソルダーレジスト4の解像度の限界によって、ソルダーレジスト4の開口31の幅が規定されるため、フリップチップ接続端子26を、ソルダーレジスト4の解像度の限界よりも長くする必要があった。また、このため、回路パターンの引き回しの自由度も制限されていた。本発明のパッケージ基
板1の第5の例によれば、フリップチップ接続端子26が絶縁層3の表面に上面が露出した埋込回路によって形成されるので、微細であっても密着力を確保することが可能になる。このため、ソルダーレジスト4によって、フリップチップ接続端子26の長手方向の両側に延長された回路パターンを上から被覆して固定する必要がなく、フリップチップ接続端子26の先端をソルダーレジスト4の開口31内に形成することができる。したがって、ソルダーレジスト4の解像度に制限されることなく、フリップチップ接続端子26を微細化できるので、より高密度化を図ることが可能となり、また回路パターンの設計の自由度を向上させることができる。
As a fifth example of the package substrate of the present invention, as shown in FIG. 3, there is one in which the tip of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4. Note that the preliminary solder is omitted. When a circuit pattern is formed by etching a metal foil adhered on the surface of the insulating layer 3 as in a conventional general package substrate, the circuit pattern is a convex circuit 32 (FIG. 1). Only the bottom surface of the formed flip chip connection terminal 26 is bonded to the insulating layer 3. Further, since the circuit pattern is formed by etching, the circuit pattern formed by the convex circuit 32 causes a so-called undercut in which the width on the bottom surface side is narrower than the surface side of the circuit pattern when viewed from the cross section. For this reason, when the size of the flip chip connection terminal 26 is miniaturized, the adhesion area between the bottom surface of the circuit pattern formed by the convex circuit 32 and the insulating layer 3 is reduced, so that the adhesive force with the insulating layer 3 is reduced, and the flip chip When connecting, a slight external force may be applied to cause peeling. Therefore, in order to secure the adhesion between the insulating layer 3 and the flip chip connection terminal 26, the circuit pattern is fixed from above by covering with the solder resist 4, and the flip chip connection terminal 26 is exposed from the opening 31 of the solder resist 4. Thus, a method of fixing both sides of the flip chip connection terminal 26 in the longitudinal direction with the solder resist 4 is adopted. However, in this method, since the width of the opening 31 of the solder resist 4 is defined by the resolution limit of the solder resist 4, it is necessary to make the flip chip connection terminal 26 longer than the resolution limit of the solder resist 4. It was. For this reason, the degree of freedom of circuit pattern routing is also limited. According to the fifth example of the package substrate 1 of the present invention, since the flip chip connection terminal 26 is formed by the embedded circuit whose upper surface is exposed on the surface of the insulating layer 3, the adhesion is ensured even if it is fine. It becomes possible. Therefore, it is not necessary to cover and fix the circuit pattern extended on both sides in the longitudinal direction of the flip chip connection terminal 26 with the solder resist 4 and fix the tip of the flip chip connection terminal 26 to the opening 31 of the solder resist 4. Can be formed inside. Therefore, since the flip chip connection terminal 26 can be miniaturized without being limited by the resolution of the solder resist 4, it is possible to achieve higher density and to improve the degree of freedom of circuit pattern design. .
 本発明のパッケージ基板の第6の例としては、図4に示すように、フリップチップ接続端子26の長手方向の両側または片側に延長された埋込回路2が設けられたものが挙げられる。本発明のパッケージ基板の第6の例によれば、第5の例と同様に、ソルダーレジスト4の解像度に制限されることなく、フリップチップ接続端子26を微細化できるので、より高密度化を図ることが可能となり、また回路パターンの設計の自由度を向上させることができる。 As a sixth example of the package substrate of the present invention, as shown in FIG. 4, there is one provided with embedded circuits 2 extending on both sides or one side of the flip chip connection terminal 26 in the longitudinal direction. According to the sixth example of the package substrate of the present invention, similarly to the fifth example, the flip chip connection terminal 26 can be miniaturized without being limited by the resolution of the solder resist 4, so that higher density can be achieved. It is possible to increase the degree of freedom of circuit pattern design.
 本発明のパッケージ基板の第7の例としては、図8に示すように、フリップチップ接続端子26の一部が、短手方向(幅方向)に拡張された部分33を有するものが挙げられる。フリップチップ接続端子26の先端は、ソルダーレジスト4の開口31内に形成されてもよい。なお、予備はんだは省略して示している。このフリップチップ接続端子26が部分的に短手方向(幅方向)に拡張された部分33を有することにより、絶縁層3との密着面積が拡大するため、フリップチップ接続端子26と絶縁層3との密着力をより向上させることができるとともに、予備はんだ19の量をより多く確保することができ、また、短手方向(幅方向)に拡張された部分33の予備はんだ19が表面張力によってそれ以外の部分のはんだを引き寄せてはんだ溜りを形成するので、はんだ溜りを所定の位置に安定して形成することができる。 As a seventh example of the package substrate of the present invention, as shown in FIG. 8, a part of the flip chip connection terminal 26 has a portion 33 extended in the short direction (width direction). The tip of the flip chip connection terminal 26 may be formed in the opening 31 of the solder resist 4. Note that the preliminary solder is omitted. Since the flip chip connection terminal 26 has a portion 33 that is partially expanded in the short direction (width direction), the contact area with the insulating layer 3 is increased. Therefore, the flip chip connection terminal 26, the insulating layer 3, The amount of the preliminary solder 19 can be secured more, and the preliminary solder 19 in the portion 33 expanded in the short side direction (width direction) is affected by the surface tension. Since the solder pool is formed by pulling the solder of other parts, the solder pool can be stably formed at a predetermined position.
 本発明の半導体パッケージの一例としては、図9に示すように、上記の第1から第7の例のパッケージ基板1に半導体素子15をフリップチップ接続により搭載したものが挙げられる。半導体素子15のバンプ25形成面と、半導体素子搭載用パッケージ基板1のフリップチップ接続端子26を有する絶縁層3との間に、アンダーフィル材23が充填されるのが望ましい。これによれば、アンダーフィル材23が半導体素子15のバンプ25形成面とフリップチップ接続端子26を有する絶縁層3との間の密着力を、さらに強固にすることが可能になる。したがって、高密度化に対応可能で信頼性にも優れた半導体パッケージ24を提供することができる。 As an example of the semiconductor package of the present invention, as shown in FIG. 9, a semiconductor element 15 mounted on the package substrate 1 of the above first to seventh examples by flip-chip connection can be mentioned. The underfill material 23 is preferably filled between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26 of the package substrate 1 for mounting the semiconductor element. According to this, it becomes possible for the underfill material 23 to further strengthen the adhesion between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26. Therefore, it is possible to provide the semiconductor package 24 that can cope with high density and has excellent reliability.
 本発明のパッケージ基板の製造方法の一例について、図10~図18を用いて以下に説明する。 An example of the manufacturing method of the package substrate of the present invention will be described below with reference to FIGS.
 まず、図10に示すように、第1キャリア金属箔10と第2キャリア金属箔11とベース金属箔12とをこの順に積層した多層金属箔9を準備する。 First, as shown in FIG. 10, a multilayer metal foil 9 in which a first carrier metal foil 10, a second carrier metal foil 11, and a base metal foil 12 are laminated in this order is prepared.
 第1キャリア金属箔10は、第2キャリア金属箔11の表面(第1キャリア金属箔10との間)を保護するためのものであり、第2キャリア金属箔11との間で物理的に剥離可能とされる。第2キャリア金属箔11の表面を保護できれば、特に材質や厚みは問わないが、汎用性や取り扱い性の点で、材質としては銅箔やアルミニウム箔が好ましく、厚みとしては1~35μmが好ましい。また、第1キャリア金属箔10と第2キャリア金属箔11との間には、これらの間での剥離強度を安定化するための剥離層(図示しない。)を設けるのが好ましく、剥離層としては、絶縁樹脂と積層する際の加熱・加圧を複数回行っても剥離強度が安定化しているものが好ましい。このような剥離層としては、特開2003-181970号公報に開示された金属酸化物層と有機剤層を形成したものや、特開2003-094553号公報に開示されたCu-Ni-Mo合金からなるもの、再公表特許WO2006/013735号公報に示されたNi及びWの金属酸化物又はNi及びMoの金属酸化物を含有するものが挙げられる。なお、この剥離層は、第1キャリア金属箔10を第2キャリア金属箔11との間で物理的に剥離する際には、第1キャリア金属箔10側に付着した状態で剥離し、第2キャリア金属箔11の表面には残留しないものが望ましい。 The first carrier metal foil 10 is for protecting the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) and physically peels from the second carrier metal foil 11. It is possible. The material and thickness are not particularly limited as long as the surface of the second carrier metal foil 11 can be protected. However, from the viewpoint of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is preferably 1 to 35 μm. Moreover, it is preferable to provide a peeling layer (not shown) for stabilizing the peeling strength between the first carrier metal foil 10 and the second carrier metal foil 11 as the peeling layer. Are preferably those that have a stable peel strength even if they are heated and pressurized a plurality of times when laminated with an insulating resin. Examples of such a release layer include those in which a metal oxide layer and an organic agent layer disclosed in JP-A-2003-181970 are formed, and Cu—Ni—Mo alloys disclosed in JP-A-2003-094553. And those containing a metal oxide of Ni and W or a metal oxide of Ni and Mo shown in re-published patent WO2006 / 013735. When the first carrier metal foil 10 is physically peeled from the second carrier metal foil 11, the peel layer is peeled off while being attached to the first carrier metal foil 10 side. What does not remain on the surface of the carrier metal foil 11 is desirable.
 第2キャリア金属箔11は、第1キャリア金属箔10を剥離した後の表面に第1のパターンめっき13を行うために電流を供給するシード層(給電層)となるものであり、第1キャリア金属箔10との間およびベース金属箔12との間で物理的に剥離可能とされる。ベース金属箔12とともに給電層として機能すればよく、特に材質や厚みは問わないが、汎用性や取り扱い性の点で、材質としては銅箔やアルミニウム箔が好ましく、厚みとしては1から18μmのものを使用できる。ただ、後述するように外層回路2を形成する際(図16(12)、(13)、(14))にはエッチングで除去されるので、エッチング量のばらつきを極力低減して高精度な微細回路を形成するためには1~5μmの極薄金属箔が好ましい。また、第1キャリア金属箔10との間およびベース金属箔12との間には、これらの間での剥離強度を安定化するため、上述したような剥離層(図示しない。)を設けるのが好ましい。なお、この剥離層は、第2キャリア金属箔11とベース金属箔12とが一体となってシード層として作用するようにするため、導電性を有するものが望ましい。なお、この剥離層は、第2キャリア金属箔11とベース金属箔12との間で物理的に剥離する際には、ベース金属箔12側に付着した状態で剥離し、第2キャリア金属箔11の表面には残留しないものが望ましい。 The second carrier metal foil 11 serves as a seed layer (feeding layer) for supplying a current to perform the first pattern plating 13 on the surface after the first carrier metal foil 10 is peeled off. It can be physically peeled between the metal foil 10 and the base metal foil 12. It only needs to function as a power feeding layer together with the base metal foil 12, and the material and thickness are not particularly limited. However, from the viewpoint of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is 1 to 18 μm. Can be used. However, as will be described later, when the outer layer circuit 2 is formed (FIGS. 16 (12), (13), and (14)), it is removed by etching. In order to form a circuit, an ultrathin metal foil of 1 to 5 μm is preferable. In addition, a release layer (not shown) as described above is provided between the first carrier metal foil 10 and the base metal foil 12 in order to stabilize the peel strength between them. preferable. The release layer is preferably conductive so that the second carrier metal foil 11 and the base metal foil 12 are integrated to act as a seed layer. In addition, when this peeling layer physically peels between the 2nd carrier metal foil 11 and the base metal foil 12, it peels in the state adhering to the base metal foil 12 side, and the 2nd carrier metal foil 11 Those that do not remain on the surface are desirable.
 ベース金属箔12は、多層金属箔9を基材16と積層してコア基板17を作製する際に、基材16と積層される側に位置するものであり、第2キャリア金属箔11との間で物理的に剥離可能とされる。基材16と積層される際に、基材16との接着性を有していれば特に材質や厚みは問わないが、汎用性や取り扱い性の点で、材質としては銅箔やアルミニウム箔が好ましく、厚みとしては9~70μmが好ましい。また、第2キャリア金属箔11との間には、これらの間での剥離強度を安定化するため、上述したような剥離層(図示しない。)を設けるのが好ましい。なお、この剥離層は、第2キャリア金属箔11とベース金属箔12との間で物理的に剥離する際には、ベース金属箔12側に付着した状態で剥離し、第2キャリア金属箔11の表面には残留しないものが望ましい。 The base metal foil 12 is positioned on the side laminated with the base material 16 when the multilayer metal foil 9 is laminated with the base material 16 to produce the core substrate 17. It can be physically peeled between. When laminated with the base material 16, the material and the thickness are not particularly limited as long as they have adhesiveness with the base material 16, but the material is copper foil or aluminum foil in terms of versatility and handleability. The thickness is preferably 9 to 70 μm. Moreover, in order to stabilize the peeling strength between these, between the 2nd carrier metal foil 11, it is preferable to provide the above peeling layers (not shown). In addition, when this peeling layer physically peels between the 2nd carrier metal foil 11 and the base metal foil 12, it peels in the state adhering to the base metal foil 12 side, and the 2nd carrier metal foil 11 Those that do not remain on the surface are desirable.
 多層金属箔9としては、3層以上の金属箔(例えば、上述したように、第1キャリア金属箔10と第2キャリア金属箔11とベース金属箔12)を有する多層金属箔9であって、少なくとも2箇所の間(例えば、上述したように、第1キャリア金属箔10と第2キャリア金属箔11との間および第2キャリア金属箔11とベース金属箔12との間)が物理的に剥離可能なものを用いる。多層金属箔9のベース金属箔12側に基材16を積層してコア基板17を形成する工程の際には、第1キャリア金属箔10の表面に樹脂粉等の異物が付着することがあるが、このような異物が付着したとしても、第1キャリア金属箔10を第2キャリア金属箔11との間で物理的に剥離することで、樹脂粉等の異物の影響のない第2キャリア金属箔11の表面が形成されるので、高品質な金属箔表面を確保することができる。したがって、第2キャリア金属箔11をシード層として使用して第1のパターンめっき13を行う場合にも、欠陥の発生を抑制することができるので、歩留りの向上を図ることが可能になる。 The multilayer metal foil 9 is a multilayer metal foil 9 having three or more layers of metal foils (for example, as described above, the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12), Physical separation between at least two locations (for example, as described above, between the first carrier metal foil 10 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the base metal foil 12) Use what is possible. In the process of laminating the base material 16 on the base metal foil 12 side of the multilayer metal foil 9 to form the core substrate 17, foreign matter such as resin powder may adhere to the surface of the first carrier metal foil 10. However, even if such foreign matter adheres, the second carrier metal that is not affected by foreign matters such as resin powder is obtained by physically peeling the first carrier metal foil 10 from the second carrier metal foil 11. Since the surface of the foil 11 is formed, a high-quality metal foil surface can be secured. Therefore, even when the first pattern plating 13 is performed using the second carrier metal foil 11 as a seed layer, the occurrence of defects can be suppressed, so that the yield can be improved.
 次に、図11(1)に示すように、多層金属箔9のベース金属箔12側と基材16とを積層してコア基板17を形成する。基材16は、多層金属箔9と積層一体化してコア基板17を形成するものであり、基材16としては、一般的に半導体素子搭載用パッケージ基板1の絶縁層3として使用されるものを用いることができる。このような基材16として、ガラスエポキシ、ガラスポリイミド等が挙げられる。コア基板17は、多層金属箔9を用いて、パッケージ基板1を製造する際に支持基板となるものであり、剛性を確保することによって、作業性を向上させること、およびハンドリング時の損傷を防いで歩留りを向上させるのを主な役割とするものである。このため、基材16としては、ガラス繊維等の補強材を有するものが望ましく、例えば、ガラスエポキシ、ガラスポリイミド等のプリプレグを、多層金属箔9と重ねて、熱プレス等を用いて加熱・加圧して積層一体化することで形成できる。基材16の両側(図11(1)の上下両側)に多層金属箔9を積層し、この後の工程を行うことで、1回の工程で2つのパッケージ基板1を製造する工程を進めることができるので、工数低減を図ることができる。また、コア基板17の両側に対称な構成の積層板を構成できるので、反りを抑制することができ、作業性や製造設備への引っ掛かり等による損傷も抑制できる。 Next, as shown in FIG. 11 (1), the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 are laminated to form a core substrate 17. The base material 16 is laminated and integrated with the multilayer metal foil 9 to form the core substrate 17. The base material 16 is generally used as the insulating layer 3 of the semiconductor element mounting package substrate 1. Can be used. Examples of the substrate 16 include glass epoxy and glass polyimide. The core substrate 17 serves as a support substrate when the package substrate 1 is manufactured using the multilayer metal foil 9. By ensuring rigidity, workability is improved and damage during handling is prevented. The main role is to improve the yield. For this reason, it is desirable that the substrate 16 has a reinforcing material such as glass fiber. For example, a prepreg such as glass epoxy or glass polyimide is overlapped with the multilayer metal foil 9 and heated / heated using a hot press or the like. It can be formed by pressing and laminating and integrating. The multilayer metal foil 9 is laminated on both sides of the base material 16 (upper and lower sides in FIG. 11 (1)), and the subsequent steps are performed to advance the process of manufacturing the two package substrates 1 in a single process. Therefore, man-hours can be reduced. Moreover, since the laminated board of a symmetrical structure can be comprised on both sides of the core board | substrate 17, a curvature can be suppressed and the damage | damage by workability | operativity, a catch to a manufacturing facility, etc. can also be suppressed.
 次に、図11(2)に示すように、多層金属箔9の第1キャリア金属箔10と第2キャリア金属箔11との間で、第1キャリア金属箔10を物理的に剥離する。第1キャリア金属箔10の表面には、積層時に基材16の材料となるプリプレグ等からの樹脂粉等の異物が付着する場合がある。このため、この第1キャリア金属箔10を用いて回路を形成する場合は、表面に付着した樹脂粉等の異物によって、回路に断線や短絡等の欠陥が生じることがあり、歩留りの低下に繋がる可能性がある。しかし、このように、第1キャリア金属箔10を剥離し除去することにより、樹脂粉等の異物が付着していない第2キャリア金属箔11を使用して回路を形成することができるので、回路欠陥の発生を抑制することができ、歩留りを改善することが可能になる。また、第1キャリア金属箔10を物理的に剥離可能であるため、第1キャリア金属箔10と第2キャリア金属箔11との間の剥離強度を調整することで、剥離作業を容易に行うことができる。このとき、多層金属箔9の第1キャリア金属箔10と第2キャリア金属箔11との間の剥離層(図示しない。)は、第1キャリア金属箔10側に移行するのが望ましい。これにより、第1キャリア金属箔10を剥離した後の第2キャリア金属箔11側には、第2キャリア金属箔11の表面が露出するので、後工程で行う第2キャリア金属箔11上へのめっきレジスト形成や第1のパターンめっき13の形成がが、剥離層によって阻害されることがない。 Next, as shown in FIG. 11 (2), the first carrier metal foil 10 is physically peeled between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9. On the surface of the first carrier metal foil 10, there may be a case where foreign matters such as resin powder from a prepreg or the like that becomes a material of the base material 16 at the time of lamination adhere. For this reason, when forming a circuit using this first carrier metal foil 10, foreign matter such as resin powder adhered to the surface may cause defects such as disconnection or short circuit in the circuit, leading to a decrease in yield. there is a possibility. However, since the first carrier metal foil 10 is peeled and removed in this way, a circuit can be formed using the second carrier metal foil 11 to which no foreign matter such as resin powder adheres. The occurrence of defects can be suppressed, and the yield can be improved. Further, since the first carrier metal foil 10 can be physically peeled off, the peeling work can be easily performed by adjusting the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. Can do. At this time, it is desirable that the release layer (not shown) between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9 moves to the first carrier metal foil 10 side. Thereby, since the surface of the 2nd carrier metal foil 11 is exposed to the 2nd carrier metal foil 11 side after peeling the 1st carrier metal foil 10, it is on the 2nd carrier metal foil 11 performed by a post process. The formation of the plating resist and the formation of the first pattern plating 13 are not hindered by the release layer.
 ここで、多層金属箔9は、第2キャリア金属箔11とベース金属箔12との間の剥離強度が、第1キャリア金属箔10と第2キャリア金属箔11との間の剥離強度よりも大きく形成された多層金属箔9であるのが望ましい。これにより、第1キャリア金属箔10と第2キャリア金属箔11との間で物理的に剥離する際に、第2キャリア金属箔11とベース金属箔12との間が同時に剥離するのを抑制することができる。剥離強度としては、加熱・加圧する前の初期において、第1キャリア金属箔10と第2キャリア金属箔11との間では2N/m~50N/m、第2キャリア金属箔11とベース金属箔12との間では10N/m~70N/mとし、第1キャリア金属箔10と第2キャリア金属箔11との間の剥離強度が、第2キャリア金属箔11とベース金属箔12との間の剥離強度よりも5N/m~20N/m小さくなるようにすると、製造工程でのハンドリングで剥離することがなく、一方で剥離する際は容易であり、しかも第1キャリア金属箔10を剥離する際に、第2キャリア金属箔11が同時に剥れるのを抑制することができるので作業性がよい。 Here, in the multilayer metal foil 9, the peel strength between the second carrier metal foil 11 and the base metal foil 12 is greater than the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. It is desirable that the multilayer metal foil 9 be formed. This suppresses simultaneous peeling between the second carrier metal foil 11 and the base metal foil 12 when physically peeling between the first carrier metal foil 10 and the second carrier metal foil 11. be able to. The peel strength is 2 N / m to 50 N / m between the first carrier metal foil 10 and the second carrier metal foil 11 in the initial stage before heating and pressing, and the second carrier metal foil 11 and the base metal foil 12. And the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11 is the peel strength between the second carrier metal foil 11 and the base metal foil 12. When the strength is made 5N / m to 20N / m smaller than the strength, it will not be peeled off during handling in the manufacturing process, but on the other hand, it is easy to peel off, and when the first carrier metal foil 10 is peeled off. Since the second carrier metal foil 11 can be prevented from peeling off at the same time, workability is good.
 剥離強度の調整は、例えば、特開2003-181970号公報や特開2003-094553号公報、再公表特許WO2006/013735号公報に示されるように、剥離層の下地となる第2キャリア金属箔11の表面(第1キャリア金属箔10との間)の粗さを調整したり、剥離層となる金属酸化物や合金めっき層を形成するためのめっき液組成や条件を調整することにより可能となる。 For example, as shown in Japanese Patent Application Laid-Open No. 2003-181970, Japanese Patent Application Laid-Open No. 2003-094553, and Republished Patent WO 2006/013735, the adjustment of the peel strength is performed by using the second carrier metal foil 11 serving as the base of the release layer. It becomes possible by adjusting the roughness of the surface (between the first carrier metal foil 10) and adjusting the plating solution composition and conditions for forming a metal oxide or alloy plating layer to be a release layer. .
 次に、図11(3)に示すように、コア基板17に残った第2キャリア金属箔11上に第1のパターンめっき13を行う。上述したように、第2キャリア金属箔11の表面(第1キャリア金属箔10との間)には、積層時に使用するプリプレグ等からの樹脂粉等の異物は付着しないので、これに起因する回路欠陥を抑制可能となる。第1のパターンめっき13は、第2キャリア金属箔11上に、めっきレジスト(図示しない。)を形成した後、電気めっきを用いて行うことができる。めっきレジストとしては、パッケージ基板1の製造プロセスで用いられる感光性レジストを使用することができる。電気めっきとしては、パッケージ基板1の製造プロセスで用いられる硫酸銅めっきを用いることができる。 Next, as shown in FIG. 11 (3), the first pattern plating 13 is performed on the second carrier metal foil 11 remaining on the core substrate 17. As described above, the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) does not adhere to foreign matters such as resin powder from the prepreg used at the time of lamination, so the circuit resulting from this Defects can be suppressed. The first pattern plating 13 can be performed using electroplating after forming a plating resist (not shown) on the second carrier metal foil 11. As the plating resist, a photosensitive resist used in the manufacturing process of the package substrate 1 can be used. As electroplating, copper sulfate plating used in the manufacturing process of the package substrate 1 can be used.
 多層金属箔9は、平均粗さ(Ra)が0.3μm~1.2μmの凹凸を予め設けた第2キャリア金属箔11の表面に、剥離層(図示しない。)を介して第1キャリア金属箔10が積層された多層金属箔9であるのが望ましい。これにより、第1キャリア金属箔10を剥離層とともに物理的に剥離した後の第2キャリア金属箔11の表面は、予め設けた平均粗さ(Ra)が0.3μm~1.2μmの凹凸を有する。このため、第2キャリア金属箔11の表面(第1キャリア金属箔10との間)に、第1のパターンめっき13用のめっきレジストを形成する際に、めっきレジストの密着や解像性を向上させることができ、高密度回路の形成に有利となる。また、第2キャリア金属箔11の表面に予め凹凸を設けておくことで、第1キャリア金属箔10を剥離した後に、第2キャリア金属箔11の表面に粗面化処理を行う必要がないため、工数の低減を図ることができる。 The multilayer metal foil 9 is formed on the surface of the second carrier metal foil 11 provided with irregularities having an average roughness (Ra) of 0.3 μm to 1.2 μm in advance via a release layer (not shown). A multilayer metal foil 9 in which the foil 10 is laminated is desirable. As a result, the surface of the second carrier metal foil 11 after physically peeling the first carrier metal foil 10 together with the release layer has irregularities with an average roughness (Ra) provided in advance of 0.3 μm to 1.2 μm. Have. For this reason, when forming the plating resist for the first pattern plating 13 on the surface of the second carrier metal foil 11 (between the first carrier metal foil 10), the adhesion and resolution of the plating resist are improved. This is advantageous for forming a high-density circuit. In addition, by providing unevenness on the surface of the second carrier metal foil 11 in advance, it is not necessary to roughen the surface of the second carrier metal foil 11 after the first carrier metal foil 10 is peeled off. The man-hour can be reduced.
 第2キャリア金属箔11の表面に設ける凹凸の表面粗さは、平均粗さ(Ra)が0.3~1.2μmであるのが、めっきレジストの密着や解像性を改善しつつ、第1のパターンめっき13後の剥離性を確保できる点で望ましい。平均粗さ(Ra)が0.3μm未満の場合、めっきレジストの密着不足が生じる傾向があり、平均粗さ(Ra)が1.2μmを超える場合、めっきレジストが追従し難くなりやはり密着不足が生じる傾向がある。さらに、めっきレジストのライン/スペースが15μm/15μmよりも微細になる場合には、平均粗さ(Ra)が0.5μm~0.9μmであるのが望ましい。ここで、平均粗さ(Ra)とは、JIS B 0601(2001)で規定される平均粗さ(Ra)であり、触針式表面粗さ計などを用いて測定することが可能である。なお、平均粗さ(Ra)の調整は、第2キャリア金属箔11が銅箔であれば、第2キャリア金属箔11としての銅箔を形成する際の電気銅めっきの組成(添加剤等を含む)や条件を調整することで可能となる。 The surface roughness of the irregularities provided on the surface of the second carrier metal foil 11 has an average roughness (Ra) of 0.3 to 1.2 μm, while improving the adhesion and resolution of the plating resist. It is desirable in that the peelability after the pattern plating 13 of 1 can be secured. When the average roughness (Ra) is less than 0.3 μm, the adhesion of the plating resist tends to be insufficient, and when the average roughness (Ra) exceeds 1.2 μm, the plating resist becomes difficult to follow and the adhesion is insufficient. Tend to occur. Further, when the line / space of the plating resist becomes finer than 15 μm / 15 μm, the average roughness (Ra) is desirably 0.5 μm to 0.9 μm. Here, the average roughness (Ra) is an average roughness (Ra) defined by JIS B 0601 (2001), and can be measured using a stylus type surface roughness meter or the like. In addition, adjustment of average roughness (Ra) is the composition (additive etc.) of the electro copper plating at the time of forming the copper foil as the 2nd carrier metal foil 11 if the 2nd carrier metal foil 11 is a copper foil. Including) and adjusting the conditions.
 次に、図12(4)に示すように、第1のパターンめっき13を含む第2キャリア金属箔11上に絶縁層3を積層して積層体22を形成する。絶縁層3としては、一般的にパッケージ基板1の絶縁層3として使用されるものを用いることができる。このような絶縁層3として、エポキシ系樹脂、ポリイミド系樹脂等が挙げられ、例えば、エポキシ系やポリイミド系の接着シート、ガラスエポキシやガラスポリイミド等のプリプレグを、熱プレス等を用いて加熱・加圧して積層一体化することで形成できる。ここで、積層体22とは、このように積層一体化した状態のもののうち、第1のパターンめっき13を含む第2キャリア金属箔11上に積層されたものをいう。絶縁層3となるこれらの樹脂の上に、さらに導体層20となる金属箔とを重ねて同時に加熱・加圧して積層一体化した場合は、この導体層20も含む。また、後述するように、導体層20により内層回路6を形成したり、導体層20を接続する層間接続5を形成した場合は、これらの内層回路6や層間接続5も含む。 Next, as shown in FIG. 12 (4), the insulating layer 3 is laminated on the second carrier metal foil 11 including the first pattern plating 13 to form a laminate 22. As the insulating layer 3, one generally used as the insulating layer 3 of the package substrate 1 can be used. Examples of the insulating layer 3 include an epoxy resin and a polyimide resin. For example, an epoxy or polyimide adhesive sheet, a glass epoxy or a glass polyimide prepreg is heated and heated using a hot press or the like. It can be formed by pressing and laminating and integrating. Here, the laminated body 22 refers to one laminated on the second carrier metal foil 11 including the first pattern plating 13 among those laminated and integrated. In the case where a metal foil to be the conductor layer 20 is further stacked on these resins to be the insulating layer 3 and simultaneously laminated by heating and pressing, this conductor layer 20 is also included. As will be described later, when the inner layer circuit 6 is formed by the conductor layer 20 or the interlayer connection 5 for connecting the conductor layer 20 is formed, the inner layer circuit 6 and the interlayer connection 5 are also included.
 次に、図12(5)、(6)に示すように、層間接続孔21を形成し、層間接続5や内層回路6を形成してもよい。層間接続5は、例えば、いわゆるコンフォーマル工法を用いて層間接続孔21を形成した後、この層間接続孔21内をめっきすることで形成することができる。このめっきには、下地めっきとして薄付け無電解銅めっきを行った後、厚付けめっきとして無電解銅めっきや電気銅めっき、フィルドビアめっき等を用いることができる。エッチングする導体層20の厚みを薄くして微細回路を形成し易くするためには、薄付けの下地めっきの後、めっきレジストを形成し、厚付けめっきを電気銅めっきやフィルドビアめっきで行うのが望ましい。内層回路6は、例えば、層間接続孔21へのめっきを行った後、エッチングによって不要部分の導体層20を除去することにより形成することができる。 Next, as shown in FIGS. 12 (5) and (6), the interlayer connection hole 21 may be formed to form the interlayer connection 5 and the inner layer circuit 6. The interlayer connection 5 can be formed, for example, by forming the interlayer connection hole 21 by using a so-called conformal method and then plating the interlayer connection hole 21. In this plating, electroless copper plating, electrolytic copper plating, filled via plating, or the like can be used as the thick plating after thin electroless copper plating is performed as the base plating. In order to reduce the thickness of the conductor layer 20 to be etched and make it easy to form a fine circuit, it is necessary to form a plating resist after the thin base plating and perform the thick plating by electrolytic copper plating or filled via plating. desirable. The inner layer circuit 6 can be formed, for example, by plating the interlayer connection hole 21 and then removing the unnecessary conductor layer 20 by etching.
 次に、図13(7)、(8)および図14(9)、(10)に示すように、内層回路6や層間接続5の上に、さらに絶縁層3と導体層20を形成し、図12(5)、(6)のときと同様にして、所望の層数となるように、内層回路6や外層回路2、7、層間接続5を形成することもできる。なお、本発明では、内層回路6と外層回路2、7とを合わせて、導体回路という場合がある。 Next, as shown in FIGS. 13 (7), (8) and FIGS. 14 (9), (10), the insulating layer 3 and the conductor layer 20 are further formed on the inner layer circuit 6 and the interlayer connection 5, In the same manner as in FIGS. 12 (5) and (6), the inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 can be formed so as to have a desired number of layers. In the present invention, the inner layer circuit 6 and the outer layer circuits 2 and 7 may be collectively referred to as a conductor circuit.
 次に、図15(11)に示すように、多層金属箔9の第2キャリア金属箔11とベース金属箔12との間で、積層体22を第2キャリア金属箔11とともにコア基板17から物理的に剥離して分離する。このとき、多層金属箔9の第2キャリア金属箔11とベース金属箔12との間の剥離層(図示しない。)は、ベース金属箔12側に移行するのが望ましい。これにより、ベース金属箔12を剥離した後の積層体22側には、第2キャリア金属箔11の表面が露出するので、後工程で行う第2キャリア金属箔11のエッチングが、剥離層によって阻害されることがない。 Next, as shown in FIG. 15 (11), between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9, the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11. Exfoliate and separate. At this time, it is desirable that the release layer (not shown) between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9 is moved to the base metal foil 12 side. As a result, the surface of the second carrier metal foil 11 is exposed on the laminated body 22 side after the base metal foil 12 is peeled off, so that the etching of the second carrier metal foil 11 performed in a later step is hindered by the peel layer. It will not be done.
 次に、図16(12)~(14)に示すように、分離して剥離した積層体22の第2キャリア金属箔11上にエッチングレジスト34を形成して積層体22の第2キャリア金属箔11をエッチングすることにより、前記第1のパターンめっき13を絶縁層3の表面に露出させて埋め込み回路2を形成したり、第1のパターンめっき13上または絶縁層3上に立体回路27を形成する。また、図17(12)~(14)に示すように、分離して剥離した積層体22の第2キャリア金属箔11上に第2のパターンめっき14を行い、第2のパターンめっきを行った部分以外のキャリア金属箔上にエッチングレジストを形成してエッチングを行うことにより、第2のパターンめっき14を行った部分及びエッチングレジストを形成した部分以外の第2キャリア金属箔11をエッチングにより除去し、第1のパターンめっき13を絶縁層3の表面に露出させて埋め込み回路2を形成したり、第1のパターンめっき13上または絶縁層3上に立体回路27を形成することもできる。なお、図16(12)~(14)及び図17(12)~(14)は、図15(11)のように分離した積層体22のうち、下側の部分のみを表している。図16(12)~(14)または図17(12)~(14)の工程により、絶縁層3から第1のパターンめっき13を露出させて形成した埋め込み回路2はフリップチップ接続端子を、積層体表面の第1のパターンめっき上に形成した立体回路27はバンプやピラーを、積層体表面の絶縁層上に形成した立体回路27はダミー端子を形成することができる。これにより、外層回路2を形成する際に、外層回路2の側面がエッチングによって侵食されないため、アンダーカットを生じないので、微細な外層回路2を形成することができる。また、本発明で形成される外層回路2は、絶縁層3に埋め込まれた状態となるため、外層回路2の底面だけでなく、両側の側面も絶縁層3と密着しているため、微細回路であっても、十分な密着性を確保することができる。また、第2キャリア金属箔11として厚さ1μm~5μmの極薄銅箔を用いた場合は、僅かなエッチング量でも第2キャリア金属箔11を除去することができるため、絶縁層3に埋め込まれ、絶縁層3から露出した外層回路2の表面は平坦であり、ワイワーボンディング端子やフリップチップ接続端子とすることで、接続信頼性を確保することができ、半導体素子との接続端子として用いられるのに適している。また、半導体素子との接続端子を、層間接続5と平面視において重なる位置の外層回路2に設けることが可能であるため、半導体素子との接続端子を層間接続5の直上または直下に設けることが可能であり、小型化・高密度化にも対応が可能である。さらに、任意の箇所に立体回路27を形成することによりバンプやピラー、ダミー端子等の種々の導体回路の構成を形成可能であり、第2キャリア金属箔11や第2のパターンめっき14の厚みを変えることで、任意の高さに形成することも可能であるため、種々の半導体素子(図示しない。)や他のパッケージ基板との接続形態に対応することができる。例えば、図18に示すように、本発明のパッケージ基板1の第1のパターンめっき13上に立体回路27を設けてピラーを形成し、トップ基板との接続を行うようにすることで、キャビティを設けなくても、PoPを構成することが可能となる。また、図18に示すように、半導体素子35側のバンプ25がペリフェラル配置(半導体素子35の周囲にバンプ25が並ぶ配置)の場合、フリップチップ接続の際に、半導体素子35を半導体素子搭載用パッケージ基板1側に押し付けると、半導体素子35の中央部が撓んで変形し易いが、ダミー端子(図18では、絶縁層上に形成された立体回路27である。)を設けておくことによって、半導体素子35の下面を支えることができるので、変形を抑制できる。また、ダミー端子を第1のパターンめっきや層間接続5に接続するように形成すると、半導体素子35からの熱を放熱することもできる。このため、信頼性を向上することができる。なお、ダミー端子とは、電気的に独立で電気回路としては機能しないものであり、図16、図17では、絶縁層上に形成されているが、電気的に機能しないようにした第1のパターンめっきや層間接続5に接続されててもよい。 Next, as shown in FIGS. 16 (12) to (14), an etching resist 34 is formed on the second carrier metal foil 11 of the laminated body 22 that has been separated and peeled to form the second carrier metal foil of the laminated body 22. 11 is exposed to expose the first pattern plating 13 on the surface of the insulating layer 3 to form the embedded circuit 2, or the three-dimensional circuit 27 is formed on the first pattern plating 13 or on the insulating layer 3. To do. Also, as shown in FIGS. 17 (12) to (14), the second pattern plating 14 was performed on the second carrier metal foil 11 of the laminate 22 separated and peeled, and the second pattern plating was performed. Etching is performed by forming an etching resist on the carrier metal foil other than the portion, and etching is performed to remove the second carrier metal foil 11 other than the portion where the second pattern plating 14 is formed and the portion where the etching resist is formed. The embedded circuit 2 can be formed by exposing the first pattern plating 13 to the surface of the insulating layer 3, or the three-dimensional circuit 27 can be formed on the first pattern plating 13 or the insulating layer 3. 16 (12) to (14) and FIGS. 17 (12) to (14) show only the lower part of the stacked body 22 separated as shown in FIG. 15 (11). In the embedded circuit 2 formed by exposing the first pattern plating 13 from the insulating layer 3 by the steps of FIGS. 16 (12) to (14) or FIGS. 17 (12) to (14), flip-chip connection terminals are stacked. The three-dimensional circuit 27 formed on the first pattern plating on the surface of the body can form bumps and pillars, and the three-dimensional circuit 27 formed on the insulating layer on the surface of the laminated body can form dummy terminals. As a result, when the outer layer circuit 2 is formed, the side surface of the outer layer circuit 2 is not eroded by etching, so that no undercut occurs, so that the fine outer layer circuit 2 can be formed. Further, since the outer layer circuit 2 formed in the present invention is embedded in the insulating layer 3, not only the bottom surface of the outer layer circuit 2 but also the side surfaces on both sides are in close contact with the insulating layer 3, so that the fine circuit Even so, sufficient adhesion can be ensured. Further, when an ultrathin copper foil having a thickness of 1 μm to 5 μm is used as the second carrier metal foil 11, the second carrier metal foil 11 can be removed even with a slight etching amount, so that it is embedded in the insulating layer 3. The surface of the outer layer circuit 2 exposed from the insulating layer 3 is flat, and by using a wire bonding terminal or a flip chip connection terminal, connection reliability can be ensured and used as a connection terminal with a semiconductor element. Suitable for Further, since the connection terminal with the semiconductor element can be provided in the outer layer circuit 2 at a position overlapping the interlayer connection 5 in plan view, the connection terminal with the semiconductor element is provided directly above or immediately below the interlayer connection 5. It is possible to cope with downsizing and high density. Furthermore, it is possible to form various conductor circuit configurations such as bumps, pillars, dummy terminals, etc. by forming the three-dimensional circuit 27 at an arbitrary location, and the thickness of the second carrier metal foil 11 or the second pattern plating 14 can be reduced. By changing, it can be formed at an arbitrary height, so that it can correspond to various semiconductor elements (not shown) and connection forms with other package substrates. For example, as shown in FIG. 18, a three-dimensional circuit 27 is provided on the first pattern plating 13 of the package substrate 1 of the present invention to form pillars and connect to the top substrate, thereby forming the cavity. Even if it is not provided, PoP can be configured. As shown in FIG. 18, when the bumps 25 on the semiconductor element 35 side are in a peripheral arrangement (arrangement of the bumps 25 around the semiconductor element 35), the semiconductor element 35 is mounted on the semiconductor element during flip chip connection. When pressed against the package substrate 1 side, the central portion of the semiconductor element 35 is easily bent and deformed, but by providing dummy terminals (in FIG. 18, the three-dimensional circuit 27 formed on the insulating layer). Since the lower surface of the semiconductor element 35 can be supported, deformation can be suppressed. Further, if the dummy terminal is formed so as to be connected to the first pattern plating or the interlayer connection 5, the heat from the semiconductor element 35 can be radiated. For this reason, reliability can be improved. The dummy terminal is electrically independent and does not function as an electric circuit. In FIG. 16 and FIG. 17, the dummy terminal is formed on the insulating layer. It may be connected to pattern plating or interlayer connection 5.
 次に、必要に応じてソルダーレジスト4や保護めっき8を形成してもよい。保護めっき8としては、一般的にパッケージ基板の接続端子の保護めっきとして用いられるニッケルめっきと金めっきが望ましい。 Next, solder resist 4 and protective plating 8 may be formed as necessary. As the protective plating 8, nickel plating and gold plating which are generally used as protective plating for connection terminals of the package substrate are desirable.
 以上のように、本発明のパッケージ基板の製造方法によれば、層間接続と重なる位置に平坦でかつ微細な埋め込み回路を有するパッケージ基板を形成することができ、ワイヤーボンディングやフリップチップ接続に適したパッケージ基板を形成することができる。また、任意の箇所に立体回路を形成することによりバンプやピラー等の種々の金属構成を備えるパッケージ基板を形成することができる。 As described above, according to the method for manufacturing a package substrate of the present invention, it is possible to form a package substrate having a flat and fine embedded circuit at a position overlapping with an interlayer connection, which is suitable for wire bonding and flip chip connection. A package substrate can be formed. Further, a package substrate having various metal structures such as bumps and pillars can be formed by forming a three-dimensional circuit at an arbitrary location.
 次に、本発明のパッケージ基板の他の製造方法の実施例について説明するが、本発明は本実施例に限定されない。 Next, examples of another method for manufacturing the package substrate of the present invention will be described, but the present invention is not limited to these examples.
 (実施例1)
 まず、図10に示すように、第1キャリア金属箔10と第2キャリア金属箔11とベース金属箔12とをこの順に積層した多層金属箔9を準備した。第1キャリア金属箔10は9μmの銅箔を、第2キャリア金属箔11は3μmの極薄銅箔を、ベース金属箔12は18μmの銅箔を用いている。ベース金属箔12の表面(第2キャリア金属箔11との間)には、物理的な剥離が可能になるように、剥離層(図示しない。)を設けた。また、第2キャリア金属箔11の表面(第1キャリア金属箔10との間)には、平均粗さ(Ra)0.7μmの凹凸を予め設けた。また、この凹凸の上、つまり第1キャリア金属箔10との間には、物理的な剥離が可能になるように、剥離層(図示しない。)を設けた。ベース金属箔12と第2キャリア金属箔11との間、及び第2キャリア金属箔11と第1キャリア金属箔10との間の剥離層は、何れもNi30g/L、Mo3.0g/L、クエン酸30g/Lの組成を持つめっき浴を用いて金属酸化物層を形成することで形成した。なお、剥離強度の調整は、電流を調整することで、剥離層を形成する金属酸化物量を調整して行った。このときの剥離強度は、ベース金属箔12と第2キャリア金属箔11との間が47N/m、第2キャリア金属箔11と第1キャリア金属箔10との間が29N/mであった。なお、加熱・加圧した後(基材16となるプリプレグを積層してコア基板17を形成した後)の剥離強度の変化率は、初期に対して約10%程度上昇した程度であった。
Example 1
First, as shown in FIG. 10, a multilayer metal foil 9 in which a first carrier metal foil 10, a second carrier metal foil 11, and a base metal foil 12 were laminated in this order was prepared. The first carrier metal foil 10 is a 9 μm copper foil, the second carrier metal foil 11 is a 3 μm ultrathin copper foil, and the base metal foil 12 is an 18 μm copper foil. A release layer (not shown) was provided on the surface of the base metal foil 12 (between the second carrier metal foil 11) so that physical peeling was possible. Further, the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) was previously provided with irregularities having an average roughness (Ra) of 0.7 μm. In addition, a release layer (not shown) was provided on the unevenness, that is, between the first carrier metal foil 10 so as to allow physical peeling. The release layers between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni 30 g / L, Mo 3.0 g / L, It formed by forming a metal oxide layer using the plating bath which has a composition of acid 30g / L. The peel strength was adjusted by adjusting the amount of metal oxide forming the peel layer by adjusting the current. The peel strength at this time was 47 N / m between the base metal foil 12 and the second carrier metal foil 11, and 29 N / m between the second carrier metal foil 11 and the first carrier metal foil 10. Note that the rate of change in peel strength after heating and pressing (after forming the core substrate 17 by laminating the prepreg serving as the base material 16) was about 10% higher than the initial level.
 図10に示す多層金属箔9の作製は、具体的には以下のように行った。
(1)ベース金属箔12として、厚さ18μmの電解銅箔を用い、硫酸30g/Lに60秒浸漬して酸洗浄後に流水で30秒間水洗を行った。
(2)洗浄した電解銅箔を陰極とし、酸化イリジウムコーテイングを施したTi(チタン)極板を陽極とし、Ni(ニッケル)、Mo(モリブデン)、クエン酸を含有するめっき浴として、硫酸ニッケル6水和物30g/L、モリブデン酸ナトリウム2水和物3.0g/L、クエン酸3ナトリウム2水和物30g/L、pH6.0、液温度30℃の浴にて、電解銅箔の光沢面に、電流密度20A/dmで5秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層(図示しない。)を形成した。
(3)剥離層(図示しない。)を形成後の表面に、硫酸銅5水和物200g/L、硫酸100g/L、液温度40℃の浴にて、酸化イリジウムコーテイングを施したTi(チタン)極板を陽極として、電流密度4A/dmで200秒間電解めっきを行い、厚さ3μmの第2キャリア金属箔11となる金属層を形成した。
(4)第2キャリア金属箔11となる金属層を形成した後の表面に、上記(2)と同様の浴を用いて、電流密度10A/dmで10秒間電解処理し、ニッケルとモリブデンからなる金属酸化物を含有する剥離層(図示しない。)を形成した。
(5)剥離層13を形成した後の表面に、上記(3)と同様の浴を用いて、電流密度4A/dmで600秒間電解めっきを行い厚さ9μmの第1キャリア金属箔10となる金属層を形成した。
(6)基材16と接触する面に、硫酸銅めっきにより粒状の粗化粒子を形成し、クロメート処理及びシランカップリング剤処理を施した。また、基材16と接しない面にはクロメート処理を施した。
Specifically, the multilayer metal foil 9 shown in FIG. 10 was produced as follows.
(1) As the base metal foil 12, an electrolytic copper foil having a thickness of 18 μm was used, immersed in sulfuric acid 30 g / L for 60 seconds, washed with acid and then washed with running water for 30 seconds.
(2) Nickel sulfate 6 as a plating bath containing Ni (nickel), Mo (molybdenum), and citric acid as a cathode, using a washed electrolytic copper foil as a cathode, a Ti (titanium) electrode plate coated with iridium oxide as an anode Hydration of electrolytic copper foil in a bath of 30 g / L hydrate, 3.0 g / L sodium molybdate dihydrate, 30 g / L trisodium citrate dihydrate, pH 6.0, liquid temperature 30 ° C. Electrolytic treatment was performed on the surface at a current density of 20 A / dm 2 for 5 seconds to form a release layer (not shown) containing a metal oxide composed of nickel and molybdenum.
(3) Ti (titanium) coated with iridium oxide coating in a bath of copper sulfate pentahydrate 200 g / L, sulfuric acid 100 g / L, and liquid temperature 40 ° C. on the surface after the release layer (not shown) is formed. ) Using the electrode plate as an anode, electrolytic plating was performed at a current density of 4 A / dm 2 for 200 seconds to form a metal layer to be the second carrier metal foil 11 having a thickness of 3 μm.
(4) The surface after forming the metal layer to be the second carrier metal foil 11 is subjected to electrolytic treatment at a current density of 10 A / dm 2 for 10 seconds using the same bath as in the above (2), from nickel and molybdenum. A release layer (not shown) containing a metal oxide was formed.
(5) The surface after forming the release layer 13 is subjected to electrolytic plating at a current density of 4 A / dm 2 for 600 seconds using the same bath as the above (3), and the first carrier metal foil 10 having a thickness of 9 μm A metal layer was formed.
(6) Granular roughened particles were formed on the surface in contact with the substrate 16 by copper sulfate plating, and subjected to chromate treatment and silane coupling agent treatment. Further, the chromate treatment was applied to the surface not in contact with the substrate 16.
 次に、図11(1)に示すように、多層金属箔9のベース金属箔12側と基材16とを積層してコア基板17を形成した。基材16としてガラスエポキシのプリプレグを用い、このプリプレグの上下両側に多層金属箔9を重ねて、熱プレスを用いて加熱・加圧して積層一体化した。 Next, as shown in FIG. 11 (1), the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 were laminated to form a core substrate 17. A glass epoxy prepreg was used as the substrate 16, and the multilayer metal foils 9 were stacked on both upper and lower sides of the prepreg, and were laminated and integrated by heating and pressing using a hot press.
 次に、図11(2)に示すように、多層金属箔9の第1キャリア金属箔10と第2キャリア金属箔11との間で、第1キャリア金属箔10を物理的に剥離した。 Next, as shown in FIG. 11 (2), the first carrier metal foil 10 was physically peeled between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9.
 次に、図11(3)に示すように、コア基板17に残った第2キャリア金属箔11上に第1のパターンめっき13を行った。第1のパターンめっき13は、第2キャリア金属箔11上に、感光性のめっきレジストを形成した後、硫酸銅電気めっきを用いて形成した。 Next, as shown in FIG. 11 (3), the first pattern plating 13 was performed on the second carrier metal foil 11 remaining on the core substrate 17. The first pattern plating 13 was formed using copper sulfate electroplating after forming a photosensitive plating resist on the second carrier metal foil 11.
 次に、図12(4)に示すように、第1のパターンめっき13を含む第2キャリア金属箔11上に絶縁層3と導体層20として銅箔(12μm)を積層して積層体22を形成した。絶縁層3としては、エポキシ系の接着シートを熱プレスを用い、加熱・加圧して積層一体化することで形成した。 Next, as shown in FIG. 12 (4), a copper foil (12 μm) is laminated as the insulating layer 3 and the conductor layer 20 on the second carrier metal foil 11 including the first pattern plating 13 to form a laminate 22. Formed. The insulating layer 3 was formed by laminating and integrating an epoxy adhesive sheet by heating and pressing using a hot press.
 次に、図12(5)、(6)に示すように、層間接続5や内層回路6を形成した。層間接続5は、コンフォーマル工法を用いて層間接続孔21を形成した後、この層間接続孔21内をめっきすることで形成した。このめっきには、下地めっきとして薄付け無電解銅めっきを行った後、感光性のめっきレジストを形成し、厚付けめっきを硫酸銅電気めっきで行った。この後、エッチングによって不要部分の導体層20を除去することにより内層回路6を形成した。 Next, as shown in FIGS. 12 (5) and (6), the interlayer connection 5 and the inner layer circuit 6 were formed. The interlayer connection 5 was formed by forming the interlayer connection hole 21 using a conformal method and then plating the interior of the interlayer connection hole 21. In this plating, thin electroless copper plating was performed as a base plating, a photosensitive plating resist was formed, and thick plating was performed by copper sulfate electroplating. Thereafter, the inner layer circuit 6 was formed by removing the unnecessary conductor layer 20 by etching.
 次に、図13(7)、(8)および図14(9)、(10)に示すように、内層回路6や層間接続5の上に、さらに絶縁層3と導体層20を形成し、内層回路6や外層回路2、7、層間接続5を形成して、4層の導体層20を有する積層体22を形成した。 Next, as shown in FIGS. 13 (7), (8) and FIGS. 14 (9), (10), the insulating layer 3 and the conductor layer 20 are further formed on the inner layer circuit 6 and the interlayer connection 5, The inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 were formed to form a laminate 22 having four conductor layers 20.
 次に、図15(11)に示すように、多層金属箔9の第2キャリア金属箔11とベース金属箔12との間で、積層体22を第2キャリア金属箔11とともにコア基板17から物理的に剥離して分離した。 Next, as shown in FIG. 15 (11), between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9, the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11. Peeled off and separated.
 次に、図16(12)~(14)に示すように、分離して剥離した積層体22の第2キャリア金属箔11上にエッチングレジスト14を形成して積層体22の第2キャリア金属箔11をエッチングして、前記第1のパターンめっき13を前記絶縁層3の表面に露出させて埋め込み回路2を形成するとともに、第1のパターンめっき13上または絶縁層3上に立体回路27を形成した。なお、絶縁層3から第1のパターンめっき13を露出させて形成した埋め込み回路2はフリップチップ接続端子とし、積層体表面の第1のパターンめっき上に形成した立体回路27はバンプとし、積層体表面の絶縁層上に形成した立体回路27はダミー端子とした。 Next, as shown in FIGS. 16 (12) to (14), an etching resist 14 is formed on the second carrier metal foil 11 of the laminated body 22 that has been separated and peeled, and the second carrier metal foil of the laminated body 22 is formed. 11 is etched to expose the first pattern plating 13 on the surface of the insulating layer 3 to form the embedded circuit 2 and to form the three-dimensional circuit 27 on the first pattern plating 13 or on the insulating layer 3. did. The embedded circuit 2 formed by exposing the first pattern plating 13 from the insulating layer 3 is a flip chip connection terminal, the three-dimensional circuit 27 formed on the first pattern plating on the surface of the laminate is a bump, and the laminate The solid circuit 27 formed on the insulating layer on the surface was a dummy terminal.
 次に、感光性のソルダーレジストを形成し、その後、保護めっきとして、無電解ニッケルめっきと無電解金めっきを行い、パッケージ基板を形成した。 Next, a photosensitive solder resist was formed, and then electroless nickel plating and electroless gold plating were performed as protective plating to form a package substrate.
 (実施例2)
 ベース金属箔12と第2キャリア金属箔11との間、及び第2キャリア金属箔11と第1キャリア金属箔10との間の剥離強度を、何れもNi(ニッケル)30g/L、Mo(モリブデン)3.0g/L、クエン酸30g/Lの組成を持つめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層を形成する金属酸化物量を調整して変化させた。このときの剥離強度は、ベース金属箔12と第2キャリア金属箔11との間が23N/m、第2キャリア金属箔11と第1キャリア金属箔10との間が18N/mであった。これ以外は実施例1と同様にしてパッケージ基板を作製した。
(Example 2)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). ) By changing the current when forming the metal oxide layer using a plating bath with a composition of 3.0 g / L and citric acid 30 g / L, the amount of metal oxide forming the release layer is adjusted and changed. It was. The peel strength at this time was 23 N / m between the base metal foil 12 and the second carrier metal foil 11, and 18 N / m between the second carrier metal foil 11 and the first carrier metal foil 10. A package substrate was fabricated in the same manner as in Example 1 except for this.
 (実施例3)
 ベース金属箔12と第2キャリア金属箔11との間、及び第2キャリア金属箔11と第1キャリア金属箔10との間の剥離強度を、何れもNi(ニッケル)30g/L、Mo(モリブデン)3.0g/L、クエン酸30g/Lの組成を持つめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層を形成する金属酸化物量を調整して変化させた。このときの剥離強度は、ベース金属箔12と第2キャリア金属箔11との間が15N/m、第2キャリア金属箔11と第1キャリア金属箔10との間が2N/mであった。これ以外は実施例1と同様にしてパッケージ基板を作製した。
(Example 3)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). ) By changing the current when forming the metal oxide layer using a plating bath with a composition of 3.0 g / L and citric acid 30 g / L, the amount of metal oxide forming the release layer is adjusted and changed. It was. The peel strength at this time was 15 N / m between the base metal foil 12 and the second carrier metal foil 11, and 2 N / m between the second carrier metal foil 11 and the first carrier metal foil 10. A package substrate was fabricated in the same manner as in Example 1 except for this.
 (実施例4)
 ベース金属箔12と第2キャリア金属箔11との間、及び第2キャリア金属箔11と第1キャリア金属箔10との間の剥離強度を、何れもNi(ニッケル)30g/L、Mo(モリブデン)3.0g/L、クエン酸30g/Lの組成を持つめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層を形成する金属酸化物量を調整して変化させた。このときの剥離強度は、ベース金属箔12と第2キャリア金属箔11との間が68N/m、第2キャリア金属箔11と第1キャリア金属箔10との間が48N/mであった。
Example 4
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). ) By changing the current when forming the metal oxide layer using a plating bath with a composition of 3.0 g / L and citric acid 30 g / L, the amount of metal oxide forming the release layer is adjusted and changed. It was. The peel strength at this time was 68 N / m between the base metal foil 12 and the second carrier metal foil 11, and 48 N / m between the second carrier metal foil 11 and the first carrier metal foil 10.
 上記で準備した多層金属箔9を用い、実施例1の図16(12)~(14)に示す工程の代わりに、図17(12)~(14)に示すように、分離して剥離した積層体22の第2キャリア金属箔11上に第2のパターンめっき14を行い、第2のパターンめっきを行った部分以外のキャリア金属箔上にエッチングレジスト34を形成してエッチングを行い、第2のパターンめっき14を行った部分及びエッチングレジストを形成した部分以外の第2キャリア金属箔11をエッチングにより除去し、第1のパターンめっき13を絶縁層3の表面に露出させて埋め込み回路2を形成するとともに、第1のパターンめっき13上または絶縁層3上に立体回路27を形成した。なお、絶縁層3から第1のパターンめっき13を露出させて形成した埋め込み回路2はフリップチップ接続端子とし、積層体表面の第1のパターンめっき上に形成した立体回路27はピラーとし、積層体表面の絶縁層上に形成した立体回路27はダミー端子とした。この工程以外は、実施例1と同様にしてパッケージ基板を作製した。 Using the multilayer metal foil 9 prepared above, instead of the steps shown in FIGS. 16 (12) to (14) of Example 1, separation and peeling were performed as shown in FIGS. 17 (12) to (14). The second pattern plating 14 is performed on the second carrier metal foil 11 of the laminated body 22, the etching resist 34 is formed on the carrier metal foil other than the portion where the second pattern plating is performed, and etching is performed. The second carrier metal foil 11 other than the portion where the pattern plating 14 is performed and the portion where the etching resist is formed is removed by etching, and the first pattern plating 13 is exposed on the surface of the insulating layer 3 to form the embedded circuit 2. In addition, a three-dimensional circuit 27 was formed on the first pattern plating 13 or the insulating layer 3. The embedded circuit 2 formed by exposing the first pattern plating 13 from the insulating layer 3 is a flip chip connection terminal, the three-dimensional circuit 27 formed on the first pattern plating on the surface of the stacked body is a pillar, and the stacked body The solid circuit 27 formed on the insulating layer on the surface was a dummy terminal. A package substrate was fabricated in the same manner as in Example 1 except for this step.
 (実施例5)
 ベース金属箔12と第2キャリア金属箔11との間、及び第2キャリア金属箔11と第1キャリア金属箔10との間の剥離強度を、何れもNi(ニッケル)30g/L、Mo(モリブデン)3.0g/L、クエン酸30g/Lの組成を持つめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層を形成する金属酸化物量を調整して変化させた。このときの剥離強度は、ベース金属箔12と第2キャリア金属箔11との間が43N/m、第2キャリア金属箔11と第1キャリア金属箔10との間が28N/mであった。これ以外は実施例4と同様にしてパッケージ基板を作製した。
(Example 5)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). ) By changing the current when forming the metal oxide layer using a plating bath with a composition of 3.0 g / L and citric acid 30 g / L, the amount of metal oxide forming the release layer is adjusted and changed. It was. The peel strength at this time was 43 N / m between the base metal foil 12 and the second carrier metal foil 11, and 28 N / m between the second carrier metal foil 11 and the first carrier metal foil 10. A package substrate was fabricated in the same manner as in Example 4 except for this.
 (実施例6)
 ベース金属箔12と第2キャリア金属箔11との間、及び第2キャリア金属箔11と第1キャリア金属箔10との間の剥離強度を、何れもNi(ニッケル)30g/L、Mo(モリブデン)3.0g/L、クエン酸30g/Lの組成を持つめっき浴を用いて金属酸化物層を形成する際の電流を変えることで、剥離層を形成する金属酸化物量を調整して変化させた。このときの剥離強度は、ベース金属箔12と第2キャリア金属箔11との間が22N/m、第2キャリア金属箔11と第1キャリア金属箔10との間が4N/mであった。これ以外は実施例4と同様にしてパッケージ基板を作製した。
(Example 6)
The peel strengths between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 are both Ni (nickel) 30 g / L and Mo (molybdenum). ) By changing the current when forming the metal oxide layer using a plating bath with a composition of 3.0 g / L and citric acid 30 g / L, the amount of metal oxide forming the release layer is adjusted and changed. It was. The peel strength at this time was 22 N / m between the base metal foil 12 and the second carrier metal foil 11, and 4 N / m between the second carrier metal foil 11 and the first carrier metal foil 10. A package substrate was fabricated in the same manner as in Example 4 except for this.
 表1に、実施例1~6について、絶縁層3に埋め込まれて形成された外層回路2の仕上がり状態、第1キャリア金属箔10と第2キャリア金属箔11との間の剥離強度、第2キャリア金属箔11とベース金属箔12との間の剥離強度、ハンドリング時のキャリア金属箔の剥れの有無を示す。実施例1~6の何れもライン/スペースが10μm/10μmまでの微細な外層回路2を形成することができた(表1の“○”は、アンダーカットのないことを示す。)。また、断面を観察した結果、何れもアンダーカットは生じていなかった。さらに、断面の観察結果から、第2キャリア金属箔11は3μmの極薄銅を用いているため、僅かなエッチング量で均一に除去されており、外層回路2の表面の凹凸は平坦であった。また、実施例1~6の何れも、製造工程でのハンドリングで第1キャリア金属箔10と第2キャリア金属箔11との間や、第2キャリア金属箔11とベース金属箔12との間が剥離することはなかった(表1の“○”は、剥れがないことを示す。)。また、第1キャリア金属箔10と第2キャリア金属箔11との間で剥離する際に、第2キャリア金属箔11とベース金属箔12との間が剥離することはなかった。 Table 1 shows the finished state of the outer layer circuit 2 embedded in the insulating layer 3 for Examples 1 to 6, the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11, the second The peel strength between the carrier metal foil 11 and the base metal foil 12 and the presence or absence of peeling of the carrier metal foil during handling are shown. In each of Examples 1 to 6, it was possible to form a fine outer layer circuit 2 having a line / space of 10 μm / 10 μm (“◯” in Table 1 indicates no undercut). In addition, as a result of observing the cross section, no undercut had occurred. Further, from the observation result of the cross section, since the second carrier metal foil 11 is made of ultra-thin copper having a thickness of 3 μm, it is uniformly removed with a slight etching amount, and the surface irregularities of the outer circuit 2 are flat. . Also, in all of Examples 1 to 6, there is a gap between the first carrier metal foil 10 and the second carrier metal foil 11 or between the second carrier metal foil 11 and the base metal foil 12 by handling in the manufacturing process. There was no peeling (“◯” in Table 1 indicates no peeling). Further, when peeling between the first carrier metal foil 10 and the second carrier metal foil 11, there was no peeling between the second carrier metal foil 11 and the base metal foil 12.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
 図18に示すように、実施例4で作製したパッケージ基板(図17(14))の埋め込み回路2に、半導体素子35のバンプ25を押し付け、はんだ(図示しない。)を用いてフリップチップ接続した。半導体素子35は、バンプ25がペリフェラル配置であったが、半導体素子35の下面をダミー端子となる立体回路27が支えていたため、半導体素子35に撓みは生じなかった。 As shown in FIG. 18, the bump 25 of the semiconductor element 35 is pressed against the embedded circuit 2 of the package substrate (FIG. 17 (14)) manufactured in the fourth embodiment, and is flip-chip connected using solder (not shown). . In the semiconductor element 35, the bumps 25 are in a peripheral arrangement, but the lower surface of the semiconductor element 35 is supported by the three-dimensional circuit 27 serving as a dummy terminal, so that the semiconductor element 35 is not bent.
 加熱・加圧する前(基材16となるプリプレグを積層してコア基板17を形成する前)の初期の剥離強度(N/m)の測定は、10mm幅にカットした多層金属箔のサンプルを作製し、テンシロンRTM-100(株式会社オリエンテック製、商品名、「テンシロン」は登録商標。)を用い、JIS Z 0237の90度引き剥がし法に準じて、室温(25℃)で、まず、第1キャリア金属箔を90度方向に毎分300mmの速さで引き剥がして測定し、次に、第2キャリア金属箔を90度方向に毎分300mmの速さで引き剥がして測定した。また、加熱・加圧した後(基材16となるプリプレグを積層してコア基板17を形成した後)の剥離強度も、初期の剥離強度と同様にして測定し、初期に対する変化率を求めた。なお、多層金属箔9と基材16となるガラスエポキシプリプレグとを積層してコア基板17を形成する際の加熱・加圧の条件は、真空プレスを用いて、圧力3MPa、温度175℃、保持時間1.5hr(時間)である。 Measurement of the initial peel strength (N / m) before heating / pressurization (before forming the core substrate 17 by laminating the prepreg to be the base material 16) is made of a multilayer metal foil sample cut to a width of 10 mm. Then, using Tensilon RTM-100 (made by Orientec Co., Ltd., trade name, “Tensilon” is a registered trademark), according to JIS Z 0237 90 degree peeling method, One carrier metal foil was peeled off at a speed of 300 mm / min in the 90 ° direction, and then the second carrier metal foil was peeled off at a speed of 300 mm / min in the 90 ° direction. Further, the peel strength after heating and pressurization (after forming the core substrate 17 by laminating the prepreg as the base material 16) was also measured in the same manner as the initial peel strength, and the rate of change relative to the initial value was obtained. . In addition, the conditions of the heating and pressurization when laminating the multilayer metal foil 9 and the glass epoxy prepreg serving as the base material 16 to form the core substrate 17 are as follows: a pressure of 3 MPa, a temperature of 175.degree. The time is 1.5 hours (hours).
 以下、本発明を実施例によって具体的に説明するが、本発明はこれらの実施例に限定されない。 Hereinafter, the present invention will be specifically described by way of examples, but the present invention is not limited to these examples.
 (実施例7)
 実施例1と同様の方法で、埋め込み回路のフリップチップ端子を有するパッケージ基板を作製した。ここで、パッケージ基板上に形成されたソルダーレジストには開口が設けられ、この開口内にはライン/スペースが20μm/20μm(40μmピッチ)のフリップチップ接続端子となる埋込回路が配置されている。ソルダーレジストの開口によって規定されるフリップチップ接続端子の長手方向の寸法(フリップチップ接続端子の長さ)は、約100μmである。
(Example 7)
In the same manner as in Example 1, a package substrate having a flip chip terminal of an embedded circuit was produced. Here, an opening is provided in the solder resist formed on the package substrate, and an embedded circuit serving as a flip chip connection terminal having a line / space of 20 μm / 20 μm (40 μm pitch) is disposed in the opening. . The dimension in the longitudinal direction of the flip chip connection terminal (the length of the flip chip connection terminal) defined by the opening of the solder resist is about 100 μm.
 次に、フリップチップ接続端子となる埋込回路上に、はんだペーストを印刷しリフローすることによって予備はんだを形成した。予備はんだ用のはんだペーストには、Sn(スズ)-Ag(銀)-Cu(銅)系のエコソルダーM705(千住金属工業株式会社製、商品名。エコソルダーは、登録商標。)を用い、リフローには赤外線リフロー装置を用いて、ピーク温度260℃の条件で行なった。 Next, preliminary solder was formed by printing a solder paste on the embedded circuit to be the flip chip connection terminal and reflowing. Sn (tin) -Ag (silver) -Cu (copper) -based eco-solder M705 (trade name, manufactured by Senju Metal Industry Co., Ltd., Eco-Solder is a registered trademark) is used as a pre-solder solder paste. The reflow was performed using an infrared reflow apparatus at a peak temperature of 260 ° C.
 次に、パッケージサイズに切断加工を施した。この切断加工されたパッケージ基板は、図2に示すように、絶縁層3と、この絶縁層3の表面に上面が露出するように設けられた埋込回路2と、絶縁層3上及び埋込回路2上に設けられたソルダーレジスト4とを有し、このソルダーレジスト4に設けられた開口31内の埋込回路2がフリップチップ接続端子26を形成している。また、このフリップチップ接続端子26を被覆する予備はんだ19の厚さは、3~5μmである。ここで、はんだの厚さは、非接触段差測定機であるハイソメット(ユニオン光学株式会社製、商品名。ハイソメットは登録商標。)を用い、予備はんだ19を形成する前後において、ソルダージストとフリップチップ接続端子26との段差を測定することにより測定した。 Next, the package size was cut. As shown in FIG. 2, the cut package substrate includes an insulating layer 3, an embedded circuit 2 provided so that the upper surface is exposed on the surface of the insulating layer 3, the insulating layer 3 and the embedded substrate The solder resist 4 provided on the circuit 2 and the embedded circuit 2 in the opening 31 provided in the solder resist 4 form the flip chip connection terminal 26. The thickness of the preliminary solder 19 that covers the flip chip connection terminal 26 is 3 to 5 μm. Here, the thickness of the solder is a solder jist and a flip chip before and after forming the preliminary solder 19 using Hi-Somet (trade name, made by Union Optical Co., Ltd., registered trademark), which is a non-contact level difference measuring machine. It measured by measuring the level | step difference with the connection terminal 26. FIG.
 図9に示すように、パッケージ基板1を作製した後、半導体素子15をフリップチップ接続により搭載した。フリップチップ接続は、パッケージ基板1上のフリップチップ接続端子26と半導体素子15のバンプ25(銅ピラー上にSn(スズ)-3.0質量%Ag(銀)-0.5質量%Cu(銅)はんだを形成したもので、40μmピッチ、高さ25μm。)とが対向するように位置合わせした後、超音波フリップチップボンダーSH-50MP(株式会社アルテクス製、製品名)を用いてフリップチップ接続を行なった。フリップチップ接続の圧着条件は、超音波を併用しつつ、230℃に昇温し1バンプ当たり50gの加圧を行いながら、4秒間保持した。その後、半導体素子15のバンプ25形成面と、パッケージ基板1のフリップチップ接続端子26を有する絶縁層3との間に、アンダーフィル剤23を充填し、半導体パッケージ24を得た。 As shown in FIG. 9, after producing the package substrate 1, the semiconductor element 15 was mounted by flip chip connection. The flip chip connection is performed by using the flip chip connection terminal 26 on the package substrate 1 and the bump 25 of the semiconductor element 15 (Sn (tin) -3.0 mass% Ag (silver) -0.5 mass% Cu (copper on the copper pillar). ) Solder formed, 40μm pitch, 25μm height)) After positioning so as to face each other, flip chip bonding using ultrasonic flip chip bonder SH-50MP (product name, manufactured by Altex Co., Ltd.) Was done. The crimping conditions for flip chip connection were held for 4 seconds while raising the temperature to 230 ° C. and applying 50 g per bump while using ultrasonic waves. Thereafter, an underfill agent 23 was filled between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26 of the package substrate 1 to obtain a semiconductor package 24.
 (実施例8)
 フリップチップ接続端子を被覆する予備はんだの厚さは、7~10μmである。これ以外は、実施例7と同様にして、第10の回路基板及び半導体パッケージを得た。
(Example 8)
The thickness of the pre-solder covering the flip chip connection terminal is 7 to 10 μm. A tenth circuit board and a semiconductor package were obtained in the same manner as in Example 7 except for the above.
 (実施例9)
 フリップチップ接続端子を被覆する予備はんだの厚さは、17~20μmである。これ以外は、実施例7と同様にして、パッケージ基板及び半導体パッケージを得た。
Example 9
The thickness of the pre-solder covering the flip chip connection terminal is 17 to 20 μm. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in Example 7.
 (比較例1)
 フリップチップ接続端子を被覆する予備はんだの厚さは、1~2μmである。これ以外は、実施例7と同様にして、パッケージ基板及び半導体パッケージを得た。
(Comparative Example 1)
The thickness of the pre-solder covering the flip chip connection terminal is 1 to 2 μm. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in Example 7.
 (参考例1)
 フリップチップ接続端子を被覆する予備はんだの厚さは、25~28μmである。これ以外は、実施例7と同様にして、パッケージ基板及び半導体パッケージを得た。
(Reference Example 1)
The thickness of the pre-solder covering the flip chip connection terminal is 25 to 28 μm. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in Example 7.
 (実施例10)
 実施例7と同様にして、フリップチップ接続端子となる埋込回路上に、予備はんだを形成した。ここで、図5に示すように、ソルダーレジスト4には開口31が設けられ、この開口31内にはフリップチップ接続端子26となる埋込回路2が配置されている。また、フリップチップ接続端子26を含む埋込回路2の底面にビア18が接続されている。これ以降は、実施例7と同様にして、パッケージ基板及び半導体パッケージを形成した。
(Example 10)
In the same manner as in Example 7, preliminary solder was formed on the embedded circuit to be the flip chip connection terminal. Here, as shown in FIG. 5, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. A via 18 is connected to the bottom surface of the embedded circuit 2 including the flip chip connection terminal 26. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in Example 7.
 (実施例11)
 実施例4と同様の方法で、図17(12)~(14)に示すように、第2キャリア金属箔11上に第2のパターンめっき14を行い、埋込回路のフリップチップ接続端子となる箇所の一部に、凸形状(立体回路)を形成した。ソルダーレジスト形成、保護めっきとしてのニッケル/金めっき(ニッケルめっきとその上に金めっき)を形成した。ここで、図6に示すように、ソルダーレジスト4には開口31が設けられ、この開口31内にはフリップチップ接続端子26となる埋込回路2が配置されている。また、フリップチップ接続端子26の長手方向の一部には、凸形状27が形成されており、この凸形状27の高さは5μm程度である。凸形状27の範囲はフリップチップ接続端子26の短手方向の寸法の100%で、フリップチップ接続端子26の長手方向の寸法の30%程度である。これ以降は、実施例7と同様にして、パッケージ基板及び半導体パッケージを形成した。
(Example 11)
As shown in FIGS. 17 (12) to (14), the second pattern plating 14 is performed on the second carrier metal foil 11 by the same method as that of the fourth embodiment, and the flip chip connection terminal of the embedded circuit is obtained. A convex shape (three-dimensional circuit) was formed in a part of the portion. Solder resist formation and nickel / gold plating (nickel plating and gold plating thereon) were formed as protective plating. Here, as shown in FIG. 6, an opening 31 is provided in the solder resist 4, and an embedded circuit 2 serving as a flip chip connection terminal 26 is disposed in the opening 31. Further, a convex shape 27 is formed on a part of the flip chip connection terminal 26 in the longitudinal direction, and the height of the convex shape 27 is about 5 μm. The range of the convex shape 27 is 100% of the dimension in the short direction of the flip chip connection terminal 26 and about 30% of the dimension in the longitudinal direction of the flip chip connection terminal 26. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in Example 7.
 (実施例12)
 実施例1と同様にして、埋め込み回路のフリップチップ端子を有するパッケージ基板を作製した。その後、エッチングレジストを形成し、上面が露出した埋込回路の上面の一部が絶縁層の表面よりも凹み、他の部分はそのまま残るようにエッチングすることによって凹み形状を形成した。その後、ソルダーレジスト形成、保護めっきとしてのニッケル/金めっき(ニッケルめっきとその上に金めっき)を形成した。ここで、図7に示すように、ソルダーレジスト4には開口31が設けられ、この開口31内にはフリップチップ接続端子26となる埋込回路2が配置されている。また、フリップ接続端子26の長手方向の一部には、凹み形状28が形成されており、この凹み形状28の深さは5μm程度である。凹み形状28の範囲はフリップチップ接続端子26の短手方向の寸法の100%で、フリップチップ接続端子26の長手方向の寸法の30%程度である。これ以降は、実施例7と同様にして、パッケージ基板)及び半導体パッケージを形成した。
(Example 12)
In the same manner as in Example 1, a package substrate having flip-chip terminals for embedded circuits was produced. After that, an etching resist was formed, and a recessed shape was formed by etching so that a part of the upper surface of the embedded circuit whose upper surface was exposed was recessed from the surface of the insulating layer and the other part remained as it was. Thereafter, solder resist formation and nickel / gold plating (nickel plating and gold plating thereon) were formed as protective plating. Here, as shown in FIG. 7, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. Further, a concave shape 28 is formed in a part of the flip connection terminal 26 in the longitudinal direction, and the depth of the concave shape 28 is about 5 μm. The range of the recessed shape 28 is 100% of the dimension in the short direction of the flip chip connection terminal 26 and about 30% of the dimension in the longitudinal direction of the flip chip connection terminal 26. Thereafter, the package substrate) and the semiconductor package were formed in the same manner as in Example 7.
 (実施例13)
 実施例7と同様にして、埋め込み回路のフリップチップ端子を有するパッケージ基板を作製した。ここで、図3に示すように、ソルダーレジスト4には開口31が設けられ、この開口31内には、フリップチップ接続端子26となる埋込回路2が配置されている。また、フリップチップ接続端子26の先端は、ソルダーレジスト4の開口31内に形成されている。これ以降は、実施例7と同様にして、パッケージ基板及び半導体パッケージを形成した。
(Example 13)
In the same manner as in Example 7, a package substrate having flip-chip terminals for embedded circuits was produced. Here, as shown in FIG. 3, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. The tip of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in Example 7.
 (実施例14)
 実施例7と同様にして、埋め込み回路のフリップチップ端子を有するパッケージ基板を作製した。ここで、図4に示すように、ソルダーレジスト4には開口31が設けられ、この開口31内には、フリップチップ接続端子26となる埋込回路2が配置されている。また、フリップチップ接続端子26の長手方向の両側または片側に延長された埋込回路2が設けられている。これ以降は、実施例7と同様にして、パッケージ基板及び半導体パッケージを形成した。
(Example 14)
In the same manner as in Example 7, a package substrate having flip-chip terminals for embedded circuits was produced. Here, as shown in FIG. 4, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. In addition, the embedded circuit 2 is provided that extends to both sides or one side of the flip chip connection terminal 26 in the longitudinal direction. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in Example 7.
 (実施例15)
 実施例7と同様にして、埋め込み回路のフリップチップ端子を有するパッケージ基板を作製した。ここで、図8に示すように、ソルダーレジスト4には開口31が設けられ、この開口31内には、フリップチップ接続端子26となる埋込回路2が配置されている。また、フリップチップ接続端子26の長手方向の一部が、短手方向(幅方向)に拡張された部分33を形成している。つまり、フリップチップ接続端子26が部分的に短手方向(幅方向)に拡張された部分33を形成している。これ以降は、実施例7と同様にして、パッケージ基板及び半導体パッケージを形成した。
(Example 15)
In the same manner as in Example 7, a package substrate having flip-chip terminals for embedded circuits was produced. Here, as shown in FIG. 8, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. Further, a part of the flip chip connection terminal 26 in the longitudinal direction forms a portion 33 extended in the short direction (width direction). That is, the flip chip connection terminal 26 forms a portion 33 that is partially expanded in the lateral direction (width direction). Thereafter, the package substrate and the semiconductor package were formed in the same manner as in Example 7.
 (比較例2)
 実施例7と同様にして、埋め込み回路のフリップチップ端子を有するパッケージ基板を作製した。ここで、図16(14)に示すように、埋め込み回路2のフリップチップ接続端子が配置されている面の反対面には、図1に示すのと同様な、凸状回路による回路パターン(外層回路7)が配置されている。
(Comparative Example 2)
In the same manner as in Example 7, a package substrate having flip-chip terminals for embedded circuits was produced. Here, as shown in FIG. 16 (14), a circuit pattern (outer layer) by a convex circuit similar to that shown in FIG. 1 is formed on the surface opposite to the surface on which the flip-chip connection terminals of the embedded circuit 2 are arranged. A circuit 7) is arranged.
 次に、この凸状回路による回路パターン(外層回路7)上に、ソルダーレジスト形成、保護めっきとしてのニッケル/金めっき(ニッケルめっきとその上に金めっき)形成を行った。ここで、ソルダーレジストには開口が設けられ、この開口内にはライン/スペースが20μm/20μm(40μmピッチ)のフリップチップ接続端子となる、凸状回路による回路パターンが配置されている。 Next, solder resist formation and nickel / gold plating (nickel plating and gold plating thereon) formation as a protective plating were performed on the circuit pattern (outer layer circuit 7) by this convex circuit. Here, an opening is provided in the solder resist, and a circuit pattern by a convex circuit that is a flip chip connection terminal having a line / space of 20 μm / 20 μm (40 μm pitch) is disposed in the opening.
 次に、フリップチップ接続端子となる、凸状回路による回路パターン(外層回路7)上に、はんだペーストを印刷しリフローすることによって予備はんだを形成した。予備はんだ用のはんだペーストには、Sn(スズ)-Ag(銀)-Cu(銅)系のエコソルダーM705(千住金属工業株式会社製、商品名。エコソルダーは、登録商標。)を用い、リフローには赤外線リフロー装置を用いて、ピーク温度260℃の条件で行なった。 Next, preliminary solder was formed by printing and reflowing a solder paste on a circuit pattern (outer layer circuit 7) by a convex circuit, which becomes a flip chip connection terminal. Sn (tin) -Ag (silver) -Cu (copper) -based eco-solder M705 (trade name, manufactured by Senju Metal Industry Co., Ltd., Eco-Solder is a registered trademark) is used as a pre-solder solder paste. The reflow was performed using an infrared reflow apparatus at a peak temperature of 260 ° C.
 次に、パッケージサイズに切断加工を施した。このパッケージ基板は、図1に示すように、絶縁層3と、この絶縁層3の表面に設けられた凸状回路32による回路パターンと、絶縁層3上及び凸状回路32による回路パターン上に設けられたソルダーレジスト4とを有し、このソルダーレジスト4に設けられた開口31内の凸状回路32による回路パターンがフリップチップ接続端子26を形成している。また、このフリップチップ接続端子26を被覆する予備はんだ19の厚さは、3~5μmである。その後、実施例7と同様にして、半導体パッケージを得た。 Next, the package size was cut. As shown in FIG. 1, the package substrate includes an insulating layer 3, a circuit pattern formed by a convex circuit 32 provided on the surface of the insulating layer 3, and a circuit pattern formed on the insulating layer 3 and the convex circuit 32. The circuit pattern of the convex circuit 32 in the opening 31 provided in the solder resist 4 forms the flip chip connection terminal 26. The thickness of the preliminary solder 19 that covers the flip chip connection terminal 26 is 3 to 5 μm. Thereafter, a semiconductor package was obtained in the same manner as in Example 7.
 (比較例3)
 フリップチップ接続端子を被覆する予備はんだの厚さは、17~20μmである。これ以外は、比較例3と同様にして、パッケージ基板び半導体パッケージを得た。
(Comparative Example 3)
The thickness of the pre-solder covering the flip chip connection terminal is 17 to 20 μm. Except for this, a package substrate and a semiconductor package were obtained in the same manner as in Comparative Example 3.
 表2に、実施例7~15、参考例1、比較例1~3のパッケージ基板について、フリップチップ接続端子の断面形状、はんだ厚み、はんだブリッジの有無を調べた結果を示す。また、実施例7~15、参考例1及び比較例1~3の半導体パッケージについて、はんだフィレットの状態を調べた結果を示す。 Table 2 shows the results of examining the cross-sectional shape of the flip chip connection terminal, the solder thickness, and the presence or absence of a solder bridge for the package substrates of Examples 7 to 15, Reference Example 1, and Comparative Examples 1 to 3. Also, the results of examining the state of the solder fillet in the semiconductor packages of Examples 7 to 15, Reference Example 1 and Comparative Examples 1 to 3 are shown.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
 フリップチップ接続端子の断面形状の観察結果から、実施例7~15では、フリップチップ接続端子の側面及び底面は絶縁層に埋め込まれて密着しており、断面形状はほぼ矩形でアンダーカットは認められなかった。一方、比較例2、3では、凸状回路であるため、フィリップチップ接続端子の底面のみが絶縁層と密着していた。また、フリップチップ接続端子の断面形状にアンダーカットが観察され、最も狭い箇所では、トップ幅(表面側の幅)に対して半分未満の幅となっていた。 From the observation results of the cross-sectional shape of the flip-chip connection terminal, in Examples 7 to 15, the side surface and bottom surface of the flip-chip connection terminal are embedded and in close contact with the insulating layer, and the cross-sectional shape is almost rectangular and undercut is recognized. There wasn't. On the other hand, in Comparative Examples 2 and 3, since it is a convex circuit, only the bottom surface of the Philip chip connection terminal was in close contact with the insulating layer. Further, undercuts were observed in the cross-sectional shape of the flip chip connection terminal, and the width at the narrowest portion was less than half the top width (width on the front surface side).
 はんだ厚みの測定結果から、実施例7~15では、はんだ厚みは3~20μmであり、また、はんだブリッジの確認結果から、このはんだ厚みの範囲ではんだブリッジの発生はなかった。一方、比較例1では、はんだ厚みは1~2μmと薄く、はんだブリッジの発生はなかった。参考例1では、はんだ厚みは25~28μmと厚く、隣接するフリップチップ接続端子間ではんだブリッジが発生した。比較例3では、はんだ厚みが17~20μmであるが、凸状回路であるため、はんだがフリップチップ接続端子の側面に回りこみ、はんだブリッジが発生した。 From the measurement results of the solder thickness, in Examples 7 to 15, the solder thickness was 3 to 20 μm, and from the confirmation result of the solder bridge, no solder bridge was generated within this solder thickness range. On the other hand, in Comparative Example 1, the solder thickness was as thin as 1 to 2 μm, and no solder bridge was generated. In Reference Example 1, the solder thickness was as thick as 25 to 28 μm, and a solder bridge was generated between adjacent flip chip connection terminals. In Comparative Example 3, the thickness of the solder was 17 to 20 μm, but because it was a convex circuit, the solder wraps around the side surface of the flip chip connection terminal, and a solder bridge occurred.
 半導体パッケージのはんだフィレットの確認結果から、実施例7~15、参考例1及び比較例3では、半導体素子のバンプとの間に形成されるはんだフィレットは、半導体素子のバンプ及びパッケージ基板のフリップチップ接続端子の両者にはんだが濡れ広がっており、状態は良好であった。一方、比較例1及び2では、半導体素子のバンプまたはパッケージ基板のフリップチップ接続端子の一部にはんだの濡れ広がりが不十分な箇所があり、はんだフィレットの形成は不十分であった。 From the results of confirming the solder fillets of the semiconductor package, in Examples 7 to 15, Reference Example 1 and Comparative Example 3, the solder fillet formed between the bumps of the semiconductor element is the bump of the semiconductor element and the flip chip of the package substrate. The solder was wet and spread on both of the connection terminals, and the state was good. On the other hand, in Comparative Examples 1 and 2, there were portions where the solder wettability was insufficient in some of the bumps of the semiconductor element or the flip chip connection terminals of the package substrate, and the formation of solder fillets was insufficient.
 フリップチップ接続端子の断面形状は、マイクロセクションを作製し、金属顕微鏡で断面を観察することにより行った。フリップチップ接続端子上のはんだの厚みは、非接触段差測定機であるハイソメット(ユニオン光学株式会社製、商品名。ハイソメットは登録商標。)を用い、予備はんだを形成する前後において、ソルダージストとフリップチップ接続端子との段差を測定することにより測定した。はんだブリッジの有無及びはんだフィレットの状態は、実体顕微鏡を用いて10倍で観察することにより確認した。 The cross-sectional shape of the flip chip connection terminal was obtained by preparing a microsection and observing the cross section with a metal microscope. The thickness of the solder on the flip-chip connection terminal is determined by flipping the solder jist and the solder jist before and after forming the preliminary solder using Hi-Somet (trade name, made by Union Optical Co., Ltd., registered trademark). It measured by measuring the level | step difference with a chip connection terminal. The presence or absence of the solder bridge and the state of the solder fillet were confirmed by observing at a magnification of 10 using a stereomicroscope.
 1:半導体素子搭載用パッケージ基板またはパッケージ基板または第10の回路基板
 2:外層回路または埋込回路
 3:絶縁層
 4:ソルダーレジスト
 5:層間接続
 6:内層回路
 7:外層回路
 8:保護めっき
 9:多層金属箔
10:第1キャリア金属箔
11:第2キャリア金属箔
12:ベース金属箔
13:第1のパターンめっき
14:第2のパターンめっき
15:半導体素子
16:基材
17:コア基板
18:ビア
19:予備はんだ
20:導体層
21:層間接続孔
22:積層体
23:アンダーフィル材
24:半導体パッケージ
25:(半導体素子側の)バンプ
26:フリップチップ接続端子
27:凸形状または立体回路
28:凹み形状
29:封止材
31:(ソルダーレジストの)開口
32:凸状回路
33:短手方向に拡張された部分
34:エッチングレジスト
35:半導体素子
1: Semiconductor device mounting package substrate or package substrate or tenth circuit substrate 2: Outer layer circuit or embedded circuit 3: Insulating layer 4: Solder resist 5: Interlayer connection 6: Inner layer circuit 7: Outer layer circuit 8: Protective plating 9 : Multi-layer metal foil 10: first carrier metal foil 11: second carrier metal foil 12: base metal foil 13: first pattern plating 14: second pattern plating 15: semiconductor element 16: base material 17: core substrate 18 : Via 19: Preliminary solder 20: Conductor layer 21: Interlayer connection hole 22: Laminated body 23: Underfill material 24: Semiconductor package 25: Bump 26 (on the semiconductor element side): Flip chip connection terminal 27: Convex shape or three-dimensional circuit 28: Recessed shape 29: Sealing material 31: Opening (of solder resist) 32: Convex circuit 33: Expanded portion in short direction 34: Edge Packaging resist 35: semiconductor element

Claims (12)

  1.  第1キャリア金属箔と第2キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、
     前記多層金属箔の第1キャリア金属箔と第2キャリア金属箔との間で、第1キャリア金属箔を物理的に剥離する工程と、
     前記コア基板の第2キャリア金属箔上に第1のパターンめっきを行う工程と、
     前記第1のパターンめっきを含む第2キャリア金属箔上に絶縁層と導体回路と層間接続とを形成して積層体を形成する工程と、
     前記多層金属箔の第2キャリア金属箔とベース金属箔との間で、前記積層体を第2キャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、
     前記剥離した積層体の第2キャリア金属箔上にエッチングレジストを形成してエッチングを行うことにより、前記積層体表面の絶縁層から第1のパターンめっきを露出させて埋め込み回路を形成する工程、または前記積層体表面の第1のパターンめっき上に立体回路を形成する工程、または前記積層体表面の絶縁層上に立体回路を形成する工程、または前記積層体表面の第1のパターンめっき上に凹み形状を形成する工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
    A multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. Process,
    Physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil;
    Performing a first pattern plating on a second carrier metal foil of the core substrate;
    Forming a laminate by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating;
    Between the second carrier metal foil and the base metal foil of the multilayer metal foil, physically separating the laminate together with the second carrier metal foil from the core substrate,
    Forming an embedded resist by exposing the first pattern plating from the insulating layer on the surface of the laminate by forming an etching resist on the second carrier metal foil of the peeled laminate and performing etching; or A step of forming a three-dimensional circuit on the first pattern plating on the surface of the laminate, a step of forming a three-dimensional circuit on the insulating layer on the surface of the laminate, or a depression on the first pattern plating on the surface of the laminate. Forming a shape, and a method of manufacturing a package substrate for mounting a semiconductor element.
  2.  第1キャリア金属箔と第2キャリア金属箔とベース金属箔とをこの順に積層した多層金属箔を準備し、この多層金属箔のベース金属箔側と基材とを積層してコア基板を形成する工程と、
     前記多層金属箔の第1キャリア金属箔と第2キャリア金属箔との間で、第1キャリア金属箔を物理的に剥離する工程と、
     前記コア基板の第2キャリア金属箔上に第1のパターンめっきを行う工程と、
     前記第1のパターンめっきを含む第2キャリア金属箔上に絶縁層と導体回路と層間接続とを形成して積層体を形成する工程と、
     前記多層金属箔の第2キャリア金属箔とベース金属箔との間で、前記積層体をキャリア金属箔とともにコア基板から物理的に剥離して分離する工程と、
     前記剥離した積層体の第2キャリア金属箔上に第2のパターンめっきを行う工程と、
     前記第2のパターンめっきを行った部分以外の第2キャリア金属箔上にエッチングレジストを形成してエッチングを行い、前記第2のパターンめっきを行った部分及びエッチングレジストを形成した部分以外の第2キャリア金属箔をエッチングにより除去することにより、前記積層体表面の絶縁層から第1のパターンめっきを露出させて埋め込み回路を形成する工程、または前記積層体表面の第1のパターンめっき上に立体回路を形成する工程、または前記積層体表面の絶縁層上に立体回路を形成する工程、または前記積層体表面の第1のパターンめっき上に凹み形状を形成する工程と、を有する半導体素子搭載用パッケージ基板の製造方法。
    A multilayer metal foil is prepared by laminating a first carrier metal foil, a second carrier metal foil, and a base metal foil in this order, and the base metal foil side of the multilayer metal foil and the base material are laminated to form a core substrate. Process,
    Physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil;
    Performing a first pattern plating on a second carrier metal foil of the core substrate;
    Forming a laminate by forming an insulating layer, a conductor circuit, and an interlayer connection on the second carrier metal foil including the first pattern plating;
    Between the second carrier metal foil and the base metal foil of the multilayer metal foil, physically separating the laminate together with the carrier metal foil from the core substrate,
    Performing a second pattern plating on the second carrier metal foil of the peeled laminate;
    Etching is performed by forming an etching resist on the second carrier metal foil other than the portion where the second pattern plating has been performed, and second etching is performed except for the portion where the second pattern plating is performed and the portion where the etching resist is formed. Removing the carrier metal foil by etching to expose the first pattern plating from the insulating layer on the surface of the laminate to form an embedded circuit, or forming a three-dimensional circuit on the first pattern plating on the surface of the laminate Or a step of forming a three-dimensional circuit on the insulating layer on the surface of the laminate, or a step of forming a concave shape on the first pattern plating on the surface of the laminate. A method for manufacturing a substrate.
  3.  請求項1または2において、
     第1のパターンめっきを含む第2キャリア金属箔上に絶縁層と導体回路と層間接続とを形成して積層体を形成する工程と、多層金属箔の第2キャリア金属箔とベース金属箔との間で、前記積層体を第2キャリア金属箔とともにコア基板から物理的に剥離して分離する工程との間に、所望の層数の絶縁層と導体回路とを形成する工程を有する半導体素子搭載用パッケージ基板の製造方法。
    In claim 1 or 2,
    Forming a laminated body by forming an insulating layer, a conductor circuit and an interlayer connection on a second carrier metal foil including a first pattern plating; and a second carrier metal foil and a base metal foil of a multilayer metal foil. A semiconductor element mounting having a step of forming a desired number of insulating layers and conductor circuits between the step of physically peeling the laminate from the core substrate together with the second carrier metal foil Method for manufacturing a package substrate.
  4.  請求項1から3の何れかにおいて、
     積層体表面の絶縁層から第1のパターンめっきを露出させて埋め込み回路を形成する工程ではフリップチップ接続端子を、積層体表面の第1のパターンめっき上に立体回路を形成する工程ではピラーまたはフリップチップ接続端子の長手方向の一部に凸形状を、積層体表面の絶縁層上に立体回路を形成する工程ではダミー端子を形成する半導体搭載用パッケージ基板の製造方法。
    In any one of Claim 1 to 3,
    A flip chip connection terminal is formed in the step of forming the embedded circuit by exposing the first pattern plating from the insulating layer on the surface of the stacked body, and a pillar or flip is formed in the step of forming a three-dimensional circuit on the first pattern plating on the surface of the stacked body. A method of manufacturing a package substrate for mounting a semiconductor, wherein a dummy terminal is formed in a step of forming a convex shape in a part of a longitudinal direction of a chip connection terminal and forming a three-dimensional circuit on an insulating layer on a surface of a laminate.
  5.  請求項1から4の何れかの半導体搭載用パッケージ基板の製造方法によって製造される半導体素子搭載用パッケージ基板であって、
     絶縁層と、この絶縁層の表面に上面が露出するように設けられた埋込回路と、前記絶縁層上及び埋込回路上に設けられたソルダーレジストとを有し、このソルダーレジストの開口内に配置された埋込回路がフリップチップ接続端子を形成し、このフリップチップ接続端子が厚さ3μm以上の予備はんだによって被覆された半導体素子搭載用パッケージ基板。
    A package substrate for mounting a semiconductor element manufactured by the method for manufacturing a package substrate for mounting a semiconductor according to any one of claims 1 to 4,
    An insulating layer; a buried circuit provided such that an upper surface is exposed on a surface of the insulating layer; and a solder resist provided on the insulating layer and the buried circuit, and the solder resist is provided in an opening of the solder resist. A package substrate for mounting a semiconductor element, wherein the embedded circuit arranged on the substrate forms a flip chip connection terminal, and the flip chip connection terminal is covered with a pre-solder having a thickness of 3 μm or more.
  6.  請求項5において、フリップチップ接続端子を形成する埋込回路の底面にビアが接続した半導体素子搭載用パッケージ基板。 6. The package substrate for mounting a semiconductor element according to claim 5, wherein vias are connected to the bottom surface of the embedded circuit forming the flip chip connection terminals.
  7.  請求項5または6において、フリップチップ接続端子の長手方向の一部に凸形状が形成された半導体素子搭載用パッケージ基板。 7. The package substrate for mounting a semiconductor element according to claim 5, wherein a convex shape is formed on a part of the flip chip connection terminal in the longitudinal direction.
  8.  請求項5から7の何れかにおいて、フリップチップ接続端子の長手方向の一部に凹み形状が形成された半導体素子搭載用パッケージ基板。 8. The package substrate for mounting a semiconductor element according to claim 5, wherein a concave shape is formed in a part of the flip chip connection terminal in the longitudinal direction.
  9.  請求項5から8の何れかにおいて、フリップチップ接続端子の先端が、ソルダーレジストの開口内に配置された半導体素子搭載用パッケージ基板。 9. The package substrate for mounting a semiconductor element according to claim 5, wherein the tip of the flip chip connection terminal is disposed in the opening of the solder resist.
  10.  請求項5から9の何れかにおいて、フリップチップ接続端子の長手方向の両側または片側に延長された部分を有する埋込回路が設けられた半導体素子搭載用パッケージ基板。 10. The package substrate for mounting a semiconductor element according to claim 5, wherein an embedded circuit having a portion extended to both sides or one side in the longitudinal direction of the flip chip connection terminal is provided.
  11.  請求項5から10の何れかにおいて、フリップチップ接続端子の一部が、短手方向に拡張された半導体素子搭載用パッケージ基板。 11. The package substrate for mounting a semiconductor device according to claim 5, wherein a part of the flip chip connection terminal is extended in the short direction.
  12.  請求項5から11の何れかの半導体素子搭載用パッケージ基板のフリップチップ接続端子上に半導体素子のバンプをフリップチップ接続により搭載した半導体パッケージ。 A semiconductor package in which bumps of a semiconductor element are mounted on a flip chip connection terminal of a package substrate for mounting a semiconductor element according to any one of claims 5 to 11 by flip chip connection.
PCT/JP2012/056125 2011-03-09 2012-03-09 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package WO2012121373A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020137025239A KR101585305B1 (en) 2011-03-09 2012-03-09 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
CN201280012341.XA CN103443916B (en) 2011-03-09 2012-03-09 The manufacture method of mounting semiconductor element base plate for packaging, mounting semiconductor element base plate for packaging and semiconductor packages

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2011-051378 2011-03-09
JP2011051378A JP5769001B2 (en) 2011-03-09 2011-03-09 Semiconductor device mounting package substrate and semiconductor package
JP2011-078583 2011-03-31
JP2011078583 2011-03-31

Publications (1)

Publication Number Publication Date
WO2012121373A1 true WO2012121373A1 (en) 2012-09-13

Family

ID=46798324

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/056125 WO2012121373A1 (en) 2011-03-09 2012-03-09 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package

Country Status (4)

Country Link
KR (1) KR101585305B1 (en)
CN (1) CN103443916B (en)
TW (1) TWI600097B (en)
WO (1) WO2012121373A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105746004A (en) * 2013-11-22 2016-07-06 三井金属矿业株式会社 Support substrate with circuit forming layer, support substrate with circuit forming layers on both surfaces, multilayer laminated plate, manufacturing method for multilayer printed wiring board, and multilayer printed wiring board
CN113196892A (en) * 2018-12-14 2021-07-30 三菱瓦斯化学株式会社 Method for manufacturing package substrate for mounting semiconductor element

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5977392B2 (en) * 2014-03-26 2016-08-24 Jx金属株式会社 Laminate made of resin plate carrier and metal layer
KR102232994B1 (en) * 2017-02-21 2021-03-26 미쓰비시덴키 가부시키가이샤 Semiconductor device
JP6988919B2 (en) * 2017-12-27 2022-01-05 株式会社村田製作所 Semiconductor composite device and package substrate used for it
DE112019000184B4 (en) * 2018-06-18 2025-04-30 Fuji Electric Co., Ltd. SEMICONDUCTOR DEVICE
CN113261094B (en) 2019-03-07 2024-04-16 爱玻索立克公司 Package substrate and semiconductor device including the same
KR102652986B1 (en) * 2019-03-07 2024-03-28 앱솔릭스 인코포레이티드 Packaging substrate and semiconductor apparatus comprising same
WO2020185016A1 (en) * 2019-03-12 2020-09-17 에스케이씨 주식회사 Packaging substrate and semiconductor device comprising same
TWI715485B (en) * 2020-04-16 2021-01-01 常州欣盛半導體技術股份有限公司 Circuit structure for improving pin glass strength in cof-ic packaging process

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242328A (en) * 1997-02-28 1998-09-11 Toshiba Corp Circuit board, circuit module having the circuit board and electronic equipment having the circuit module
JP2002052614A (en) * 2000-08-11 2002-02-19 Kanegafuchi Chem Ind Co Ltd Method for manufacturing laminated sheet
JP2004253648A (en) * 2003-02-20 2004-09-09 Sumitomo Bakelite Co Ltd Printed circuit board and method for manufacturing the same, and multi-layer printed wiring board and method for manufacturing the same
JP2008166464A (en) * 2006-12-28 2008-07-17 Toppan Printing Co Ltd Wiring board and manufacturing method thereof
JP2008252042A (en) * 2007-03-30 2008-10-16 Sharp Corp Circuit substrate and forming method therefor
JP2009253261A (en) * 2008-04-07 2009-10-29 Samsung Electro Mech Co Ltd High density circuit board and manufacturing method thereof
JP2010206192A (en) * 2009-02-27 2010-09-16 Ibiden Co Ltd Method for manufacturing printed wiring board, and printed wiring board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3420076B2 (en) * 1998-08-31 2003-06-23 新光電気工業株式会社 Method for manufacturing flip-chip mounting board, flip-chip mounting board, and flip-chip mounting structure
TWI223577B (en) * 1999-11-01 2004-11-01 Kaneka Corp Manufacturing method and manufacturing apparatus of laminated plate
JP2009289868A (en) * 2008-05-28 2009-12-10 Kyocer Slc Technologies Corp Wiring substrate and its manufacturing method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242328A (en) * 1997-02-28 1998-09-11 Toshiba Corp Circuit board, circuit module having the circuit board and electronic equipment having the circuit module
JP2002052614A (en) * 2000-08-11 2002-02-19 Kanegafuchi Chem Ind Co Ltd Method for manufacturing laminated sheet
JP2004253648A (en) * 2003-02-20 2004-09-09 Sumitomo Bakelite Co Ltd Printed circuit board and method for manufacturing the same, and multi-layer printed wiring board and method for manufacturing the same
JP2008166464A (en) * 2006-12-28 2008-07-17 Toppan Printing Co Ltd Wiring board and manufacturing method thereof
JP2008252042A (en) * 2007-03-30 2008-10-16 Sharp Corp Circuit substrate and forming method therefor
JP2009253261A (en) * 2008-04-07 2009-10-29 Samsung Electro Mech Co Ltd High density circuit board and manufacturing method thereof
JP2010206192A (en) * 2009-02-27 2010-09-16 Ibiden Co Ltd Method for manufacturing printed wiring board, and printed wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105746004A (en) * 2013-11-22 2016-07-06 三井金属矿业株式会社 Support substrate with circuit forming layer, support substrate with circuit forming layers on both surfaces, multilayer laminated plate, manufacturing method for multilayer printed wiring board, and multilayer printed wiring board
CN113196892A (en) * 2018-12-14 2021-07-30 三菱瓦斯化学株式会社 Method for manufacturing package substrate for mounting semiconductor element
EP3897083A4 (en) * 2018-12-14 2022-01-26 Mitsubishi Gas Chemical Company, Inc. METHOD OF MANUFACTURING HOUSING SUBSTRATE FOR SEMICONDUCTOR ELEMENT INSTALLATION
US11990349B2 (en) 2018-12-14 2024-05-21 Mitsubishi Gas Chemical Company, Inc. Method for producing package substrate for loading semiconductor device

Also Published As

Publication number Publication date
CN103443916B (en) 2016-03-02
TW201246414A (en) 2012-11-16
KR101585305B1 (en) 2016-01-13
KR20130129292A (en) 2013-11-27
CN103443916A (en) 2013-12-11
TWI600097B (en) 2017-09-21

Similar Documents

Publication Publication Date Title
WO2012121373A1 (en) Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
JP5896200B2 (en) Manufacturing method of package substrate for mounting semiconductor device
US10117336B2 (en) Method of manufacturing a wiring substrate
KR20200094780A (en) Method for manufacturing semiconductor device
JP2012216824A (en) Manufacturing method of package substrate for mounting semiconductor element
WO2016116980A1 (en) Wiring substrate laminate and method for manufacturing semiconductor device using same
KR20120085673A (en) Multilayer wiring substrate
WO2011122532A1 (en) Composite metal layer provided with supporting body metal foil, wiring board using the composite metal layer, method for manufacturing the wiring board, and method for manufacturing semiconductor package using the wiring board
JP4170266B2 (en) Wiring board manufacturing method
JP2015144157A (en) Circuit board, electronic device, and method of manufacturing electronic device
JP6455197B2 (en) Wiring substrate, semiconductor device, and manufacturing method of semiconductor device
JP5672524B2 (en) Manufacturing method of package substrate for mounting semiconductor device
JP5287220B2 (en) Manufacturing method of component-embedded substrate
JP5716948B2 (en) Manufacturing method of package substrate for mounting semiconductor device
US10170405B2 (en) Wiring substrate and semiconductor package
JP5769001B2 (en) Semiconductor device mounting package substrate and semiconductor package
JP5846407B2 (en) Manufacturing method of package substrate for mounting semiconductor device
JP2014072326A (en) Semiconductor element mounting package substrate and manufacturing method therefor
KR101314712B1 (en) Thin PCB substrate having via layer and method of manufacturing the same
JP5034885B2 (en) Electronic device and method of manufacturing the same
JP2011159695A (en) Semiconductor element-mounting package substrate, and method for manufacturing the same
JP2008210835A (en) Substrate for mounting electronic parts and manufacturing method thereof
JP2011146569A (en) Ceramic circuit board

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12755708

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20137025239

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 12755708

Country of ref document: EP

Kind code of ref document: A1