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WO2012103928A1 - Arrangement of carriers for optoelectronic chips - Google Patents

Arrangement of carriers for optoelectronic chips Download PDF

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Publication number
WO2012103928A1
WO2012103928A1 PCT/EP2011/051322 EP2011051322W WO2012103928A1 WO 2012103928 A1 WO2012103928 A1 WO 2012103928A1 EP 2011051322 W EP2011051322 W EP 2011051322W WO 2012103928 A1 WO2012103928 A1 WO 2012103928A1
Authority
WO
WIPO (PCT)
Prior art keywords
base body
arrangement
metallization
top surface
carriers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2011/051322
Other languages
French (fr)
Other versions
WO2012103928A8 (en
Inventor
Lye Yee WONG
Mei Ling YEOH
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Priority to PCT/EP2011/051322 priority Critical patent/WO2012103928A1/en
Priority to TW101101894A priority patent/TWI499014B/en
Publication of WO2012103928A1 publication Critical patent/WO2012103928A1/en
Publication of WO2012103928A8 publication Critical patent/WO2012103928A8/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10W72/07554—
    • H10W90/754—

Definitions

  • ARRANGEMENT OF CARRIERS FOR OPTOELECTRONIC CHIPS An arrangement of carriers of optoelectronic chips is specified. Further a method for producing an optoelectronic device is specified.
  • One object to be achieved consists in specifying an
  • the arrangement comprises a base body.
  • the base body is formed with a ceramic material.
  • the base body can comprise a ceramic material or the base body
  • the base body consists of a ceramic material. Particularly suitable ceramic materials are AI 2 O 3 and A1N.
  • the base body is given in the form of a panel. That means that the base body can be shaped like a cuboid wherein the extension in lateral directions is great in comparison to the extension in a vertical direction.
  • the base body comprises a top surface, a bottom surface and at least one side surface which connects the top surface with the bottom surface. If the base body is, for example, in the form of a cuboid the base body comprises exactly four side surfaces wherein each side surface connects the top surface with the bottom surface of the base body.
  • the arrangement of carrier comprises a plurality of chip
  • Each chip connection region is configured to carry at least one optoelectronic chip. That means the chip connection region has a large enough extension in order to carry at least one optoelectronic chip.
  • these chip connection regions are arranged on the top surface of the base body.
  • the arrangement of carriers comprises a plurality of chip connection regions so that a plurality of optoelectronic devices can be produced from the arrangement of carriers. For example each carrier of the arrangement is assigned to exactly one of the chip connection regions.
  • each carrier then comprises exactly one chip connection region which can carry at least one optoelectronic chip.
  • the arrangement of carriers comprises a protection
  • the protection metallization particularly covers all side surfaces of the base body. If the base body comprises, for example, four surfaces all four side surfaces are covered by the protection metallization. Thereby the protection metallization is, for example, in direct contact with the ceramic material of the base body.
  • the protection metallization comprises one or more metal materials. It is possible that the protection metallization covers the whole area of nearly the whole area of all side surfaces of the base body. For example at least 90% of the area of the side surfaces of the base body are covered by the protection metallization.
  • the protection metallization is configured to absorb external impact force which is, for example, directed to the base body during handling of the arrangement of carriers. Thereby the protection metallization blocks or even prevents the
  • the arrangement of carriers for optoelectronic chips comprises a base body which is formed with a ceramic material, a plurality of chip connection regions and a protection metallization.
  • the base body comprises a top surface, a bottom surface and at least one side surface which connects the top surface with the bottom surface.
  • the chip connection regions are arranged on the top surface of the base body and each chip connection region is configured to carry at least one optoelectronic chip.
  • the protection metallization covers all side surfaces of the base body.
  • the carriers of the arrangement are suitable for
  • Optoelectronic chips like light- emitting diode chips are formed by a semiconductor dye which emits light when a current flows through it. Due to the customer application and demand high current flows are required for the light-emitting diode chip to emit the amount of light wanted. Thereby heat is generated in the light- emitting diode chip which has to be dissipated.
  • the carriers comprise a base body formed with a ceramic material such as for example aluminum oxide or aluminum nitride which exhibits a good heat diffusion characteristic and an ability to lower the thermal resistance of the optoelectronic device.
  • the arrangement of carriers and in particular the base body is exposed to external mechanical forces which could lead to damage occurring to the base body, for example by the
  • the protection metallization covers a part of the top surface of the base body, wherein the part of the protection
  • the protection metallization is formed on all side surfaces and part of the top surface of the base body.
  • the protection metallization is given by a single continuous layer which is formed over all side surfaces of the base body and part of the top surface of the base body.
  • the part of the protection metallization on the top surface is for example formed frame-like and surrounds all chip connection regions of the arrangement of carriers. That means, the part of the protection metallization on the top surface is, for the case of a base body of cuboid shape, for example formed as a rectangle which surrounds all chip connection regions of the arrangement of carriers.
  • the arrangement further comprises mounting regions which are arranged on the bottom surface of the base body.
  • the mounting regions are configured for the electrical and mechanical connection of the carriers of the arrangement to another carrier, e.g. a circuit board.
  • each mounting region is configured for the electrical and
  • each carrier of the arrangement comprises exactly one mounting region.
  • each mounting region is assigned to one chip connection region of the arrangement of carriers in a one-to-one
  • each carrier of the arrangement then comprises exactly one chip connection region and exactly one mounting region wherein the chip connection region and the mounting region are assigned to the carrier in a one-to-one
  • the mounting region or the carrier of the arrangement is arranged on the bottom surface of the base body opposite to the connection region of the carrier which is arranged on the top surface of the base body .
  • the protection metallization covers a part of the bottom surface and the part of the protection metallization on the bottom surface of the base body surrounds all mounting regions of the arrangement.
  • the protection metallization can be formed as a rectangle in case the base body is in the form of a cuboid.
  • the protection metallization covers all side surfaces of the base body and a part of the bottom surface.
  • the protection metallization covers a part of the bottom surface, all side surfaces and a part of the top surface of the base body.
  • the protection metallization can then be formed as a single continuous layer which spans from the top surface over the side surfaces to the bottom surface of the base body. Such a protection metallization is particularly suited for crack prevention.
  • each chip connection region is electrically connected to its assigned mounting region via at least one through hole wherein the through hole is formed through the base body and reaches from the top surface to the bottom surface of the base body.
  • the through hole is an opening in the base body which is filled or plated with a metal material.
  • this metal material is the same material as the material of the protection metallization and is formed with the protection metallization during the same production step or steps. Crack prevention by the described protection metallization which covers all side surfaces of the base body has proved to be particularly helpful in case of through holes being formed through the base body. Such through holes impair the
  • each chip connection region and/or each mounting region comprises at least one unit metallization.
  • the unit metallization of the chip connection region is configured for the mechanical mounting and electrical connection of an optoelectronic chip.
  • the unit metallization of a mounting region is configured for the mounting of the optoelectronic device produced from the carriers of the carrier arrangement.
  • each metallization comprises at least one metal layer which is in direct contact with the base body. It is further possible that each metallization comprises at least one or at least two additional layers of different metals wherein a first layer of these layers is in direct contact with the base body and the remaining layers are arranged above each other on the first layer.
  • mechanically stable metallizations can be formed by using at least three layers of different metals.
  • the first layer in direct contact with the base body is formed with copper.
  • This layer can consist of copper.
  • the second layer which is applied directly on the first layer can be formed for example with nickel and can consist of nickel .
  • the third layer which is applied on the second layer can be formed with gold and, for example, consist of gold.
  • each metallization is formed by at least one of the following: sputtering, vapor deposition, galvanic deposition,
  • metallization is formed by sputtering or vapor deposition. Following layers of the metallization can then be formed by plating processes like galvanic deposition or electroless plating .
  • the through holes are formed by laser drilling. The formation of the through holes takes place before the formation of the protection metallization.
  • a method for producing an optoelectronic device is specified.
  • an arrangement of carriers as described here is provided. That means all features described for the arrangement are also described for the method for producing an optoelectronic device.
  • At least one optoelectronic chip is electrically and mechanically connected to each connection region of the arrangement of carriers.
  • the optoelectronic chips are glued or soldered to one unit metallization of the connection region and electrically connected via a bonding wire to a further unit metallization of the connection region.
  • the arrangement of carriers is separated into single carriers, each carrier having one of the connection regions with at least one optoelectronic chip.
  • the carrier can further have a mounting region opposite to the connection region.
  • the connection region and mounting region that means unit metallizations of connection regions and mounting regions can be electrically connected with each other by through holes spanning through the base body of the carrier.
  • the separation into singe carries is e.g. done by sawing or the like.
  • Figures 2A and 2B show an exemplary embodiment of an
  • Figures 3A to 3E show method steps of an exemplary embodiment of the method described in schematic illustrations.
  • Figures 4A to 4C show an exemplary embodiment of an
  • Figure 1A shows an arrangement of carriers having a base body 1.
  • the base body 1 is formed with a ceramic material and comprises for example AI 2 O 3 and/or A1N.
  • a plurality of unit metallizations 7 is applied to a top surface la of the base body 1.
  • pairs of unit metallizations 7 form chip connection regions 2.
  • Each chip connection region 2 is assigned to a carrier 10 of the arrangement of carriers.
  • a protection metallization 30, which only covers the top surface la of the base body, is applied to the base body.
  • a protection metallization 30 which only covers the top surface la of the base body
  • FIGS. 1A and 2B show schematic illustrations of an
  • the protection metallization 3 covers all four side surfaces lb of the base body 1. The side surfaces lb thereby connect the top surface la to the bottom surface lb of the base body 1.
  • the protection metallization 3 also covers part of the top surface la.
  • the part of the protection metallization 3 on the top surface la surrounds the unit metallization 7 in a frame-like manner.
  • the protection metallization 3 on the top surface la and on the side surface lb are formed as a single continuous layer.
  • the unit metallization 7 and the protection metallization 3 are formed with the same materials in the same method step or steps.
  • the unit metallizations 7 are arranged on the top surface la of the base body in a matrix-like manner that is in columns and rows. For example pairs of unit metallizations 7 belong to the same chip connection region which is assigned to a carrier 10 of the arrangement in a one-to-one correspondence.
  • a ceramic base body 1 is provided.
  • the base body 1 consists of a ceramic material or comprises ceramic
  • through holes 6 are formed in the base body which span from the top surface la to the bottom surface lc of the base body 1.
  • the through holes are formed via laser drilling.
  • a metallization layer 71 is formed on the top surface la and all side
  • the metallization layers 71 which later form the unit metallizations 7 cover the through holes 6.
  • the through holes 6 are filled with the material of layers 71.
  • the layer 71 is, for example, formed during a photolithography process.
  • the layers 71 can consist of copper.
  • the layers 71 serve as seed layers for a galvanic deposition of at least one further layer, for example two further layers 72 and 73 (see for example Figure 4C) .
  • a layer 72 of nickel is deposited on each seed layer 71 and then a layer 73 of gold is deposited on each layer 72 of nickel.
  • deposition is, for example, implemented by means of a
  • the seed layer 71 can, for example, be applied by sputtering or a vapor deposition method like CVD (chemical vapor deposition).
  • CVD chemical vapor deposition
  • optoelectronic chip 4 can be applied to a unit metallization 7 and can be connected via a bonding wire 42 to a unit metallization of the same chip connection region. Further the chips 4 can be encapsulated with a light-transmitting
  • FIG. 4A shows a schematic illustration of such a device.
  • the optoelectronic device is a light-emitting diode comprising a light-emitting diode chip 4.
  • the light- emitting diode chip 4 is arranged on a unit metallization 7.
  • the unit metallization 7 comprises three layers 71, 72, 73 as explained above.
  • the chip 4 comprises on its top surface which faces away from the base body 1, a bonding pad 41.
  • the bonding pad 41 is connected via the bonding wire 42 to a further unit metallization 7 of the same chip connection region 2.
  • the unit metallizations 7 on the top surface la of the base body 1 are connected via through holes 6 in an electrical way to unit metallizations 7 on the bottom surface lc of the base body 1.
  • the unit metallizations 7 on the top surface la of the base body 1 are connected via through holes 6 in an electrical way to unit metallizations 7 on the bottom surface lc of the base body 1.
  • metallization 7 on the bottom surface lc is formed in the same manner as the unit metallization 7 on the top surface la .
  • the two unit metallizations 7 on the bottom surface lc form a mounting region which is assigned in a one-to-one
  • a protection metallization 3 serves as a crack stopper barrier and prevents propagation of crack lines into the inner portion of the ceramic base body 1.
  • the protection metallization 3 covers the top surface and/or the bottom surface of the base body 1 only at a small region near the edge of the base body 1, the number of unit metallizations and thereby the number of chip connection regions can be maximized.

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Abstract

An arrangement of carriers (10) for optoelectronic chips (4) comprising - a base body (1) formed with a ceramic material, - a plurality of chip connection regions (2), and - a protection metallization (3), wherein - the base body (1) comprises a top surface (1a), a bottom surface (1c) and at least one side surface (1b) which connects the top surface (1a) with the bottom surface (1c), - the chip connection regions (2) are arranged on the top surface (1a) of the base body (2), - each chip connection regions (2) is configured to carry at least one optoelectronic chip (4), - the protection metallization (3) covers all side surfaces (1b) of the base body (1) is specified.

Description

Description
ARRANGEMENT OF CARRIERS FOR OPTOELECTRONIC CHIPS An arrangement of carriers of optoelectronic chips is specified. Further a method for producing an optoelectronic device is specified.
One object to be achieved consists in specifying an
arrangement of carriers for optoelectronic chips which is mechanically stable during the handling of the arrangement for the production of an optoelectronic device.
In accordance with at least one aspect of the arrangement, the arrangement comprises a base body. For example the base body is formed with a ceramic material. Than means the base body can comprise a ceramic material or the base body
consists of a ceramic material. Particularly suitable ceramic materials are AI2O3 and A1N. For example the base body is given in the form of a panel. That means that the base body can be shaped like a cuboid wherein the extension in lateral directions is great in comparison to the extension in a vertical direction. In accordance with at least aspect of the arrangement the base body comprises a top surface, a bottom surface and at least one side surface which connects the top surface with the bottom surface. If the base body is, for example, in the form of a cuboid the base body comprises exactly four side surfaces wherein each side surface connects the top surface with the bottom surface of the base body. In accordance with at least one aspect of the arrangement of carrier the arrangement comprises a plurality of chip
connection regions. Each chip connection region is configured to carry at least one optoelectronic chip. That means the chip connection region has a large enough extension in order to carry at least one optoelectronic chip. For example, these chip connection regions are arranged on the top surface of the base body. The arrangement of carriers comprises a plurality of chip connection regions so that a plurality of optoelectronic devices can be produced from the arrangement of carriers. For example each carrier of the arrangement is assigned to exactly one of the chip connection regions.
Consequently, each carrier then comprises exactly one chip connection region which can carry at least one optoelectronic chip.
In accordance with at least one aspect of the arrangement of carriers the arrangement comprises a protection
metallization. The protection metallization particularly covers all side surfaces of the base body. If the base body comprises, for example, four surfaces all four side surfaces are covered by the protection metallization. Thereby the protection metallization is, for example, in direct contact with the ceramic material of the base body. The protection metallization comprises one or more metal materials. It is possible that the protection metallization covers the whole area of nearly the whole area of all side surfaces of the base body. For example at least 90% of the area of the side surfaces of the base body are covered by the protection metallization.
The protection metallization is configured to absorb external impact force which is, for example, directed to the base body during handling of the arrangement of carriers. Thereby the protection metallization blocks or even prevents the
formation of cracks in the base body. In accordance with at least one aspect of the arrangement of carriers, the arrangement of carriers for optoelectronic chips comprises a base body which is formed with a ceramic material, a plurality of chip connection regions and a protection metallization. Thereby the base body comprises a top surface, a bottom surface and at least one side surface which connects the top surface with the bottom surface. The chip connection regions are arranged on the top surface of the base body and each chip connection region is configured to carry at least one optoelectronic chip. The protection metallization covers all side surfaces of the base body.
The carriers of the arrangement are suitable for
optoelectronic chips. Optoelectronic chips like light- emitting diode chips are formed by a semiconductor dye which emits light when a current flows through it. Due to the customer application and demand high current flows are required for the light-emitting diode chip to emit the amount of light wanted. Thereby heat is generated in the light- emitting diode chip which has to be dissipated. According to the specified arrangement of carriers the carriers comprise a base body formed with a ceramic material such as for example aluminum oxide or aluminum nitride which exhibits a good heat diffusion characteristic and an ability to lower the thermal resistance of the optoelectronic device.
During the handling of the arrangement of carriers, for example the assembly process of the optoelectronic device, the arrangement of carriers and in particular the base body is exposed to external mechanical forces which could lead to damage occurring to the base body, for example by the
formation of cracks or breaks. It was found that a protection metallization which at least covers all side surfaces of the base body helps to
efficiently lower the possibility of such cracks or breaks in the base body. In accordance with one aspect of the arrangement of carriers the protection metallization covers a part of the top surface of the base body, wherein the part of the protection
metallization on the top surface surrounds all chip
connection region. According to this aspect the protection metallization is formed on all side surfaces and part of the top surface of the base body. In particular it is possible that the protection metallization is given by a single continuous layer which is formed over all side surfaces of the base body and part of the top surface of the base body. The part of the protection metallization on the top surface is for example formed frame-like and surrounds all chip connection regions of the arrangement of carriers. That means, the part of the protection metallization on the top surface is, for the case of a base body of cuboid shape, for example formed as a rectangle which surrounds all chip connection regions of the arrangement of carriers.
According to at least one aspect of the arrangement of carriers the arrangement further comprises mounting regions which are arranged on the bottom surface of the base body. The mounting regions are configured for the electrical and mechanical connection of the carriers of the arrangement to another carrier, e.g. a circuit board. For example each mounting region is configured for the electrical and
mechanical connection of exactly one carrier of the
arrangement. In other words each carrier of the arrangement comprises exactly one mounting region. Thereby it is possible that each mounting region is assigned to one chip connection region of the arrangement of carriers in a one-to-one
correspondence .
For example each carrier of the arrangement then comprises exactly one chip connection region and exactly one mounting region wherein the chip connection region and the mounting region are assigned to the carrier in a one-to-one
correspondence. For example the mounting region or the carrier of the arrangement is arranged on the bottom surface of the base body opposite to the connection region of the carrier which is arranged on the top surface of the base body .
In accordance with at least one aspect of the arrangement the protection metallization covers a part of the bottom surface and the part of the protection metallization on the bottom surface of the base body surrounds all mounting regions of the arrangement. For example the protection metallization can be formed as a rectangle in case the base body is in the form of a cuboid. Thereby it is possible that the protection metallization covers all side surfaces of the base body and a part of the bottom surface. It is further possible that the protection metallization covers a part of the bottom surface, all side surfaces and a part of the top surface of the base body. The protection metallization can then be formed as a single continuous layer which spans from the top surface over the side surfaces to the bottom surface of the base body. Such a protection metallization is particularly suited for crack prevention.
According to at least one aspect of the arrangement each chip connection region is electrically connected to its assigned mounting region via at least one through hole wherein the through hole is formed through the base body and reaches from the top surface to the bottom surface of the base body. For example the through hole is an opening in the base body which is filled or plated with a metal material. For example this metal material is the same material as the material of the protection metallization and is formed with the protection metallization during the same production step or steps. Crack prevention by the described protection metallization which covers all side surfaces of the base body has proved to be particularly helpful in case of through holes being formed through the base body. Such through holes impair the
mechanical stability, in particular of a ceramic base body. Cracks in the base body could proceed from a side surface of the base body along the through holes, from one through hole to another through hole thereby forming a crack line which can lead to the rupture of the base body. The described protection metallization prevents such damage from occurring.
According to at least one aspect of the arrangement each chip connection region and/or each mounting region comprises at least one unit metallization. The unit metallization of the chip connection region is configured for the mechanical mounting and electrical connection of an optoelectronic chip. The unit metallization of a mounting region is configured for the mounting of the optoelectronic device produced from the carriers of the carrier arrangement. According to one aspect of the arrangement all
metallizations, that means the protection metallization and the unit metallizations, are formed in the same manner. For example the metallizations are formed by the same method step or steps. Thereby it is possible that each metallization comprises at least one metal layer which is in direct contact with the base body. It is further possible that each metallization comprises at least one or at least two additional layers of different metals wherein a first layer of these layers is in direct contact with the base body and the remaining layers are arranged above each other on the first layer.
In particular mechanically stable metallizations can be formed by using at least three layers of different metals.
For example, the first layer in direct contact with the base body is formed with copper. This layer can consist of copper.
The second layer which is applied directly on the first layer can be formed for example with nickel and can consist of nickel .
The third layer which is applied on the second layer can be formed with gold and, for example, consist of gold.
Such a layer stack has proven to be especially suitable for the formation of metallizations which have a good mechanical stability and good electrical characteristics. Consequently such a layer stack can form the protection metallization and the unit metallization. According to at least one aspect of the arrangement each metallization is formed by at least one of the following: sputtering, vapor deposition, galvanic deposition,
electroless plating. For example a first layer of the
metallization is formed by sputtering or vapor deposition. Following layers of the metallization can then be formed by plating processes like galvanic deposition or electroless plating .
For example, the through holes are formed by laser drilling. The formation of the through holes takes place before the formation of the protection metallization.
Further a method for producing an optoelectronic device is specified. In a first step of the method an arrangement of carriers as described here is provided. That means all features described for the arrangement are also described for the method for producing an optoelectronic device.
In a further method step at least one optoelectronic chip is electrically and mechanically connected to each connection region of the arrangement of carriers. For example the optoelectronic chips are glued or soldered to one unit metallization of the connection region and electrically connected via a bonding wire to a further unit metallization of the connection region.
In a further method step the arrangement of carriers is separated into single carriers, each carrier having one of the connection regions with at least one optoelectronic chip. The carrier can further have a mounting region opposite to the connection region. The connection region and mounting region, that means unit metallizations of connection regions and mounting regions can be electrically connected with each other by through holes spanning through the base body of the carrier. The separation into singe carries is e.g. done by sawing or the like.
The arrangement of carriers and the method for producing an optoelectronic device described here are explained in greater detail below on the basis of exemplary embodiments and the associated figures.
In accordance with Figures 1A and IB the underlying problem of the described arrangement of carriers is described in detail .
Figures 2A and 2B show an exemplary embodiment of an
arrangement of carriers described here in schematic
illustrations. Figures 3A to 3E show method steps of an exemplary embodiment of the method described in schematic illustrations.
Figures 4A to 4C show an exemplary embodiment of an
optoelectronic device produced with the described method in schematic illustrations.
Elements which are identical, of identical type or act identically are provided with the same reference symbols in the figures. The figures and the size relationship of the elements illustrated in the figures among one another should not be regarded as to scale. Rather, individual elements - for example the layers of the metallizations - may be
illustrated with an exaggerated size in order to enable better illustration and/or in order to afford a better understanding .
In accordance with the schematic illustrations of Figures 1A and IB the underlying problem of the described arrangement of carriers is explained in more detail. Figure 1A shows an arrangement of carriers having a base body 1. The base body 1 is formed with a ceramic material and comprises for example AI2O3 and/or A1N. Further a plurality of unit metallizations 7 is applied to a top surface la of the base body 1. For example pairs of unit metallizations 7 form chip connection regions 2. Each chip connection region 2 is assigned to a carrier 10 of the arrangement of carriers. In order to prevent cracks or breaks in the base body 1 a protection metallization 30, which only covers the top surface la of the base body, is applied to the base body. However, as
illustrated in Figure IB a crack 8, for example arising during handling of the arrangement, propagates through this protection metallization 30 and leads to a break of the base body. Consequently, a protection metallization 30 which only covers the top surface la of the base body 1 is not
sufficient for the prevention of crack propagation through the base body 1. Figures 2A and 2B show schematic illustrations of an
arrangement of carriers according to one embodiment of the here-described arrangement. In Figure 2A unit metallizations 7 are not shown for clarity reasons. As shown in Figure 2A the protection metallization 3 covers all four side surfaces lb of the base body 1. The side surfaces lb thereby connect the top surface la to the bottom surface lb of the base body 1. In the embodiment of Figures 2A and 2B the protection metallization 3 also covers part of the top surface la. The part of the protection metallization 3 on the top surface la surrounds the unit metallization 7 in a frame-like manner. The protection metallization 3 on the top surface la and on the side surface lb are formed as a single continuous layer. For example the unit metallization 7 and the protection metallization 3 are formed with the same materials in the same method step or steps.
The unit metallizations 7 are arranged on the top surface la of the base body in a matrix-like manner that is in columns and rows. For example pairs of unit metallizations 7 belong to the same chip connection region which is assigned to a carrier 10 of the arrangement in a one-to-one correspondence. In connection with the schematic illustrations of Figures 3A to 3E method steps of an exemplary embodiment of the here- described method for production of optoelectronic devices are explained in more detail. In a first method step, Figure 3A, a ceramic base body 1 is provided. For example the base body 1 consists of a ceramic material or comprises ceramic
materials .
In a next method step, see Figure 3B, through holes 6 are formed in the base body which span from the top surface la to the bottom surface lc of the base body 1. For example the through holes are formed via laser drilling.
In a further method step, see Figure 3C, a metallization layer 71 is formed on the top surface la and all side
surfaces lb of the base body 1. The metallization layers 71 which later form the unit metallizations 7 cover the through holes 6. For example, the through holes 6 are filled with the material of layers 71. The layer 71 is, for example, formed during a photolithography process. The layers 71 can consist of copper.
In the following method step, see Figure 3D, the layers 71 serve as seed layers for a galvanic deposition of at least one further layer, for example two further layers 72 and 73 (see for example Figure 4C) . For example first a layer 72 of nickel is deposited on each seed layer 71 and then a layer 73 of gold is deposited on each layer 72 of nickel. The
deposition is, for example, implemented by means of a
galvanic or electroless plating.
The seed layer 71 can, for example, be applied by sputtering or a vapor deposition method like CVD (chemical vapor
deposition) .
In a next method step, see Figure 3E, the arrangement of carriers is separated along the shown lines into single carriers 10, each comprising a chip connection region 2 with one or more unit metallizations 7.
Due to the protection metallization 3, which covers the side surfaces lb of the base body 1, no cracks occur on the side surfaces of the base body 1.
Further processing steps can be performed before the
separation step shown in Figure 3E . For example, an
optoelectronic chip 4 can be applied to a unit metallization 7 and can be connected via a bonding wire 42 to a unit metallization of the same chip connection region. Further the chips 4 can be encapsulated with a light-transmitting
material like silicon, forming for example a lens 11 which spends over the unit metallizations 7 of the chip connection region 2. During these method steps the protection metallization 3 prevents cracking and breaking of the base body 1. In connection with Figures 4A to 4C an exemplary embodiment of a thus produced optoelectronic device is illustrated.
Figure 4A shows a schematic illustration of such a device. For example the optoelectronic device is a light-emitting diode comprising a light-emitting diode chip 4. The light- emitting diode chip 4 is arranged on a unit metallization 7. As shown in Figure 4C the unit metallization 7 comprises three layers 71, 72, 73 as explained above. The chip 4 comprises on its top surface which faces away from the base body 1, a bonding pad 41. The bonding pad 41 is connected via the bonding wire 42 to a further unit metallization 7 of the same chip connection region 2. The unit metallizations 7 on the top surface la of the base body 1 are connected via through holes 6 in an electrical way to unit metallizations 7 on the bottom surface lc of the base body 1. The unit
metallization 7 on the bottom surface lc is formed in the same manner as the unit metallization 7 on the top surface la .
The two unit metallizations 7 on the bottom surface lc form a mounting region which is assigned in a one-to-one
correspondence to the chip connection region 2 of the carrier 10.
In the finished optoelectronic device the protection
metallization 3 is absent.
The proposed arrangement of carriers has inter alia the following advantages: A protection metallization 3 serves as a crack stopper barrier and prevents propagation of crack lines into the inner portion of the ceramic base body 1.
Due to the fact that the protection metallization 3 covers the top surface and/or the bottom surface of the base body 1 only at a small region near the edge of the base body 1, the number of unit metallizations and thereby the number of chip connection regions can be maximized.
Consequently, the loss can be reduced and the yield of devices can be increased due to the described arrangement of carriers .
The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary
embodiments. Rather, the invention encompasses any new feature and also any combination of features, which in particular comprises any combination of features in the patent claims and any combination of features in the
exemplary embodiments, even if this feature or this
combination itself is not explicitly specified in the patent claims or exemplary embodiments.

Claims

Claims
1. Arrangement of carriers (10) for optoelectronic chips (4) comprising
- a base body (1) formed with a ceramic material,
- a plurality of chip connection regions (2), and
- a protection metallization (3) , wherein
- the base body (1) comprises a top surface (la), a bottom surface (lc) and at least one side surface (lb) which connects the top surface (la) with the bottom surface (lc),
- the chip connection regions (2) are arranged on the top surface (la) of the base body (2),
- each chip connection regions (2) is configured to carry at least one optoelectronic chip (4),
- the protection metallization (3) covers all side surfaces (lb) of the base body (1) .
2. The arrangement of claim 1, wherein
- the protection metallization (3) covers a part of the top surface (la), and
- the part of the protection metallization (3) on the top surface (la) surrounds all chip connection regions (2) .
3. The arrangement according to one of the preceding claims further comprising a plurality of mounting regions (5) , wherein
- the mounting regions (5) are arranged on the bottom surface (lc) of the base body (1),
- each mounting region (5) is configured for the electrical and mechanical connection of one carrier (10) of the
arrangement to a circuit board, and
- each mounting region (5) is assigned to one chip connection region (2) in a one-to-one correspondence.
4. The arrangement of claim 3, wherein
- the protection metallization (3) covers a part of the bottom surface (lc), and
- the part of the protection metallization (3) on the bottom surface (lc) surrounds all mounting regions (5) .
5. The arrangement of claim 3 or 4, wherein
- each chip connection region (2) is electrically connected to its assigned mounting regions (5) via at least one through hole ( 6) , and
- the trough hole (6) is formed through the base body (1) and reaches from the top surface (la) to the bottom surface (lb) of the base body (1) .
6. The arrangement according to one of the preceding claims, wherein
each chip connection region (2) and/or each mounting region (5) comprises at least one unit metallization (7) . 7. The arrangement of claim 6, wherein
all metallizations (3,
7) are formed in the same manner.
8. The arrangement according to one of the preceding claims, wherein each metallization (3, 7) comprises at least one metal layer (71) which is in direct contact with the base body.
9. The arrangement according to one of the preceding claims, wherein each metallization (3, 7) comprises at least three layers (71,72,73) of different metals, wherein a first layer (71) of theses layers is in direct contact with the base body (1) and the remaining layers (72, 73) are arranged above each other on the first layer.
10. The arrangement according to one of the preceding claims, wherein each metallization (3, 7) is formed by at least one of the following techniques: sputtering, vapor deposition, galvanic deposition, electroless plating.
11. Method for producing an optoelectronic device comprising the steps of
- providing an arrangement of carriers (10) according to one of the preceding claims,
- electrically and mechanically connecting at least one optoelectronic chip (4) to each connection region (2),
- separating the arrangement into single carriers (10), each carrier (10) having one of the connection region (2) with at least one optoelectronic chip (4).
PCT/EP2011/051322 2011-01-31 2011-01-31 Arrangement of carriers for optoelectronic chips Ceased WO2012103928A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/EP2011/051322 WO2012103928A1 (en) 2011-01-31 2011-01-31 Arrangement of carriers for optoelectronic chips
TW101101894A TWI499014B (en) 2011-01-31 2012-01-18 Carrier configuration for photovoltaic wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2011/051322 WO2012103928A1 (en) 2011-01-31 2011-01-31 Arrangement of carriers for optoelectronic chips

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050184387A1 (en) * 2004-02-25 2005-08-25 Collins William D.Iii Ceramic substrate for a light emitting diode where the substrate incorporates ESD protection
US20060157722A1 (en) * 2004-12-03 2006-07-20 Kabushiki Kaisha Toshiba Semiconductor light emitting device
US20080217762A1 (en) * 2007-03-09 2008-09-11 Phoenix Precision Technology Corporation Chip carrier structure having semiconductor chip embedded therein and metal layer formed thereon

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050184387A1 (en) * 2004-02-25 2005-08-25 Collins William D.Iii Ceramic substrate for a light emitting diode where the substrate incorporates ESD protection
US20060157722A1 (en) * 2004-12-03 2006-07-20 Kabushiki Kaisha Toshiba Semiconductor light emitting device
US20080217762A1 (en) * 2007-03-09 2008-09-11 Phoenix Precision Technology Corporation Chip carrier structure having semiconductor chip embedded therein and metal layer formed thereon

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TW201248794A (en) 2012-12-01
TWI499014B (en) 2015-09-01
WO2012103928A8 (en) 2012-10-11

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