WO2012075461A1

WO2012075461A1 - Defect-free group iii - nitride nanostructures and devices based on repetitive multiple step growth-etch sequence

Info

Publication number: WO2012075461A1
Application number: PCT/US2011/063179
Authority: WO
Inventors: Lei Zhang; Petros M. Varangis
Original assignee: Nanocrystal Corporation
Priority date: 2010-12-02
Filing date: 2011-12-02
Publication date: 2012-06-07

Abstract

Embodiments provide semiconductors including defect free Group III - Nitride nanostructures and uniform nanostructure arrays as well as processes for manufacturing, where features can be precisely controlled. A Repetitive Multiple Step Growth-Etch Sequence can be used to fabricate uniform Group III - Nitride semiconductor nanostructures and/or nanostructure arrays. Furthermore, core-shell nanostructure/MQW active structures can be formed by a core-shell growth on the non-polar sidewalls of each nanostructure and can be configured in nanoscale optoelectronic devices to provide very high efficiencies. Additional growth mode transitions between different Repetitive Multiple Step Growth-Etch Sequences or between a Repetitive Multiple Step Growth-Etch Sequence and conventional growth mode are employed in order to incorporate certain Group III - Nitride compounds into the nanostructures and form devices. In addition. Group III - Nitride substrate structures can be formed by coalescing Group III - Nitride nanostructures and/or nanostructure arrays to fabricate visible LEDs and lasers.

Description

DEFECT-FREE GROUP III - NITRIDE NANOSTRUCTURES AND DEVICES BASED ON REPETITIVE MULTIPLE STEP GROWTH-ETCH SEQUENCE

BY

LEI ZHANG AND

PETROS VARANGIS

DESCRIPTION OF THE INVENTION

Field of the Invention

[0001] This invention relates generally to Group III - Nitride semiconductor materials, including for example Gallium Nitride (GaN), Aluminum Nitride (AIN), Indium Nitride (InN), Aluminum Gallium Nitride (AIGaN), Indium Gallium Nitride (InGaN), and Aluminum Indium Gallium Nitride (AllnGaN), devices, and methods for their manufacture and, more particularly, relates to semiconductor nanostructures and semiconductor nanostructures active devices, such as light emitting diodes (LEDs) and laser diodes (LDs).

Background of the Invention

[0002] Nanostructures composed of Group Ill-Nitride alloys provide the potential for new semiconductor device configurations such as nanoscale

optoelectronic devices. For example, GaN nanostructures can provide large bandgap, high melting point, and chemical stability that is useful for devices operating in corrosive or high-temperature environments. To fully realize this potential, a scalable process is needed for making high-quality Group III - Nitride nanostructures and/or nanostructure arrays with precise and uniform control of the geometry, position and/or crystallinity of each nanostructure.

[0003] Conventional nanostructure fabrication is based on a vapor-liquid-solid (VLS) growth mechanism and involves the use of catalysts such as Au, Ni, Fe, or In. Problems arise, however, because these conventional catalytic processes cannot control the position and uniformity of the resulting nanostructures. A further problem with conventional catalytic processes is that the catalyst is inevitably incorporated into the nanostructures. This degrades the crystalline quality of the resulting nanostructures, which limits their applications. [0004] In order to overcome these and other problems of the VLS growth technique and to provide high-quality nanostructures and/or nanostructure arrays, a new GaN nanowire growth technique called "pulsed MOCVD growth" was proposed by Hersee et al. in Patent US 7,521 ,274 B2 entitled "Pulsed Growth of Catalyst-Free Growth of GaN Nanowires and Application in Group III Nitride Semiconductor Bulk Materiaf. In the aforementioned technique, the substrate used for epitaxial growth was patterned with a selective-area growth mask bearing a two-dimensional pattern and a "pulsed MOCVD growth" method was used for epitaxial growth. The dielectric selective-area growth mask is deposited on the substrate and openings are made on the mask to expose the substrate at locations precisely defined by the nano-scale patterning method such as interferometric lithography or nano-imprint lithography. The growth of GaN nanowires starts with a nucleation step using conventional MOCVD growth in which the Group III precursors, such as Trimethylgallium (TMG), trimethylaluminum (TMA), Trimethylindium (TMI), and, Group V precursors, such as ammonia (NH₃), are introduced simultaneously into the growth chamber of the MOCVD reactor. After the nucleation step, the "pulsed MOCVD growth" technique is used to grow the Group III - Nitride nanowires. The term "pulsed MOCVD growth" refers to a growth process in which the Group III and Group V precursors are introduced alternatively (not simultaneously) into the chamber of the MOCVD reactor. An example of the Group III and Group V precursors' flow rate during the "pulsed MOCVD growth" technique is illustrated in Figure 14. This technique has successfully achieved the formation defect-free Group III - Nitride nanowires with controllable size and location.

[0005] However, the alternate introduction and flow of Group III and Group V precursors during the "pulsed MOCVD growth" mode limits significantly the overlap of the Group III and Group V precursors on the surface of the substrate where epitaxial growth occurs. The growth of Group III - Nitride material occurs only when both Group III and Group V precursors are present at the same location on the surface of the substrate. The "pulsed MOCVD growth" technique relies on the residual presence of Group III and Group V precursors on or near the substrate surface for the growth of the Group III - Nitride nanowires to take place, and also requires that each Group III or Group V precursor is replenished or re-introduced before it is completely depleted. Such growth mode results in a low growth rate and waste of precursor material, which in turn translate into a higher manufacturing cost for wafers and electronic devices. Constantly switching on and off the valves and mass flow controllers of the MOCVD reactor, required in order to implement the "pulsed MOCVD growth" technique, results in the continuous and abrupt change of Group III and Group V partial pressures and V-lll ratio. In turn this results in poor control of the growth conditions, poor repeatability of the epitaxial growth, and to a higher maintenance cost for the MOCVD reactor since the valves and mass flow controllers for the Group III and Group V precursors may need to be replaced more often due to the continuous on-off switching. In this patent application we propose a lower cost, scalable, and controllable growth method defined as "Repetitive Multiple Step Growth-Etch Sequence" for the epitaxial growth of defect-free single-crystal Group III - Nitride nanostructures, which will form the basis of high performance optoelectronic and microelectronic devices.

SUMMARY OF THE INVENTION

[0006] According to various embodiments, the present teachings include a method of making nanostructures. In the method, a selective growth mask can be formed over a substrate. The selective growth mask can include a plurality of patterned apertures that expose a plurality of portions of the substrate. A

semiconductor material can then be grown on each of the plurality of portions of the substrate exposed in each of the patterned apertures using the Repetitive Multiple Step Growth-Etch Sequence growth technique. By continuing the Repetitive Multiple Step Growth-Etch Sequence growth technique of the semiconductor material, a plurality of semiconductor nanostructures can be formed.

[0007] The Repetitive Multiple Step Growth-Etch Sequence refers to a growth process with at least one growth step to allow Group III - Nitride semiconductor nanowires or nanostructures to grow vertically (i.e., along a direction which is vertical with respect to surface of the wafer or substrate) and at least one etch step to remove or etch back the lateral growth of the nanowires or nanostructures which occurred during the preceding growth step (by "lateral growth" we are referring to the growth of nanowires or nanostructures along a direction which is parallel to the surface of the wafer or substrate). The optimized Repetitive Multiple Step Growth- Etch Sequence will result in a zero net growth rate in the lateral direction and a positive net growth rate in the vertical direction for the Group III - Nitride

semiconductor nanostructures. This optimized Repetitive Multiple Step Growth-Etch Sequence then can be repeated as many times as needed in order to manufacture a Group III - Nitride nanostructure array with the desirable characteristics, including height, width, center-to-center spacing and composition. According to various embodiments, the present teachings also include a Group III - Nitride nanostructure array, in accordance with the growth methods described in this section, which array can include a selective area growth mask disposed over a substrate. The selective growth mask can include a plurality of patterned apertures that expose a plurality of portions of the substrate. A Group III - Nitride nanostructure can be connected to and extend from the exposed plurality of portions of the substrate and extend over the top of the selective growth mask. The Group III - Nitride nanostructure can be oriented along a single direction and can maintain a cross-sectional feature of one of the plurality of selected surface regions.

[0008] According to various embodiments, the present teachings further include a Group III - Nitride semiconductor substrate, for example grown as described in the previous section. The substrate structure can be a Group III - Nitride semiconductor film coalesced from a plurality of Group III - Nitride

nanostructures, which is defect-free or almost defect-free (that is, free or almost free of any material defects or dislocations). The Group III - Nitride film can have a defect density of about 100 million defects per centimeter square (cm^"2) or lower.

[0009] Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.

[0012] Figures 1 A, 1 B, andl C depict cross-sectional views of an exemplary semiconductor nanostructure device at various stages of fabrication in accordance with the present teachings. [0013] Figure 2 depicts another exemplary semiconductor nanostructure device in accordance with the present teachings.

[0014] Figures 3A, 3B, 3C and 3D depict the three distinct crystal facet sets existing on a Group III - Nitride nanostructure and the evolution of these facets during the Repetitive Multiple Step Growth-Etch Sequence growth process.

[0015] Figures 4A, 4B, and 4C depict another exemplary semiconductor nanostructure device in accordance with the present teachings.

[0016] Figure 5 depicts another exemplary semiconductor nanostructure device in accordance with the present teachings.

[0017] Figures 6A, 6B, 6C and 6D depict exemplary results for a plurality of ordered Group III - Nitride semiconductor nanostructure arrays grown using the Repetitive Multiple Step Growth-Etch Sequence growth process..

[0018] Figures 7A, 7B, 7C and7D depict four exemplary variants of semiconductor devices including Group III - Nitride semiconductor substrate structures formed from the plurality of nanostructures and/or nanostructure arrays shown in Figures 1 through 6 in accordance with the present teachings.

[0019] Figure 8 depicts an exemplary core-shell Group III - Nitride

semiconductor nanostructure / Multiple Quantum Well ("MQW") active structure device in accordance with the present teachings.

[0020] Figure 9 depicts another exemplary core-shell Group III - Nitride semiconductor nanostructure / MQW active structure device in accordance with the present teachings.

[0021] Figures 10A, 10B and10C depict an exemplary Group III - Nitride semiconductor nanostructure Light Emitting Diode ("LED") device formed using the core-shell nanostructure/MQW active structure described in Figures 8 and 9 in accordance with the present teachings.

[0022] Figure 1 1 depicts an exemplary Group III - Nitride semiconductor nanostructure laser device using the core-shell nanostructure/MQW active structure described in Figures 8 and 9 in accordance with the present teachings.

[0023] Figure 12 depicts another exemplary Group III - Nitride semiconductor nanostructure laser device using the core-shell nanostructure/MQW active structure described in Figures 8 and 9 in accordance with the present teachings.

[0024] Figures 13A, 13B, 13C and 13D depict examples of the flow rate of

Group III precursors, such as Trimethylgallium (TMG), trimethylaluminum (TMA), Trim ethyl indium (TMI), and Group V precursors, such as ammonia (NH₃), as a function of time during the Repetitive Multiple Step Growth-Etch Sequence growth process. The flow rates "0", "1 ", and "0.5" mean completely shut off, high flow rate, and intermediate flow rate, respectively. These examples are used to demonstrate the key concept of the growth method described in the present teachings, whereas the actual value of each parameter will be optimized according to the specifications for the nanostructures or devices.

[0025] Figure 14 depicts the flow rate of Group III precursors, such as

Trimethylgallium (TMG), trimethylaluminum (TMA), Trimethylindium (TMI), and Group V precursors, such as ammonia (NH₃), as a function of time for the prior art "pulsed MOCVD growth" technique.

DESCRIPTION OF THE EMBODIMENTS

[0026] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings.

Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, merely exemplary.

[0027] While the invention has been illustrated with respect to one or more implementations, alterations and/or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular function. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." The term "at least one of is used to mean one or more of the listed items can be selected. [0028] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of "less than 10" can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5.

[0029] Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) Group III - Nitride nanostructures and uniform Group III - Nitride nanostructure arrays as well as scalable processes for their manufacturing, where the position, orientation, cross-sectional features, length and/or the

crystallinity of each nanostructure can be precisely controlled. Specifically, a plurality of nanostructures and/or nanostructure arrays can be formed using a

Repetitive Multiple Step Growth-Etch Sequence. The cross-sectional features, for example, the cross-sectional dimensions (e.g., diameter or width), and the cross- sectional shapes, of each nanostructure obtained can be maintained by continuing the growth using the Repetitive Multiple Step Growth-Etch Sequence. In this manner, nanostructures with a high aspect ratio can be formed. In an exemplary embodiment, the length of each nanostructure can be, for example, about 10 nanometers (nm) to about 20 micrometers (μηη), or more. After the Repetitive Multiple Step Growth-Etch Sequence achieves the desired Group-Ill Nitride nanostructures, further growth includes transitions between the Repetitive Multiple Step Growth-Etch Sequence and conventional growth mode which can be used to form a desired device epi-structure, for example, an InGaN MQW structure, on the surface of the Group-Ill Nitride nanostructures.

[0030] In addition, high-quality (i.e., defect-free) Group III - Nitride

semiconductor films, for example, high-quality GaN films, can be formed by terminating and coalescing the plurality of nanostructures and/or nanostructure arrays. These Group III - Nitride films can be used as Group III - Nitride substrate structures to facilitate the fabrication of visible LEDs and lasers for the emerging solid-state lighting and UV sensor industries. [0031] Furthermore, because each of the nanostructures and/or arrays can provide non-polar sidewalls, a core-shell growth can be realized on each Group III - Nitride nanostructure with an MQW active shell structure formed thereon. Such core-shell nanostructure/MQW active structures can be used in nanoscale

optoelectronic devices, such as, for example, nanostructure LEDs and/or

nanostructure lasers having high efficiencies.

[0032] As used herein, the term "nanostructure" generally refers to any elongated conductive or semiconductive material that includes at least one minor dimension, for example, one of the cross-sectional dimensions such as width or diameter, of less than or equal to about 100 micrometers (μηη). In various

embodiments, the minor dimension can be less than about 100 nm. In various other embodiments, the minor dimension can be less than about 10 nm. The

nanostructures can have an aspect ratio (e.g., length: width and/or major dimension: minor dimension) of about 3 or greater. In various embodiments, the aspect ratio can be about 10 or greater. In various other embodiments, the aspect ratio can be about 100 or greater. In an exemplary embodiment the cross-section of the nanostructure can be highly asymmetric such that in one direction the cross- sectional dimension can be much less than 1000 nanometers (nm) and in an orthogonal direction the dimension can be substantially greater than 1000 nm.

[0033] It is also intended that the term "nanostructures" also encompass other elongated structures of like dimensions including, but not limited to, nanoshafts, nanopillars, nanoneedles, nanorods, nanowalls, and nanotubes (e.g., single wall nanotubes, or multiwall nanotubes), and their various functionalized and derivatized fibril forms, such as nanofibers in the form of thread, yarn, fabrics, etc.

[0034] The nanostructures can have various cross-sectional shapes, such as, for example, rectangular, polygonal, square, oval, one-dimensional stripe, or circular shape. Accordingly, the nanostructures can have cylindrical and/or cone-like three dimensional (3-D) shapes. In various embodiments, a plurality of nanostructures can be, for example, substantially parallel, sinusoidal, etc., with respect to each other.

[0035] The nanostructures can be formed on/from a support, which can include selected surface regions where the nanostructures can be connected to and extend (e.g., be grown) from. The support of the nanostructures can also include a substrate formed from a variety of materials including Si (Silicon), SiC (Silicon Carbide), sapphire, Group III - Group V semiconductor compounds such as, for example, GaN (Gallium Nitride) or GaAs (Gallium Arsenide), metals, ceramics or glass. The support of the nanostructures can also include a selective growth mask formed on the substrate. In various embodiments, the support of the nanostructures can further include a buffer layer disposed between the selective growth mask and the substrate.

[0036] In various embodiments, semiconductor nanostructure active devices, for example, nanostructure LEDs or nanostructure lasers, can be formed using the nanostructures and/or nanostructure arrays. In various embodiments, the nanostructures and/or nanostructure arrays and the nanostructure active devices can be formed using a Group III - Group V compound semiconductor materials system, for example, the Group III - Nitride compound materials system. Examples of the Group III elements can include Ga, In, or Al, which can be formed from exemplary Group III precursors, such as trimethylgallium (TMGa) or triethylgallium (TEGa), trimethylindium (TMIn) or trimethylaluminum (TMAI). Exemplary Group V precursors can be Nitrogen (N) precursors, for example, ammonia (NH₃). Other Group V elements can also be used, for example, P or As, with exemplary Group V precursors, such as tertiarybutylphoshine (TBP), or arsine (AsH₃).

[0037] In the following description, Group III - Nitride semiconductor alloy compositions can be described by the combination of Group III - Nitride elements, such as, for example, GaN (Gallium Nitride), AIN (Aluminum Nitride), InN (Indium Nitride), InGaN (Indium Gallium Nitride), AIGaN (Aluminum Gallium Nitride), or AllnGaN (Aluminum Indium Gallium Nitride). Generally, the elements in a composition can be combined with various molar fractions. For example, the semiconductor alloy composition InGaN can stand for ln_xGai- N, where the molar fraction, x, can be any number less than 1 .00. In addition, depending on the molar fraction value, various active devices can be made by similar compositions. For example, an lno_.3Gao_.7N (where x is about 0.3) can be used in the MQW (Multi- Quantum Well) active region of LEDs for a blue light emission, while an lno_.43Gao_.57N (where x is about 0.43) can be used in the MQW active region of LEDs for a green light emission.

[0038] In various embodiments, the Group III - Nitride nanostructures, nanostructure arrays, and/or the nanostructure active devices can include a dopant from a group consisting of: a p-type dopant from Group III of the periodic table, for example B, Al and In; an n-type dopant from Group V of the periodic table, for example, P, As and Sb; a p-type dopant from Group II of the periodic table, for example, Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table, for example, C; or an n-type dopant selected from a group consisting of: Si, Ge, Sn, S, Se and Te.

[0039] In various embodiments, the Group III - Nitride nanostructures and/or nanostructure arrays as well as the nanostructure active devices can have high- quality heterogeneous structures and be formed by various crystal growth

techniques including, but not limited to, metal-organic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE), gas source MBE (GSMBE), metal- organic MBE (MOMBE), atomic layer epitaxy (ALE), hydride vapor phase epitaxy (HVPE), or organometallic vapor phase epitaxy (OMVPE). When a Group III - Nitride semiconductor is to be grown by one of the aforementioned methods the molar ratio of a nitrogen source or Group V precursor gas to a Group III source or precursor gas is usually referred to as V/lll ratio.

[0040] In various embodiments, a Repetitive Multiple Step Growth-Etch Sequence, for example, a two step growth-etch sequence, can be used for the high- quality crystal growth of nanostructures and/or nanostructure arrays as well as nanostructure active devices. For example, a growth step can be used first to allow the Group III - Nitride semiconductor nanostructures to grow in all directions, then followed by an etch step to selectively etch back, in the lateral direction, the growth that occurred during the preceding growth step. The result of this two step growth- etch sequence is that the nanostructures have a positive growth rate in the vertical direction and zero growth rate in the lateral direction. By repeating this two step growth-etch sequence, continuous growth of nanostructures in the vertical direction only can be achieved.

[0041] The term Repetitive Multiple Step Growth-Etch Sequence refers to a growth process that has at least one growth step to allow the Group III - Nitride semiconductor nanowires to grow in the vertical direction, and at least one etch step which will etch back, in the lateral direction, the growth that occurred during the preceding growth step(s). The aforementioned growth step(s) has to terminate before the growth in the lateral direction causes the individual nanowires to coalesce with each other. Also, the aforementioned etch step(s) has to terminate before the etching in the lateral direction completely dissolves the nanowires. [0042] As illustrated in Figures 3A, 3B, 3C and 3D, three distinctive facet sets exist in Group III - Nitride nanostructures or nanowires, namely the {0001 } or top facets, the {1011} or slanted facets, and the {1010} or sidewall facets. These three facet sets may exhibit different growth rate during a growth step, and different etch rate during an etch step of the Repetitive Multiple Step Growth-Etch Sequence.

[0043] The Repetitive Multiple Step Growth-Etch Sequence may include more than one growth steps and more than one etch steps in order to achieve nanowires with the desired characteristics and shape, e.g. flat top (i.e., eliminating the {1011} facet).

[0044] For each growth step and etch step of the Repetitive Multiple Step Growth-Etch Sequence, the growth rate and the etch rate, respectively, are functions of growth parameters including but not limited to: Growth chamber pressure, Growth temperature, Flow rates of various gases, V/lll ratio, H₂ partial pressure, duration of each step, etc.

[0045] Within each growth step and etch step of the Repetitive Multiple Step Growth-Etch Sequence, each of the growth parameters can be set to (1 ) Holding constant or (2) Ramping up or down.

[0046] Transition from one step to the next step of the Repetitive Multiple Step Growth-Etch Sequence (for example, transition from a growth step to an etch step or vice versa), each of the growth parameters can be increased or decreased abruptly or gradually, for example: (1 ) The flow of precursor gases (e.g., TMGa, NH3, SiH4, (Mg)2xxx etc) and carrier gases (e.g., H2/N2) can be shut off, increased or decreased abruptly or gradually; (2) The Growth temperature and pressure can be increased or decreased abruptly or gradually; (3) The duration of a step can be increased or decreased or remain the same as in the previous step.

[0047] Examples of the flow rates of the Group-Ill and Group-V precursors during the Repetitive Multiple Step Growth-Etch Sequence are illustrated in Figures 13A, 13B, 13C and 13D. The optimized Repetitive Multiple Step Growth-Etch Sequence will result in Group III - Nitride nanostructures with a zero net growth rate in the lateral direction and a positive net growth rate in the vertical direction. Such optimized Repetitive Multiple Step Growth-Etch Sequence can be applied until Group III - Nitride nanostructures with the desirable shape, height, morphology and characteristics are formed. [0048] In various embodiments, an initial nucleation growth step can be used before the Repetitive Multiple Step Growth-Etch Sequence is applied in order to nucleate the growth surface and create the desired platform for the subsequent growth of the Group III - Nitride semiconductor nanostructures with a desired thickness of, for example, about 1 nm or more.

[0049] In various embodiments, a second Repetitive Multiple Step Growth- Etch Sequence or a conventional growth can be used to allow further growth, for example, of InGaN MQW structures on the surface of Group III - Nitride

nanostructures, both in the lateral direction and in the vertical direction, to form an InGaN/GaN MQW core-shell nanostructure. In this growth period, the optimized growth should result in a positive growth rate for the nanostructures both in the vertical and lateral directions.

[0050] In various embodiments, a third Repetitive Multiple Step Growth-Etch Sequence or a conventional growth can be used to allow further growth, for example, of p-type GaN on the surface of InGaN/GaN MQW core-shell nanostructures, both in the lateral direction and in the vertical direction, to form InGaN/GaN MQW p-i-n core- shell nanostructure-LED epitaxial structures. In this growth period, the optimized growth should result in a positive growth rate for the nanostructures both in the vertical and lateral directions.

[0051] In various embodiments, dielectric materials can be involved in the disclosed Group III - Nitride nanostructures, nanostructure arrays, and/or

nanostructure active devices. For example, the selective growth mask can be made of dielectric materials during the formation of the plurality of nanostructures and/or nanostructure arrays. In another example, dielectric materials can be used for electrical isolation for active devices such as nanostructure LEDs and/or

nanostructure lasers. As used herein, the dielectric materials can include, but are not limited to, silicon oxide (S1O2), silicon nitride (Si3N ), silicon oxynitride (SiON), fluorinated silicon dioxide (SiOF), silicon oxycarbide (SiOC), hafnium Oxide (HfO₂), hafnium-silicate (HfSiO), nitride hafnium-silicate (HfSiON), zirconium oxide (ZrO2), aluminum oxide (AI2O3), barium strontium titanate (BST), lead zirconate titanate (PZT), zirconium silicate (ZrSiO2), tantalum oxide (TaO2) or other insulating materials. [0052] Exemplary embodiments for semiconductor devices of nanostructures and/or nanostructure arrays and their scalable processes for growth are shown in Figure 1 through Figure 12.

[0053] Figures 1A, 1 B and 1 C depict cross-sectional views of an exemplary semiconductor nanostructure device 100 at various stages of fabrication in

accordance with the present teachings. It should be readily apparent to one of ordinary skill in the art that the nanostructure device 100 depicted in Figures 1A through 1 C represents a generalized schematic illustration and that other

layers/nanostructures may be added or existing layers/nanostructures may be removed or modified.

[0054] As shown in Figure 1A, the nanostructure device 100 can include a substrate 1 10, a selective growth mask 135, and a plurality of patterned apertures 138. The selective growth mask 135 and the plurality of patterned apertures 138 can be disposed over the substrate 1 10, wherein the plurality of patterned apertures 138 can be interspersed through the selective growth mask 135.

[0055] The substrate 1 10 can be any substrate on which a Group III - Nitride semiconductor material can be grown. In various embodiments, the substrate 1 10 can include, but is not limited to, sapphire, silicon carbide, silicon, silicon-on-insulator (SOI), Group III - Group V semiconductor compounds such as GaN or GaAs, metals, ceramics or glass.

[0056] The selective growth mask 135 can be formed by patterning and etching a dielectric layer (not shown) formed over the substrate 1 10. In various embodiments, the dielectric layer can be made of any dielectric material and formed using techniques known to one of ordinary skill in the art. The dielectric layer can then be patterned using one or more of interferometric lithography ("IL") including immersion interferometric lithography and nonlinear interferometric lithography, nanoimprint lithography ("NL"), e-beam lithography and other patterning techniques, which can produce nanostructures or patterns of nanostructures over wide and macroscopic areas. After the patterning, an etching process, for example, a reactive ion etching can be used to form the plurality of patterned apertures 138. The etching process can be stopped at the surface of the underlying layer, i.e., the substrate 1 10, and exposing a plurality of surface portions 139 of the substrate 1 10. In various embodiments the selective growth mask 135 can be a metal or other material growth mask made of, for example, tungsten or other material, to provide selective growth of nanostructures as desired by the Repetitive Multiple Step Growth-Etch Sequence.

[0057] The plurality of patterned apertures 138 can have a thickness the same as the selective growth mask 135, for example, about 10 micrometers (V^m") or less, and a cross-sectional dimension, such as a diameter, of about 10 nanometers ("nm") to about 100 μΐη or more. As an additional example, the diameter can be about 10 to about 1000 nm. In an exemplary embodiment, the plurality of patterned apertures 138 can have a hexagonal array with a pitch (i.e., center-to-center spacing between any two adjacent patterned apertures) ranging from about 20 nm to about 200 micrometers (μηη) or more. In various embodiments, arrays of the plurality of patterned apertures 138 can be formed. Thereafter, the nanoscale features of the plurality of the patterned apertures 138 can be transferred to the subsequent processes for the formation of nanostructures and/or nanostructure arrays as desired by the Repetitive Multiple Step Growth-Etch Sequence.

[0058] In various embodiments, various cleaning procedures can be

conducted on the device 100 shown in Figure 1A prior to the subsequent growth of the nanostructures and/or nanostructure arrays. For example, the cleaning processes can include an ex-situ cleaning (i.e., the cleaning is conducted outside the growth reactor) followed by an in-situ cleaning (i.e., the cleaning is conducted within the growth reactor). Depending on materials used for the selective growth mask 135, various cleaning methods can be used. In an exemplary embodiment, a silicon nitride selective growth mask can be cleaned by a standard ex-situ cleaning followed by an in-situ cleaning by loading the device 100 into an exemplary MOCVD reactor and heating the device 100 to about 950 °C for approximately 3 minutes under flowing hydrogen. This hydrogen-reducing-atmosphere can remove undesirable native oxides on the surfaces of the device 100. Depending on the material combination of the substrate 1 10 and the selective growth mask 135, one of ordinary skill in the art will understand that alternative cleaning procedures can be used.

[0059] In Figure 1 B, a plurality of nanostructure nuclei 140 can be selectively grown from the exposed plurality of surface portions 139 of the substrate 1 10 to fill each of the plurality of patterned apertures 138, which can be defined by the selective growth mask 135. The selective growth mask 135 can serve as a selective growth mold to negatively replicate its nanopatterns from the plurality of patterned apertures 138 to the plurality of nanostructure nuclei 140. In this manner, the position and the cross-sectional features, such as the shape and dimensions, of each of the plurality of nanostructure nuclei 140 can be determined by that of each patterned aperture of the plurality of patterned apertures 138. For example, the plurality of patterned apertures 138 can include a hexagonal array with a dimension of about 250 nm. The hexagonal array can then be transferred to the growth of the plurality of nanostructure nuclei 140 with a similar or smaller dimension of about 250 nm or less. In another example, if the one or more apertures of the plurality of patterned apertures 138 are approximately circular with an exemplary diameter of about 100 nm, one or more nuclei of the plurality of nanostructure nuclei 140 can be grown in the circular apertures with a similar diameter of about 100 nm or less. Thus, the plurality of nanostructure nuclei 140 can be positioned in a well-defined location and shaped correspondingly to the plurality of the patterned apertures 138 defined by the selective growth mask 135. In various embodiments, the plurality of nanostructure nuclei 140 can be formed during the initial nucleation growth step by, for example, a standard MOCVD process.

[0060] In this manner, the device 100 shown in Figure 1 B can be used as a support for nanostructures and/or nanostructure arrays, which can include a plurality of selected surface regions (i.e., each surface of the plurality of nanostructure nuclei 140). A plurality of nanostructures and/or nanostructure arrays can then be grown from the plurality of selected surface regions. In various embodiments, the selective growth mask 135 can be removed by a suitable etching process to expose the plurality of nanostructure nuclei 140 after the formation of the plurality of the nanostructures.

[0061] In Figure 1 C, a plurality of Group III - Nitride semiconductor

nanostructures 145 can be formed by continuing the growth of the plurality of nanostructure nuclei 140 by, for example, terminating the nucleation growth step and starting a Repetitive Multiple Step Growth-Etch Sequence growth mode, before the plurality of nanostructure nuclei 140 protrudes from a top of the selective growth mask 135. The plurality of nanostructures 145 can be formed of the same material of the nanostructure nuclei 140, for example, GaN, AIN, InN, InGaN, AllnGaN, or AIGaN, as well as any other Group III - Nitride semiconductor material. In various embodiments, heterostructures can be formed from each of the plurality of nanostructures 145. In various embodiments, n-type and/or p-type dopants can be incorporated into the plurality of nanostructures 145 depending on the desired application.

[0062] By transitioning to the Repetitive Multiple Step Growth-Etch Sequence growth mode before the growth of the plurality of nanostructure nuclei 140 protrudes from the top of the selective growth mask 135, features such as cross-sectional shape and dimensions of each of the plurality of nanostructures 145 can be preserved until a desired length is reached. In other words, the cross-sectional features of the nanostructures 145, such as, for example, shape and/or dimension, can remain substantially constant, the same or similar as that of the apertures 138. In various embodiments, the length of each nanostructure can be on an order of micrometers, for example, up to about 20 μηη or more.

[0063] After the initial growth of nanostructures 145 is completed, one or more subsequent growth mode transitions from the Repetitive Multiple Step Growth-Etch Sequence to the conventional growth mode or other Repetitive Multiple Step Growth- Etch Sequences, as well as subsequent growth mode transitions from the

conventional growth mode to the Repetitive Multiple Step Growth-Etch Sequence, are performed in order to more effectively incorporate Group III - Nitride

semiconductor compounds, such as GaN, AIN, InN, InGaN, AllnGaN, or AIGaN, into the structure of the nanostructures 145 and in order to form nanostructures 145 of the designed shape, size, diameter, length, morphology, stochiometric composition and other characteristics.

[0064] In various embodiments, a buffer layer can be formed in the

nanostructure devices. Figure 2 depicts a second exemplary Group III - Nitride semiconductor nanostructure device 200 including a buffer layer in accordance with the present teachings. As shown, the nanostructure device 200 can include a buffer layer 220 disposed between a substrate such as the substrate 1 10 and a selective growth mask such as the selective growth mask 135 (see Figures 1A-1 C). In various embodiments, the buffer layer 220 can be a planar Group III - Nitride semiconductor film formed of, for example, GaN, AIN, InN, InGaN, AllnGaN or AIGaN, by, for example, standard MOCVD. In various embodiments, the thickness of the buffer layer 220 can be, for example, about 10 nm to about 10 micrometers (μηη) or more. In various embodiments the buffer layer 220 can be doped with either an n-type or a p-type dopant in order to provide an electrical connection to the lower end of each nanostructure of the plurality of nanostructures 140. Various dopants known to one of ordinary skill can be used.

[0065] In various embodiments, the orientation of the plurality of nanostructure nuclei 140 can be controlled along a single direction, which can in turn be controlled by intentionally orienting the plurality of patterned apertures 138 along the single crystal direction. For example, the plurality of patterned apertures 138 can be intentionally oriented along a single direction of the buffer layer 220 as shown in Figure 2. In an exemplary embodiment during interferometric lithography or imprint lithography patterning, the apertures in the selective growth mask 135 can be intentionally oriented along the <1 1_00> direction of a GaN buffer layer. In another exemplary embodiment when the GaN buffer layer is grown on a sapphire substrate, there can be a 30° rotation about the c axis between the GaN buffer layer and the sapphire unit cells.

[0066] In various embodiments, a Repetitive Multiple Step Growth-Etch Sequence consists of at least one growth step and at least one etch step. Figures 13A through 13D depict exemplary processes for the first two loops (cycles) of the Repetitive Multiple Step Growth-Etch Sequence. Specifically, Figures 13A through 13D illustrate gas flow curves of exemplary precursors (e.g., TMGa, NH3) and carrier gases (e.g., N2, H2). Figure 13A depicts one example of a Repetitive Multiple Step Growth-Etch Sequence in which each cycle or loop consists of one growth step ("Step 1 ") and one etch step ("Step 2"). During the growth step (Step 1 ), the Group-Ill precursor (TMGa) and Group-V precursor (NH3) are introduced to the growth chamber simultaneously to facilitate the growth of Group III - Nitride nanostructures. The H2 flow rate is holding low during this growth step to avoid etching or excessive etching of the Group III - Nitride nanostructures. During the etch step (Step 2), both the Group-Ill precursor (TMGa) and Group-V precursor (NH3) are turned off while the H2 flow rate is increased, which results in etching back the part of the Group III - Nitride nanostructures that grew along the lateral direction during the preceding growth step (Step 1 ) and therefore prevents the growth of the Group III - Nitride nanostructures along the lateral direction and furthermore allows the growth of the Group III - Nitride nanostructures only along the vertical direction. In this example, the gas flow rates are constant during each growth step (Step 1 ) and etch step (Step 2) and change abruptly between such steps. [0067] Figure 13B depicts another example of a Repetitive Multiple Step Growth-Etch Sequence in which each cycle or loop consists of two growth steps (Step 1 and Step 2) and one etch step (Step 3). During the growth steps, the Group- Ill precursor (TMGa) and Group-V precursor (NH3) are introduced into the growth chamber simultaneously, in order to facilitate the growth of Group III - Nitride nanostructures, and the H2 flow rate is held at a low level in order to avoid etching or excessive etching of the Group III - Nitride nanostructures. The utilization of two growth steps during each loop allows for more flexibility and easier optimization of the growth rate of each facet set of the Group III - Nitride nanostructures. During the etch step (Step 3), the Group-Ill precursor (TMGa) is turned off and the Group-V precursor (NH3) is held at a lower level or turned off, while the H2 flow rate is increased, which results in etching back the part of the Group III - Nitride

nanostructures that grew along the lateral direction during the preceding two growth steps (Step 1 and Step 2) and therefore prevents the growth of the Group III - Nitride nanostructures along the lateral direction and furthermore allows the growth of the Group III - Nitride nanostructures only along the vertical direction. In this example, the gas flow rates are constant during the growth steps (Step 1 and Step 2) and during the etch step (Step 2) and change abruptly between such steps.

[0068] In various embodiments, one or more of the growth parameters, such as the flow rate of precursor gases (e.g., NH3, TMGa, TMIn, TMAI etc) and carrier gases (e.g., N2, H2), chamber pressure, and growth temperature, can be held constant or ramp up or down during a growth or etch step. Figure 13C depicts another example of a Repetitive Multiple Step Growth-Etch Sequence where each loop consists of two growth steps (Step 1 and Step 2) and one etch step (Step 3). In this example, the gas flow rates are constant within each step and change abruptly between steps, with the exception of the flow rate of TMGa which changes gradually by ramping down during Step 2.

[0069] Figure 13D depicts another example of a Repetitive Multiple Step Growth-Etch Sequence in which each loop consists of one growth step (Step 1 ) and two etch steps (Step 2 and Step 3). During the growth step, the Group-Ill precursor (TMGa) and the Group-V precursor (NH3) are introduced into the growth chamber simultaneously whereas the H2 gas is completely off (i.e., zero flow rate). During the first etch step (Step 2), both the Group-Ill precursor (TMGa) and the Group-V precursor (NH3) ramp down to zero while the H2 gas is turned on (i.e., high flow rate). Subsequently, the flow rates of the aforementioned gases remain constant during the second etch step (Step 3). The use of two etch steps provides additional flexibility in tailoring the shape and other characteristics of the Group III - Nitride nanostructures.

[0070] All the growth parameters in the preceding examples are merely exemplary and will be optimized in order to achieve zero growth rate for the Group III - Nitride nanostructures along the lateral directions and positive growth rate along the vertical direction after each loop of the Repetitive Multiple Step Growth-Etch Sequence. Such optimized Repetitive Multiple Step Growth-Etch Sequence can be repeated until Group III - Nitride nanostructures with the desired characteristics are formed.

[0071] In various embodiments, the growth of the plurality of the Group III - Nitride semiconductor nanostructures and/or nanostructure arrays can be affected by the timing of the transition from the nucleation growth step to the Repetitive Multiple Step Growth-Etch Sequence. For example, such growth mode transition can be applied after the growth of the plurality of nanostructure nuclei 140 protrude over the top of the selective growth mask 135shown in Figures 1 and 2. In various

embodiments, Group III - Nitride nanostructures and/or nanostructure arrays with different characteristics are obtained depending on whether the aforementioned growth mode transition is applied "before" (e.g., as shown in Figures 1 and 2) or "after" the nanostructure nuclei have grown to protrude over the top of the selective growth mask.

[0072] Figures 4A, 4B and 4C depict an exemplary Group III - Nitride semiconductor nanostructure device 400 formed by having the aforementioned growth mode transition from the nucleation growth step to the Repetitive Multiple Step Growth-Etch Sequence after the nanostructure nuclei have grown to protrude over the top of the selective growth mask 435. It should be readily apparent to one of ordinary skill in the art that the nanostructure device 400 depicted in Figures 4A through 4C represents a generalized schematic illustration and that other

layers/nanostructures can be added or existing layers/nanostructures can be removed or modified.

[0073] In Figure 4A, the device 400 can include a similar structure and be formed by a similar fabrication process as described in Figure 1 C for the device 100. As shown, the device 400 can include a substrate 410, a selective growth mask 435 and a plurality of nanostructure nuclei 440. The selective growth mask 435 and the plurality of nanostructure nuclei 440 can be formed over the substrate 410, wherein the plurality of nanostructure nuclei 440 can be interspersed through the selective growth mask 435.

[0074] The substrate 410 can be any substrate similar to the substrate 1 10 of the device 100, on which a Group III - Nitride semiconductor material can be grown. The substrate 410 can be, for example, sapphire, silicon carbide, or silicon or other. Likewise, the plurality of nanostructure nuclei 440 can be formed similarly to that of the plurality of nanostructure nuclei 140 of the device 100 shown in Figure 1 B. For example, the plurality of nanostructure nuclei 440 can be formed by first forming a plurality of patterned apertures (not shown) defined by the selective growth mask 435 over the substrate 410. Each of the plurality of patterned apertures can then be filled by growing a semiconductor material (e.g., GaN or other Group III - Nitride semiconductor compound) therein using, for example, standard MOCVD or other epitaxial growth techniques. The plurality of nanostructure nuclei 440 can have a thickness of the selective growth mask 435, for example, about 5 nm or larger, and a cross-sectional dimension, such as a width or a diameter, of, for example, about 10 nm to about 100 micrometers (μηη) or any other. And as an additional example, the width or diameter of the cross-sectional dimension can be about 10 nm to about 10 micrometers (μηη) or other.

[0075] In Figure 4B, the device 400 can include a plurality of nanostructures 442 grown laterally as well as vertically from the plurality of nanostructure nuclei 440, when the growth mode transition from the nucleation growth step to the Repetitive Multiple Step Growth-Etch Sequence occurs after the plurality of nanostructure nuclei 440 protrudes over the top of the selective growth mask 435. For example, each of the plurality of nanostructures 442 can be grown laterally, spreading sideways and partially on the surface of the selective growth mask 435. In various embodiments, the plurality of nanostructures 442 can include a pyramid-shaped structure providing a top crystal facet. For example, a plurality of GaN or other Group III - Nitride semiconductor pyramid-shaped nanostructures can include a (0001 ) top facet and the dimensions of this top facet can be controlled by the extent of the growth of each nanostructure. Specifically, at the early stage of the growth, when the plurality of nanostructures 442 is growing laterally, partially on the surface of the selective growth mask 435, the top facet dimensions can be increased and be broader than the cross-sectional dimensions of the plurality of nanostructure nuclei 440. When the growth is continued, the top facet dimensions can be decreased such that a point of the top facet dimensions can be smaller than that of the plurality of nanostructure nuclei 440. Therefore, the dimensions of each pyramid top facet can be controlled by applying the growth mode transition to stop the growth of the plurality of pyramid-shaped nanostructures. The top facet dimension can then be maintained for the subsequent growth of the nanostructures and/or nanostructure arrays using the Repetitive Multiple Step Growth-Etch Sequence. In various embodiments, the top facet diameter of each of the plurality of nanostructures 442 can be controlled to be smaller than that of each of the plurality of the nanostructure nuclei 440.

[0076] The device 400 shown in Figure 4B can be used as a support of nanostructures and/or nanostructure arrays, which can also include a plurality of selected surface regions (i.e., the surface of each top facet of the plurality of nanostructures 442). A plurality of Group III - Nitride semiconductor nanostructures and/or nanostructure arrays can then be grown from the plurality of selected surface regions and maintain the cross-sectional features (e.g., dimensions and shapes) of each of the plurality of selected surface regions.

[0077] In Figure 4C, a plurality of Group III - Nitride semiconductor

nanostructures 445 can be formed by continuing the growth of the Group III - Nitride semiconductor material (e.g., GaN) from the plurality of selected surface regions of the device 400 (i.e., from each top facet of the plurality of nanostructures 442) using the Repetitive Multiple Step Growth-Etch Sequence. As a result, the plurality of nanostructures 445 can be regularly spaced and have an exemplary diameter ranging from about 10 nanometers (nm) to about 100 micrometers (μηη) or larger.

[0078] By using the Repetitive Multiple Step Growth-Etch Sequence after the semiconductor material is grown to protrude over the top of the selective growth mask 435, the plurality of nanostructures 445 can be formed on the top facets of the exemplary pyramid-shaped structures of the plurality of nanostructures 442.

Features such as cross-sectional shapes and dimensions of each of the plurality of nanostructures 445 can remain constant until a desired length is reached. In various embodiments, the length of each nanostructure can be controlled on an order of micrometers, such as, for example, up to about 20 μηη or higher. [0079] After the initial growth of nanostructures 445 is completed, one or more subsequent growth mode transitions between one Repetitive Multiple Step Growth- Etch Sequence and another Repetitive Multiple Step Growth-Etch Sequence, or between one Repetitive Multiple Step Growth-Etch Sequence and a conventional growth mode , are performed in order to more effectively incorporate Group III - Nitride semiconductor compounds, such as GaN, AIN, InN, InGaN, AllnGaN, or AIGaN or other, into the structure of the nanostructures 445 and in order to form nanostructures 445 of the designed shape, size, diameter, length, morphology and stochiometric composition or other characteristics.

[0080] Figure 5 depicts another exemplary Group III - Nitride semiconductor nanostructure device 500 including a buffer layer in accordance with the present teachings. As shown, the nanostructure device 500 can include a buffer layer 520 disposed between a substrate, such as the substrate 410, and a selective growth mask, such as the selective growth mask 435. The buffer layer 520 can be a similar layer to the buffer layer 220 shown in Figure 2. The buffer layer 520 can be a planar Group III - Nitride semiconductor film formed of, for example, GaN, AIN, InN or AIGaN, or other semiconductor or material compound using, for example, standard MOCVD or other growth technique. In various embodiments, the thickness of the buffer layer 520 can be about 1 nm to about 100 micrometers (μηη) or larger. In various embodiments the buffer layer 520 can be doped with either a p-type or n- type dopant in order to provide with an electrical connection to the lower end of each nanostructure.

[0081] Figures 6A through 6D depict exemplary results for a plurality of ordered Group III - Nitride semiconductor nanostructures and/or nanostructure arrays without use of a catalyst using the Repetitive Multiple Step Growth-Etch Sequence. As shown in Figures 6A-6D, the plurality of Group III - Nitride

semiconductor nanostructures 610 can grow with large scale uniformity of position, orientation, length, cross-sectional features (e.g., the dimensions and/or shapes), and crystal I in ity. As described herein, in some embodiments, the position and dimensions of each nanostructure can correspond with that of each aperture of the plurality of patterned apertures 138 shown in Figures 1 -2. In other embodiments, the position and dimensions of each nanostructure can correspond with that of each top facet of the plurality of nanostructures 442 shown in Figures 4-5. [0082] Figure 6A shows a close-up scanning electron micrograph (SEM) result for the exemplary Group III - Nitride semiconductor nanostructures 610, while Figure 6B shows a SEM result with long-range order for the Group III - Nitride

nanostructures 610. In various embodiments, each Group III - Nitride nanostructure can have a single crystal nature.

[0083] Figure 6C shows that the orientation of the Group III - Nitride

nanostructures 610 can be along a single crystal direction, for example, along the (0001 ) crystallographic direction of the exemplary nanostructures 610. Additionally, the small central (0001 ) top facet of each nanostructure can be bounded by inclined {1102} facets on top of each nanostructure.

[0084] Figure 6D is a plan view of the exemplary Group III - Nitride

nanostructures 610 showing the hexagonal symmetry of the sidewall facets of each nanostructure. The sidewall facets can be perpendicular to the direction of the selective growth mask having the sidewall facets of the {1100} family. In various embodiments, the diameter of the exemplary nanostructures 610 can be about 10 nanometers (nm) or larger.

[0085] In various embodiments, the uniform and high-quality Group III - Nitride semiconductor nanostructures and/or nanostructure arrays can be used for fabrication of high-quality ultra-low defect density Group III - Nitride semiconductor substrate structures. Commercially viable Group III - Nitride substrates are desired because such substrates can greatly facilitate the fabrication of visible LEDs and lasers for the emerging solid-state lighting and UV sensor industries. Moreover, Group III - Nitride substrates can also be used in other related applications, such as high-power RF circuits and devices.

[0086] In various embodiments, Group III - Nitride semiconductor substrate structures can be formed by coalescing the plurality of Group III - Nitride

semiconductor nanostructures such as those described in Figures 1 -6 using techniques such as nanoheteroepitaxy. Figures 7A-7D depict four exemplary semiconductor devices including Group III - Nitride semiconductor substrate structures 712, 714, 715, and 717 formed from the plurality of Group III - Nitride semiconductor nanostructures of the device 100 (see Figure 1 C), the device 200 (see Figure 2), the device 400 (see Figure 4C), and the device 500 (see Figure 5), respectively. [0087] For example, the conditions for the growth of Group III - Nitride semiconductor material can be modified to allow coalescence of the formed plurality of Group III - Nitride semiconductor nanostructures (e.g., 145 or 445) after they have grown to a suitable height, resulting in the formation of a Group III - Nitride

semiconductor substrate structure (e.g., the substrates 712, 714, 715, or 717 in Figures 7A, 7B, 7C and 7D). The Group III - Nitride semiconductor substrate structure can be a continuous, epitaxial, and fully coalesced planar film. The

"suitable height" can be determined for each nanostructure (e.g., GaN) and substrate (e.g., SiC or Si) combination and can be a height that allows a significant reduction in defect density in the upper coalesced Group III - Nitride semiconductor film (i.e., the GaN substrate structure). In addition, the "suitable height" can be a height that can maintain a mechanically-robust structure for the resulting semiconductor devices, for example, those shown in Figures 7A-7D. In various embodiments, because threading defects are not present in the plurality of Group III - Nitride semiconductor nanostructures (e.g., 145 or 445), the coalescence of the Group III - Nitride substrate structure (e.g., the substrate 712, 714, 715, or 717) on top of these pluralities of nanostructures can then occur and provide the Group III - Nitride semiconductor substrate structure containing an extremely low defect density, such as, for example, about 100 million defects per square centimeter or much lower.

[0088] According to various embodiments of the nanostructure formation process, the process steps, (e.g., the deposition, patterning and etching of the selective growth mask, the selective growth of nanostructure nuclei, the growth of nanostructures using Repetitive Multiple Step Growth-Etch Sequence, and the formation of the exemplary Group III - Nitride semiconductor substrate structures) can be scalable to large diameter substrate areas. They can also be readily extended to manufacturing requirements including automatic wafer handling and extended to larger size wafers for establishing efficacy of photonic crystals for light extraction from visible, near-Ultra Violet (UV) and UV LEDs.

[0089] Figures 8 through 12 depict exemplary embodiments for Group III - Nitride semiconductor nanostructure active devices including nanostructure LEDs and nanostructure lasers, and their scalable processes for manufacturing. In various embodiments, the disclosed Group III - Nitride nanostructures and nanostructure arrays such as GaN nanostructures and/or nanostructure arrays can provide their active devices with unique properties. This is because each Group III - Nitride nanostructure can have sidewalls of {1100} family and the normal to each of these side planes can be a non-polar direction for Group III - Nitride materials. High-quality Group III - Nitride quantum wells such as InGaN/GaN quantum well, AIGaN/GaN quantum well or other Group Ill-Nitride quantum wells, can therefore be formed on these side facets of each Group III - Nitride nanostructure.

[0090] In various embodiments, the core-shell nanostructure/multi-quantum well (MQW) active structure can be used to provide high efficiency Group III - Nitride nanoscale optoelectronic devices, such as, for example, nanostructure LEDs and/or nanostructure lasers. For example, the resulting core-shell nanostructure/MQW active structure (i.e., having the MQW active shell on sidewalls of each

nanostructure core) can be free from piezoelectric fields, and also free from the associated quantum-confined Stark effect (QCSE) because each nanostructure core has non-polar sidewalls. The elimination of the QCSE can increase the radiative recombination efficiency in the active region to improve the performance of the LEDs and lasers. Additionally, the absence of QCSE can allow wider quantum wells to be used, which can improve the overlap integral and cavity gain of the nanostructure based lasers. A further exemplary efficiency benefit of using the core-shell nanostructure/MQW active structure is that the active region area can be significant increased because of the unique core-shell structure.

[0091] Figure 8 depicts a cross-sectional layered structure of an exemplary

Group III - Nitride semiconductor core-shell nanostructure/MQW active structure device 800 in accordance with the present teachings. It should be readily apparent to one of ordinary skill in the art that the device 800 depicted in Figure 8 represents a generalized schematic illustration and that other materials/layers/shells can be added or existing materials/layers/shells can be removed or modified.

[0092] As shown, the device 800 can include a substrate 810, a buffer layer 820, a selective growth mask 825, a doped nanostructure core 830, and a shell structure 835 including a first doped shell 840, a MQW shell structure 850, a second doped shell 860, and a third doped shell 870.

[0093] The selective growth mask 825 can be formed over the buffer layer 820 over the substrate 810. The doped nanostructure core 830 can be connected to and extend from the buffer layer 820 through the selective growth mask 825, wherein the doped nanostructure core 830 can be isolated by the selective growth mask 825. The shell structure 835 can be formed to "shell" the doped nanostructure core 830 having a core-shell active structure, and the shell structure 835 can also be situated on the selective growth mask 825. In addition, the shell structure 835 can be formed by depositing the third doped shell 870 over the second doped shell 860, which can be formed over the MQW shell structure 850 over a first doped shell 840.

[0094] The substrate 810 can be a substrate similar to the substrates 1 10 and 410 (see Figures 1 -2 and Figures 4-5) including, but not limited to, sapphire, silicon carbide, silicon and Group III- Group V substrates such as GaAs, or GaN.

[0095] The buffer layer 820 can be formed over the substrate 810. The buffer layer 820 can be similar to the buffer layers 220 and/or 520 (see Figure 2 and Figure 5). The buffer layer 820 can be formed of, for example, GaN, AIN, InN, AIGaN, InGaN or AllnGaN or any other Group III - Nitride semiconductor compound, by various crystal growth methods known to one of ordinary skill in the art. In various embodiments, the buffer layer 820 can be doped with a conductivity type similar to the doped nanostructure core 830. In some embodiments, the buffer layer 820 can be removed from the device 800.

[0096] The selective growth mask 825 can be a selective growth mask similar to the selective growth masks 135 and/or 435 (see Figures 1 -2 and Figures 4-5) formed on the buffer layer 820. In various embodiments, the selective growth mask 825 can be formed directly on the substrate 810. The selective growth mask 825 can define the selective growth of the plurality of Group III - Nitride nanostructures and/or nanostructure arrays. The selective growth mask 825 can be formed of any dielectric material known to one of ordinary skill in the art.

[0097] The Group III - Nitride semiconductor doped nanostructure core 830 can use any nanostructure of the plurality of nanostructures shown in Figures1 -2 and Figures 4-7 formed using the Repetitive Multiple Step Growth-Etch Sequence. The doped nanostructure core 830 can be formed of, for example, GaN, AIN, InN, AIGaN, InGaN or AllnGaN, or any other Group III - Nitride semiconductor compound, which can be made an n-type by doping with various impurities such as silicon, germanium, selenium, sulfur and tellurium or other elements. In various embodiments, the doped nanostructure core 830 can be made p-type by introducing beryllium, strontium, barium, zinc, or magnesium or other elements. Other dopants known to one of ordinary skill in the art can be used. In various embodiments, the height of the doped nanostructure core 830 can define the approximate height of the active structure device 800. For example, the doped nanostructure core 830 can have a height of about 10 nanometers (nm) to about 1000 micrometers (μηη) or more.

[0098] The doped nanostructure core 830 can have non-polar sidewall facets of {1100} family (i.e., "m"-plane facets), when the material GaN or other Group III - Nitride compound is used for the doped nanostructure core 830. The shell structure 835 including the MQW shell structure 850 can be grown on these facets and the device 800 can therefore be free from piezoelectric fields, and free from the associated quantum-confined Stark effect (QCSE).

[0099] The first doped shell 840 can be formed from and coated on the non- polar sidewall facets of the doped nanostructure core 830 by increasing the growth effect and/or reducing the etch effect during the Repetitive Multiple Step Growth-Etch Sequence. For example, the first doped shell 840 can be formed by lowering the growth temperature, increasing the duration of the growth steps, and/or decreasing the duration of the etch steps. The conductivity type of the first doped shell 840 and the doped nanostructure core 830 can be made similar, for example, an n-type. In various embodiments, the first doped shell 840 can include a material of Al_xGai_-xN, where x can be any number less than 1 .00 such as 0.05 or 0.10.

[00100] The MQW shell structure 850 can be formed on the first doped shell 840. . In various embodiments, the MQW shell structure 850 can include, for example, alternating layers of Al_xGai_-xN and GaN where x can be, for example, 0.05 or any other number less than 1 .00. The MQW shell structure 850 can also include alternating layers of, for example, ln_xGai_-xN and GaN, where x can be any number less than 1 .00, for example, any number in a range from about 0.20 to about 0.45, or any other Group III - Nitride semiconductor compounds.

[00101] The second doped shell 860 can be formed on the MQW shell structure 850. The second doped shell 860 can be used as a cladding layer for the MQW shell structure 850 with a sufficient thickness of, such as, for example, about 10 nm to about 2000 nm or more. The second doped shell 860 can be formed of, for example, Al_xGai_-xN, where x can be any number less than 1 .00 such as 0.20 or 0.30. The second doped shell 860 can be doped with a conductivity type similar to the third doped shell 870.

[00102] The third doped shell 870 can be formed by continuing the core-shell growth from the second doped shell 860 to cap the active structure device 800. The third doped shell 870 can be formed of, for example, GaN or other Group III - Nitride compound and doped to be an n-type or a p-type. In various embodiments, if the first doped shell 830 is an n-type shell, the second doped shell 860 and/or the third doped shell 870 can be a p-type shell and vice versa. In various embodiments, the third doped shell 870 can have a thickness of about 10 nm to about 500 nm or more.

[00103] During the growth of nanostructures 830 and core-shell structure 835, growth mode transitions from one Repetitive Multiple Step Growth-Etch Sequence to another Repetitive Multiple Step Growth-Etch Sequence, or from one Repetitive Multiple Step Growth-Etch Sequence to a conventional growth mode, are performed in order to more effectively incorporate Group III - Nitride semiconductor

compounds, such as GaN, AIN, InN, InGaN, AllnGaN, or AIGaN, into the structure of the nanostructures 830 and core-shell structure 835, and in order to form devices 800 of the designed shape, size, diameter, length, morphology, stochiometric composition and operational characteristics.

[00104] In various embodiments, the core-shell active structure devices 800 shown in Figure 8 can be electrically isolated from each other, when a number of devices 800 are included in a large area such as a wafer. Figure 9 depicts an active structure device 900 including a dielectric material 910 deposited to isolate each core-shell nanostructure/MQW active structure shown in Figure 8 in accordance with the present teachings.

[00105] As shown in Figure 9, the dielectric material 910 can be deposited on the selective growth mask 825 and laterally connected with the sidewalls of the shell structure 835, more specifically, the sidewalls of the third doped shell 870. In various embodiments, the dielectric material 910 can be any dielectric material for electrical isolation, such as, for example, silicon oxide (SiO₂), silicon nitride (Si₃N₄), silicon oxynitride (SiON), or other insulating materials. In some embodiments, the dielectric material 910 can be a curable dielectric. The dielectric material 910 can be formed by, for example, chemical vapor deposition (CVD) or spin-on techniques, with a desired height or thickness. In various embodiments, the height/thickness of the dielectric material 910 can be further adjusted by removing a portion of the dielectric material from the top of the deposited dielectric material using, for example, a etch back process known to one of ordinary skill in the art. The thickness of the dielectric material 910 can be adjusted depending on specific applications where the core- shell nanostructure/MQW active structure is used. [00106] In various embodiments, various nanostructure LEDs and nanostructure lasers can be formed by the core-shell growth described in Figures 8- 9, because MQW active shell structures can be created on the nonpolar sidewalls of the nanostructures. For example, if the nanostructures are arranged in a hexagonal array with a pitch that is equal to λ/2, where λ is the emission wavelength of the exemplary LED or laser, the array of nanostructures can provide optical feedback to stimulate light-emitting action. Figures 10-12 depict exemplary nanoscale active devices formed based on the structures shown in Figures 8-9 in accordance with the present teachings.

[00107] Figures 10A-10C depict an exemplary Group III - Nitride

semiconductor nanostructure LED device 1000 using the core-shell

nanostructure/MQW active structure described in Figures 8-9 in accordance with the present teachings.

[00108] In various embodiments, the nanostructure LED device 1000 can be fabricated including electrical contacts formed on, for example, the device 900. The electrical contacts can include conductive structures formed from metals such as titanium (Ti), aluminum (Al), platinum (Pt), nickel (Ni) or gold (Au) in a number of multi-layered combinations such as Al/Ti/Pt/Au, Ni/Au, Ti/AI, Ti/Au, Ti/AI/Ti/Au, Ti/AI/Au, Al or Au or other materials using techniques known to one of ordinary skill in the art.

[00109] In Figure 10A, the device 1000 can include a conductive structure 1040 formed on the surface of the device 900, i.e., on each surface of the dielectric material 910 and the third doped shell 870 of the shell structure 835. The conductive structure 1040 can be a transparent layer used for a p-type electrode of the LED device 1000 fabricated subsequently. In an exemplary embodiment, the conductive structure 1040 (or p-electrode) can be, for example, a layered metal combination of Ni/Au.

[00110] In various embodiments, the device 1000 can further include a dielectric layer 1010 having an adjusted thickness (or height). By adjusting the thickness of the dielectric layer 1010, the extent (e.g., thickness or height) of the conductive structure 1040 (or p-electrode) formed on and along the sidewall of the shell structure 835 can be adjusted according to the desired application of nanostructure active device. For example, a thick layer of the dielectric 1010 can confine the conductive structure 1040 (or p-electrode) to the top of the core-shell structured active devices, for example, for nanostructure LEDs and/or nanostructure lasers. Alternatively, an adjusted thin dielectric layer 1010 can allow the conductive structure 1040 (or p-electrode) to have a higher thickness or height (i.e., an increased extent), which can reduce the resistance of the active devices. In various embodiments, the higher thickness of the conductive structure 1040 (or p-electrode) can however be expected to contribute loss to the active devices such as laser cavity. As known to one of ordinary skill in the art, optimum performance of the conductive structure 1040 (or p-electrode) can be achieved by balancing the reduction of resistance of the active devices with the expected loss.

[00111] In various embodiments, the thickness of the conductive structure 1040 (or p-electrode) along the sidewalls of the shell structure 835 of the exemplary LED device 1000 can be in a range of about 0.01 micrometer (μηη) to about 30

micrometers (μηη) or larger for a high efficiency performance. In various

embodiments the LED device 1000 can have a total height of up to 100 micrometers (μηη) or higher.

[00112] In Figure 10B, the device 1000 can further include a p-electrode 1045, a dielectric 1015, and a selective growth mask 1025 having trenches 1035 converted from the selective growth mask 825.

[00113] The p-electrode 1045 and the underlying dielectric 1015 can be formed by patterning and etching the conductive structure 1040 and the dielectric layer 1010 (see Figure 10A). As a result, portions (not shown) of surface of the selective growth mask 835 can be exposed and separated by the dielectric 1015 on both sides of each core-shell structure. After the patterning and etching processes, a selective growth mask 1025 can be formed by forming trenches 1035 through the exposed portions of surface of the selective growth mask 825, wherein each side of the core- shell active structure can include at least one trench 1035. As a result, surface portions of the underlying buffer layer 820 can be used as bottoms of the trenches 1035.

[00114] In various embodiments, the thickness of the selective growth mask 1025 can be critical for the performance of the LED device 1000. For example, a silicon nitride selective growth mask having a thickness of 30 nm can be sufficiently thick to support a voltage of about 20 Volts or higher before breakdown of the LED device 1000. In various embodiments, the selective growth mask 1025 can have a thickness of about 30 nm or less. However, one of ordinary skill in the art will understand that a thicker selective growth mask can be readily accommodated in the nanostructure and nanostructure active device processes.

[00115] In Figure 10C, the device 1000 can include the n-electrodes 1080 formed to assure the conduction between the n-side contact and the central conductive region including the buffer layer 820 and the nanostructure core 830. The central conductive region can be, for example, a heavily doped n⁺ GaN region. In various embodiments, the n-electrodes 1080 can include conductive structures formed by depositing electrode materials onto each surface of the selective growth mask 1025 and the bottoms of the trenches 1035. In an exemplary embodiment, the n-electrodes 1080 can be formed of, for example, a layered metal combination, such as Al/Ti/Pt/Au.

[00116] At 1099, the resulting light of the nanostructure LED device 1000 in Figure 10C can be extracted through the substrate 820, which can be transparent at green and blue wavelengths and different wavelengths. In various embodiments, a more diffuse light output can occur on the top side of the device 1000 (not shown) since the nanostructure LED device 1000 can be small enough for sufficient diffraction. This diffuse light output can be advantageous in solid-state lighting applications.

[00117] In this manner, the disclosed nanostructure LED device 1000 can provide unique properties as compared with traditional LED devices. First, it can have a higher brightness because the core-shell grown active region area (i.e., the MQW active shell area) can be increased, for example, by a factor of approximately 10 times compared to a conventional planar LED structure. Second, the light extraction can be improved to increase the output efficiency of the LED. This is because the LED device's geometry can make the most of the active region area oriented normal to the wafer surface, i.e., the substrate surface. The confinement regions on either side of the MQW active region can tend to guide the LED light in the vertical direction. Third, because of the high precision of the position and diameter of each of the plurality of nanostructures and/or nanostructure arrays, the resulting arrays of the LED devices 1000 can also be configured as a photonic- crystal, which can further improve the light output coupling efficiency. Fourth, the nanostructure LED resistance can be significantly decreased because of the increase of the electrical contact area, for example, the contact area of the p- electrode 1045. Finally, since the LED device 1000 can provide a specified light power with higher brightness, more devices can be processed on a given wafer, which can decrease the cost of production and also increase the manufacture efficiency. For example to allow for metal contacts the LED device 1000 can include a pitch spacing (i.e., a center-to-center spacing between any two adjacent

nanostructure devices) of for example 100 micrometers (μηη), without any limitation to any other value. For example, a 4-inch diameter wafer can then include a number of nanostructure LED devices 1000, for example, about 0.78 million devices or more, which can be manufactured simultaneously. In various embodiments the pitch spacing between LED devices 1000 can be reduced further to allow a single 4-inch diameter wafer to contain, for example, more than one million LED devices 1000.

[00118] Figures 1 1 -12 depict exemplary Group III - Nitride semiconductor nanostructure laser devices using the core-shell grown nanostructure/MQW active structure shown in Figures 8-10 in accordance with the present teachings. Because the sidewall facets of the nanostructures and/or nanostructure arrays are exact {1100} facets with a flatness on the scale of an atomic monolayer, high quality MQW active regions for laser devices can be formed on these superior flat "sidewall substrates". In addition, the vertical orientation of the sidewall facets and the uniform periodicity of the nanostructures can allow a photonic crystal optical cavity to be established straightforwardly.

[00119] As shown in Figure 1 1 , the Group III - Nitride semiconductor nanostructure laser device 1 100 can be fabricated from the processes described in Figures 8-10 using the core-shell grown nanostructure/MQW active structure as laser active structure. The nanostructure laser device 1 100 can include a polished shell structure 1 135, a polished p-electrode 1 145, and a passivation layer 1 195, which can be formed on each surface of the polished shell structure 1 135 and the polished p-electrode 1 145 to cap the laser active structure.

[00120] The polished shell structure 1 135 and the polished p-electrode 1 145 can be formed by polishing (i.e., removing) on the top end (with respect to the substrate 810 as the bottom end) of the core-shell nanostructure/MQW active structure (i.e., laser active structure) such as that shown in Figure 10C. Various polishing processes, for example, a chemical-mechanical polishing, can be used using the etched dielectric 1015 as a mechanical support.

[00121] The polishing step can be used to polish a number of laser facets at the same time without diminishing the manufacturability of the nanostructure laser devices 1 100. For example, a number of nanostructure laser devices 1 100 such as about 0.78 million or more, can be formed on a 4-inch wafer for a high manufacturing efficiency. In various embodiments the pitch spacing can be reduced further to allow a single 4-inch wafer to contain, for example, more than one million laser devices 1 100.

[00122] In various embodiments, the extent (e.g., thickness or height) of the polished p- electrode 1 145 formed along the sidewalls of the polished shell structure 1 135 can be adjusted by adjusting thickness of the underlying etched dielectric 1015 for optimum performance of the laser device 1 100. In various embodiments, the thickness of the polished p-electrode 1 145 along the sidewall of the polished shell structure 1 135 shown in Figure 1 1 can range from about 0.1 micrometer (μηη) to about 5 micrometers (μηη) when the overall height is about 10 micrometers (μηη).

[00123] The passivation layer 1 195 can be formed at the polished top end of each laser active structure, i.e., on each surface of the polished p-electrode 1 145 and the polished shell structure 1 135. The passivation layer 1 195 can be configured to avoid undue non-radiative recombination or junction leakage of the nanostructure laser device 1 100. In various embodiments, the passivation layer 1 195 can be formed of, for example, any dielectric material known to one of ordinary skill in the art with a thickness of about 10 to 100 nanometers (nm) or larger.

[00124] In some embodiments, the composition and refractive index of the materials used for the polished shell structure 1 135 surrounding the nanostructure cavity (i.e., the nanostructure core 830) can affect the optical lasing process at 1 199. For example, when the nanostructures have an exemplary diameter of about 200 nm, some of the optical lasing mode can exist outside the cavity. The laser can therefore be more sensitive to the composition and refractive index of the materials surrounding the cavity, that is, materials used for each layer of the polished shell structure 1 135.

[00125] In other embodiments, because there is no physical lower facet on the laser optical cavity (i.e., the nanostructure core 830), there can be a change of effective refractive index in the vicinity of the selective growth mask 1025. This index change can in fact be helped (i.e., made larger) by the fact that some of the optical lasing mode can exist outside the cavity. In an exemplary embodiment, the nanostructure laser device 1 100 (see Figure 1 1 ) can be optically tuned by adjusting the thickness of the selective growth mask 1025 for a maximum reflectivity. For example, the thickness of the selective growth mask 1025 for the laser device 1 100 can be in a range of about 220 nanometers (nm) to about 230 nanometers (nm) when the device emits blue light at 450 nm.

[00126] Figure 12 depicts another exemplary Group III - Nitride semiconductor laser device 1200, in which a distributed Bragg reflector (DBR) mirror stack 1220 can be disposed between the layers of the substrate 810 and the selective growth mask 1025, as opposed to the buffer layer 820 being disposed between these two layers of the laser device 1 100 shown in Figure 1 1 .

[00127] The DBR mirror stack 1220 can be an epitaxial DBR mirror stack. The DBR mirror stack 1220 can include, for example, quarter-wave alternating layers of, for example, GaN and AIGaN or other Group III - Nitride semiconductor materials. In various embodiments, the DBR mirror stack 1220 can be tuned to improve reflectivity and to increase cavity Q of the laser 1299.

[00128] In various embodiments, all the nanostructure active devices shown in Figures 10-12 can provide a low device resistance because more resistive p- electrodes (e.g., the p-electrode 1045 and/or 1 145) of the heterostructure can be located at the larger-area, which is outer periphery of each core-shell

nanostructure/MQW active structure. For example, for the LED device 1000 (shown in Figure 10), the p-electrode 1045 can be patterned to completely cover the top of the device 1000 to further decrease the device resistance.

[00129] Although a single Group III - Nitride semiconductor nanostructure is depicted in Figures 8-12 for the purpose of description, one of ordinary skill in the art will understand that the core-shell growth processes on each nanostructure of the plurality of nanostructures and/or nanostructure arrays (e.g., shown in Figures 1 -7) for nanoscale active devices can be simultaneously conducted in a large area (e.g., a whole wafer).

[00130] Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

WHAT IS CLAIMED IS:

1 . A method of making Group III - Nitride semiconductor nanostructures comprising:

forming a selective growth mask over a substrate, wherein the selective growth mask comprises a plurality of patterned apertures that exposes a plurality of portions of the substrate;

performing an initial nucleation growth step to grow a semiconductor material nuclei on each of the plurality of portions of the substrate;

performing a first growth-mode transition from the nucleation growth step to a Repetitive Multiple Step Growth-Etch Sequence;

forming a plurality of group III - Nitride semiconductor nanostructures by continuing the Repetitive Multiple Step Growth-Etch Sequence;

performing a second growth-mode transition from the first Repetitive Multiple Step Growth-Etch Sequence to a second Repetitive Multiple Step Growth-Etch Sequence or conventional growth mode; and

continuing the formation of the Group III - Nitride semiconductor core-shell nanostructures by continuing the second Repetitive Multiple Step Growth-Etch Sequence or conventional growth mode of the semiconductor material.

2. The method of claim 1 , wherein the substrate comprises a buffer layer over a supporting substrate surface and the semiconductor material is selectively grown through the plurality of patterned apertures on the buffer layer.

3. The method of claim 1 , wherein each loop of the first Repetitive Multiple Step Growth-Etch Sequence contains at least one growth step to allow the Group III - Nitride semiconductor nanostructures to grow along the vertical direction and at least one etch step to etch back and remove those portions of the aforementioned nanostructures that grew along the lateral direction during the preceding growth step(s), thus resulting in a zero growth rate along the lateral direction and a positive growth rate along the vertical direction for the aforementioned nanostructures. Such a Repetitive Multiple Step Growth-Etch Sequence can be continued until Group III - Nitride semiconductor nanostructures with the desired characteristics are formed.

4. The method of claim 1 , wherein each loop of the second Repetitive Multiple Step Growth-Etch Sequence contains at least one growth step to allow the Group III - Nitride semiconductor nanostructures to grow along the vertical direction and at least one etch step to partially etch back and partially remove those portions of the aforementioned nanostructures that grew along the lateral direction during the preceding growth step(s), thus resulting in a positive growth rate along the lateral direction and a positive growth rate along the vertical direction for the aforementioned nanostructures. Such a Repetitive Multiple Step Growth-Etch Sequence can be continued until Group III - Nitride

semiconductor core-shell nanostructures with the desired characteristics are formed.

5. The method of claim 1 or 2, wherein the substrate comprises one or more materials including, but not limited to, those from the group consisting of silicon (Si), silicon carbide (SiC), sapphire, GaN, InN, AIN, InGaN, AIGaN, InGaAIN, InP and GaAs.

6. The method of claim 1 or 2, further comprising one or more cleaning processes prior to the selective growth of the semiconductor material.

7. The method of claim 1 or 2, wherein the plurality of patterned apertures forms a hexagonal array having a diameter of about 10 nanometers (nm) to about 500

micrometers (μηη) and a pitch of about 20 nm to about 1000 micrometers (μηη).

8. The method of claim 1 or 2, wherein a cross-sectional feature of each of the plurality of Group III - Nitride semiconductor nanostructures and each of the plurality of patterned apertures is substantially similar.

9. The method of claim 8, wherein the cross-sectional feature is a shape selected from the group consisting of a polygon, a rectangle, a square, an oval, and a circle.

10. The method of claim 8, wherein the step of performing a first growth mode transition from the initial nucleation step to the first Repetitive Multiple Step Growth-Etch Sequence occurs before growth of the semiconductor material protrudes over a top of the selective growth mask.

1 1 . The method of claim 1 or 2, wherein the material for the plurality of semiconductor nanostructures comprises one or more Group III - Nitride semiconductor materials including, but not limited to, those from the group consisting of GaN, AIN, InN, InGaN, AllnGaN and AIGaN.

12. The method of claim 1 or 2, wherein the growth of the Group III - Nitride semiconductor nanostructures is conducted by using at least one of the following methods: Metal Organic Chemical Vapor Deposition (MOCVD); Vapor Phase Epitaxy; Hydride Vapor Phase Epitaxy (HVPE); OrganoMetallic pyrolysis in Vapor Phase Epitaxy (OMVPE); Close Space vapor Transport (CSVT); and Molecular Beam Epitaxy (MBE) as well any other method used for the growth of semiconductor materials.

13. The method of claim 1 or 2, wherein the initial nucleation growth comprises Group III and Group V precursor gases having a V/lll ratio ranging from about 50 to about 5000, without any limitation to any other value .

14. The method of claim 1 or 2, wherein the first Repetitive Multiple Step Growth- Etch Sequence comprises a growth rate along the vertical direction of about 0.1

micrometers (μηη) per hour or higher.

15. The method of claim 1 or 2, wherein each of the plurality of Group III - nitride semiconductor nanostructures has a length of about 10 nm to about 10,000 micrometers

(μηη).

16. The method of claim 1 or 2, wherein:

the step of the first growth mode transition from the initial nucleation step to the first Repetitive Multiple Step Growth-Etch Sequence occurs after growth of the semiconductor material protrudes over a top of the selective growth mask to form a plurality of truncated pyramid-shaped nanostructures partially disposed on a surface of the selective growth mask; and

the step of forming the plurality of Group III - Nitride semiconductor nanostructures comprises forming a semiconductor nanostructure on each of the plurality of aforementioned pyramid-shaped nanostructures by continuing the growth of the semiconductor material by the first Repetitive Multiple Step Growth-Etch Sequence such that a cross-sectional feature of the semiconductor nanostructure and a top facet of each of the plurality of pyramid-shaped nanostructures is substantially similar.

17. The method of claim 16, wherein the Group III - Nitride semiconductor nanostructure comprises a cross-sectional dimension smaller than that of each of the plurality of patterned apertures.

18. The method of claim 1 , further comprising:

performing additional growth mode transitions between different Repetitive Multiple Step Growth-Etch Sequences or between a Repetitive Multiple Step Growth- Etch Sequence and conventional growth mode; and

continuing the formation of the plurality of Group III - Nitride semiconductor nanostructures by continuing the Repetitive Multiple Step Growth-Etch Sequence or conventional growth mode, as applicable, of the semiconductor material after each growth mode transition; until Group III - Nitride semiconductor nanostructures of the designed shape, size, morphology and stochiometry and other characteristics are formed.

19. A Group Ill-Nitride semiconductor nanostructure array formed by the method of claim 1 or 2, comprising:

a support comprising a plurality of selected surface regions;

a Group III - Nitride semiconductor nanostructure connected to and

extending from each of the plurality of selected surface regions of the support, wherein the Group III - Nitride semiconductor nanostructure is oriented along a single direction and maintains a cross-sectional feature of one of the

plurality of selected surface regions.

20. The nanostructure array of claim 19, further comprising a GaN nanostructure oriented along the (0001 ) crystallographic direction.

21 . The nanostructure array of claim 19, wherein the Group III - Nitride

semiconductor nanostructure comprises one or more materials selected from the group consisting of GaN, AIN, InN, InGaN, AIGaN, AllnGaN.

22. The nanostructure array of claim 19, wherein the Group III - Nitride

semiconductor nanostructure comprises one or more cross-sectional shapes selected from the group consisting of a stripe, a polygon, a rectangle, a square, an oval, and a circle.

23. The nanostructure array of claim 19, wherein the Group III - Nitride

semiconductor nanostructure further comprises an aspect ratio of about 2 or higher and a cross sectional dimension of about 10 nm (nanometers) or larger.

24. The nanostructure array of claim 19, wherein the support comprises a Group III - Nitride semiconductor nanostructure nucleus disposed on each of a plurality of portions of a substrate through a selective growth mask disposed on the substrate, wherein a surface of the Group III - Nitride semiconductor nanostructure nucleus comprises one of the plurality of selected surface regions of the support.

25. The nanostructure array of claim 24, wherein the support further comprises a pyramid-shaped Group III - Nitride semiconductor nanostructure formed from the Group III - Nitride nanostructure nucleus and partially disposed on the selective growth mask, wherein a top facet of the pyramid-shaped Group III - Nitride nanostructure comprises one of the plurality of selected surface regions of the support.

26. A Group III - Nitride semiconductor substrate structure comprising:

a Group III - Nitride semiconductor nanostructure array formed by the method of claim 1 or 2 comprising a plurality of Group III - Nitride semiconductor

nanostructures, wherein each of the plurality of semiconductor nanostructures is defect-free or largely defect-free; and

a Group III - Nitride semiconductor film coalesced from the plurality of Group III - Nitride semiconductor nanostructures, wherein the semiconductor film has a defect density of about 100 million defects per square centimeter, or lower.

27. The substrate of claim 26, wherein the Group III - Nitride semiconductor film comprises one or more materials selected from the group consisting of GaN, AIN, InN, InGaN, AIGaN, AllnGaN.

28. A substrate comprising a plurality of Group III - Nitride semiconductor nanostructures formed by the method of claim 1 or 2.