WO2012047591A1

WO2012047591A1 - Electronic device including a semiconductor layer and a metal-containing layer, and a process of forming the same

Info

Publication number: WO2012047591A1
Application number: PCT/US2011/053288
Authority: WO
Inventors: Leo Mathew; Rajesh A. Rao
Original assignee: Astrowatt Inc
Current assignee: Astrowatt Inc
Priority date: 2010-09-27
Filing date: 2011-09-26
Publication date: 2012-04-12
Anticipated expiration: 2013-03-27
Also published as: TW201314739A

Abstract

An electronic device can include a heterojunction portion closer to a first surface of the electronic device, wherein the first surface is a light-receiving surface, a homojunction portion closer to a second surface of the electronic device opposite the first surface. In an embodiment, the electronic device can further include point electrical connections to regions of the homojunction portion, wherein the point electrical connections are spaced apart from each other. A method of forming an electronic device can include providing a combination of a first semiconductor layer and a metal-containing layer, wherein the combination is curved. In an embodiment, mounting the combination to a workpiece holder, wherein, while the combination is mounted, the combination is less curved as compared to before mounting. In a particular embodiment, a heterojunction portion can be formed over the combination after mounting the combination to the workpiece holder.

Description

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR LAYER AND A METAL- CONTAINING LAYER, AND A PROCESS OF FORMING THE SAME

FIELD OF THE DISCLOSURE

The present invention relates generally to semiconductors, and in particular to methods for making semiconductor devices on a layer that has been separated from a substrate.

RELATED ART

Photovoltaic cells can include heterojunctions on both sides of a wafer or a heterojunction along one side and a homojunction along the opposite side of the wafer. A variety of contacting systems may be used with photovoltaic cells for a standalone wafer. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example and are not limited in the accompanying figures.

FIG. 1 includes an illustration of a cross-sectional view of a portion of a workpiece after forming a pad layer and a hard mask layer over a substrate. FIG. 2 includes an illustration of a cross-sectional view of the workpiece of FIG. 1 after patterning the pad layer and the hard mask layer.

FIG. 3 includes an illustration of a cross-sectional view of the workpiece of FIG. 2 after forming a metal-containing layer.

FIG. 4 includes an illustration of a cross-sectional view of the workpiece of FIG. 3 after creating a weakened region within the substrate.

FIG. 5 includes an illustration of a cross-sectional view of the workpiece of FIG. 4 after separation of a portion of the substrate from a remaining portion of the substrate.

FIG. 6 includes an illustration of a cross-sectional view of the workpiece of FIG. 5 illustrating the workpiece inverted as compared to FIG. 5. FIG. 7 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 after mounting the portion of the substrate onto a workpiece holder. FIG. 8 includes an illustration of a cross-sectional view of the workpiece of FIG. 7 after forming a he teroj unction portion of the electronic device in accordance with an embodiment.

FIG. 9 includes an illustration of a cross-sectional view of a substantially completed photovoltaic cell in accordance with an embodiment. Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.

DETAILED DESCRIPTION

The following description in combination with the figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other teachings can certainly be utilized in this application. Before addressing details of embodiments described below, some terms are defined or clarified. The term "metal" and any of its variants are intended to refer to a material that includes an element that is (1) within any of Groups 1 to 12, or (2) within Groups 13 to 15, an element that is along and below a line defined by atomic numbers 13 (Al), 50 (Sn), and 83 (Bi), or any combination thereof. Metal does not include silicon or germanium. Note, however, that a metal silicide is a metallic material.

The term "semiconductor composition" is intended to mean that a material, layer, or region having a particular composition of semiconductor element(s) or compound, excluding dopants. For example, an n-type doped silicon layer may consist of phosphorus and silicon, but the semiconductor composition is solely silicon. Other semiconductor compositions can include silicon germanium, gallium arsenide or the like.

As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited only to those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to an inclusive-or and not to an exclusive-or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).

Also, the use of "a" or "an" is employed to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be read to include one or at least one and the singular also includes the plural, or vice versa, unless it is clear that it is meant otherwise. For example, when a single item is described herein, more than one item may be used in place of a single item.

Similarly, where more than one item is described herein, a single item may be substituted for that more than one item. Group numbers corresponding to columns within the Periodic Table of the elements use the "New Notation" convention as seen in the CRC Handbook of Chemistry and Physics, 81^st Edition (2000-2001).

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronic arts.

An electronic device can include a photovoltaic device that includes heterojunction. In a particular embodiment, the electronic device includes point electrical connections to regions of a homojunction portion of the electronic device, wherein the point electrical connections are spaced apart from each other. The electronic device of the particular embodiment can include a heterojunction portion adjacent to the homojunction portion, wherein the heterojunction portion has a light-receiving surface. The point electrical connections can help to reduce the contact area between the metal used for the electrical connections and the semiconductor surface that is being contacted. Reducing the contact area can reduce potential recombination sites for light generated carriers and can improve the power conversion efficiency of the photovoltaic device.

In another particular embodiment, the electronic device can include a semiconductor layer, and a metal-containing layer electrically connected to the semiconductor layer. The combination of the semiconductor layer and the metal-containing layer is curved. Such an electronic device can be flexible and allow the electronic device to be used with a variety of geometric shapes. For example, when the electronic device includes a photovoltaic device, the photovoltaic device may be mounted to a cylinder, and such a cylinder may be partly surrounded by a hemispherical reflector to allow light to be captured at different angles and may allow incident light to be directed at the photovoltaic device at a wider variety of angles. Further, the electronic device may be attached to irregular shapes, rather than being limited to flat surfaces. Still further, the electronic device may be able to withstand more bending and flexing than many conventional photovoltaic cells before the electronic device would become nonfunctional.

Although the description below provides many details, including particular numerical values and configurations, after reading this specification, skilled artisans will appreciate that the embodiments described herein merely illustrate and do not limit the scope of the present invention. FIG. 1 illustrates a workpiece 100 comprising a substrate 102. The substrate may be a semiconductor substrate comprising a Group 14 element (silicon, germanium, or carbon), any combination of Group 14 elements (silicon germanium, carbon-doped silicon, or the like), or Group 13 -Group 15 semiconductors (gallium arsenide, gallium nitride, indium phosphide, gallium indium arsenide, or the like). In an embodiment, the substrate 102 is substantially

monocrystalline and can have a thickness of at least approximately 50 microns or at least approximately 200 microns. Although there is no theoretical upper limit on the thickness, the substrate 102 may be no greater than approximately 5 meters or no greater than approximately 0.1 meter. As will be described in an alternative embodiment, ingot processing can be used to form substantially rectangular sheets. The substrate 102 may have a dopant concentration of at least approximately lxlO¹⁴ atoms/cm³ and no greater than approximately lxlO¹⁸ atoms/cm³ of an n-type or a p-type dopant. A doped region 104 can be formed from or over the substrate 102. In an embodiment, the doped region may be formed by implanting or diffusing a dopant into the substrate 102. The peak dopant concentration is at least approximately lxlO¹⁹ atoms/cm³. In another embodiment, the doped regions 104 can be formed by epitaxially growing a semiconductor layer from the substrate 102. In another embodiment, the semiconductor layer may be doped as grown or may be subsequently doped as previously described with respect to doping the substrate 102. Such semiconductor layer will have a peak dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In an embodiment, the substrate 102 and the doped region 104 can be part of a homojunction portion of the electronic device being formed. In a particular embodiment, the substrate 102 and the doped region 104 have substantially the same semiconductor composition and are both substantially monocrystalline. The doped region 104 may have a depth (if implanted or diffused) or thickness (if grown) no greater than approximately 900 nm, no greater than approximately 500 nm, or no greater than 300 nm.

If needed or desired the topology of the substrate 102 or doped region 104 may be modified to aid in reducing reflection or in junction formation. The varying topology can be formed by a process including anodization, lithographic or litholess patterning, imprinting, another suitable technique or any combination thereof. Wet etching may be performed using a basic solution (KOH, NaOH, N(CH₃)₄OH, or the like), a colloidal metal-aided etching solution, another suitable wet etchant, or the like. Alternatively, dry etching may be performed, such as reactive ion etching, sputter etching, or any combination thereof. In a further alternative embodiment, a mechanical removal technique may be used. Such topology modification can substantially improve the reflection and current collection capabilities of the electronic device as a photovoltaic cell.

A patterned insulating layer is formed over the doped layer 104, as illustrated in FIG. 2. In the embodiment as illustrated, the patterned layer includes a pad layer 106 and a hardmask layer 108. The pad layer 106 and the hardmask layer 108 can include an oxide, a nitride or an oxynitride. In a particular embodiment, the pad layer 106 includes an oxide that is thermally grown from or deposited over the doped layer 104, and the hardmask layer 108 includes nitride that is deposited over the pad layer 106. The pad layer has a thickness in a range of

approximately 3 nm to approximately 500 nm, and the hardmask layer 108 has a thickness in a range of approximately 5 nm to approximately 150 nm.

A resist layer (not illustrated) is formed over the hardmask layer 108 and patterned to including openings where portions of the pad layer 106 and hardmask layer 108 are to be removed. Portions of the pad layer 106 and hardmask layer 108 are etched to expose portions of the doped region 104. The resist layer is then removed. Thus, the patterned insulating layer includes the pad layer 106 and hardmask layer 108 and defines openings extending to the doped region 104.

In an alternative embodiment, the patterned insulating layer may be formed using a stencil mask (not illustrated). In a particular embodiment, a stencil mask can be placed over the doped region 104, and material for the patterned insulating layer may be deposited onto the doped region 104, wherein the pattern corresponds to openings extending through the stencil mask.

A metal-containing layer 302 is formed over the patterned layer and the doped regions 104, as illustrated in FIG. 3. The metal-containing layer 302 can include an adhesion film, a barrier film, a seed film, another suitable film, or any combination thereof. The adhesion film can include a refractory metal (titanium, tantalum, tungsten, or the like), and the barrier film can include a metal nitride (TiN, TaN, WN of the like) or a metal semiconductor nitride (TaSiN, WSiN, or the like). The seed film can include a transition metal or transition metal alloy, and in a particular embodiment, the seed film can include titanium, nickel, palladium, tungsten, copper, silver, or gold. In other embodiments, other materials may be used within the adhesion film, barrier film, seed film, or any combination thereof. The metal-containing film can be formed by physical vapor deposition (PVD, such as evaporation or sputtering), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemistry, another suitable method, or any combination thereof. In another embodiment, the metal-containing film may be bonded to the doped region 104 by forming a metal film over the workpiece 100 and reacting the metal- containing film to form a metal silicide from exposed portions of the doped region 104. In an embodiment, the metal-containing film can have a thickness of at least approximately 1 nm or at least approximately 10 nm, and in another embodiment, the metal-containing film 206 can have a thickness no greater than approximately 10 microns or no greater than approximately 0.1 microns.

A conductive film is plated (electroplating, electroless plating, or any combination thereof) over the patterned insulating layer. The conductive film can have a relatively higher conductance as compared to the other metal-containing film in the metal-containing layer 302. In a particular embodiment, the conductive film is at least approximately 11 times, approximately 50 times, or approximately 500 times thicker than the other metal-containing film.

The conductive film may include any of the metals or metal alloys previously described with respect to the other metal-containing film. In a particular embodiment, the conductive film comprises tin, nickel, chromium, copper, silver, gold, or a combination thereof. Similar to the other metal-containing film, the conductive film can include a single film or a plurality of films. In a particular embodiment, the conductive film can consist essentially of gold or nickel, and in another embodiment, the conductive film can be mostly copper with a relatively thin indium-tin alloy to help improve soldering during a subsequent bonding operation. Other combinations of materials can be used such that the composition of the conductive film is tailored to a particular application. In an embodiment, the conductive film, and accordingly, the metal-containing layer 302, can have a thickness of at least approximately 1 microns or at least approximately 30 microns, and in another embodiment, the substantially thicker metal-containing film, and accordingly, the metal-containing layer 302 can have a thickness no greater than approximately 2 mm or no greater than approximately 100 mm.

In one embodiment, the conductive film can create stresses within the substrate 102 at a location 402, as illustrated in FIG. 4. As will be described later, these stresses can help separate a portion of the substrate, in the form of a semiconductor layer, from a remaining portion of the substrate 102. In a particular embodiment, the stresses are created within the substrate by an annealing process involving a change in temperature of the substrate 102. The annealing process can be controlled based on the uniformity and defect levels desired in the workpiece 100. The annealing temperature may be determined at least in part on the composition of the substrate 102 and layers of the workpiece 100. In an embodiment, the anneal is performed at a temperature of at least approximately 25 °C or at least approximately 100 °C, and in another embodiment, the anneal is performed at a temperature no greater than approximately 700 °C or no greater than approximately 500 °C. In an embodiment, the anneal is performed for a time of at least approximately 1 second or at least approximately 1 hour, and in another embodiment, the anneal is performed for a time no greater than approximately 20 hours or no greater than approximately 6 hours.

In another embodiment, the conductive film can be formed such that a separation- enhancing species is incorporated within the conductive film when it is formed. The separation- enhancing species can help separate a portion of the substrate, in the form of a semiconductor layer, from a remaining portion of the substrate 102. In a particular embodiment, the separation- enhancing species is hydrogen. Hydrogen may be incorporated within the conductive film from the plating bath, such as an acidic solution.

FIG. 4 illustrates the workpiece after the stresses are created in the substrate and the separation-enhancing species is diffused, transported, or otherwise moved from the metal- containing layer 302 into the substrate 102 of the workpiece 100. In an embodiment, the movement of the separation-enhancing species may aid in separating a combination of the metal- containing layer 302, the doped region 104, and a semiconductor layer, which is a portion of the substrate 102, from a remaining portion of the substrate 102. In one embodiment, the movement of the separation-enhancing species can be accomplished by the annealing process used to create stresses in the substrate as described previously.

The temperature and time of the anneal may depend on the particular application for the semiconductor device being formed. The thickness of the semiconductor layer may be based at least on part on the composition of substrate 102 and the particular electronic application, such as a photovoltaic cell, a light emitting device, a radiation detector, or the like. In an embodiment, the semiconductor layer can have a thickness of at least approximately 1 micron or at least approximately 20 microns, and in another embodiment, the semiconductor layer can have a thickness no greater than approximately 100 microns or no greater than approximately 50 microns. As the semiconductor layer thickness increases, the anneal temperature, the anneal time, or a combination of the anneal temperature and time may increase, and conversely, as the semiconductor layer thickness decreases, the anneal temperature, the anneal time, or a combination of the anneal temperature and time may decrease.

Note that even though the metal-containing film may include a barrier film, such barrier film helps to reduce the likelihood that a metallic material from the conductive film from entering the substrate 102. However, the separation-enhancing species may diffuse or otherwise migrate through the barrier film. Thus, a barrier film is effectively a barrier to the metallic material within the conductive film and not a barrier to the separation-enhancing species.

In another embodiment, the plating may be performed using a plating bath maintained at a temperature higher than room temperature (for example, approximately 20 °C), for example in a range of approximately 40 °C to approximately 95 °C). After plating the conductive film, the workpiece 100 can be cooled to a temperature closer to room temperature.

In any of the previously described embodiments during or following plating the conductive film, the conductive film is exposed to a temperature change that can include cooling, heating, or a combination of heating followed by cooling. As illustrated in FIG. 4, such a temperature change can create a weakened region at a location 402 within the substrate due to a combination of the stresses within the substrate and movement of the separation-enhancing species. In an embodiment, the location 402 can be at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns from a surface of the substrate 102 closest to the patterned insulating layer, and in another embodiment, the location 402 may be no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns from a surface of the substrate 102 closest to the patterned insulating layer.

Accordingly, such a temperature change can help to separate the combination of the metal-containing layer 302, the doped region 104, and a semiconductor layer 502, which is a portion of the substrate 102, from a remaining portion of the substrate 102, as illustrated in FIG. 5. Thus, the location 402 in FIG. 4 represents a weak point from which separation may occur, and the semiconductor layer 502 can have a thickness at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns, and in another embodiment, the semiconductor layer can have a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns. The separation may occur during the cooling, heating, or a combination of heating followed by cooling or thereafter. In an embodiment, the separation may occur by spalling without using a mechanical operation. In another embodiment, a mechanical operation may be used to help with the separation. In a particular embodiment, the separation may occur by cleaving or fracturing the substrate 102 at or near the location 402. A wedge, wire, or saw may be used to aid in the mechanical separation. In another embodiment, a metallic paste can be mechanically applied over the workpiece, and a stiffened or handling substrate can be attached to the metallic paste and used to aid the separation operation. In a particular embodiment, the separation can be analogous to an exfoliation operation. The separated portion of the device may remain attached to the handling substrate or may be removed. Because the metal-containing layer provides sufficient mechanical support, the partially formed device may be free standing. As illustrated in FIG. 5, the semiconductor layer 502 remains bonded to the portion of the workpiece which includes the metal-containing layer 302. The combination of the semiconductor layer 502, the metal-containing layer 302, and the doped region 104 (not separately illustrated in FIG. 5) are now thick enough to be handled mechanically for further processing.

FIG. 5 includes an expanded view of the workpiece as compared to the other figures, and such an expanded view illustrates that the combination of the semiconductor layer 502, the metal- containing layer 302, the doped region 104, and the patterned insulating layer is curved or can be flexed or bent to obtain a curved profile. Due to the scale, the doped region 104 and patterned insulating layer are not illustrated. In the embodiment illustrated, the combination has a concave surface and a convex surface opposite the concave surface. The metal-containing layer 302 is disposed at the concave surface, and the semiconductor layer 502 is disposed at the convex surface.

The curvature may be characterized by a vertical displacement per unit of lateral dimension associated with the curve. As illustrated in FIG. 5, dimension 522 corresponds to the vertical displacement, and dimension 524 corresponds to the lateral dimension. In an embodiment, a ratio of the lateral dimension to the vertical displacement is at least approximately 1: 1, at least approximately 2: 1, or at least approximately 4: 1, and in another embodiment, the ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1. In another embodiment, the ratio may be higher or lower than the values described without departing from the concepts as described herein.

The combination of the semiconductor layer 502, the metal-containing layer 302, the doped region 104, and the patterned insulating layer can be mounted to a workpiece holder 602, as illustrated in FIG. 6. The workpiece holder 602 may help to keep the combination of the semiconductor layer 502, the metal-containing layer 302, the doped region 104, and the patterned insulating layer relatively flat or less curved during subsequent processing. The workpiece holder 602 may have a coating including a fluoropolymer, a silicon nitride, a silicon carbide, anodized aluminum, or the like. In one embodiment, workpiece holder 602 may include a magnet. The metal-containing layer 302 may be attracted to the magnet. In another embodiment, an adhesive compound, double-sided adhesive tape, or the like may be used to adhere the combination of the semiconductor layer 502, the metal-containing layer 302, the doped region 104, and the patterned insulating layer to the workpiece holder 602. In a further embodiment, clips, an annular ring, or the like may be used to secure the combination of the semiconductor layer 502, the metal- containing layer 302, the doped region 104, and the patterned insulating layer to the workpiece holder 602.

FIG. 7 illustrates a portion of the combination of the semiconductor layer 502, the metal- containing layer 302, the doped region 104, and the patterned insulating layer. In FIG. 7, a homojunction portion of the electronic device being formed includes the semiconductor layer 502 and the doped region 104 because the semiconductor layer 502 and doped region 104 includes substantially the same semiconductor composition and crystal structure. The dopants in semiconductor layer 502 and the doped region 104 may be the same or different and still form a homojunction portion. Because the doped region has a higher dopant concentration that the semiconductor layer 502, the homojunction portion 702 has a high-low configuration. A heterojunction portion 802 is formed over the homojunction portion 702, as illustrated in FIG. 8. The heterojunction portion 802 has a higher energy bandgap than the homojunction portion 702. In an embodiment, the heterojunction portions 802 and the homojunction portion 702 may have a semiconductor composition that includes only one or more Group 14 elements. Monocrystalline Ge has an energy bandgap of approximately 0.7 eV, monocrystalline Si has an energy bandgap of approximately 1.1 eV, and amorphous silicon has an energy bandgap in a range of approximately 1.7 eV to approximately 2.1 eV. In a particular embodiment, the homojunction and heterojunction portions 702 and 802 may have semiconductor compositions that include solely silicon. In this particular embodiment, the homojunction portion 702 can include substantially monocrystalline silicon, and the heterojunction portion 802 can include polycrystalline or amorphous silicon.

Referring to FIG. 8, a semiconductor layer 804 having a higher energy bandgap than the semiconductor layer 502 is formed over the semiconductor layer 502. A heterojunction is formed at the interface of the semiconductor layers 502 and 804. The semiconductor layer 804 can be deposited as an intrinsic (undoped) semiconductor layer. This semiconductor layer 804 can passivate the surface of the semiconductor layer 502 by saturating the dangling Si bonds at the surface. . The semiconductor layer 804 may include a single film or a plurality of films having successively higher energy bandgaps. The semiconductor layer has a thickness in a range of approximately 2 nm to approximately 10 nm.

A doped region 806 is formed from a portion of the semiconductor layer 804 or deposited as a separate doped semiconductor layer. The doped region 806 has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In a particular embodiment, the doped region 806 comprises heavily doped p-type amorphous silicon. The doped region 806 has a thickness in a range of approximately 3 nm to approximately 30 nm. In one embodiment the semiconductor layer 804 is not implemented in the heterojunction portion 802 and the doped region 806 is formed directly over the semiconductor layer 502.

An electrode can be formed over the doped region 806, as illustrated in FIG. 9. The electrode can include a principal conductor 904, and if needed or desired, a conductive layer 902. The conductive layer 902 is disposed along the light-receiving side of the electronic device and can be substantially transparent to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. The conductive layer 902 can include indium-tin-oxide, aluminum-tin- oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof. The thickness of the conductive layer 902 may be selected to ensure a substantial amount of light can be transmitted through the conductive layer 902.

The principal conductor 904 can include a metal-containing material, such as aluminum, copper, nickel, gold, silver, another suitable metal or metal alloy, or any combination thereof. Unlike the electrode 902, the principal conductor can be substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm and does not need to be substantially transparent to such radiation. Thus, the principal conductor 904 may be substantially thicker than the electrode 902. The thickness of the principal conductor 904 may be at least approximately 100 nm. The principal conductor 904 can be a patterned layer that defines openings through which radiation may pass to the underlying semiconductor layers. The principal conductor 904 can have a pattern in the form of strips, a grid, serpentine lines, or another suitable pattern. At this point in the process, a substantially-completed photovoltaic cell is formed.

The photovoltaic cell may be implemented into an electronic device, such as a photovoltaic apparatus. The electrode can be electrically connected to a cathode terminal, and the metal-containing layer 302 can be electrically connected to an anode terminal. When the electronic device is exposed to sunlight, the electronic device can generate electricity. After reading this specification, skilled artisans will appreciate that other embodiments may be used without deviating from the teachings as described herein. In another embodiment (not illustrated), the doped region 104 may not be formed. After forming the patterned insulating layer, spaced-apart doped regions may be formed in the substrate using implantation or dopant diffusion to allow ohmic contacts to be subsequently formed between the portion of the substrate 102, which will later become the semiconductor layer 502, and the metal-containing layer 302. Thus, point electronic connections can include the space-apart doped regions.

In another embodiment, the homojunction portion 702 and the heterojunction portion 802 may include different semiconductor compositions, of which at least one of which does not include a Group 14 element. For example, the homojunction portion 702 may include silicon, and the heterojunction portion 802 may include a III-V semiconductor (for example, GaAs, GaN, InP, or the like), a II-V semiconductor (for example, CdSe, ZnTe, or the like).

The process are previously described may be performed using a substrate in wafer form and produce substantially circular disk-shaped devices. In another embodiment, the substrate may be in an ingot form. In a particular embodiment the ingot can be substantially cylindrical and have a diameter of approximately 50 mm to approximately 300 mm or even larger. The length of the ingot can be greater than the diameter and can range from approximately 150 mm to approximately 5 meters. The process as described with respect to the FIGs. 1 to 5 is performed. Before plating the conductive film of the metal-containing layer 302, a portion of the metal- containing film of the metal-containing layer 302 may be removed or covered with a relatively narrow strip (that is, the width of the strip is substantially less than the circumference of the ingot) of an insulator to substantially prevent the conductive film from plating completely around the ingot. The lack of plating around a complete circumference of the ingot may create a relative weak spot from which the semiconductor layer 502 may be removed from a remainder of the ingot. In another embodiment, the metal-containing layer 302 may be scored or cut along part of all of a length of the ingot to aid in the separation. The ingot may be beneficial to produce a photovoltaic device that can be shaped to be substantially rectangular in shape.

Embodiments in accordance with the concepts as described herein can be particularly beneficial. Backside (opposite the light-receiving surface) electrical connection can be in the form of point electrical connections. In particular, the point electrical connections help in reducing the contact area between the metal used for the electrical connections and the semiconductor surface that is being contacted. Reducing the contact area can reduce potential recombination sites for light generated carriers and improve the power conversion efficiency of the photovoltaic device. Furthermore, the point electrical connections allow for the metal to be separated from the semiconductor surface by a dielectric film, which provides additional benefits of surface passivation of the semiconductor layer and internal light reflection within the device.

The electronic devices fabricated as described can be useful to allow much more flexibility in incorporating such devices into a larger apparatus, such as a photovoltaic apparatus. Significantly, most fabrication equipment is designed for flat and not curved surfaces. As such, fabrication costs can be lower than a comparable electronic device formed from a curved surface. Yet, even though the electronic device may be relatively flat when being formed, such an electronic device formed in accordance with embodiments as described herein can produce a freestanding electronic device that can be flexed, bent or shaped into a variety of positions. Thus, the electronic device can be attached or mounted to a non-planar or irregular surface. The example, the electronic device can be mounted into a photovoltaic apparatus having a curved surface. For example, the electronic device may be mounted onto a cylinder that is partly surrounded by hemispherical reflectors. In another embodiment, the electronic device can also be shaped to cover a surface having an abrupt surface feature, such as a corner, a ridge, or the like. Such an abrupt surface feature may be represented as a discontinuous mathematical function. The ability to shape the electronic device greatly improves the ability to implement the electronic device in apparatuses having a wide variety of different surface shapes.

Further, an electronic device can be fabricated from a curved surface and be mounted in a photovoltaic apparatus along a flat surface. For example, an electronic device may be fabricated from a cylindrical ingot. When the electronic device separates from the cylindrical ingot, the electronic device may be flattened and result in a rectangular shaped electronic device. The rectangular shape may be useful when implemented in a photovoltaic apparatus having a rectangular shaped light-receiving surface.

Many of the embodiments as described may be implemented using existing fabrication equipment and materials. Therefore, exotic new materials and new designs of fabrication equipment do not need to be developed.

While benefits have been described with respect to particular embodiment, such benefits are not required of all embodiments. For example, the point electrical connections do not only need to be implemented in an electronic device that is curved. Also, a curved or flexible electronic device does not require backside electrical connections with point contacts.

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that those aspects and embodiments are only illustrative and do not limit the scope of the present invention.

In a first aspect, an electronic device can include a heterojunction portion closer to a first surface of the electronic device, wherein the first surface is a light-receiving surface, and a homojunction portion closer to a second surface of the electronic device opposite the first surface. The electronic device can further include point electrical connections to regions of the homojunction portion, wherein the point electrical connections are spaced apart from each other.

In an embodiment of the first aspect, the point electrical connections include point contacts. In another embodiment, the point electrical connections include spaced-apart doped regions within the homojunction portion. In still another embodiment, each of the point electrical connections includes point contacts and a corresponding doped region within the homojunction portion. In yet another embodiment, the homojunction portion includes a doped region having a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In a further embodiment, the homojunction portion has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns, and in still a further embodiment, the homojunction portion has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

In another embodiment of the first aspect, the point electrical connections are part of a metal-containing layer electrically connected to the homojunction region, wherein the metal- containing layer is a substantially continuous layer that extends between and overlies the point electrical connections. In a particular embodiment, the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns. In another particular embodiment, the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns. In still another particular embodiment, the metal containing layer includes a principal film including 100 %, at least 99%, at least 95%, or at least 90% of a total thickness of the metal-containing layer. In a more particular embodiment, the metal-containing layer further includes an adhesion film, a barrier film, a seed film, or any combination thereof. In yet another particular embodiment, the electronic device further includes a patterned insulating layer defining openings, wherein the point electrical connections extend into the openings.

In still another embodiment of the first aspect, the electronic device further includes an electrode electrically connected to the heterojunction portion. In a particular embodiment, the electrode includes a principal conductor that is electrically connected to the electrode, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of

approximately 250 nm to approximately 700 nm. In a more particular embodiment, the principal conductor is in the form of a grid. In another more particular embodiment, the electrode further includes a conductive layer that is substantially transparent to the radiation, and the conductive layer is disposed between the principal conductor and the heterojunction portion. In an even further more particular embodiment, the conductive layer includes indium-tin-oxide, aluminum- tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof.

In yet another embodiment of the first aspect, the heterojunction portion and the homojunction portion have a same semiconductor composition. In a particular embodiment, the heterojunction portion is amorphous, polycrystalline, or a combination of thereof, and the homojunction portion is substantially monocrystalline. In a further embodiment, a semiconductor composition of the heterojunction portion and a semiconductor composition of the homojunction portion include only one or more Group 14 elements. In still a further embodiment, a semiconductor composition of the heterojunction portion and a semiconductor composition of the homojunction portion include solely silicon. In yet a further embodiment, the heterojunction portion includes silicon, the homojunction portion includes germanium, and the heterojunction portion has a higher energy bandgap as compared to the semiconductor material of the homojunction portion. In another embodiment, the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm. In still another embodiment, the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm.

In a further embodiment of the first aspect, the heterojunction portion includes an undoped semiconductor layer. In a particular embodiment, the heterojunction portion further includes a doped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the homojunction portion. In a more particular embodiment, the homojunction portion includes a first doped region having a doping concentration no greater than approximately lxlO¹⁸ atoms/cm³, wherein a heterojunction is formed at the junction of the undoped semiconductor layer and the first doped region; and a second doped region spaced apart from the heterojunction portion and having a doping concentration of at least approximately lxlO¹⁹ atoms/cm³, wherein the second doped region is part of the point electrical connections or is in contact with at least one of the point electrical connections. In another more particular embodiment, the homojunction portion includes an n-type substantially monocrystalline semiconductor layer, the doped semiconductor layer includes a p-type semiconductor layer, a heterojunction is formed at a junction of the n-type substantially monocrystalline semiconductor layer and the undoped semiconductor layer, and the undoped semiconductor layer is an only layer disposed between the n-type substantially monocrystalline semiconductor layer and the p-type semiconductor layer.

In still a further embodiment, the homojunction portion has a surface with a varying topology. In a particular embodiment, the point electrical connections are disposed along the surface with the varying topology. In another embodiment, the electronic device includes a photovoltaic device that is curved. In a particular embodiment, the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1 : 1, at least approximately 2: 1, or at least approximately 4: 1. In another particular embodiment, the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1. In still another particular embodiment, the photovoltaic device has a concave surface and a convex surface opposite the concave surface. In a more particular embodiment, as compared to the heterojunction portion, the homojunction portion is disposed closer to the concave surface, and as compared to the homojunction portion, the heterojunction portion is disposed closer to the convex surface.

In a second aspect, a method of forming an electronic device can include forming one or more doped regions adjacent to a substrate including a semiconductor material, forming point electrical connections to the substrate, and forming a metal-containing layer over the point electrical connections and the substrate. The method can further include separating a first semiconductor layer, the point electrical connections, and the metal-containing layer from a remaining portion of the substrate, wherein, immediately after separating, a newly-formed surface of a first semiconductor layer and a newly-formed surface of the remaining portion have substantially a same semiconductor composition. The method can still further include forming a heterojunction portion after separating the first semiconductor layer.

In an embodiment of the second aspect, the first semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns. In another embodiment, the first semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns. In still another embodiment, the method further includes forming a patterned insulating layer over the substrate before forming the point electrical connections, wherein the patterned insulating layer defines openings overlying the substrate. In a particular embodiment, the method further includes forming spaced-apart doped regions within the substrate after forming the patterned insulating layer and before forming the point electrical connections. In another particular embodiment, the doped region is formed before forming the patterned insulating layer. In a more particular embodiment, the doped region has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In an even more particular embodiment, forming the doped region includes doping the substrate. In still an even more particular embodiment, forming the doped region includes epitaxially growing a doped semiconductor layer from the substrate.

In a further embodiment of the second aspect, the method further includes modifying a topology of an exposed surface at or adjacent to the substrate before plating the metal-containing layer. In a particular embodiment, modifying the topology includes wet etching the exposed surface. In a more particular embodiment, wherein wet etching is performed using a basic solution, a colloidal metal solution, or any combination thereof. In another particular embodiment, modifying the topology includes dry etching the exposed surface. In a more particular embodiment, dry etching is performed using a reactive ion etch, a sputter etch, or any combination thereof. In a further particular embodiment, modifying the topology includes mechanically removing a portion of the substrate at the exposed surface. In a more particular embodiment, mechanical removing includes cutting groove or a pattern into a material at the exposed surface, abrading the exposes surface, or any combination thereof.

In another embodiment of the second aspect, the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns. In still another embodiment, the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns. In a further embodiment, forming the metal containing layer includes a plating principal film including 100 %, or at least 99%, or at least 95%, or at least 90% of a total thickness of the metal-containing layer. In a particular embodiment, forming the metal-containing layer further includes forming an adhesion film, a barrier film, a seed film, or any combination thereof, before plating the principal film.

In a further embodiment of the second aspect, the method further includes cooling the metal-containing layer and the substrate after plating the metal-containing layer and before separating the first semiconductor layer. In a particular embodiment, the method further includes heating the metal-containing layer and the substrate after plating the metal-containing layer and before cooling the metal-containing layer and the substrate. In still a further embodiment, the method further includes creating a weakened region within the substrate during cooling the metal- containing layer and the substrate, heating the metal-containing layer and the substrate, or heating then cooling the metal-containing layer and the substrate. In still another embodiment, separating the first semiconductor layer includes fracturing the substrate at a depth corresponding to a thickness of the first semiconductor layer. In a particular embodiment, separating the first semiconductor layer is performed without using a mechanical separating tool. In a further embodiment, separating the first semiconductor layer includes cleaving the substrate at a depth corresponding to a thickness of the first semiconductor layer. In still a further embodiment, separating the first semiconductor layer is performed using a wedge, a wire, a saw, a laser, an acoustical device, or any combination thereof. In yet a further, embodiment, separating the first semiconductor layer comprises applying a metallic paste over the metal-containing layer;

attaching a handling substrate; pulling the handling substrate from the substrate such that the first semiconductor layer, the point electrical connections, and the metal-containing layer remain attached to the handling substrate; and removing the first semiconductor layer, the point electrical connections, and the metal-containing layer from the handling substrate before forming the heterojunction portion.

In another embodiment of the second aspect, the heterojunction portion and the first semiconductor layer have a same semiconductor composition. In a particular embodiment, forming the heterojunction portion includes depositing a layer of an amorphous semiconductor material, a polycrystalline semiconductor material, or a combination of thereof; and the first semiconductor layer is substantially monocrystalline. In still another embodiment, a

semiconductor composition of the heterojunction portion and a semiconductor composition of the first semiconductor layer include only one or more Group 14 elements. In yet another embodiment, a semiconductor composition of the heterojunction portion and the semiconductor composition of the first semiconductor layer include solely silicon. In a further embodiment, a semiconductor composition of the heterojunction portion includes silicon, the first semiconductor layer includes germanium, and the heterojunction portion has a higher energy bandgap as compared to the first semiconductor layer. In another embodiment of the second aspect, the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm. In still another embodiment, the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm. In a further embodiment, the heterojunction portion includes a plurality of layers. In a particular embodiment, the heterojunction portion includes an undoped semiconductor layer. In a more particular embodiment, forming the heterojunction portion further includes forming a doped semiconductor layer over the undoped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the first semiconductor layer. In an even more particular embodiment, the homojunction portion includes an n-type substantially monocrystalline semiconductor layer, the doped semiconductor layer includes a p-type semiconductor layer, a heterojunction is at a junction of the n-type substantially monocrystalline semiconductor layer and the undoped semiconductor layer, and the undoped semiconductor layer is an only layer disposed between the n-type substantially monocrystalline semiconductor layer and the p-type semiconductor layer. In another embodiment of the second aspect, forming the heterojunction includes chemical vapor depositing or physical vapor depositing a second semiconductor layer. In a particular embodiment, chemical vapor depositing includes plasma-enhanced chemical vapor deposition, remote plasma chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition, atmospheric chemical vapor deposition, or any combination thereof. In still another embodiment, the substrate has a doping concentration no greater than approximately lxlO¹⁸ atoms/cm³, the one or more doped regions having a doping concentration of at least approximately lxlO¹⁹ atoms/cm³, forming the metal-containing layer is performed such that the metal-containing layer directly contacts the doped region, and after separating the first semiconductor layer, the doped region directly contacts the metal-containing layer. In a further embodiment, the method further includes forming an electrode adjacent to the heterojunction portion. In a particular embodiment, forming the electrode includes forming a principal conductor over the heterojunction portion, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. In a more particular embodiment, the principal conductor is in the form of a grid. In another more particular embodiment, forming the electrode further includes forming a conductive layer that is substantially transparent to the radiation, wherein forming the principal conductor is performed after forming the conductive layer. In an even more particular embodiment, the conductive layer includes a layer of indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof along a surface of the heterojunction portion.

In a third aspect, a method of forming an electronic device including a photovoltaic device can include providing a combination of a first semiconductor layer and a metal-containing layer, wherein the combination is curved. The method can further include mounting the combination to a workpiece holder, wherein, while the combination is mounted, the combination is less curved as compared to before mounting; and forming another layer over the combination while the combination is mounted.

In an embodiment of the third aspect, the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1: 1, at least approximately 2: 1, or at least approximately 4: 1. In another embodiment, the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1. In still another embodiment, the combination has a concave surface and a convex surface opposite the concave surface. In a particular embodiment, as compared to the first semiconductor layer, the metal-containing layer is disposed closer to the concave surface; and as compared to the metal-containing layer, the first semiconductor layer is disposed closer to the convex surface.

In a further embodiment of the third aspect, the workpiece holder includes a coating that including a fluoropolymer, a silicon nitride, a silicon carbide, anodized aluminum. In still a further embodiment, the first semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns. In yet a further embodiment, the first semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

In another embodiment of the third aspect, the method further includes separating the first semiconductor layer and the metal-containing layer from a remaining portion of the substrate, wherein, immediately after separating, a newly-formed surface of the first semiconductor layer and a newly-formed surface of the remaining portion have substantially a same semiconductor composition. In a particular embodiment, the method further includes forming a patterned insulating layer over the substrate, wherein the patterned insulating layer defines openings extending to the first layer of semiconductor layer, and forming the point electrical connections at locations adjacent to the openings in the patterned insulating layer.

In a more particular embodiment of the third aspect, the method further includes forming spaced-apart doped regions within the substrate after forming the patterned insulating layer and before separating the first semiconductor layer. In another more particular embodiment, the method further includes forming a doped region along a side of the substrate, wherein the doped region is formed before forming the patterned insulating layer. In an even more particular embodiment, the doped region has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In yet even more particular embodiment, forming the doped region includes doping the substrate. In another yet even more particular embodiment, forming the doped region includes epitaxially growing a doped semiconductor layer from the substrate.

In a particular embodiment of the third aspect, separating the first semiconductor layer includes fracturing the substrate at a depth corresponding to a thickness of the first semiconductor layer. In a more particular embodiment, separating the first semiconductor layer is performed without using a mechanical separating tool. In another particular embodiment, separating the first semiconductor layer includes cleaving the substrate at a depth corresponding to a thickness of the first semiconductor layer. In still another particular embodiment, separating the first semiconductor layer is performed using a wedge, a wire, a saw, a laser, an acoustical device, or any combination thereof. In yet another particular embodiment, separating the first

semiconductor layer comprises applying a metallic paste over the metal-containing layer, attaching a handling substrate, pulling the handling substrate from the substrate such that the first semiconductor layer and the metal-containing layer remain attached to the handling substrate, and removing the first semiconductor layer and the metal-containing layer from the handling substrate before mounting the combination to a workpiece holder.

In a further embodiment of the third aspect, the method further includes: modifying a topology of an exposed surface at or adjacent to the substrate, and forming the metal-containing layer over the substrate after modifying the topology. In a particular embodiment, modifying the topology includes wet etching the exposed surface. In a more particular embodiment, wet etching is performed using a basic solution, a colloidal metal solution, or any combination thereof. In another particular embodiment, modifying the topology includes dry etching the exposed surface. In a more particular embodiment, dry etching is performed using a reactive ion etch, a sputter etch, or any combination thereof. In still another particular embodiment, modifying the topology includes mechanically removing a portion of the substrate at the exposed surface. In a more particular embodiment, mechanical removing includes cutting groove or a pattern into a material at the exposed surface, abrading the exposes surface, or any combination thereof.

In another embodiment of the third aspect, the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns. In still another embodiment, the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns. In yet another embodiment, forming the metal-containing layer includes plating a principal film including 100 %, or at least 99%, or at least 95%, or at least 90% of a total thickness of the metal-containing layer. In a particular embodiment, forming the metal-containing layer further includes forming an adhesion film, a barrier film, a seed film, or any combination thereof, before plating the principal film. In another particular embodiment, the method further includes cooling the principal film and the substrate after plating the principal film and before separating the first semiconductor layer. In still another particular embodiment, the method further includes heating the principal film and the substrate after plating the principal film and before cooling the principal film and the substrate. In yet another particular embodiment, the method further includes creating a weakened region within the substrate during cooling the principal film and the substrate, heating the principal film and the substrate, or heating then cooling the principal film and the substrate.

In a further embodiment of the third aspect, forming the other layer includes forming a second semiconductor layer over the first semiconductor layer, wherein a junction between the first and second layer is a heterojunction. In a particular embodiment, the first and second semiconductor layers have substantially a same semiconductor material. In a more particular embodiment, forming the second semiconductor layer includes depositing a layer of an amorphous semiconductor material, a polycrystalline semiconductor material, or a combination of thereof, and the first semiconductor layer is substantially monocrystalline. In another particular embodiment, a semiconductor composition of the second semiconductor layer and a

semiconductor composition of the first semiconductor layer include only one or more Group 14 elements. In still another particular embodiment, semiconductor materials of the first and second semiconductor layers include solely silicon. In yet another particular embodiment, the first semiconductor layer includes germanium, the second semiconductor layer includes silicon, and the heterojunction portion has a higher energy bandgap as compared to the first semiconductor layer.

In a further particular embodiment of the third aspect, the second semiconductor layer has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm. In still a further particular embodiment, the second semiconductor layer has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm. In yet a further particular embodiment, forming the second semiconductor layer includes chemical vapor depositing or physical vapor depositing the second semiconductor layer. In a more particular embodiment, chemical vapor depositing includes plasma-enhanced chemical vapor deposition, remote plasma chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition, atmospheric chemical vapor deposition, or any combination thereof.

In another particular embodiment of the third aspect, the second semiconductor layer includes an undoped semiconductor film. In a more particular embodiment, forming a doped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the first semiconductor layer. In an even more particular embodiment, the first semiconductor layer includes an n-type substantially monocrystalline semiconductor layer, the doped semiconductor layer includes a p-type semiconductor layer, a heterojunction is formed at a junction of the n-type substantially monocrystalline semiconductor layer and an undoped semiconductor portion of the second semiconductor layer, and the undoped semiconductor portion is an only semiconductor material disposed between the n-type substantially monocrystalline semiconductor layer and the p-type semiconductor layer.

In another particular embodiment of the third aspect, the method further includes forming an electrode adjacent to the second semiconductor layer. In a more particular embodiment, forming the electrode includes forming a principal conductor over the second semiconductor layer, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. In an even more particular embodiment, the principal conductor is in the form of a grid. In another even more particular embodiment, forming the electrode further includes forming a conductive layer that is substantially transparent to the radiation, wherein forming the principal conductor is performed after forming the conductive layer. In yet an even more particular embodiment, the conductive layer includes a layer of indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof along a surface of the heterojunction portion. Note that not all of the activities described above in the general description or the examples are required, that a portion of a specific activity may not be required, and that one or more further activities may be performed in addition to those described. Still further, the order in which activities are listed is not necessarily the order in which they are performed.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims.

The specification and illustrations of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The specification and illustrations are not intended to serve as an exhaustive and comprehensive description of all of the elements and features of apparatus and systems that use the structures or methods described herein. Separate embodiments may also be provided in combination in a single embodiment, and conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, reference to values stated in ranges includes each and every value within that range. Many other embodiments may be apparent to skilled artisans only after reading this specification. Other embodiments may be used and derived from the disclosure, such that a structural substitution, logical substitution, or another change may be made without departing from the scope of the disclosure. Accordingly, the disclosure is to be regarded as illustrative rather than restrictive.

Claims

WHAT IS CLAIMED IS:

1. An electronic device comprising:

a heterojunction portion closer to a first surface of the electronic device, wherein the first surface is a light-receiving surface;

a homojunction portion closer to a second surface of the electronic device opposite the first surface; and

point electrical connections to regions of the homojunction portion, wherein the point electrical connections are spaced apart from each other.

2. The electronic device of claim 1, wherein the point electrical connections include point

contacts.

3. The electronic device of claim 1, wherein the point electrical connections include spaced-apart doped regions within the homojunction portion.

4. The electronic device of claim 1, wherein each of the point electrical connections includes point contacts and a corresponding doped region within the homojunction portion.

5. The electronic device of claim 1, wherein the homojunction portion comprises a doped region having a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³.

6. The electronic device of claim 1, wherein the homojunction portion has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns.

7. The electronic device of claim 1, wherein the homojunction portion has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

8. The electronic device of claim 1, wherein the point electrical connections are part of a metal- containing layer electrically connected to the homojunction region, wherein the metal- containing layer is a substantially continuous layer that extends between and overlies the point electrical connections.

9. The electronic device of claim 8, wherein the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns.

10. The electronic device of claim 8, wherein the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns.

11. The electronic device of claim 8, wherein the metal containing layer comprises a principal film comprising 100 %, at least 99%, at least 95%, or at least 90% of a total thickness of the metal-containing layer.

12. The electronic device of claim 11, wherein the metal-containing layer further comprises an adhesion film, a barrier film, a seed film, or any combination thereof.

13. The electronic device of claim 8, further comprising a patterned insulating layer defining openings, wherein the point electrical connections extend into the openings.

14. The electronic device of claim 1, further comprising an electrode electrically connected to the heterojunction portion.

15. The electronic device of claim 14, wherein the electrode comprises a principal conductor that is electrically connected to the electrode, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm.

16. The electronic device of claim 15, wherein the principal conductor is in the form of a grid.

The electronic device of claim 15, wherein the electrode further comprises a conductive layi that is substantially transparent to the radiation, and the conductive layer is disposed between the principal conductor and the heterojunction portion.

18. The electronic device of claim 17, wherein the conductive layer comprises indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof.

19. The electronic device of claim 1, wherein the heterojunction portion and the homojunction portion have a same semiconductor composition.

20. The electronic device of claim 19, wherein the heterojunction portion is amorphous,

polycrystalline, or a combination of thereof, and the homojunction portion is substantially monocrystalline.

21. The electronic device of claim 1, wherein a semiconductor composition of the heterojunction portion and a semiconductor composition of the homojunction portion include only one or more Group 14 elements.

22. The electronic device of claim 1, wherein a semiconductor composition of the heterojunction portion and a semiconductor composition of the homojunction portion include solely silicon.

23. The electronic device of claim 1, wherein the heterojunction portion comprises silicon, the homojunction portion comprises germanium, and the heterojunction portion has a higher energy bandgap as compared to the semiconductor material of the homojunction portion.

24. The electronic device of claim 1, wherein the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm.

25. The electronic device of claim 1, wherein the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm.

26. The electronic device of claim 1, wherein the heterojunction portion comprises an undoped semiconductor layer.

27. The electronic device of claim 26, wherein the heterojunction portion further comprises a doped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the homojunction portion.

28. The electronic device of claim 27, wherein the homojunction portion comprises:

a first doped region having a doping concentration no greater than approximately lxlO¹⁸ atoms/cm³, wherein a heterojunction is formed at the junction of the undoped semiconductor layer and the first doped region; and a second doped region spaced apart from the heterojunction portion and having a doping concentration of at least approximately lxlO¹⁹ atoms/cm³, wherein the second doped region is part of the point electrical connections or is in contact with at least one of the point electrical connections.

29. The electronic device of claim 27, wherein:

the homojunction portion comprises an n-type substantially monocrystalline

semiconductor layer;

the doped semiconductor layer comprises a p-type semiconductor layer;

a heterojunction is formed at a junction of the n-type substantially monocrystalline

semiconductor layer and the undoped semiconductor layer; and

the undoped semiconductor layer is an only layer disposed between the n-type

substantially monocrystalline semiconductor layer and the p-type semiconductor layer.

30. The electronic device of claim 1, wherein the homojunction portion has a surface with a varying topology.

31. The electronic device of claim 30, wherein the point electrical connections are disposed along the surface with the varying topology.

32. The electronic device of claim 1, wherein the electronic device comprises a photovoltaic device that is curved.

33. The electronic device of claim 32, wherein the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1 : 1, at least approximately 2: 1, or at least approximately 4: 1.

34. The electronic device of claim 32, wherein the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1.

35. The electronic device of claim 32, wherein the photovoltaic device has a concave surface and a convex surface opposite the concave surface.

36. The electronic device of claim 35, wherein:

as compared to the heterojunction portion, the homojunction portion is disposed closer to the concave surface; and

as compared to the homojunction portion, the heterojunction portion is disposed closer to the convex surface.

37. A method of forming an electronic device comprising:

forming one or more doped regions adjacent to a substrate including a semiconductor material;

forming point electrical connections to the substrate;

forming a metal-containing layer over the point electrical connections and the substrate; separating a first semiconductor layer, the point electrical connections, and the metal- containing layer from a remaining portion of the substrate, wherein, immediately after separating, a newly-formed surface of a first semiconductor layer and a newly- formed surface of the remaining portion have substantially a same semiconductor composition; and

forming a heterojunction portion after separating the first semiconductor layer.

38. The method of claim 37, wherein the first semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns.

39. The method of claim 37, wherein the first semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

40. The method of claim 37, further comprising forming a patterned insulating layer over the substrate before forming the point electrical connections, wherein the patterned insulating layer defines openings overlying the substrate.

41. The method of claim 40, further comprising forming spaced-apart doped regions within the substrate after forming the patterned insulating layer and before forming the point electrical connections.

42. The method of claim 40, wherein the doped region is formed before forming the patterned insulating layer.

43. The method of claim 42, wherein the doped region has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³.

44. The method of claim 43, wherein forming the doped region comprises doping the substrate.

45. The method of claim 43, wherein forming the doped region comprises epitaxially growing a doped semiconductor layer from the substrate.

46. The method of claim 37, further comprising modifying a topology of an exposed surface at or adjacent to the substrate before plating the metal-containing layer.

47. The method of claim 46, wherein modifying the topology comprises wet etching the exposed surface.

48. The method of claim 47, wherein wet etching is performed using a basic solution, a colloidal metal solution, or any combination thereof.

49. The method of claim 46, wherein modifying the topology comprises dry etching the exposed surface.

50. The method of claim 49, wherein dry etching is performed using a reactive ion etch, a sputter etch, or any combination thereof.

51. The method of claim 46, wherein modifying the topology comprises mechanically removing a portion of the substrate at the exposed surface.

52. The method of claim 51, wherein mechanical removing comprises cutting groove or a pattern into a material at the exposed surface, abrading the exposes surface, or any combination thereof.

53. The method of claim 37, wherein the metal-containing layer has a thickness of at least

approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns.

54. The method of claim 37, wherein the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than

approximately 200 microns.

55. The method of claim 37, wherein forming the metal containing layer comprises a plating principal film comprising 100 %, or at least 99%, or at least 95%, or at least 90% of a total thickness of the metal-containing layer.

56. The method of claim 55, wherein forming the metal-containing layer further comprises forming an adhesion film, a barrier film, a seed film, or any combination thereof, before plating the principal film.

57. The method of claim 37, further comprising cooling the metal-containing layer and the

substrate after plating the metal-containing layer and before separating the first semiconductor layer.

58. The method of claim 57, further comprising heating the metal-containing layer and the

substrate after plating the metal-containing layer and before cooling the metal-containing layer and the substrate.

59. The method of claim 37, further comprising creating a weakened region within the substrate during cooling the metal-containing layer and the substrate, heating the metal-containing layer and the substrate, or heating then cooling the metal-containing layer and the substrate.

60. The method of claim 37, wherein separating the first semiconductor layer comprises

fracturing the substrate at a depth corresponding to a thickness of the first semiconductor layer.

61. The method of claim 60, wherein separating the first semiconductor layer is performed

without using a mechanical separating tool.

62. The method of claim 37, wherein separating the first semiconductor layer comprises cleaving the substrate at a depth corresponding to a thickness of the first semiconductor layer.

63. The method of claim 37, wherein separating the first semiconductor layer is performed using a wedge, a wire, a saw, a laser, an acoustical device, or any combination thereof.

64. The method of claim 37, wherein separating the first semiconductor layer comprises:

applying a metallic paste over the metal-containing layer;

attaching a handling substrate; pulling the handling substrate from the substrate such that the first semiconductor layer, the point electrical connections, and the metal-containing layer remain attached to the handling substrate; and

removing the first semiconductor layer, the point electrical connections, and the metal- containing layer from the handling substrate and before forming the heterojunction portion.

65. The method of claim 37, wherein the heterojunction portion and the first semiconductor layer have a same semiconductor composition.

66. The method of claim 65, wherein:

forming the heterojunction portion comprises depositing a layer of an amorphous

semiconductor material, a polycrystalline semiconductor material, or a combination of thereof; and

the first semiconductor layer is substantially monocrystalline.

67. The method of claim 37, wherein a semiconductor composition of the heterojunction portion and a semiconductor composition of the first semiconductor layer include only one or more Group 14 elements.

68. The method of claim 37, wherein a semiconductor composition of the heterojunction portion and the semiconductor composition of the first semiconductor layer include solely silicon.

69. The method of claim 37, wherein a semiconductor composition of the heterojunction portion comprises silicon, the first semiconductor layer comprises germanium, and the heterojunction portion has a higher energy bandgap as compared to the first semiconductor layer.

70. The method of claim 37, wherein the heterojunction portion has a thickness of at least

approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm.

71. The method of claim 37, wherein the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm.

72. The method of claim 37, wherein the heterojunction portion comprises a plurality of layers.

73. The method of claim 72, wherein the heterojunction portion comprises an undoped semiconductor layer.

74. The method of claim 73, wherein forming the heterojunction portion further comprises

forming a doped semiconductor layer over the undoped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the first semiconductor layer.

75. The method of claim 74, wherein:

the homojunction portion comprises an n-type substantially monocrystalline

semiconductor layer;

the doped semiconductor layer comprises a p-type semiconductor layer;

a heterojunction is at a junction of the n-type substantially monocrystalline semiconductor layer and the undoped semiconductor layer; and

the undoped semiconductor layer is an only layer disposed between the n-type

76. The method of claim 37, wherein forming the heterojunction comprises chemical vapor depositing or physical vapor depositing a second semiconductor layer.

77. The method of claim 76, wherein chemical vapor depositing comprises plasma-enhanced chemical vapor deposition, remote plasma chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition, atmospheric chemical vapor deposition, or any combination thereof.

78. The method of claim 37, wherein:

the substrate has a doping concentration no greater than approximately lxlO¹⁸ atoms/cm³; the one or more doped regions having a doping concentration of at least approximately lxlO¹⁹ atoms/cm³;

forming the metal-containing layer is performed such that the metal-containing layer directly contacts the doped region; and

after separating the first semiconductor layer, the doped region directly contacts the metal-containing layer.

79. The method of claim 37, further comprising forming an electrode adjacent to the

heterojunction portion.

80. The method of claim 79, wherein forming the electrode comprises forming a principal conductor over the heterojunction portion, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm.

81. The method of claim 80, wherein the principal conductor is in the form of a grid.

82. The method of claim 80, wherein forming the electrode further comprises forming a

conductive layer that is substantially transparent to the radiation, wherein forming the principal conductor is performed after forming the conductive layer.

83. The method of claim 82, wherein the conductive layer comprises a layer of indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof along a surface of the heterojunction portion.

84. A method of forming an electronic device comprising a photovoltaic device, wherein the method comprises:

providing a combination of a first semiconductor layer and a metal-containing layer, wherein the combination is curved;

mounting the combination to a workpiece holder, wherein, while the combination is mounted, the combination is less curved as compared to before mounting; and forming another layer over the combination while the combination is mounted.

85. The method of claim 84, wherein the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1 : 1, at least approximately 2: 1, or at least approximately 4: 1.

86. The method of claim 84, wherein the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1.

87. The method of claim 84, wherein the combination has a concave surface and a convex

surface opposite the concave surface.

88. The method of claim 87, wherein:

as compared to the first semiconductor layer, the metal-containing layer is disposed closer to the concave surface; and

as compared to the metal-containing layer, the first semiconductor layer is disposed closer to the convex surface.

89. The method of claim 84, wherein the workpiece holder comprises a coating that including a fluoropolymer, a silicon nitride, a silicon carbide, anodized aluminum.

90. The method of claim 84, wherein the first semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns.

91. The method of claim 84, wherein the first semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

92. The method of claim 84, further comprising separating the first semiconductor layer and the metal-containing layer from a remaining portion of the substrate, wherein, immediately after separating, a newly-formed surface of the first semiconductor layer and a newly- formed surface of the remaining portion have substantially a same semiconductor composition.

93. The method of claim 92, further comprising:

forming a patterned insulating layer over the substrate, wherein the patterned insulating layer defines openings extending to the first layer of semiconductor layer; and forming the point electrical connections at locations adjacent to the openings in the

patterned insulating layer.

94. The method of claim 93, further comprising forming spaced-apart doped regions within the substrate after forming the patterned insulating layer and before separating the first semiconductor layer.

95. The method of claim 93, further comprising forming a doped region along a side of the

substrate, wherein the doped region is formed before forming the patterned insulating layer.

96. The method of claim 95, wherein the doped region has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³.

97. The method of claim 96, wherein forming the doped region comprises doping the substrate.

98. The method of claim 96, wherein forming the doped region comprises epitaxially growing a doped semiconductor layer from the substrate.

99. The method of claim 92, wherein separating the first semiconductor layer comprises

100. The method of claim 99, wherein separating the first semiconductor layer is performed without using a mechanical separating tool.

101. The method of claim 92, wherein separating the first semiconductor layer comprises cleaving the substrate at a depth corresponding to a thickness of the first semiconductor layer.

102. The method of claim 92, wherein separating the first semiconductor layer is performed using a wedge, a wire, a saw, a laser, an acoustical device, or any combination thereof.

103. The method of claim 92, wherein separating the first semiconductor layer comprises: applying a metallic paste over the metal-containing layer;

attaching a handling substrate;

pulling the handling substrate from the substrate such that the first semiconductor layer and the metal-containing layer remain attached to the handling substrate; and removing the first semiconductor layer and the metal-containing layer from the handling substrate before mounting the combination to a workpiece holder.

104. The method of claim 84, further comprising:

modifying a topology of an exposed surface at or adjacent to the substrate; and forming the metal-containing layer over the substrate after modifying the topology.

105. The method of claim 104, wherein modifying the topology comprises wet etching the exposed surface.

106. The method of claim 105, wherein wet etching is performed using a basic solution, a colloidal metal solution, or any combination thereof.

107. The method of claim 104, wherein modifying the topology comprises dry etching the exposed surface.

108. The method of claim 107, wherein dry etching is performed using a reactive ion etch, a sputter etch, or any combination thereof.

109. The method of claim 104, wherein modifying the topology comprises mechanically

removing a portion of the substrate at the exposed surface.

110. The method of claim 109, wherein mechanical removing comprises cutting groove or a pattern into a material at the exposed surface, abrading the exposes surface, or any combination thereof.

111. The method of claim 84, wherein the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns.

112. The method of claim 84, wherein the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns.

113. The method of claim 84, wherein forming the metal-containing layer comprises plating a principal film comprising 100 %, or at least 99%, or at least 95%, or at least 90% of a total thickness of the metal-containing layer.

114. The method of claim 113, wherein forming the metal-containing layer further comprises forming an adhesion film, a barrier film, a seed film, or any combination thereof, before plating the principal film.

115. The method of claim 113, further comprising cooling the principal film and the substrate after plating the principal film and before separating the first semiconductor layer.

116. The method of claim 113, further comprising heating the principal film and the substrate after plating the principal film and before cooling the principal film and the substrate.

117. The method of claim 113, further comprising creating a weakened region within the substrate during cooling the principal film and the substrate, heating the principal film and the substrate, or heating then cooling the principal film and the substrate.

118. The method of claim 84, wherein forming the other layer comprises forming a second

semiconductor layer over the first semiconductor layer, wherein a junction between the first and second layer is a heterojunction.

119. The method of claim 118, wherein the first and second semiconductor layers have

substantially a same semiconductor material.

120. The method of claim 119, wherein forming the second semiconductor layer comprises depositing a layer of an amorphous semiconductor material, a polycrystalline

semiconductor material, or a combination of thereof, and the first semiconductor layer is substantially monocrystalline.

121. The method of claim 118, wherein a semiconductor composition of the second

semiconductor layer and a semiconductor composition of the first semiconductor layer include only one or more Group 14 elements.

122. The method of claim 118, wherein semiconductor materials of the first and second

semiconductor layers include solely silicon.

123. The method of claim 118, wherein the first semiconductor layer comprises germanium, the second semiconductor layer comprises silicon, and the heterojunction portion has a higher energy bandgap as compared to the first semiconductor layer.

124. The method of claim 118, wherein the second semiconductor layer has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm.

125. The method of claim 118, wherein the second semiconductor layer has a thickness no

greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm.

126. The method of claim 118, wherein forming the second semiconductor layer comprises chemical vapor depositing or physical vapor depositing the second semiconductor layer.

127. The method of claim 126, wherein chemical vapor depositing comprises plasma-enhanced chemical vapor deposition, remote plasma chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition, atmospheric chemical vapor deposition, or any combination thereof.

128. The method of claim 118, wherein the second semiconductor layer comprises an undoped semiconductor film.

129. The method of claim 128, wherein forming a doped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the first semiconductor layer.

130. The method of claim 129, wherein:

the first semiconductor layer comprises an n-type substantially monocrystalline

semiconductor layer;

the doped semiconductor layer comprises a p-type semiconductor layer;

a heterojunction is formed at a junction of the n-type substantially monocrystalline semiconductor layer and an undoped semiconductor portion of the second semiconductor layer; and

the undoped semiconductor portion is an only semiconductor material disposed between the n-type substantially monocrystalline semiconductor layer and the p-type semiconductor layer.

131. The method of claim 118, further comprising forming an electrode adjacent to the second semiconductor layer.

132. The method of claim 131, wherein forming the electrode comprises forming a principal conductor over the second semiconductor layer, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm.

133. The method of claim 132, wherein the principal conductor is in the form of a grid.

134. The method of claim 132, wherein forming the electrode further comprises forming a conductive layer that is substantially transparent to the radiation, wherein forming the principal conductor is performed after forming the conductive layer. The method of claim 134, wherein the conductive layer comprises a layer of indium-tin- oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof along a surface of the heterojunction portion.