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WO2011134896A2 - Amincissement par rognage - Google Patents

Amincissement par rognage Download PDF

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Publication number
WO2011134896A2
WO2011134896A2 PCT/EP2011/056444 EP2011056444W WO2011134896A2 WO 2011134896 A2 WO2011134896 A2 WO 2011134896A2 EP 2011056444 W EP2011056444 W EP 2011056444W WO 2011134896 A2 WO2011134896 A2 WO 2011134896A2
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
wheel
layer
bonding
grinding
Prior art date
Application number
PCT/EP2011/056444
Other languages
English (en)
Other versions
WO2011134896A3 (fr
Inventor
Alexandre Vaufredaz
Marcel Broekaart
Arnaud Castex
Original Assignee
S.O.I. Tec Silicon On Insulator Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S.O.I. Tec Silicon On Insulator Technologies filed Critical S.O.I. Tec Silicon On Insulator Technologies
Publication of WO2011134896A2 publication Critical patent/WO2011134896A2/fr
Publication of WO2011134896A3 publication Critical patent/WO2011134896A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Definitions

  • the present invention relates to the field of the production of multilayer semiconductor structures or substrates (also known as “multilayer semiconductor wafers") produced by transfer of at least one layer onto a support ,
  • the production of multilayer structures generally comprises direct wafer bonding or fusion bonding of a first wafer, for example a silicon wafer or a wafer of the SOI (silicon on insulator) type, onto a second wafer or support formed, for example, from silicon or sapphire, a bonding reinforcing anneal, and thinning the first wafer to form a transferred layer on the second wafer.
  • a first wafer for example a silicon wafer or a wafer of the SOI (silicon on insulator) type
  • SOI silicon on insulator
  • the invention provides multilayer structures having a relatively weak bonding interface due to limitations placed upon the bonding reinforcing anneal temperature.
  • the structure is normally annealed in order to reinforce the bond between the two wafers, i.e. to increase the surface energy of the bond between them.
  • a first kind concerns the production of multilayer structures termed "heterogeneous" multilayer structures, since the two wafers for assembling together have
  • heterostructures are in particular those of the silicon on sapphire type (AI 2 O 3 ) known by the acronym SOS (silicon on sapphire) ; they are used in particular in microelectronics or optoelectronics.
  • Si on sapphire silicon on sapphire
  • SOS silicon on sapphire
  • heterostructure that can cause delamination or detachment of the wafers or layers that are present, and/or plastic deformation and/or fractures and/or breakage of one or more of the substrates or layers that are present. For this reason, with such structures, the temperature of the bonding reinforcing anneal is limited.
  • a second kind concerns multilayer structures in which the first wafer further comprises all or a portion of a component or a plurality of microcomponents , as happens with three-dimensional component integration technology (3D-integration) , which requires the transfer of one or more layers of microcomponents onto a final support, and also when transferring circuits such as in the fabrication of back-lit imaging devices, for example, in such circumstances, the temperature of the bonding reinforcing anneal needs to be limited so that the microcomponents are not damaged.
  • 3D-integration three-dimensional component integration technology
  • the sides of - the wafers used in particular to form the transfer layers and the supports generally have chamfers or edge roundings that act to facilitate their manipulation and to avoid breakage of the sides that could occur if those sides projected out, such breakages being sources for contamination of the wafer surfaces with particles.
  • the chamfers may have a rounded and/or beveled shape.
  • the transfer layer may then be trimmed in order to remove the peripheral zone over which the chamfers extend. Trimming is usually carried out by mechanical machining, in particular by abrasion from the exposed surface of the transferred layer and just into the second support wafer.
  • the bonding energy is lower in the vicinity of the periphery of the layer due to the presence of the chamfers. As a consequence, at this region said trimming may cause partial detachment of the layer at its bonding interface with the support substrate.
  • the method comprising bonding a first wafer to a second wafer and a step of thinning the first wafer carried out at least by grinding using a wheel having its working surface in contact with the exposed surface of the first wafer, in which method the working surface of the wheel comprises abrasive particles with a mean dimension of 44 micrometers or less or 325 mesh or more while the rate of descent of the wheel during the grinding step is reduced to at least 1 ⁇ /sec [micrometer per second] when the working surface of the wheel is at a distance of at least 250 um from the bonding interface, said grinding step at 1 um/sec being continued until the working surface of the wheel is at a distance from said bonding interface of 35 um or less.
  • the back face of the second wafer is held on a support that is driven in rotation, the wheel used for grinding and said support having an identical direction of rotation.
  • the method includes, before the bonding step, at least one step of producing a layer of
  • a step of producing a second layer of microcomponents on the face of the first wafer opposite to the face comprising the first layer of components may also be carried out.
  • Using the method of the invention means that three- dimensional structures may be produced by stacking two wafers or more, minimizing risks of delamination both at the bonding interfaces between the wafers and at the layers of the components.
  • components may in particular comprise image sensors .
  • Figures 1A to IF are diagrammatic views of a method of producing a multilayer structure in accordance with one implementation of the invention.
  • FIG. 2 is a flow chart of the steps carried out during the method illustrated in Figures 1A to IF;
  • Figure 3 is a top view showing the movement of a grinding wheel in accordance with one implementation of the method of the invention.
  • Figures 4A to 4H are diagrammatic views showing the production of a three-dimensional structure
  • Figure 5 is a flow chart of the steps carried out during the production of the three-dimensional structure illustrated in Figures 4A to 4H.
  • the present invention is of general application to trimming a multilayer structure comprising at least two wafers assembled together by bonding and for which the bonding surface energy is limited, for example to a value of 1 J/m 2 [joule per square meter] or less, at least one of the two wafers including chamfers or edge roundings at its periphery.
  • Such multilayer structures correspond in particular to structures produced from at least two wafers having different thermal expansion coefficients or including microcomponents and for which the temperature of the bonding reinforcing anneal for stabilizing it and increasing its energy needs to be limited.
  • the invention could also be applied to multilayer structures in which the wafers are assembled together by any type of bonding such as anodic, or metallic bonding, or using an
  • the bonding surface energy remains limited, especially to a value of less than 1 J/m 2 .
  • the wafers are in the form of wafers with a
  • components may already have been formed in one of the wafers that is then bonded to another wafer that constitutes a support.
  • components as used here means any type of element produced with materials that differ from that of the wafer and that are sensitive to the high temperatures usually used to reinforce the bonding interface. These components correspond in particular to elements forming all or a portion of an electronic component or a plurality of electronic
  • microcomponents such as circuits or contacts or even active layers .
  • the invention is of more particular but not
  • heterostructures of the SOS (silicon on sapphire) type formed from an assembly of a first wafer or substrate formed from sapphire and a second wafer or substrate comprising silicon such as an SOI structure.
  • SOS silicon on sapphire
  • heterostructures comprising a layer of silicon on a sapphire substrate have particular
  • SOS structures can be used to produce high frequency devices with low energy consumption.
  • the present invention proposes carrying out thinning by grinding the first wafer under specific conditions in order to create thermomechanical effects that result in an annular portion remaining on the first wafer snapping off, thereby simultaneously thinning (grinding) the first wafer and trimming it. In this manner, the first wafer is trimmed without having to attack the first wafer all the way to the bonding interface , as is usually necessary. This therefore avoids problems with peel-off and unbonding as described above.
  • grinding during thinning of the first wafer is carried out with a wheel or grinder having its working surface or active portion including abrasive particles with a mean
  • the rate of descent of the wheel during the grinding step being reduced to 1 um/sec or less when the working surface of the wheel is at a distance of at least 250 um from the bonding interface. Further, the remaining thickness of the first wafer after the grinding step at
  • 1 um/sec is 35 um or less.
  • That step is generally followed by grinding with a finer wheel resulting in more controlled removal and being used to obtain a narrower work-hardened zone.
  • the wheel used for grinding has a mean
  • abrasive particle size and a rate of descent from under 250 um from the bonding interface that are smaller than those normally employed.
  • Adjustment of these parameters and the weakness of the bonding interface between the two layers at their periphery means that the thermal and mechanical effects of grinding on the first wafer, in particular at the end of the grinding operation, can be maximized, which means that the ring or annular portion of the first wafer subsisting beneath the wheel can be mechanically
  • a grinding wheel with abrasive pa ticles with a dimension of less than 2000 mesh is selected in order to limit the forces exerted on the layer that could result in it snapping off .
  • One implementation of a trimming method is described below with reference to Figures 1A to IF and 2.
  • Figures 1A to IF and 2 describe a method of
  • the first wafer 110 includes at its periphery an upper chamfer 117a and a lower chamfer 117b.
  • the second wafer 120 includes at its periphery an upper chamfer 127a and a lower chamfer 127b.
  • the thickness of the first wafer 110 is in the range approximately 600 um to 900 um .
  • the first wafer 110 is constituted by an SOI (silicon on insulator) type
  • the exterior surface of the first wafer 110 has also been covered with a thermal oxide layer 114 with a thickness in the range 10 nm
  • the first wafer 110 may also be constituted by a monolithic silicon wafer that may optionally include components.
  • the second wafer 120 is constituted by a wafer formed from sapphire ( Figure 1A) .
  • the face 111a (here covered with the oxide layer 114) of the first wafer 110 and the surface 120a of the second wafer 120 are brought into intimate contact and a pressure is applied to one of the two wafers in order to initiate propagation of a bonding wave between the surfaces in contact (step SI, Figure IB) .
  • direct wafer bonding As is well known per se, the principle of direct wafer bonding, also termed direct bonding, is based on bringing two surfaces into direct contact, i.e. without using a specific material (adhesive, wax, solder, etc) . Such an operation requires that the surfaces for bonding be sufficiently smooth, free of particles or
  • the bond that is produced is not stabilized, since a bonding reinforcing anneal has not been carried out. It is possible for the assembly of the two wafers to undergo an anneal, but the temperature needs to be limited because of the difference in the thermal expansion coefficients between the two wafers. In the example described here, the anneal cannot exceed 180°C, for a period of less than ten hours . Such an anneal cannot stabilize the bond because the bonding surface energy does not exceed 700 mJ/m 2 .
  • Production of the heterostructure is continued by thinning the first wafer 110 to form a transferred layer corresponding to a portion of said first wafer.
  • Thinning is initially carried out by grinding a major portion of the support 113 of the first wafer (step S2, Figure 1C to IE).
  • grinding is carried out with a wheel or grinder 150 having its working surface or active grinding portion 152 comprising abrasive particles with a mean dimension of 44 micrometers or less or 325 mesh or more.
  • the abrasive particles may in particular be diamond particles.
  • a support 160 also known as the " chuck” , comprising a plate 162 that can hold the second wafer 120 , for example by suction or by an electrostatic system.
  • the support 160 may be stationary while the wheel 150 is driven in rotation about its axis 151, or vice versa. Alternatively, as in the example described here, the support 160 may also be movable in rotation about an axis 161.
  • the direc ion of rotation of the wheel is the reverse of that of the support .
  • the wheel is preferably driven in the same direction of rotation as the support .
  • the Applicant has established that by driving the wheel 150 and the support 160 in the same direction of rotation as illustrated in Figure 3, the side of the first wafer is attacked more aggressively, which favors snap-off of the annular portion of the first wafer to be trimmed.
  • the wheel 150 may be driven at a rate of 2800 rpm [revolutions per minute] the support 160 is driven in rotation in the same direction at a rate of 593 rpm.
  • the rate of descent V D of the wheel 150 in the first wafer 110 is controlled as a function of the distance or drop present between the working surface 152 of the wheel 150 and the bonding interface (here the contact plane between the thermal oxide layer 114 and the bonding face 120a of the second wafer 120 ) .
  • the remaining thickness of the layer is constantly measured, for example using a height measurement sensor present on the grinder device.
  • the rate of descent V D of the wheel is 3 pm/sec. From less than 650 um, the rate of descent V D is reduced to
  • the grinding depth is selected so as to stop the descent of the wheel 150, or more precisely its working surface 152, at a distance from the bonding interface ⁇ ⁇ 10 of the order of 35 um, from which distance the annular portion or ring 1110 subsisting beneath the wheel 150 snaps off under the thermomechanical effects ( Figure ID) .
  • Figure ID thermomechanical effects
  • Thinning of the first wafer 110 is continued by chemical etching, also known as wet etching, of the remaining portion 113b (step S3, Figure IF), for example using a TMAH ( tetramethylammonium hydroxide) etching solution or KOH, or by RIE ( reactive ion etching) type dry etching.
  • chemical etching also known as wet etching
  • an SOS type multilayer structure 130 is obtained, comprising a sapphire support formed by the second wafer 120 and a transferred layer 115
  • the oxide layer 112 being retained or removed depending on the requirements, for example by HF deoxidation .
  • a method of producing a three-dimensional structure by transfer of a layer of microcomponents formed in a first wafer or an initial substrate 200 on a second wafer or support substrate 300 (base) in accordance with one implementation of the invention is described below with reference to Figures 4A to 4H and 5.
  • the first wafer 200 is an SOI type multilayer structure, i.e. it comprises a layer of silicon 201 disposed on a substrate 203, also formed from silicon, a buried layer of oxide 202 (for example a layer of Si0 2 ) being present between the layer 201 and the substrate 203.
  • the first wafer 200 has a thickness in the range approximately 600 ⁇ to 900 urn.
  • the microcomponents 204 are formed by
  • the outer surface of the first wafer 200 is then covered with a thermal oxide layer 205 with a thickness in the range 0.1 pm to 3 um, for example, and formed, for example, by oxidation of the wafer surface in order to protect it during the
  • the first wafer 200 may also be constituted by a monolithic silicon wafer .
  • the second wafer or support substrate 300 is a silicon wafer the peripheral side of which has an upper chamfer 306a and a lower chamfer 206b.
  • the outer surface of the wafer 300 is covered with a thermal oxide layer 305 having a thickness in the range 0.1 ⁇ to 3 ⁇ , for example ⁇ Figure 4B, step S13).
  • the face of the first wafer 200 comprising the naicrocomponents 204 is then brought into intimate contact with one face of the second wafer 300 via the thermal oxide layers 205 and 305 and a pressure is applied to one of the two wafers in order to initiate propagation of a bonding wave between the surfaces in contact (step S14, Figure 4C) .
  • the bond between the two wafers is produced at a low temperature so as not to damage the components and/or the first wafer. More precisely, after bringing the wafers into contact at ambient temperature, a bonding
  • reinforcing anneal may be carried out, but at a
  • Thinning is initially carried out by grinding a major portion of the support 203 of the first wafer (step S15, Figures 4D to 4F) .
  • grinding is carried out with a wheel or grinding 250 the working surface or active grinding portion 252 of which comprises abrasive particles with a mean dimension of 44 micrometers or less or 325 mesh or more.
  • the abrasive particles may in particular be diamond particles.
  • a support 260 also known as a "chuck”, comprising a plate 262 that can hold the second wafer 300 , for example by suction or by an electrostatic system.
  • the support 260 is also movable in rotation about an axis 261 in a direction of rotation identical to that of the wheel as described above with reference to Figure 3.
  • the support 260 may be fixed while the wheel 250 is driven in rotation about its axis 251 or vice versa.
  • the rate of descent V D of the wheel 250 in the first wafer 210 is controlled as a function of the distance or drop present between the working surface 252 of the wheel 250 and the bonding interface (here the contact plane between the thermal oxide layers 205 and 305) , for example as follows :
  • the rate of descent V D is reduced to 2 ⁇ /sec;
  • the rate of descent V D is further reduced to 1 um/sec.
  • the depth of grinding is selected so as to stop the descent of the wheel 250 or more precisely its working surface 252, at a distance from the bonding interface h 2 oo of the order of 35 pm, below which distance the annular portion or ring 210 subsisting beneath the wheel 250 snaps off under the thermomechanical effects ( Figure 4E) .
  • Figure 4E thermomechanical effects
  • the remaining portion 203b of the support 203 of the first wafer 200 has a work-hardened surface 203a ( Figure 4F) .
  • Thinning of the first wafer 200 is continued by chemically etching the remaining portion 203b (step S16, Figure 3G) , for example by means of a TMAH
  • a second layer of microcomponents 214 is formed at the exposed surface of the layer 201 ( Figure 4H, step S17) .
  • the microcomponents 214 are formed in alignment with the buried microcomponents 204.
  • a photolithography mask similar to that used to form the microcomponents 204 is used.
  • a composite structure 500 is obtained, formed by the second wafer 300 and a transferred layer 215 corresponding to the remaining portion of the first wafer 200 comprising the microcomponents 204 and 214.
  • the three-dimensional structure is formed by a stack of layers, i.e. by bonding one or more additional wafers or substrates on the layer 201, each additional wafer being aligned with the directly adjacent layer or layers .
  • a partial trim carried out between the two thinning steps of the invention as described above is carried out for each wafer in order to form a transferred layer.
  • an oxide layer may be deposited on the exposed layer, for example a layer of TEOS oxide, in order to facilitate assembly and protect the trimmed zones (for which the material of the subjacent wafer is exposed) from subsequent chemical attack.
  • one of the layers of microcomponents may in particular comprise image sensors .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)

Abstract

La présente invention concerne un procédé de production d'une hétérostructure, le procédé comprenant les étapes consistant à coller une première plaquette (110) à une seconde plaquette (120) et à amincir la première plaquette (110) en ayant recours au moins au meulage en utilisant une roue (150) dont la surface de travail (152) est en contact avec la surface mise à nu (113a) de la première plaquette (110). La surface de travail (152) de la roue (150) comprend des particules abrasives dotées d'une dimension moyenne de 44 micromètres ou moins ou de 325 mesh ou plus. La vitesse de descente de la roue (150) lors de l'étape de meulage est réduite à au moins 1 μm/sec lorsque la surface de travail (152) de la roue est à une distance d'au moins 250 μm par rapport à l'interface de liaison entre les première et seconde plaquettes, l'étape de meulage à 1 μm/sec étant poursuivie jusqu'à ce que la surface de travail (152) de la roue (150) soit à une distance, par rapport à de ladite interface de liaison, égale à 35 μm ou moins.
PCT/EP2011/056444 2010-04-30 2011-04-21 Amincissement par rognage WO2011134896A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1053356A FR2959596B1 (fr) 2010-04-30 2010-04-30 Amincissement detourant
FR1053356 2010-04-30

Publications (2)

Publication Number Publication Date
WO2011134896A2 true WO2011134896A2 (fr) 2011-11-03
WO2011134896A3 WO2011134896A3 (fr) 2012-03-15

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FR (1) FR2959596B1 (fr)
TW (1) TW201207924A (fr)
WO (1) WO2011134896A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950267A (zh) * 2019-03-26 2019-06-28 德淮半导体有限公司 图像传感器的制作方法
CN116072533A (zh) * 2023-03-28 2023-05-05 成都功成半导体有限公司 一种晶圆及其晶圆减薄制程加工工艺
US12205865B2 (en) 2021-11-01 2025-01-21 Micron Technology, Inc. Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230139914A1 (en) * 2021-11-01 2023-05-04 Micron Technology, Inc. Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3352896B2 (ja) * 1997-01-17 2002-12-03 信越半導体株式会社 貼り合わせ基板の作製方法
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950267A (zh) * 2019-03-26 2019-06-28 德淮半导体有限公司 图像传感器的制作方法
US12205865B2 (en) 2021-11-01 2025-01-21 Micron Technology, Inc. Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same
CN116072533A (zh) * 2023-03-28 2023-05-05 成都功成半导体有限公司 一种晶圆及其晶圆减薄制程加工工艺
CN116072533B (zh) * 2023-03-28 2023-06-13 成都功成半导体有限公司 一种晶圆及其晶圆减薄制程加工工艺

Also Published As

Publication number Publication date
FR2959596A1 (fr) 2011-11-04
WO2011134896A3 (fr) 2012-03-15
FR2959596B1 (fr) 2012-07-06
TW201207924A (en) 2012-02-16

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