WO2011074873A2 - Class e power amplifier - Google Patents

Abstract

Disclosed is a CMOS class E power amplifier. One embodiment of the present invention provides a class E power amplifier comprising: a main stage which comprises a first power amplifier implemented by a transistor; a driver stage which comprises a second power amplifier implemented by a transistor, and in which the output terminal of the driver stage is connected to the input terminal of the main stage and wherein an input signal is inputted to the second power amplifier; a first LC resonator which has one terminal connected to the output terminal of the driver stage and the other terminal connected to a ground and thus can be made AC circuit equivalent; and a second LC resonator which has one terminal connected to the input terminal of the main stage and the other terminal connected to a ground and thus can be made AC circuit equivalent.

Description

E power amplifier

The present invention relates to a class E power amplifier, and more particularly, to implement a double resonant circuit for controlling harmonics to reduce the voltage stress on the transistor, the negative capacitance is implemented to compensate for the excess capacitance on the drain of the transistor The present invention relates to a CMOS Class E power amplifier, which improves overall efficiency and ensures reliability in operation.

Recently, due to the development of mobile communication technology, mobile terminals and the like have been used a lot. In such a mobile terminal, high RF signal transmission efficiency is required. In the transmission of the RF signal, a power amplifier, which consumes the most part of the DC power, can be treated as an important factor for the overall transmission efficiency of the RF signal. Therefore, in order to improve the overall efficiency, it is necessary to increase the efficiency of the power amplifier.

Typically, class E power amplifiers are widely used due to advantages such as high efficiency and simplicity of implementation. This class E power amplifier was proposed by Sokal in 1975 and tested by Raab. Specifically, in a switching type power amplifier, an ideal 100% drain (or collector) efficiency can be obtained by forming a voltage waveform and a current waveform. To date, the development of circuit designs such as As HBTs, GaN HEMTs, and InP DHBTs (Double HBTs) for active applications in microwave and high frequency bands with high RF performance has been actively developed. In addition, in recent years, research has been conducted on power amplifiers having watt-level output power using CMOS technology operating in a microwave frequency band to reduce costs.

Using a power amplifier using this CMOS technology may reduce the design cost, but there are many problems. One of these problems is due to the low breakdown voltage. The breakdown voltage decreases even further as the process size decreases. When the breakdown voltage decreases, the power supply voltage is limited to prevent breakdown. In order to deliver a wide range of output power under low supply voltage conditions, the load impedance must be lowered. However, this causes a decrease in efficiency and a narrow band load matching network.

In addition, power amplifiers using CMOS technology need to reduce the on-resistance for high efficiency and drive sufficient current for the watt-level output power. widths) is required. However, the maximum operating frequency (f _MAX ) of the class E power amplifier is proportional to the peak value (I _MAX ) of the drain current, so that the gate width is only several millimeters. In addition, even when the gate width is made wide, it generates parasitic elements such as parasitic capacitances, which increases the parallel drain capacitance C _P , which becomes an element limiting operating conditions. This is because the maximum operating frequency f _MAX of a class E power amplifier is determined by the value of I _MAX / C _P. On the other hand, due to parasitic capacitance, the efficiency of the parallel drain capacitance C _P is lowered from the optimum value determined by the operating conditions of the class E power amplifier.

The object of the present invention is to solve all the problems of the prior art described above.

In addition, another object of the present invention is to provide a double resonance circuit for harmonic control in a CMOS Class E power amplifier to prevent breakdown and to control the voltage waveform applied to the gate of the power amplifier to apply a voltage across the transistor. This reduces the stress, thereby enabling the application of a high power supply voltage and allowing the same efficiency to be obtained even with a high load impedance.

Meanwhile, another object of the present invention is to provide a higher output power by applying a differential structure instead of a single-ended structure in a CMOS Class E power amplifier, and to minimize interference with other circuits during operation. will be.

Representative configuration of the present invention for achieving the above object is as follows. According to an embodiment of the present invention, a main stage including a first power amplifier implemented as a transistor, and a second power amplifier implemented as a transistor, in which the input signal is input to the second power amplifier, A driving stage connected to an input terminal of the main stage, and a first LC resonator and one end connected to an output terminal of the driving stage and AC-equivalent to the other end connected to ground, and connected to an input terminal of the main stage; A class E power amplifier is provided that includes a second LC resonator that can be AC equivalent to the other end connected to ground.

According to the present invention, in class E power amplifiers using CMOS technology, breakdown can be prevented and voltage stress applied to the CMOS transistor can be reduced.

In addition, according to the present invention, as the voltage stress applied to the CMOS Class E power amplifier is reduced, it is possible to apply a high power supply voltage, thereby increasing the load impedance while maintaining the same efficiency.

On the other hand, according to the present invention, the differential structure is applied to the CMOS Class E power amplifier, it is possible to deliver a higher output power than the single-ended structure, and the interference to other circuits can be minimized during operation.

1 is a circuit diagram showing the basic configuration of a conventional class E power amplifier.

2A is a circuit diagram schematically illustrating a configuration of a class E amplifier including a double resonance circuit according to an embodiment of the present invention.

FIG. 2B is an AC equivalent circuit diagram of the circuit diagram shown in FIG. 2A.

3 is a graph showing the degree of reduction of input voltage, output voltage and voltage stress in a class E power amplifier in which a double resonance circuit is implemented according to an exemplary embodiment of the present invention.

4 is a graph illustrating waveforms of transistor drain voltages and current values flowing through transistors in accordance with a change in ω C _P R _L in a conventional class E power amplifier.

5A is a circuit diagram in which negative capacitance is actually applied to a part of a class E power amplifier according to an embodiment of the present invention.

FIG. 5B is an equivalent circuit diagram of the circuit shown in FIG. 5A.

6 is a circuit diagram showing the overall configuration of a class E power amplifier according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating an actual state of a chip implementing a CMOS class E power amplifier according to an embodiment of the present invention.

8 is a graph illustrating simulation results and actual measurement results of output power, drain efficiency, and power addition efficiency values with respect to a power supply voltage in a class E power amplifier according to an embodiment of the present invention.

9 is a graph illustrating an output spectrum and an emission mask in a class E power amplifier according to an embodiment of the present invention.

FIG. 10 is a graph illustrating drain efficiency, power adding efficiency, and output power according to an operating frequency in a class E power amplifier according to an embodiment of the present invention.

11 is a graph showing the reliability of the class E power amplifier implemented in the form of a cascode in accordance with an embodiment of the present invention.

12 is a graph comparing performance of a CMOS Class E power amplifier and another CMOS power amplifier according to an embodiment of the present invention.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be embodied in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. In addition, it is to be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. Like reference numerals in the drawings refer to the same or similar functions throughout the several aspects.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

[Preferred Embodiments of the Invention]

Prior to describing the features of the present invention, the basic configuration and operation of a class-E power amplifier, which is a technical field of the present invention, will be described.

E power amplifier

1 is a circuit diagram showing the basic configuration of a class E power amplifier.

Referring to FIG. 1, a conventional class E power amplifier may include a switch implemented with a transistor T, a parallel capacitor C _P connected in parallel with the switch, and a load resistor R _L. In addition, one or more lumped elements (eg, capacitors and inductors) having a predetermined impedance may be connected in series to the load resistor R _L. Here, the transistor T may be a CMOS transistor.

At this time, the parallel capacitor (C _P) and the load resistance (R _L) is forming a loop, or a parallel capacitor (C _P), load resistance (R _L) and a load resistance (R _L) and other elements in series connection forming a loop The current i _R flowing along can be expressed by the following equation.

Equation 1

In addition, the voltage v _C (ωt) applied to the transistor T and the current i (ωt) flowing through the transistor T may be represented by Equations 2 and 3 below.

Equation 2

Equation 3

값은 -32.482°가 된다.　 이에 따라, 수학식 2 및 수학식 3은 다음과 같은 수학식 4 및 수학식 5에 의해 표준 형식으로 표현될 수 있다.The class E power amplifier operates to charge or discharge the capacitor C _P according to an operation signal. Here, v _C (ωt) satisfies two conditions. The first condition of zero voltage switching (ZVS; Zero Voltage Switching) is prevented that the energy loss is stored in time and the capacitor (C _P) is turned on (on) the capacitor (C _P), the second condition of zero-voltage differential switch ( Zero Voltage Derivative Switching (ZVDS) makes the circuit less susceptible to changes in device, frequency, and switching cycles. In an environment where a class E power amplifier has a 50% duty cycle (the transistor is on in the interval 0≤ωt <π, and off in the interval π≤ωt <2π),

The value is -32.482 °. Accordingly, Equations 2 and 3 may be expressed in a standard format by Equations 4 and 5 as follows.

Equation 4

Equation 5

이다.In Equation 4 and Equation 5, V _DD is the power supply voltage of the class E power amplifier shown in Figure 1,

to be.

Class E power amplifiers operating on the waveforms represented by Equations 4 and 5 above are theoretically 100% because they do not generate DC losses due to overlapping V _C (ωt) and i (ωt) during operation. It has a drain (or collector) efficiency of. The relationship between the operating frequency, the capacitor C _P and the load resistance R _L can be represented by a relationship such as ω C _{P L} = 0.1836 for a theoretical Class E power amplifier.

However, in a practical environment, a change in the capacitance value of the capacitor C _P desirable occurs depending on the parasitic capacitance or the process change in the CMOS process. Therefore, when the load resistance R _L is fixed at a predetermined frequency, the ω C _P R _L value cannot be maintained at 0.1836. If the ω C _P R _L value deviates from 0.1836, loss occurs in the class E power amplifier and the drain (or collector) efficiency is reduced.

Another feature of the Class E power amplifier is that it has a high-peak voltage swing. In the above operating conditions, when the power supply voltage is V _DD , the maximum voltage V _MAX value applied to the drain (or collector) of the transistor T is expressed by Equation 6 below.

Equation 6

Here, the maximum voltage (V _MAX ) value affects the reliability of the transistor (T). In particular, in the case of CMOS transistors, the breakdown voltage is inevitably lowered, but the maximum voltage V _MAX is limited in order to avoid breakdown.

In order to solve this problem, the present invention forms a double resonance circuit in the class E power amplifier, thereby ensuring the reliability of the circuit and reducing the voltage stress applied to the transistor.

Hereinafter, a class E power amplifier according to an embodiment of the present invention will be described in detail.

First, a double resonance circuit included in a class E power amplifier according to an embodiment of the present invention will be described in detail.

Double resonant circuit

FIG. 2A schematically illustrates a circuit diagram of a double resonance circuit implemented in a class E amplifier according to an exemplary embodiment of the present invention, and FIG. 2B is an AC equivalent circuit diagram of the circuit diagram of FIG. 2A.

The double resonant circuit may form a predetermined voltage waveform at the node A, that is, the gate of the transistor included in the power amplifier, which may be performed through harmonic control. On the other hand, since the output of the power amplifier driven in the switching mode can be suitably formed for driving the class E power amplifier, the voltage waveform of the node B is applied by the switching mode driver stage (DS). Can be. Thus, a power amplifier driven in a switching mode operates in the nonlinear region, and its output waveform contains many harmonics. When the output signal of the driving stage DS is applied to the main stage MS, the DC bias difference between the output node B of the driving stage DS and the input node A of the main stage MS is applied. Only exists. Here, the waveform at the node A can be represented by the following equation (7).

Equation 7

In Equation 7 above, a _i represents the i-th harmonic coefficient.

The resonant frequency of the double resonant circuit is the fundamental frequency and the second harmonic. The double resonant circuit penetrates the fundamental frequency and the third harmonic from the driving stage DS to the main stage MS, and removes the second harmonic. That is, the operation to reduce even harmonics and infiltrate odd harmonics is performed. A voltage (v _G ) waveform according to the control of such harmonics, that is, a waveform in which even harmonics are reduced is shown in FIG. 3.

In FIG. 3, when V _G , v _C , and ΔV each have a transistor threshold voltage of 0.5 V and a power supply voltage V _DD of 1.0 V, and a constant duty cycle is maintained, as shown in FIG. The implemented class E power amplifier shows the reduction of input voltage, output voltage and voltage stress.

Referring to FIG. 3, when the switch is in the off state, the voltage of the drain (or collector) in the transistor included in the main stage MS is 3.56 V at a peak value (theoretically, 50% duty cycle). _DD ), where the maximum voltage stress is applied to the oxide layer of the gate. Let it applies to the double resonant circuit voltage (v _G) DC offset value during the turned off increases (off) state voltage (v _G) of the are from falling much while the duty cycle is not reduced below the threshold voltage of the transistor . Therefore, the high voltage v _G value in the off state can reduce the maximum voltage stress of the transistor.

This voltage formation obtained through harmonic control in the double resonant circuit is different from the DC bias increase. Increasing the DC bias will change the duty cycle of the power amplifier and the drain (or collector) peak voltage will vary depending on the changed duty cycle. As the duty cycle increases, the peak voltage also increases and worsens the voltage stress on the transistors. However, the formation of voltage through harmonic control results in the same duty cycle in transistors with a predetermined threshold voltage (eg, 0.5V), and the power amplifier maintains the same performance.

The double resonant circuit using harmonic control according to an embodiment of the present invention has the effect of protecting the transistor from breakdown through voltage stress reduction. In particular, in a CMOS class E power amplifier having a 1.0V supply voltage, the voltage stress is reduced by about 0.3V from 4.3V to 4.0V. In addition, the elimination of the second harmonic and the infiltration of odd harmonics facilitate the operation of the switching power amplifier by making the rise time and fall time of the voltage (v _G ) waveform faster.

Referring again to FIG. 2B, the present invention used two resonators to implement such a double resonant circuit. One of them is a series LC resonator DR1 including an inductor L ₁ and a capacitor C ₁ connected to the output node B of the driving stage DS and connected in series with each other, and the other is a gate inductor. And a parallel LC resonator DR2 comprising an input capacitor C _IN of L ₂ and main stage MS. The input capacitor C _IN is an equivalent capacitance component when the main stage MS is viewed from the input terminal of the main stage MS. In FIG. 2B, the portions marked with two boxes represent the series LC resonator DR1 and the parallel LC resonator DR2, respectively.

The parallel LC resonator (DR2) is designed to resonate at the fundamental frequency to overcome large input capacitances and drive the main power amplifier efficiently, and the series LC resonator (DR1) blocks the second harmonic at node B and the fundamental frequency. And third harmonics. By such a double resonant circuit, the transistor included in the main stage MS is protected from breakdown, and a margin for increasing the power supply voltage V _DD at the main stage MS is ensured. When the power load voltage of the power amplifier is high when the same load impedance, the high power can be output, the higher the power supply voltage, the performance of the power amplifier can be improved, according to the present invention as described above the power supply voltage ( Since V _DD ) can be high, the performance of the power amplifier can be improved. In addition, for CMOS power amplifiers with watt-level output power, the load impedance is typically a few ohms, so that the impedance transformer should have a high transformation rate, which is high when using the double resonant circuit of the present invention. As the power supply voltage V _DD can be applied, a high load impedance for high efficiency can be applied at the same output power.

Hereinafter, a negative capacitance included in a class E power amplifier according to an embodiment of the present invention will be described.

Negative capacitance

Prior to the description of the negative capacitance, the parallel capacitance in the class E power amplifier shown in FIG. 1 will be described.

1. Parallel capacitance

와ωC_PR_L 간의 관계는 다음과 같은 수학식으로 나타낼 수 있다.In the class E power amplifier shown in Figure 1, as described above, the efficiency is reduced if the ω C _P R _L value deviates from the optimum value,

The relationship between and ω C _P R _L can be expressed by the following equation.

Equation 8

와 ωC_PR_L 사이에는 역(inverse) 관계가 성립한다.　 ωC_PR_L가 0.1836에서부터 증가할 때,

는 감소하고 트랜지스터 드레인 전압은 ωt=2π에서 양의 값을 갖는다.　 한편, ωC_PR_L가 0.1836에서부터 감소할 때,

는 증가하고 트랜지스터 드레인 전압은 ωt=2π에서 음의 값을 갖게 된다.As can be seen in Equation 8,

An inverse relationship is established between and ωC _P R _L. When ω C _P R _L increases from 0.1836,

Decreases and the transistor drain voltage is positive at ωt = 2π. On the other hand, when ωC _P R _L decreases from 0.1836,

Is increased and the transistor drain voltage becomes negative at ωt = 2π.

The waveform of the transistor drain voltage v _C and the current i flowing through the transistor according to the change of ω C _P R _L is as shown in FIG. 4. 4 is a diagram showing a waveform of the normalized drain voltage v _c and the current i of a class E power amplifier according to the present invention when the duty cycle is 50% for a single period.

Referring to FIG. 4, it can be seen that the transistor is turned on in an interval of 0 ≦ ωt <π and turned off in an interval of π ≦ ωt <2π. When zero-voltage switching (ZVS) environment is not satisfied, that is, when the ωC _P R _L value is not 0.1836, the voltage and current waveforms are to be overlapped at the beginning of the next cycle. This is because a transient time that takes a voltage of 0V is required between the drain and the source of the transistor. This elapsed time causes a loss for a finite time. Therefore, it is preferable that the fixed R _L and C _P values are maintained at optimum values for the high efficiency of the class E amplifier at a predetermined frequency.

Hereinafter, the negative capacitance will be described based on the description of the parallel capacitance.

2. Negative capacitance

FIG. 5A is a circuit diagram in which negative capacitance is actualized, and FIG. 5B is an equivalent circuit diagram of the circuit shown in FIG. 5A.

In the CMOS power amplifier shown in Figs. 5A and 5B, the gate width is preferably wide because it must deliver watt level output power. The gate width is a few millimeters (mm) and a transistor of this width may contain a capacitance of several pico farads (F) at the drain node. This will exert a parasitic capacitance component in parallel to a drain capacitor (C _P), thereby becomes larger than the capacitance value C _P is an ideal optimal value of the capacitor (C _P) which will cause a decrease in drain efficiency. In addition, in the class E power amplifier, it is preferable to adopt a cascode form to ensure reliability, which causes a high peak voltage. Common gate (CG) power amplifiers added with the use of cascode forms typically have a wide gate width, which also reduces the on resistance and causes an increase in the capacitance value of the capacitor C _P. . Therefore, in order to suppress the decrease in efficiency, it is important to compensate for the excess capacitance generated as the capacitance value of the capacitor C _P increases.

Excess capacitance must be compensated for to maintain an optimal C _P value. One method used to remove excess capacitance is to place an inductor at the same node as the DC block (see Figure 2). However, in integrated circuit implementation, a large area is required for inductor placement. In addition, the inductor includes parasitic components such as parasitic capacitance or parasitic resistance, and has a disadvantage of having a low Q-factor. Therefore, the present invention adopts a configuration in which negative capacitance components are arranged in a cascode form instead of inductors in order to remove excess capacitance components. That is, in FIG. 5A, a negative capacitor C _n is disposed between the node A and the node B in series with the capacitor C _P.

Basically, the negative capacitance value acts like a Polarity Inversed Miller Capacitance. The negative capacitor C _n in FIG. 5A may be equivalent to the Miller capacitor C _M in FIG. 5B. This Miller capacitance is expressed by the following equation (9).

Equation 9

Where K is the voltage gain of the negative capacitor (C _n ) node, typically K value is negative. That is, the Miller capacitor C _M increases the capacitance value by a value of (1-K) -C _n . Miller capacitor C _M at node A as shown in FIG. 5B by connecting a negative capacitor C _n between an input node and an output node of a common gate power amplifier having a gain as positive as K. The same effect as that formed can be obtained. The negative capacitor C _n compensates for the excess capacitance of the node A, and adjusts the capacitance value of the capacitor C _P to an optimal value to ensure the operation performance of the class E power amplifier.

Negative capacitance implemented using capacitors offers several advantages for CMOS power amplifiers. First, capacitors have a smaller area than the inductor in their implementation, have a high Q factor, and have relatively small parasitics, making it easier to maintain optimal performance. Second, because they are placed in parallel with the switch implemented as a transistor, they can be turned on or off with the switch and are doubled by the gain of the common gate power amplifier (e.g., K described above). It can also be implemented with small values.

On the other hand, since the parasitic capacitance of node B in FIG. 5A and FIG. 5B is smaller than that in node A, the parasitic capacitance value of node B can be ignored compared to the problem in node A. FIG. Also, since the common gate power amplifier always operates on to reduce the on resistance, most of the charge / discharge of the capacitor occurs at node A. Thus, a negative capacitor may be used only to compensate for the parasitic capacitance value of node A.

Hereinafter, the actual design circuit of the class E power amplifier according to an embodiment of the present invention will be described.

Configuration of Design Circuit

6 is a view showing the configuration of a circuit actually designed a class E power amplifier according to an embodiment of the present invention, Figure 7 is a view showing the actual state of the chip implementing the CMOS class E power amplifier.

First, a configuration of a main stage MS included in a design circuit of a class E power amplifier according to an embodiment of the present invention will be described.

1. Main Stage

In a class E power amplifier, a voltage having a high peak value is applied to a transistor (for example, a CMOS transistor) to generate voltage stress. As described above, since the cascode structure can distribute a wide output voltage swing to transistors connected in series, in order to prevent breakdown, the main stage (MS) circuit can be designed with the cascode structure as shown in FIG. It is preferable.

Referring to FIG. 6, the main stage MS includes one or more common gate power amplifiers and one or more common source (CS) power amplifiers. The common gate power amplifier and the common source power amplifier form a cascode structure, and one or more cascode structures form a differential structure.

In the circuit diagram shown in FIG. 6, transistors T3 and T4 composed of thin gate oxides are used as the common source power amplifier, and thick gate oxide transistors T1 and T2 are used as the common gate power amplifier. . As an example, the thin gate oxide transistor may be a transistor having a gate length of 0.13 μm at a 1.2 V supply voltage, and the thick gate oxide transistor may be a transistor having a gate length of 0.34 μm at a 3.3 V supply voltage. Improved RF performance can reduce the complexity of the drive power amplifier and achieve high operating efficiency. Two thin gate oxide transistors exhibit high RF performance and have low on-resistance compared to thick gate oxide transistors. Rather than using thick gate oxide transistors, it is preferable to combine the above-described combinations, that is, thin gate oxide transistors and thick gate oxide transistors.

On the other hand, the circuit includes several parasitic components (eg, drain capacitance) that increase the value of the capacitor C _P (see FIG. 5). In order to reduce this, a transistor having a predetermined gate width is used as a common source power amplifier. Can be used. As an example, as illustrated in FIG. 6, a transistor having a gate width of 4000 μm may be used.

In the common gate power amplifier, since a wide voltage swing is applied, it is preferable to use a thick gate oxide transistor. The use of thick gate oxide transistors prevents breakdown and can be biased at all times, thereby reducing the on resistance to maintain high efficiency. As an example, a transistor having a gate width of 7000 μm may be used as the common gate power amplifier.

Next, the configuration of the driving stage DS included in the design circuit of the class E power amplifier according to an embodiment of the present invention will be described.

2. Drive stage

As shown in FIG. 6, the driving stage DS according to an embodiment of the present invention includes one or more common source power amplifiers and one or more common gate power amplifiers. The common source power amplifier and the common gate power amplifier form a cascode structure, and one or more cascode structures form a differential structure.

Since a wide voltage swing appears at the output of the E-class power amplifier, the power amplifier can be driven sufficiently with a low supply voltage. When a low power supply voltage is applied to the driving power amplifier, the DC power loss is reduced, thereby reducing the efficiency reduction from the drain efficiency DE to the power added efficiency (PAE). Also, a double resonant circuit may be considered to design the load impedance of the drive stage DS. In fact, in the drive stage DS shown in Fig. 6, the difference between the drain efficiency and the power adding efficiency is only 3% to 4%.

Meanwhile, in order to prevent breakdown, it is preferable to arrange the driving stage DS and the thick gate oxide transistor in a cascode form as shown in FIG. 6. As an example, transistors T5, T6, T7, and T8 having a gate width of 200 mu m can be used.

6 and 7, a predetermined transformer may be connected to the gate of the common source transistor and used as an input balb (IB). These transformers convert single-ended structures into differential ones to drive differential amplifiers.

Hereinafter, a double resonance circuit included in a design circuit of a class E power amplifier according to an embodiment of the present invention will be described.

3. Double resonant circuit

As described above, the voltage waveform at the input of the main power amplifier included in the main stage MS may be formed by the double resonant circuit. The double resonant circuit may be configured as a first resonator and a second resonator, wherein the first resonator is formed at the output node N1 of the driving power amplifier. This resonator is implemented as a series LC resonator comprising an inductor L1 and a capacitor C1 connected in series. The series LC resonator removes the second harmonic from the signal flowing through the input node of the main power amplifier and infiltrates the third harmonic into the main power amplifier included in the main stage MS. In addition, the second resonator includes an inductor L2 connected to the gate of the main power amplifier. The inductor L2 resonates at the resonant frequency with the input capacitance C _IN of the main power amplifier (see FIG. 2).

The double resonant circuit reduces voltage stress on a common source power amplifier implemented by a thin gate oxide transistor formed in a cascode form in the main stage MS, and a voltage waveform in which performance and duty cycle of the power amplifier are not deteriorated. To form. As a result of directly simulating the circuit shown in Fig. 6, the voltage stress was reduced by 0.2V in the CMOS transistor.

Next, a negative capacitor C _n connected to the input terminal and the output terminal of the main stage MS will be described.

4. Negative capacitance

As described above, the negative capacitor C _n compensates for the excess capacitance value of the drain capacitor C _P of the transistor included in the main stage MS to restore the optimal C _P value. The capacitor C _n having such a function may be implemented by appropriately connecting a capacitor having a predetermined value between the drain and the source of the common gate transistor included in the main stage MS, as shown in FIG. 6.

On the other hand, the capacitor in the main stage (MS) (C _n) is large, the capacitance C _n value because it provides a feedback path to the common gate power amplifier becomes difficult to secure the stability. However, as described above, even if the capacitance C _n value is small due to the gain value (for example, K) of the common gate power amplifier, it can serve as a sufficient negative capacitor. For example, in FIG. 6, a capacitor C _n having a capacitance value of 1.0 pF is used. As a result of the simulation, it was found that the stability was not degraded even when the capacitor C _n was inserted. In addition, this negative capacitor (C _n ) was able to compensate for the excess capacitance of about 10.0pF and the power added efficiency is improved by about 6%.

Hereinafter, the actual operating characteristics and performance of the class E power amplifier designed according to an embodiment of the present invention will be described.

Operation Characteristics and Performance of Class E Power Amplifiers

The inventors of the present patent application implemented a power amplifier including a drive stage DS and an input balloon as shown in Figs. 6 and 7 using a standard CMOS process having a gate length of 0.13 mu m. In the chip as shown in FIG. 7, the total die area including the bonding pads was 1.0 mm 2. On the other hand, multiple bonding pads were used to minimize the effects of changes in bonding inductance. A total of 12 pads were used to reduce ground resistance and provide a heat sink to the power amplifier. Passive devices other than the chip are implemented in a FR4 printed circuit board (PCB).

8 is a simulation of output power (Pout), drain efficiency (DE), and power added efficiency (PAE) values with respect to a power supply voltage (V _DD ) in a class E power amplifier according to an embodiment of the present invention. This graph shows the results and the actual measurement results. Here, the operating frequency was 1.8 GHz.

Referring to FIG. 8, the power supply voltage V _DD varies from 0.3V to 3.5V while the gate bias of the common gate power amplifier is maintained at 2.5V in the sweep mode. Here, when the power supply voltage V _DD was 3.5V, the output power Pout was measured at 31.5 dBm, the drain efficiency DE at 54%, and the power added efficiency PAE at 51%. In addition, the output power Pout was measured to increase by 0.4 dB while the supply voltage V _DD varied from 3.3V to 3.5V. During this measurement, the input signal was set at 6.5 dBm and a power gain of 25 dB was obtained.

9 is a graph illustrating an output spectrum and an emission mask in a class E power amplifier according to an embodiment of the present invention.

Since the class E power amplifier is a switching power amplifier, a modulated signal having a constant size is suitable. Therefore, in the present measurement, the output spectrum was measured by applying a GSMK modulated signal with BT = 0.3. Referring to FIG. 9, it can be seen that at an average output power of 31.5 dBm, the power amplifier satisfies the spectral mask with an error vector magnitude (EVM) of 0.6%. It can also be seen that the degree of suppression for the second and third harmonics appears as -52 dBc and -29 dBc, respectively. As the power amplifier is differentially designed, it can be seen that the second harmonic is clearly suppressed.

FIG. 10 is a graph illustrating a drain efficiency (DE), a power added efficiency (PAE), and an output power according to an operating frequency in a class E power amplifier according to an embodiment of the present invention. The maximum output power was measured at 31.5 dBm at 1.8 GHz operating frequency, and the maximum drain efficiency (DE) and maximum power added efficiency (PAE) were 58% and 54% at 31 dBm output power at 1.9 GHz operating frequency, respectively. Was measured. On the other hand, in the operating frequency range of 1.6 GHz to 2.0 GHz, an output power of 29 dBm was measured.

11 is a graph showing the reliability of the class E power amplifier implemented in the form of a cascode in accordance with an embodiment of the present invention.

The power amplifier was run for 4 hours at full output power for reliability measurements. In addition, while maintaining the power supply voltage (V _DD ) at 3.5V for 4 hours, the output power, drain efficiency (DE) and power addition efficiency (PAE) were measured. Measurements for 4 hours showed no degradation in output power or efficiency. In addition, the output power after 4 hours was reduced by only about 0.05 dB, and the drain efficiency (DE) and power addition efficiency (PAE) were also reduced by only 0.7% and 0.8%, respectively.

12 is a graph comparing performance of a class E power amplifier and another power amplifier according to an embodiment of the present invention. The power amplifier here is a watt-level CMOS power amplifier implemented in a differential structure. For comparison, a figure of merit (FoM) proposed by the International Technology Roadmap for Semiconductor (ITRS) was used. The figure of merit is an index that standardizes key performance such as the square of the output power (Pout), power addition efficiency (PAE), output gain (G) and operating frequency (f ₀ ² ). This figure of merit is expressed by the following equation (10).

Equation 10

Fig. 12 shows FoM _PA values according to maximum outputs, in which squares represent the figure of merit of a class E amplifier according to the invention at operating frequencies of 1.8 GHz and 1.9 GHz, respectively, Represents a figure of merit. Specifically, the rhombus represented by [14] is K.-C. Tsai and PR Gray, “A 1.9-GHz, 1-W CMOS Class-E power amplifier for wireless communications,” IEEE J. Solid-State Circuit, vol. 34, pp. 962-970, Jul. Performance index of CMOS Class E power amplifiers introduced in 1999. The rhombus represented by [16] is J. Jang, C. Park, H. Kim, and S. Hong, “A CMOS RF power amplifier using an off. -chip transmision line transformer with 62% PAE, ”IEEE Microwave and Wireless Components Letters, vol. 17, pp. 385-387, May 2007. The figure represents the figure of merit for CMOS power amplifiers, [17] and [17] ^* where the rhombus is represented by R. Brama, L. Larcher, A. Mazzanti, and F. Svelto, “ A 30.5 dBm 48% PAE CMOS class-E PA with integrated balun for RF applications, ”IEEE J. Solid-State Circuits. vol. 43, pp. 1755-1762, Aug. In the CMOS Class E power amplifier introduced in 2008, the figure shows the case where the output balloon is not included and when it is included. The rhombus represented by [18] is represented by KLR Mertens and MSJ Steyaert, “A 700-MHz, 1-W fully differential CMOS class-E power amplifier, ”IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 137-141, Jan. Performance index of CMOS Class E power amplifier introduced in 2006. The description of the power amplifiers disclosed in the above documents will be omitted.

12, it can be seen that the power amplifier according to the present invention exhibits a high performance index compared to other power amplifiers.

As can be seen from above, when the class E differential amplifier of the present invention is implemented using a standard CMOS process of 0.13㎛, 31.5dBm output power, 54% drain efficiency (DE) at an operating frequency of 1.8GHz, A power addition efficiency (PAE) of 51% was obtained. In addition, it can be seen that a long time operation at the maximum output does not cause a degradation in performance.

Although the present invention has been described by specific embodiments such as specific components and limited embodiments and drawings, it is provided to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments, Those skilled in the art to which the present invention pertains can make various modifications and variations from this description.

Therefore, the spirit of the present invention should not be limited to the embodiments described above, and all of the equivalents or equivalents of the claims, as well as the claims below, are included in the scope of the spirit of the present invention. I will say.

Claims (17)

A first power amplifier implemented with a transistor, wherein the first power amplifier includes a driving stage to which an input signal is input; A main stage including a second power amplifier implemented with a transistor, the input stage of which is connected to the output stage of the driving stage, and A first LC resonator, one end of which is connected to an output end of the drive stage and the other end is connected to ground, and the first LC resonator and one end of which is connected to an input end of the main stage, and the other end is AC equivalent, connected to ground. Second LC resonator E power amplifier comprising a. The method of claim 1, The first LC resonator includes an inductor and a capacitor connected in series with each other. The method of claim 2, The first LC resonator blocks the even harmonics during operation and injects the odd harmonics into the main stage. The method of claim 1, And a DC BLOCK portion formed between the one end of the first LC resonator and the one end of the second LC resonator and including a capacitor. The method of claim 1, The second LC resonator may be AC equivalent, in which one end is connected to an input terminal of the main stage and the other end is connected to ground, and an input capacitance component when looking at the main stage from the inductor is connected in parallel. E power amplifier. The method of claim 5, The second LC resonator resonates at a fundamental frequency during operation. The method of claim 1, The main stage, A class E power amplifier comprising at least one cascode structure consisting of a common gate transistor and a common source transistor. The method of claim 7, wherein And said at least one cascode structure forms a differential structure. The method of claim 7, wherein And the output signal of the driving stage is input to the gate of the common source transistor. The method of claim 7, wherein The common gate transistor is a class E power amplifier, characterized in that consisting of a transistor having a thick oxide gate compared to the common source transistor. The method of claim 7, wherein E further comprising a negative capacitance component connected between the drain and the source of the common gate transistor, the negative capacitance component to cancel the parasitic capacitance component generated between the drain and the source of the common source transistor due to the gate width of the transistor. Class power amplifier. The method of claim 11, When the value of the negative capacitance is C _n , the negative capacitance component is equalized to Miller capacitance having a capacitance value of (1-K) · C _n in parallel with the parasitic capacitance component. The K value is a gain value of the common gate transistor, and the absolute value of the (1-K) -C _n value is substantially equal to the parasitic capacitance value. The method of claim 1, The drive stage, A class E power amplifier comprising at least one cascode structure consisting of a common gate transistor and a common source transistor. The method of claim 13, And said at least one cascode structure forms a differential structure. The method of claim 13, The class E power amplifier, characterized in that the input signal of the class E power amplifier is input to the gate of the common source transistor. The method of claim 15, The Class E power amplifier, characterized in that the input balun (Input Balun) is formed on the gate of the common source transistor. The method of claim 16, And the input balloon converts the input signal having a single-ended structure into a differential structure and inputs the input signal to a gate of the common source transistor included in the one or more cascode structures.

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